U.S. patent application number 15/491989 was filed with the patent office on 2017-09-21 for hybrid integration fabrication of nanowire gate-all-around ge pfet and polygonal iii-v pfet cmos device.
The applicant listed for this patent is Zing Semiconductor Corporation. Invention is credited to Deyuan Xiao.
Application Number | 20170271211 15/491989 |
Document ID | / |
Family ID | 59383181 |
Filed Date | 2017-09-21 |
United States Patent
Application |
20170271211 |
Kind Code |
A1 |
Xiao; Deyuan |
September 21, 2017 |
HYBRID INTEGRATION FABRICATION OF NANOWIRE GATE-ALL-AROUND GE PFET
AND POLYGONAL III-V PFET CMOS DEVICE
Abstract
The present invention provides a method of manufacturing
nanowire semiconductor device. In the active region of the PMOS the
first nanowire is formed with high hole mobility and in the active
region of the NMOS the second nanowire is formed with high electron
mobility to achieve the objective of improving the performance of
nanowire semiconductor device.
Inventors: |
Xiao; Deyuan; (Shanghai,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Zing Semiconductor Corporation |
Shanghai |
|
CN |
|
|
Family ID: |
59383181 |
Appl. No.: |
15/491989 |
Filed: |
April 20, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15157421 |
May 18, 2016 |
9721846 |
|
|
15491989 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/02639 20130101;
H01L 21/02546 20130101; H01L 29/4908 20130101; H01L 29/1079
20130101; H01L 29/0673 20130101; H01L 27/1207 20130101; H01L 29/517
20130101; H01L 29/42392 20130101; H01L 21/823821 20130101; H01L
29/66439 20130101; H01L 29/78696 20130101; H01L 29/7853 20130101;
H01L 21/02603 20130101; H01L 29/78684 20130101; H01L 21/02532
20130101; H01L 27/0924 20130101; H01L 21/823857 20130101; H01L
21/823807 20130101; H01L 29/42364 20130101; H01L 29/66227 20130101;
H01L 29/78681 20130101; H01L 27/092 20130101; H01L 21/823828
20130101; B82Y 10/00 20130101; H01L 21/8258 20130101; H01L 29/66469
20130101; H01L 27/0922 20130101; H01L 21/84 20130101 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238; H01L 29/06 20060101 H01L029/06; H01L 21/02 20060101
H01L021/02; H01L 29/786 20060101 H01L029/786; H01L 29/51 20060101
H01L029/51; H01L 29/49 20060101 H01L029/49; H01L 27/092 20060101
H01L027/092; H01L 29/423 20060101 H01L029/423 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 16, 2016 |
CN |
201610150107.3 |
Claims
1. A nanowire semiconductor device characterized in comprising: a
substrate, said substrate including an active region of PMOS and an
active region of NMOS; forming a first nanowire in the active
region of PMOS; forming a second nanowire on the active region of
NMOS; and completely surrounding the first nanowire and partially
surrounding the second nanowire with gate dielectric layer and the
gate electrode layer.
2. The nanowire semiconductor device according to claim 1,
characterized in that the length of the first nanowire is in the
range of between 2 nm to 50 nm, the diameter of said first nanowire
is in the range of between 2 nm to 5 nanometers.
3. The nanowire semiconductor device according to claim 1, wherein
the first nanowire is germanium nanowire, the shape of the section
of said germanium nanowire is circular, oval or prism; said second
nanowire is InGaAs nanowire, the cross-sectional shape of said
second nanowire is polygon.
4. The nanowire semiconductor device according to claim 3,
characterized in that the germanium content of the first nanowire
is in the range of between 65% to 100%.
5. The nanowire semiconductor device according to claim 1, wherein
said gate dielectric layer is a high-k gate dielectric layer, the
material of said gate dielectric layer material is Al.sub.2O.sub.3
or TiSiO.sub.x. The gate electrode layer is a metal electrode
layer, the material of said gate electrode layer is TiN, NiAu or
one of CrAu.
6. A method for implementing a nanowire semiconductor device, the
method comprising: providing a substrate, said substrate including
an active region of PMOS and an active region of NMOS; forming a
first nanowire in the active region of PMOS; forming a second
nanowire on the active region of NMOS; and completely surrounding
the first nanowire and partially surrounding the second nanowire
with gate dielectric layer and the gate electrode layer.
7. The method for implementing nanowire semiconductor device
according to claim 6, characterized in that the length of the first
nanowire is in the range of between 2 nm to 50 nm, the diameter of
said first nanowire is in the range of between 2 nm to 5
nanometers.
8. The method for implementing nanowire semiconductor device
according to claim 6, wherein the first nanowire is germanium
nanowire, the shape of the section of said germanium nanowire is
circular, oval or prism; said second nanowire is InGaAs nanowire,
the cross-sectional shape of said second nanowire is polygon.
9. The method for implementing nanowire semiconductor device
according to claim 8, characterized in that the germanium content
of the first nanowire is in the range of between 65% to 100%.
10. The method for implementing nanowire semiconductor device
according to claim 6, wherein said gate dielectric layer is a
high-k gate dielectric layer, the material of said gate dielectric
layer material is Al.sub.2O.sub.3 or TiSiO.sub.x. The gate
electrode layer is a metal electrode layer, the material of said
gate electrode layer is TiN, NiAu or one of CrAu.
Description
[0001] The present application is a divisional application of the
U.S. application Ser. No. 15/157,421 filed on May 18, 2016, which
claims the priority to Chinese Patent Applications No.
201610150107.3, filed with the Chinese State Intellectual Property
Office on Mar. 16, 2016, which is incorporated herein by reference
in its entirety.
TECHNICAL FIELD
[0002] The present invention relates to the field of semiconductor
technology, in particular to a nanowire semiconductor device and
its manufacturing method.
BACKGROUND
[0003] Over the past four decades, the development of the
microelectronics industry has been consistently following the pace
of Moore's Law to shrink the characteristic sizes of semiconductor
devices. Currently, the physical size of the semiconductor devices
has reached its limit, any further reduction of the physical size
to improve performance is becoming extremely difficult.
[0004] To meet the challenge of size reduction and market demand,
the design of new types of semiconductor devices have turned to the
development of nanowire field effect transistor (NWFET). NWFET
structure has a one-dimensional line channel. Due to the quantum
confinement effect, the motion of carriers in the channel is
restricted in specific energy levels, free from the disturbance of
surface scattering and the channel transverse electric field. As a
result, the carriers are transported in NWFET with significantly
higher mobility. On the other hand, NWFET channel is smaller in
size and usually designed with wrap around gate. The all-around
gate enables the modulation of the channel from a plurality of
directions, thereby enhancing the regulatory capacity of the gate
to improve the threshold characteristics. Therefore, the short
channel effect in NWFET can be very well suppressed, enabling
further size reduction of the field effect transistor. Meanwhile,
NWFET, owing to the fine channel size and the unique all-around
gate design, allows easing the demand of shrinking the gate
dielectric thickness, thereby reducing the gate leakage current.
Consequently, NWFET is gaining increasing attention of
researchers.
[0005] However, in reality, the performance of manufactured
nanowire semiconductor devices remains relatively poor, cannot meet
the market requirements. The challenge remains for people in the
field of semiconductor manufacturing to further improve the
performance of the nanowire semiconductor device to meet the
technical performance and market demands.
SUMMARY
[0006] The main purpose of the present invention is to provide a
method of fabrication of a nanowire semiconductor device to remedy
the problem of poor performance of nanowire semiconductor device
manufactured with prior art. The method of manufacturing a nanowire
semiconductor device of the present invention comprising:
[0007] providing a substrate, said substrate including an active
region NMOS and PMOS active region;
[0008] at first, a selective epitaxial growth process is performed
to produce a first polygon structure nanowire in the active region
of NMOS;
[0009] a second selective epitaxial growth process performed to
form a polygon structure second nanowire in the PMOS active
region;
[0010] removing a portion of the substrate through an etching
process, such that the first of the nanowire is suspended above the
substrate;
[0011] said first nanowire is treated with oxidation and
annealing;
[0012] and sequentially forming a gate dielectric layer and a gate
electrode layer on said substrate, first nanowire, and second
nanowire.
[0013] Alternatively, in the method of manufacturing a nanowire
semiconductor device, providing a substrate comprising an isolation
structure formed on the substrate prior to performing the first
selective epitaxial growth process to form a first polygon
structure in the NMOS active region.
[0014] In the method of manufacturing a nanowire semiconductor
device, a first selective epitaxial growth process is performed to
form a first polygon structure nanowire in the active region of
NMOS comprising: forming a first patterned hard mask layer on the
substrate and the isolation structure. The first hard mask layer
has a first through hole and exposing a portion of the substrate of
said first NMOS active region at the bottom of the through
hole.
[0015] The first selective epitaxial growth process is to form a
first polygonal structure nanowire on the exposed substrate of said
first through hole and removing the first hard mask layer.
[0016] Alternatively, in the method of manufacturing a nanowire
semiconductor device, a second selective epitaxial growth process
is performed to form a second polygon structure nanowire in the
active region of PMOS comprising:
[0017] forming a patterned second hard mask layer on the substrate,
the isolation structure and the first nanowire, said second hard
mask layer has a second via hole and the bottom of the second
through hole exposing a portion of the substrate of the active
region of PMOS; a recess is formed at the exposed substrate at the
bottom of the second through hole by wet etching.
[0018] A second selective epitaxial growth process is performed to
form a second nanowire of polygonal cross-section on said recess;
and removing the second hard mask layer.
[0019] Alternatively, in the method of manufacturing a nanowire
semiconductor device, the process of oxidation and annealing
treatment of the first nanowire comprising:
[0020] thermal oxidation of said first nanowires; the oxide layer
on the first nanowire surface is removed by wet etching process;
and annealing the first nanowire in a hydrogen environment at high
temperature.
[0021] Alternatively, in the method of manufacturing a nanowire
semiconductor device, the material of the first nanowire and the
second nanowire are group III-V semiconductor material.
Alternatively, in the method of manufacturing a nanowire
semiconductor device, the material of said first nanowire is
germanium, the material of said second nanowire is indium gallium
arsenide.
[0022] The present invention also provides a nanowire semiconductor
device comprising:
[0023] a substrate, said substrate including active regions in PMOS
and NMOS; forming a first nanowire in the active region of
PMOS;
[0024] a second nanowire in the active region of NMOS;
[0025] surrounding completely said first nanowire and partially the
second nanowire with gate dielectric layer and gate electrode
layer.
[0026] Alternatively, in said nanowire semiconductor device, the
length of the first nanowire is in the range of between 2 nm to 50
nm, the diameter of the first nanowire is in the range of between 2
nm to 5 nm.
[0027] Alternatively, in said semiconductor device, the first
nanowire is germanium nanowire, the shape of the cross-section of
germanium nanowire is circular, elliptical or prismatic. Said
second nanowire is InGaAs nanowire, the shape of the cross-section
of the second nanowire is polygon.
[0028] Alternatively, in said nanowire semiconductor device, the
first nanowire has germanium content in the range of between 65% to
100%. Alternatively, in said nanowire semiconductor device, the
dielectric layer is high-k gate dielectric layer. The gate
dielectric layer material is Al.sub.2O.sub.3 or TiSiO.sub.x. The
gate electrode layer is a metal electrode layer, the material of
the gate electrode layer is TiN, NiAu or anyone of CrAu.
[0029] In summary, the present invention provides a method of
manufacturing nanowire semiconductor device. In the active region
of the PMOS the first nanowire is formed with high hole mobility
and in the active region of the NMOS the second nanowire is formed
with high electron mobility to achieve the objective of improving
the performance of nanowire semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG. 1 is a flowchart for an embodiment of the present
invention describing the processes of manufacturing a nanowire
semiconductor device;
[0031] S10: providing a substrate, said substrate including active
region of NMOS and PMOS;
[0032] S11: the first selective epitaxial growth process to form a
first nanowire having a polygon structure on the NMOS active
region;
[0033] S12: second selective epitaxial growth process to form a
second nanowire having a polygon structure on the PMOS active
region;
[0034] S13: removing a portion of the substrate through an etching
process, such that the first nanowire is suspended above the
substrate;
[0035] S14: oxidation annealing treatment of the first
nanowire;
[0036] S15: in the substrate, sequentially forming on the first
nanowire and the second nanowire the gate dielectric layer and the
gate electrode layer.
[0037] FIGS. 2 to 12 are schematics of the processes of
manufacturing a semiconductor nanowire device showing the
structural views of an embodiment the present invention.
DETAILED DESCRIPTION
[0038] The following is a detail description with accompanying
drawings of an embodiment of the present invention providing the
method to manufacture a nanowire semiconductor device. The purposes
of the following description are to highlight and clarify the
advantages and features of the present invention. It should be
noted that the drawings are used in a very simplified form and are
using a non-precise proportion, only to facilitate and for the
purpose of assisting lucid description of an embodiment of the
present invention.
[0039] FIG. 1 is a flowchart for an embodiment of the present
invention describing the method and procedures of manufacturing a
nanowire semiconductor device, comprising:
[0040] S10: providing a substrate, said substrate including active
regions of NMOS and PMOS;
[0041] S11: performing the first selective epitaxial growth process
to form a polygon structure first nanowire in the active region of
NMOS;
[0042] S12: performing the second selective epitaxial growth
process to form a polygonal structure second nanowire on the active
region of PMOS;
[0043] S13: removing a portion of the substrate through an etching
process, such that the first nanowire is suspended above the
substrate;
[0044] S14: oxidation and annealing treatment of the first
nanowires;
[0045] S15: in the substrate, sequentially forming on the first
nanowire and the second nanowire the gate dielectric layer and the
gate electrode layer.
[0046] FIGS. 2 to 12 are schematics of the processes of
manufacturing an embodiment the present invention a semiconductor
nanowire device. FIGS. 2 to 12, in conjunction with FIG. 1, are
detailed descriptions of the present invention of the method of
manufacturing a nanowire semiconductor device:
[0047] firstly, as shown in FIG. 2, providing a substrate 210, said
substrate 210 comprises patterned active region 210a of PMOS and
active region 210b of NMOS;
[0048] subsequently, as shown in FIG. 3, an oxide layer is formed
on the substrate 210 and the excessive oxide layer is removed using
chemical mechanical polishing to form an isolation structure 220,
and the top of the isolation structure 220 is substantially
leveling with the top of the substrate 210.
[0049] Performing the first selective epitaxial growth process to
form a polygon structure in the PMOS active region 210a the first
nanowire 240. The processes of formation of a first nanowire 240
comprises:
[0050] step one: a first patterned hard mask layer 230 is formed on
the substrate 210 and isolation structure 220, the first hard mask
layer 230 having a first through hole 230a, the bottom of the first
through hole 230a exposing a portion of the substrate 210 of the
PMOS active region 210a;
[0051] step two: performing the first selective epitaxial growth
process to form a first polygonal structure nanowire 240 on the
exposed substrate 210 at the bottom of the first through hole
230a;
[0052] step three: removing the first hard mask layer 230.
[0053] After step one, as shown in FIG. 4, the first patterned hard
mask layer 230 is formed on the substrate 210 and the isolation
structure 220. A portion of the first hard mask layer 230 covering
the active region 210a of PMOS is etched away to form a first
through hole 230a. At the bottom of the first through hole 230a the
substrate 210 is exposed.
[0054] As shown in FIG. 5, after the execution of step two, a
polygonal first nanowire 240 is formed. The first nanowire 240 is
in contact with the substrate 210 of the PMOS active region
210a.
[0055] Thereafter, a second selective epitaxial growth process is
performed to form a second polygonal nanowire 260 in the active
region 210b of NMOS. The processes of forming the second nanowire
260 comprising:
[0056] step one: forming a second patterned hard mask layer 250 on
the substrate 210, the isolation structure 220 and the top of the
first nanowire 240. At the bottom of the second through hole 250a
of the second hard mask layer 250 a portion of the substrate 210 of
NMOS active region 210b is exposed;
[0057] step two: wet etching the exposed substrate 210 at the
bottom of the through hole 250a to form a recess 212 on the exposed
substrate 210;
[0058] step three: the second selective epitaxial growth process is
performed to form a second polygonal nanowire 260 growing from the
recess 212;
[0059] step four: removing the second hard mask layer 250.
[0060] As shown in FIG. 6, after step one, on the substrate 210,
the top of the isolation structure 220 and the first nanowire 240,
a second patterned hard mask layer 250 is formed. A portion of the
hard mask layer 250 located in the NMOS active region 210b is
etched away to form a second through hole 250a. The substrate 210
is exposed at the bottom of the second through hole 250a.
[0061] As shown in FIG. 7, a recess 212 is formed by etching the
substrate 210 exposed at the bottom of through hole 250a.
Preferably, the cross-sectional shape of the recess 212 is
V-shaped. The etching solution to use in the etching process is
Tetra-Methyl-Ammonium-Hydroxide (TMAH) or KOH.
[0062] As shown in FIG. 8, after the execution of step three, in
the V-shaped recess 212 a second polygonal element nanowire 260 is
formed. The second nanowire 260 is in contact with substrate 210 of
the active region 210b of NMOS.
[0063] Thereafter, a second etching is performed to remove a
portion of the isolation structure 220 and the substrate 210 such
that the first nanowire 240 is suspended above said substrate 210.
The etching solution using in the etching process is
Tetra-Methyl-Ammonium-Hydroxide (TMAH).
[0064] As shown in FIG. 9, after the second etching, the first
nanowire 240 is suspended above the substrate 210, i.e., the first
nanowire 240 is not in contact with the substrate 210.
[0065] Thereafter, the first nanowire 240 is treated with oxidation
and annealing. The processes of oxidation and annealing of the
first nanowires 240 include:
[0066] step one: thermal oxidizing the first nanowire 240;
[0067] step two: removing the surface oxide layer of the first
nanowire 240 by a wet etching process;
[0068] step three: in a hydrogen environment, annealing the first
nanowire 240 at high temperature.
[0069] As shown in FIG. 10, during the oxidation and the annealing
treatment, germanium silicon is oxidation concentrated, so that the
first nanowire 240 formed is a germanium nanowire. The oxidation
and wet etching processes smooth the surface of germanium nanowire.
After oxidation and annealing treatment, the cross-sectional shape
of the polygonal first nanowire 240 (i.e., germanium nanowire)
becomes round, elliptical or prismatic.
[0070] Finally, sequentially forming on the substrate 210, the
first nanowire 240 and the second nanowire 260 the gate dielectric
layer 270 and the gate electrode layer 280.
[0071] As shown in FIG. 11, forming a gate dielectric layer 270 on
the substrate 210, isolation structure 220, the first nanowire 240
and the second nanowire 260. The gate dielectric layer 270 is
overlying the substrate 210, the isolation structure surface 220,
the first nanowires 240 and the second nanowire 260.
[0072] As shown in FIG. 12, a gate electrode layer 280 is formed on
the gate dielectric layer 270. The gate electrode layer 280
completely surrounds the first nanowire 240, and surrounding most
portion of the surface of the second nanowire 260.
[0073] The process of forming the gate dielectric layer 270 may be
an atomic layer deposition (ALD) process, metal organic chemical
vapor deposition (MOCVD) process, a chemical vapor deposition (CVD)
process or other existing technology. The process of forming the
gate electrode layer 280 may be an atomic layer deposition (ALD)
process, metal organic chemical vapor deposition (MOCVD) process,
molecular beam epitaxy (MBE) process or other existing
technology.
[0074] Thus, a nanowire semiconductor device 200 is formed. Said
semiconductor device 200 has a Ge nanowire formed in the active
region 210a of the PMOS, an InGaAs nanowire in the active region
210b of NMOS. The germanium (Ge) nanowire has high hole mobility,
and the indium gallium arsenide (InGaAs) nanowire has high electron
mobility. The performance of the so formed nanowire semiconductor
device 200 is significantly improved.
[0075] Nanowire formation is the key process in manufacturing
nanowire semiconductor devices and is directly related to the
performance of the nanowire semiconductor device. Existing process
of making germanium nanowires typically includes: first, forming a
nanowire having silicon nuclei; then followed by oxidation and
annealing treatment to centralize germanium to facilitate the
formation of a germanium nanowire. However, the kernel has much
higher silicon content, this increases the difficulty of making
nanowires with high germanium content. The performance of nanowire
semiconductor devices is adversely affected by the nanowire made
with low germanium content.
[0076] In this embodiment, the germanium nanowire is not formed
with a silicon core. The nanowire is formed directly by epitaxial
growth of germanium. The germanium nanowire is made following
subsequent oxidation and annealing treatment. The nanowire thus
formed has high Ge content.
[0077] Tests show that the first nanowire 240 of the nanowire
semiconductor device 200 has germanium content in the range of
between 65% to 100%, which is significantly higher than
conventional germanium content of germanium nanowires (typically
50% or less). Thus, using of the method of the present invention to
manufacture the nanowire semiconductor device effectively improves
the device performance.
[0078] Here another embodiment of the present invention of a
nanowire semiconductor device is provided. FIG. 12 is a schematic
diagram of the structure of a nanowire semiconductor device. The
nanowire semiconductor device comprising: a substrate 210, the
substrate 210, including active region 210a of PMOS and active
region 210b of NMOS; the first nanowire 240 is formed in the active
region 210a of PMOS and the second nanowire 260 is formed in the
active region 210b of NMOS; The gate dielectric layer 270 and gate
electrode layer completely surrounds the first nanowire 240 and
partially surrounds the second nanowire 260.
[0079] Specifically, the first nanowire 240 and the second
nanowires 260 are grown from the substrate 210 of the PMOS active
region 210a and the active region 210b of NMOS. The gate dielectric
layer 270 is formed on the substrate 210, on the first nanowire 240
and the second nanowire 260. The gate electrode layer 280 is formed
on the gate dielectric layer 270. The first nanowire 240 is
completely surrounded by the gate dielectric layer 270 and the gate
electrode layer 280. A portion of the second nanowire 260 in the
region above the isolation structure 220 is also surrounded by the
gate dielectric layer 270 and the gate electrode layer 280. Wherein
said gate dielectric layer 270 is a high-k dielectric layer. For
example, the material of the gate dielectric layer 270 is
Al.sub.2O.sub.3 or TiSiO.sub.x. Using high k material for gate
dielectric layer 270 improves the electrical properties of the
nanowire semiconductor device. The gate electrode layer 280 is a
metal electrode layer, the material of the gate electrode layer 280
is TiN, NiAu or one of CrAu.
[0080] The material of said first nanowire 240 and second nanowire
260 is group III-V semiconductor material. The Group III-V
semiconductor materials include silicon, silicon germanium,
germanium, or silicon carbide. Preferably, the material of the
first nanowire 240 is germanium (Ge), the material of the second
nanowire 260 is indium gallium arsenide (InGaAs).
[0081] The cross-sectional shape of the first nanowire 240 is
circular. The cross-sectional shape of the second nanowire 260 is
polygonal. Preferably, the polygonal second nanowire 260 has sides
equal to or greater than five.
[0082] Preferably, the length of the first nanowire 240 is in the
range of between 2 nm to 50 nm. The diameter of the first nanowire
240 is in the range of between 2 nm to 5 nm.
[0083] In summary, the present invention provides a method of
manufacturing nanowire semiconductor device. In the active region
of the PMOS the first nanowire is formed with high hole mobility
and in the active region of the NMOS the second nanowire is formed
with high electron mobility. This achieves the objective of
improving the performance of nanowire semiconductor device.
[0084] While the present invention has been described in an
illustrative manner, it should be understood that the terminology
used is intended to be in a nature of words of description rather
than of limitation. Many modifications and variations of the
present invention and other versions are possible in light of the
above teachings, and could be apparent for those skilled in the
art. The above described embodiments of the present invention do
not limit the present invention in any way. Any person skilled in
the art, without departing from the technical scope of the present
invention, can modify and vary technical solutions and technical
content of the disclosed present invention. The modifications and
variations still fall within the scope of the present
invention.
* * * * *