U.S. patent application number 15/267689 was filed with the patent office on 2017-08-17 for laminar phased array antenna.
The applicant listed for this patent is Anokiwave, Inc.. Invention is credited to Timothy Carey, David W. Corman, Nitin Jain, Vipul Jain.
Application Number | 20170237180 15/267689 |
Document ID | / |
Family ID | 58283158 |
Filed Date | 2017-08-17 |
United States Patent
Application |
20170237180 |
Kind Code |
A1 |
Corman; David W. ; et
al. |
August 17, 2017 |
Laminar Phased Array Antenna
Abstract
A phased array has a laminar substrate, a plurality of elements
on the front side of the substrate, and a plurality of integrated
circuits also on the front side of the substrate. This structure is
arranged to form a patch phased array. The plurality of integrated
circuits, which are configured to control receipt and/or
transmission of signals by the plurality of elements in the phased
array, preferably are wafer level chip scale packaging integrated
circuits. Moreover, the plurality of integrated circuits are
configured to operate at one or more satellite frequencies to have
the capability of transmitting signals and/or receiving signals
from a satellite.
Inventors: |
Corman; David W.; (Gilbert,
AZ) ; Jain; Vipul; (Irvine, CA) ; Carey;
Timothy; (San Diego, CA) ; Jain; Nitin; (San
Diego, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Anokiwave, Inc. |
San Diego |
CA |
US |
|
|
Family ID: |
58283158 |
Appl. No.: |
15/267689 |
Filed: |
September 16, 2016 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
62220522 |
Sep 18, 2015 |
|
|
|
Current U.S.
Class: |
343/824 |
Current CPC
Class: |
H04L 5/16 20130101; H01Q
3/38 20130101; H01Q 1/2283 20130101; H01Q 1/245 20130101; H01Q
21/24 20130101; H04L 5/1469 20130101; H01Q 3/26 20130101; H01Q
21/22 20130101; H01Q 21/065 20130101; H01Q 1/38 20130101 |
International
Class: |
H01Q 21/22 20060101
H01Q021/22; H04L 5/14 20060101 H04L005/14; H01Q 1/38 20060101
H01Q001/38; H01Q 1/24 20060101 H01Q001/24; H01Q 1/22 20060101
H01Q001/22; H01Q 3/38 20060101 H01Q003/38 |
Claims
1. A phased array comprising: a laminar substrate having a front
side; a plurality of elements on the front side of the laminar
substrate forming a patch phased array; a plurality of integrated
circuits on the front side of the laminar substrate, the plurality
of integrated circuits being wafer level chip scale packaging
integrated circuits, the plurality of integrated circuits
configured to control receipt and/or transmission of signals by the
plurality of elements in the patch phased array, the plurality of
integrated circuits configured to operate the phased array at one
or more satellite frequencies to transmit signals to and/or receive
signals from a satellite.
2. The phased array as defined by claim 1 wherein the plurality of
elements forms a triangular lattice.
3. The phased array as defined by claim 1 wherein each integrated
circuit is configured to control at least two elements.
4. The phased array as defined by claim 1 wherein each integrated
circuit includes a phase shifter to control the phase of signals
transmitted by at least one of the elements, the phase shifter
being a four bit or smaller phase shifter.
5. The phased array as defined by claim 1 wherein each integrated
circuit includes a splitter between a common arm and two side arms,
each of the integrated circuits having a side arm beam gain control
of no more than about 5 db.
6. The phased array as defined by claim 1 wherein each integrated
circuit is positioned between at least two elements.
7. The phased array as defined by claim 1 wherein each integrated
circuit is flip-chip bonded to the substrate, the integrated
circuit having a bottom side forming an open space with the
substrate.
8. The phased array as defined by claim 1 further comprising a
polarizer and a radome, the polarizer being between the substrate
and the radome.
9. The phased array as defined by claim 1 wherein each integrated
circuit includes an active phase shifter.
10. The phased array as defined by claim 1 wherein each integrated
circuit is configured to use time division duplex waveforms to
enable the phased array to be used for both transmission and
receipt of signals.
11. The phased array as defined by claim 1 wherein the plurality of
integrated circuits are configured to operate the phased array
using 5G protocols to transmit signals and/or receive signals.
12. A communication apparatus comprising: a printed circuit board
having a front side; a plurality of elements on the front side of
the printed circuit forming a patch phased array; a plurality of
integrated circuits on the front side of the printed circuit board,
the plurality of integrated circuits being wafer level chip scale
packaging integrated circuits, the plurality of integrated circuits
having means for controlling receipt and/or transmission of signals
by the plurality of elements in the patch phased array.
13. The communication apparatus as defined by claim 12 wherein each
integrated circuit is configured to control at least two
elements.
14. The communication apparatus as defined by claim 12 wherein each
integrated circuit includes a phase shifter to control the phase of
signals transmitted by at least one of the elements, the phase
shifter being a four bit or smaller phase shifter.
15. The communication apparatus as defined by claim 12 wherein each
integrated includes a splitter between a common arm and two side
arms, each of the integrated circuits having a side arm beam gain
control of no more than about 5 db.
16. The communication apparatus as defined by claim 12 further
comprising a polarizer and a radome, the polarizer being between
the printed circuit board and the radome.
17. The communication apparatus as defined by claim 12 wherein each
integrated is configured to use time division duplex waveforms to
enable the phased array to be used for both transmission and
receipt of signals.
18. The communication apparatus as defined by claim 12 wherein the
plurality of integrated circuits have means for operating the
phased array at one or more frequencies of the Ka-band, Ku-band,
and/or X-band to communicate with at least one satellite.
19. The communication apparatus as defined by claim 12 wherein the
plurality of integrated circuits are configured to operate the
plurality of elements using 5G protocols to transmit signals and/or
receive signals.
20. The communication apparatus as defined by claim 12 wherein the
plurality of elements forms a triangular lattice.
21. A method of producing a phased array, the method comprising:
forming a plurality of elements on a front side of a laminar
substrate to form a patch array; flip chip mounting a plurality of
integrated circuits to the front side of the laminar substrate, the
plurality of integrated circuits being wafer level chip scale
packaging integrated circuits, at least two of the plurality of
elements having at least one integrated circuit therebetween, the
plurality of integrated circuits configured to control receipt
and/or transmission of signals by the plurality of elements in the
patch phased array, the plurality of integrated circuits configured
to operate the phased array at one or more frequencies of the
Ka-band, Ku-band, and/or X-band to communicate with at least one
satellite, electrically connecting each of the plurality of
integrated circuits to at least two elements.
22. The method as defined by claim 21 further comprising securing a
polarizer and a radome to the patch array, the polarizer being
between the laminar substrate and the radome.
23. The method as defined by claim 21 wherein each integrated
circuit is configured to use time division duplex waveforms to
enable the phased array to be used for both transmission and
receipt of signals.
24. The method as defined by claim 21 wherein forming comprises
forming the plurality of elements in a triangular lattice on the
substrate.
25. The method as defined by claim 21 wherein each integrated
circuit is configured to control at least two elements.
26. The method as defined by claim 21 wherein each integrated
circuit includes a phase shifter to control the phase of signals
transmitted by at least one of the elements, the phase shifter
being a four bit or smaller phase shifter.
27. The method as defined by claim 21 wherein each integrated
circuit includes a splitter between a common arm and two side arms,
each of the integrated circuits having a side arm beam gain control
of no more than about 5 db.
Description
PRIORITY
[0001] This patent application claims priority from provisional
U.S. Patent Application No. 62/220,522, filed Sep. 18, 2015,
attorney docket number 4181/1002, entitled, "LAMINAR PHASED ARRAY
ANTENNA," and naming David Corman, Vipul Jain, Timothy Carey, and
Nitin Jain as inventors, the disclosure of which is incorporated
herein, in its entirety, by reference.
RELATED APPLICATIONS
[0002] This patent application is related to U.S. patent
application Ser. No. ______, filed on even date herewith, attorney
docket number 4181/1008, entitled, "LAMINAR PHASED ARRAY WITH
POLARIZATION-ISOLATED TRANSMIT/RECEIVE INTERFACES," and naming
David Corman, Vipul Jain, Timothy Carey, and Nitin Jain as
inventors, the disclosure of which is incorporated herein, in its
entirety, by reference.
FIELD OF THE INVENTION
[0003] The invention generally relates to phased array systems and,
more particularly, the invention relates to laminar phased
arrays/patch arrays.
BACKGROUND OF THE INVENTION
[0004] Antennas that emit electronically steered beams are known in
the art as "phased array antennas." Such antennas are used
worldwide in a wide variety of commercial and radar applications.
They typically are produced from many small radiating elements that
are individually phase controlled to form a beam in the far field
of the antenna.
[0005] Among other things, phased array antennas are popular due to
their ability to rapidly steer beams without requiring moving
parts. One problem, however, is their cost. They can cost on the
order of $1000 per element. Thus, for a 1000 element array, the
cost can reach or exceed $1,000,000.
SUMMARY OF VARIOUS EMBODIMENTS
[0006] In accordance with one embodiment of the invention, a phased
array has a laminar substrate, a plurality of elements on the front
side of the substrate, and a plurality of integrated circuits also
on the front side of the substrate. This structure is arranged to
form a patch phased array. The plurality of integrated circuits,
which are configured to control receipt and/or transmission of
signals by the plurality of elements in the phased array,
preferably are wafer level chip scale packaging integrated
circuits. Moreover, the plurality of integrated circuits are
configured to operate the phased array at one or more satellite
frequencies to have the capability of transmitting signals and/or
receiving signals from a satellite.
[0007] The plurality of elements may take on any of a variety of
forms, such as those of a triangular, rectangular, or hexagonal
lattice. To improve efficiency, each integrated circuit is
configured to control at least two elements (e.g., four elements or
more). For example, each integrated circuit may include a phase
shifter to control the phase of signals transmitted by at least one
of the elements. The phase shifter preferably is a four bit or
smaller phase shifter.
[0008] As another example, each integrated circuit may include a
splitter between a common arm and two side arms. In this case, each
of the integrated circuits may have a side arm beam gain control of
no more than about 5 db. Each integrated circuit may further
include an active phase shifter (e.g., using no passive elements),
and/or may be configured to use time division duplex waveforms to
enable the phased array to be used for both transmission and
receipt of signals.
[0009] Some of the integrated circuits, which may be flip-chip
bonded to the substrate, preferably are positioned on the substrate
between at least two elements. The flip-chip bonding also may
produce an open space between the bottom side of the integrated
circuit and the substrate (e.g., if no fill is included in that
space). To provide more structural protection and filter certain
frequencies, the phased array also may position a polarizer between
the substrate and a radome.
[0010] In accordance with another embodiment, an apparatus for
communicating with a satellite has a printed circuit board with a
front side supporting a plurality of elements and a plurality of
integrated circuits. These elements and integrated circuits form a
patch phased array. As such, the plurality of integrated circuits
have circuitry for controlling receipt and/or transmission of
signals by the plurality of elements in the patch phased array.
Moreover, the plurality of integrated circuits are wafer level chip
scale packaging integrated circuits. To communicate effectively
with at least one satellite, the plurality of integrated circuits
have circuitry for operating the phased array at one or more
frequencies of the Ka-band, Ku-band, and/or X-band.
[0011] In accordance with other embodiments, a method of producing
a phased array forms a plurality of elements on a front side of a
laminar substrate to form a patch array. The method also flip chip
mounts a plurality of wafer level chip scale packaged integrated
circuits to the front side of the laminar substrate. At least two
of the plurality of elements have at least one integrated circuit
therebetween. The plurality of integrated circuits are configured
to control receipt and/or transmission of signals by the plurality
of elements in the patch phased array. In addition, the plurality
of integrated circuits also are configured operate the phased array
at one or more frequencies of the Ka-band, Ku-band, and/or X-band
to communicate with at least one satellite. The method electrically
connects each of the plurality of integrated circuits to at least
two elements.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Those skilled in the art should more fully appreciate
advantages of various embodiments of the invention from the
following "Description of Illustrative Embodiments," discussed with
reference to the drawings summarized immediately below.
[0013] FIG. 1 schematically shows an active electronically steered
antenna system ("AESA system") configured in accordance with
illustrative embodiments of the invention and communicating with a
satellite.
[0014] FIGS. 2A and 2B schematically show generalized diagrams of
an AESA system that may be configured in accordance with
illustrative embodiments of the invention.
[0015] FIG. 3A schematically shows a plan view of a laminar printed
circuit board portion of an AESA configured in accordance with
illustrative embodiments of the invention.
[0016] FIG. 3B schematically shows a close-up of a portion of the
laminated printed circuit board of FIG. 3A.
[0017] FIG. 4 schematically shows a cross-sectional view of the
laminated printed circuit board of 3A to highlight the mounting of
its integrated circuits.
[0018] FIG. 5 schematically shows a circuit diagram of a portion of
an integrated circuit mounted on the laminated printed circuit
board of FIG. 3A.
[0019] FIG. 6 shows a process of forming an AESA system in
accordance with illustrative embodiments of the invention.
DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0020] Illustrative embodiments form a low cost phased array with a
high sensitivity to received signals. In addition, the phased array
also efficiently transmits outgoing signals/beams to other
communication devices at the required power levels. To that end,
the phased array preferably has a laminar substrate with a front
face supporting both 1) an array of antennas (also referred to as
"elements" or "patches"), and 2) a corresponding array of wafer
level chip scale packaged ("WLCSP") integrated circuits. In
addition to controlling the antennas, the WLCSP integrated circuits
are configured to operate the phased array at one or more satellite
frequencies, thus enabling communication with orbiting satellites.
Details of illustrative embodiments are discussed below.
[0021] FIG. 1 schematically shows an active electronically steered
antenna system ("AESA system 10") configured in accordance with
illustrative embodiments of the invention and communicating with an
orbiting satellite 12. A phased array (discussed below and
identified by reference number "10A") implements the primary
functionality of the AESA system 10. Specifically, as known by
those skilled in the art, the phased array 10A forms one or more of
a plurality of electronically steerable beams that can be used for
a wide variety of applications. As a satellite communication
system, for example, the AESA system 10 preferably is configured
operate at one or more satellite frequencies. Among others, those
frequencies may include the Ka-band, Ku-band, and/or X-band.
[0022] The satellite communication system may be part of a cellular
network operating under a known cellular protocol, such as the 3G,
4G, or 5G protocols. Accordingly, in addition to communicating with
satellites, the system may communicate with earth-bound devices,
such as smartphones or other mobile devices, using any of the 3G,
4G, or 5G protocols. As another example, the satellite
communication system may transmit/receive information between
aircraft and air traffic control systems. Of course, those skilled
in the art may use the AESA system 10 (implementing the noted
phased array 10A) in a wide variety of other applications, such as
broadcasting, optics, radar, etc. Some embodiments may be
configured for non-satellite communications and instead communicate
with other devices, such as smartphones (e.g., using 4G or 5G
protocols). Accordingly, discussion of communication with orbiting
satellites 12 is not intended to limit all embodiments of the
invention.
[0023] FIGS. 2A and 2B schematically show generalized diagrams of
the AESA system 10 configured in accordance with illustrative
embodiments of the invention. Specifically, FIG. 2A schematically
shows a block diagram of the AESA system 10, while FIG. 2B
schematically shows a cross-sectional view of a small portion of
the same AESA system 10 across line B-B. This latter view shows a
single silicon integrated circuit 14 (controlling elements 18,
discussed below) mounted onto a substrate 16 between two transmit
and/or receive elements 18, i.e., on the same side of a supporting
substrate 16 and juxtaposed with the two elements 18. In
alternative embodiments, however, the integrated circuit 14 could
be on the other side of the substrate 16. The phased array 10A also
has a polarizer 20 to selectively filter signals to and from the
phased array 10A, and a radome 22 to environmentally protect the
phased array 10A. A separate antenna controller 24 (FIG. 2B)
electrically connects with the phased array 10A to calculate beam
steering vectors for the overall phased array 10A, and to provide
other control functions.
[0024] FIG. 3A schematically shows a plan view of a primary portion
of an AESA system 10 that may be configured in accordance with
illustrative embodiments of the invention. In a similar manner,
FIG. 3B schematically shows a close-up of a portion of the phased
array 10A of FIG. 3A.
[0025] Specifically, the AESA system 10 of FIG. 3A is implemented
as a laminar phased array 10A having a laminated printed circuit
board 16 (i.e., acting as the substrate and also identified by
reference number "16") supporting the above noted plurality of
elements 18 and integrated circuits 14. The elements 18 preferably
are formed as a plurality of square or rectangular patch antennas
oriented in a triangular patch array configuration. In other words,
each element 18 forms a triangle with two other adjacent elements
18. When compared to a rectangular lattice configuration, this
triangular lattice configuration requires fewer elements 18 (e.g.,
about 15 percent fewer in some implementations) for a given grating
lobe free scan volume. Other embodiments, however, may use other
lattice configurations, such as a pentagonal configuration or a
hexagonal configuration. Moreover, despite requiring more elements
18, some embodiments may use a rectangular lattice configuration.
Like other similar phased arrays, the printed circuit board 16 also
may have a ground plane (not shown) that electrically and
magnetically cooperates with the elements 18 to facilitate
operation.
[0026] Indeed, the array shown in FIGS. 3A and 3B is a small phased
array 10A. Those skilled in the art can apply principles of
illustrative embodiments to laminar phased arrays 10A with
hundreds, or even thousands of elements 18 and integrated circuits
14. In a similar manner, those skilled in the art can apply various
embodiments to smaller phased arrays 10A.
[0027] As a patch array, the elements 18 have a low profile.
Specifically, as known by those skilled in the art, a patch antenna
(i.e., the element 18) typically is mounted on a flat surface and
includes a flat rectangular sheet of metal (known as the patch and
noted above) mounted over a larger sheet of metal known as a
"ground plane." A dielectric layer between the two metal regions
electrically isolates the two sheets to prevent direct conduction.
When energized, the patch and ground plane together produce a
radiating electric field. As discussed below with regard to FIG. 6,
illustrative embodiments may form the patch antennas using
conventional semiconductor fabrication processes, such as by
depositing one or more successive metal layers on the printed
circuit board 16. Accordingly, using such fabrication processes,
each radiating element 18 in the phased array 10A should have a
very low profile.
[0028] The AESA system 10 can have one or more of any of a variety
of different functional types of elements 18. For example, the AESA
system 10 can have transmit-only elements 18, receive-only elements
18, and/or dual mode receive and transmit elements 18 (referred to
as "dual-mode elements 18"). The transmit-only elements 18 are
configured to transmit outgoing signals (e.g., burst signals) only,
while the receive-only elements 18 are configured to receive
incoming signals only. In contrast, the dual-mode elements 18 are
configured to either transmit outgoing burst signals, or receive
incoming signals, depending on the mode of the phased array 10A at
the time of the operation. Specifically, when using dual-mode
elements 18, the phased array 10A can be in either a transmit mode,
or a receive mode. The noted controller 24 at least in part
controls the mode and operation of the phased array 10A, as well as
other array functions.
[0029] The AESA system 10 has a plurality of the above noted
integrated circuits 14 (noted with regard to FIG. 2B) for
controlling operation of the elements 18. Those skilled in the art
often refer to these integrated circuits 14 as "beam steering
integrated circuits." Prior art beam steering integrated circuits
known to the inventors took up a lot of real estate on the printed
circuit board 16. This is contrary to one general goal of
maximizing the surface area of the elements 18 on the front face of
the substrate 16. To solve this problem, those in the art relegated
prior art integrated circuits known to the inventors to the
opposite side of the circuit board 16--i.e., the side opposite the
elements 18. While it may have helped maximize/optimize element
area, it caused certain noise issues due to the relatively long
transmission line to the elements 18. The inventors recognized both
of these problems and, consequently, modified the phased array 10A,
including the integrated circuits 14, to enable them to be mounted
on the same side as the elements 18; namely, on the front side of
the printed circuit board 16.
[0030] To that end, each integrated circuit 14 preferably is
configured with at least the minimum number of functions to
accomplish the desired effect. Indeed, integrated circuits 14 for
dual mode elements 18 are expected to have some different
functionality than that of the integrated circuits 14 for the
transmit-only elements 18 or receive-only elements 18. Accordingly,
integrated circuits 14 for such non-dual-mode elements 18 typically
have a smaller footprint than the integrated circuits 14 that
control the dual-mode elements 18. Despite that, some or all types
of integrated circuits 14 fabricated for the phased array 10A can
be modified to have a smaller footprint.
[0031] As an example, depending on its role in the phased array
10A, each integrated circuit 14 may include some or all of the
following functions: [0032] phase shifting, [0033] amplitude
controlling/beam weighting, [0034] switching between transmit mode
and receive mode, [0035] output amplification to amplify output
signals to the elements 18, [0036] input amplification for received
RF signals (e.g., signals received from the satellite 12), and
[0037] power combining/summing and splitting between elements
18.
[0038] Indeed, some embodiments of the integrated circuits 14 may
have additional or different functionality, although illustrative
embodiments are expected to operate satisfactorily with the above
noted functions. Those skilled in the art can configure the
integrated circuits 14 in any of a wide variety of manners to
perform those functions. For example, the input amplification may
be performed by a low noise amplifier, the phase shifting may use
conventional active phase shifters, and the switching functionality
may be implemented using conventional transistor-based switches.
Additional details of the structure and functionality of integrated
circuits 14 are discussed below with reference to FIG. 5.
[0039] As noted above, the AESA system 10 preferably communicates
with one or more orbiting satellites 12 and thus, uses satellite
frequencies for that communication. Accordingly, the plurality of
integrated circuits 14 preferably are configured operate the phased
array 10A at one or more frequencies of the Ka-band, Ku-band,
and/or X-band to communicate with at least one satellite 12. Of
course, as satellite communication technology progresses, future
implementations may modify the frequency bands of the integrated
circuits 14 to communicate using new satellite frequencies.
[0040] The inventors recognized that the cost of the phased array
10A is directly related to the number of elements 18 and integrated
circuits 14. Moreover, the number of integrated circuits 14 also
has a direct relation to the size of the printed circuit board 16.
In fact, the total number of integrated circuits 14 used and the
size of the printed circuit board 16 accounts for a substantial
majority of the total array costs. The inventors thus designed the
array so that multiple elements 18 share the integrated circuits
14, thus reducing the required total number of integrated circuits
14. This reduced number of integrated circuits 14 correspondingly
reduces the required size of the printed circuit board 16, which
reduces the cost of the AESA system 10. In addition, more surface
area on the top face of the printed circuit board 16 may be
dedicated to the elements 18.
[0041] To that end, each integrated circuit 14 preferably operates
on at least one element 18 in the array. For example, one
integrated circuit 14 can operate on two or four different elements
18. Of course, those skilled in the art can adjust the number of
elements 18 sharing an integrated circuit 14 based upon the
application. For example, a single integrated circuit 14 can
control two elements 18, three elements 18, five elements 18, six
elements 18, seven elements 18, eight elements 18, etc., or some
range of elements 18. Sharing the integrated circuits 14 between
multiple elements 18 in this manner reduces the required total
number of integrated circuits 14, correspondingly reducing the
required size of the printed circuit board 16.
[0042] As noted above, the dual-mode elements 18 may operate in a
transmit mode, or a receive mode. To that end, the integrated
circuits 14 may generate time division diplex or duplex waveforms
so that a single aperture or phased array 10A can be used for both
transmitting and receiving. In a similar manner, some embodiments
may eliminate a commonly included transmit/receive switch in the
side arms (discussed below with regard to FIG. 5) of the integrated
circuit 14. Instead, such embodiments may duplex at the element 18.
This process can be performed by isolating one of the elements 18
between transmit and receive by an orthogonal feed connection. The
inventors discovered that such a feed connection may eliminate
about a 0.8 dB switch loss and improve G/T (i.e., the ratio of the
gain or directivity to the noise temperature) by about 1.3 dB for
some implementations. Additional details of the orthogonal feed
connection are discussed below with regard to FIG. 5.
[0043] RF interconnect and/or beam forming lines 26 electrically
connect the integrated circuits 14 to their respective elements 18.
To further minimize the feed loss, illustrative embodiments mount
the integrated circuits 14 as close to their respective elements 18
as possible. Specifically, this close proximity preferably reduces
RF interconnect line lengths, reducing the feed loss. To that end,
each integrated circuit 14 preferably is packaged either in a
flip-chipped configuration using wafer level chip scale packaging
(WLCSP), or a traditional package, such as quad flat no-leads
package (QFN package). While other types of packaging may suffice,
WLCSP techniques are preferred to minimize real estate on the
substrate 16.
[0044] In addition to reducing feed loss, using WLCSP techniques
reduces the overall footprint of the integrated circuits 14,
enabling them to be mounted on the top face of the printed circuit
board 16 with the elements 18--providing more surface area for the
elements 18. The inventors thus discovered that using WLCSP
techniques, coupled with other innovations discussed herein, and
able the system to operate within acceptable operation
specifications.
[0045] It should be reiterated that although FIGS. 3A and 3B show
the AESA system 10 with some specificity (e.g., the layout of the
elements 18 and integrated circuits 14), those skilled in the art
may apply illustrative embodiments to other implementations. For
example, as noted above, each integrated circuit 14 can connect to
more or fewer elements 18, or the lattice configuration can be
different. Accordingly, discussion of the specific configuration of
the AESA system 10 of FIG. 3A (and other figures) is for
convenience only and not intended to limit all embodiments.
[0046] FIG. 4 schematically shows a cross-sectional view of the
layout of components on the laminated printed circuit board 16 of
3A to highlight the flip-chip mounting of its integrated circuits
14. The integrated circuit 14 in this drawing intentionally is
enlarged to show details of a flip-chip mounting technique. Unlike
techniques that permit input/output ("I/O") only on the edge of the
integrated circuit 14, flip-chip mounting permits I/O on interior
portions of the integrated circuit 14.
[0047] As shown, the integrated circuit 14 has a plurality of pads
28 aligned with a plurality of corresponding pads 28 on the printed
circuit board 16. These opposing pads 28 on the integrated circuit
14 and the printed circuit board 16 may be considered to form pairs
of pads 28. Solder 30 (e.g., solder balls) electrically connects
each the pads in corresponding pairs of pads 28. Interconnect
lines, traces, and other electrical interconnects on/in the printed
circuit board 16 (e.g., lines 26) thus permit the integrated
circuit 14 to communicate with other elements 18 through this
electrical interface.
[0048] The embodiment shown in FIG. 4 forms a space or void
(identified by reference number "32") between the bottom of the
integrated circuit 14 (from the perspective of this drawing) and
the top surface of the printed circuit board 16. This space 32 may
remain an open void--containing no material. Some embodiments may
take advantage of this extra space 32 to add further components,
such as additional circuit elements, without requiring more circuit
board space. Alternatively, this space 32 may contain fill material
(not shown) for further stability and thermal management of the
integrated circuit 14.
[0049] Other embodiments, however, still may use similar integrated
circuits 14, but not use flip-chip mounting techniques. Instead,
other mounting techniques may couple the integrated circuits 14
with the substrate 16. Among other things, those techniques may
incorporate surface mounting, or wirebond mounting with the
integrated circuit 14 rotated 180 degrees from the orientation of
FIG. 4. Accordingly, discussion of flip chip mounting techniques is
but one of a variety of different techniques that may be used with
various embodiments of the invention.
[0050] As noted above, each integrated circuit 14 preferably has a
minimal amount of circuitry to perform its required function. To
that end, FIG. 5 schematically shows relevant portions of one
integrated circuit 14 that may be configured in accordance with
illustrative embodiments of the invention to control two elements
18. This exemplary integrated circuit 14 is shown and described as
connected to two different elements 18 identified as element E1 and
element E2. Of course, principles described with regard to FIG. 5
can apply equally to integrated circuits 14 controlling more than
two elements 18, such as four elements 18.
[0051] As shown, the integrated circuit 14 has a first vector
modulator 34 for controlling receipt and transmission of signals of
a first element E1, and a second vector modulator 34 for
controlling receipt and transmission of signals of a second element
E2. The two vector modulators 34 each have a receive arm 36,
coupled to their respective elements 18, for receiving signals. In
FIG. 5, because they transmit signals away from their elements E1
or E2, the receive arms 36 have arrows pointing away from their
respective elements E1 and E2. To that end, each receive arm 36 has
a phase shift modulator 38 (also referred to as a "phase shifter
38") for changing the phase of the incoming signals, and an
amplifier 40 for amplifying the incoming signal. Among other
things, the amplifiers 40 in the receive arms 36 are implemented as
low noise amplifiers.
[0052] In illustrative embodiments, the amplifier 40 is a fixed
gain amplifier. Accordingly, to control the amplification with more
precision, each receive arm 36 also has an active gain controller
42 that increases or decreases the amplification provided by the
amplifier 40. Alternatively, the amplifier 40 may be a variable
gain amplifier. Accordingly, in that case, the active gain
controller 42 may be omitted. As known by those skilled in the art,
the amplifier(s) 40 and the phase shifter 38 cooperate to control
incoming received signals.
[0053] In a corresponding manner, the two vector modulators 34 also
each have a transmit arm 44 coupled to their respective elements
18. In an opposite manner to the receive arms 36, the transmit arms
44 in FIG. 5 have arrows pointing toward their respective elements
18. Each transmit arm 44 thus has a phase shifter 38 for changing
the phase of the incoming signals, and an amplifier 40 for
amplifying the incoming signal. The transmit arms 44 also may have
an active gain controllers 42 if the transmit amplifiers 40 have a
fixed gain. Alternatively, the transmit arms 44 may omit the active
gain controllers 42 if the amplifier 40 is a variable gain
amplifier. As known by those skilled in the art, the amplifier(s)
40 and the phase shifter 38 cooperate to steerably beam outgoing
signals to other devices, such as to the satellite 12 of FIG.
1.
[0054] As noted above, the inventors recognized that reducing the
overall footprint of the integrated circuit 14 should improve
overall performance. To that end, the inventors discovered that if
they provided a sufficient number of elements 18 in the AESA system
10, they could reduce the sizes of the phase shifters 38. For
example, after testing, the inventors discovered that use of a 4
bit phase shifter 38 would provide sufficient results with a
sufficient number of elements 18. The 4 bit phase shifter 38 thus
provides up to 16 different vectors for transmitting a beam from a
given element. In illustrative embodiments, each of the 16
different vectors is substantially evenly partitioned between zero
and 360 degrees (e.g., 0 degrees, 22.4 degrees, 45 degrees, etc.).
Other embodiments, however, may use smaller phase shifters 38
(e.g., 3 bit phase shifters 38) or larger phase shifters 38 (e.g.,
5 or 6 bit phase shifters 38). Again, this number should be
coordinated with the number of elements 18, as well as the gain of
the amplifiers 40.
[0055] The inventors further discovered that the receive and
transmit arms 36 and 44 of the vector modulators 34 could use
relatively low gain amplifiers 40 if they appropriately selected of
other element parameters. For example, the amplifiers 40 may have
active gain control from 1 dB up to 3 dB, 4 dB, 5 dB, or greater
(e.g., 6 dB). Again, low gain amplifiers 40 used in this
application should further reduce the size of the integrated
circuit 14.
[0056] The receive arms 36 and the transmit arms 44 may be
considered to be "side arms" that combine and/or distribute signals
at a summation point (also referred to as a "splitter" when
splitting signals). Specifically, the two receive arms 36 meet at a
receiving summing node 46A that combines the received signals from
both the first and second elements 18. In a corresponding manner,
the two transmit arms 44 also meet at a transmitting summing node
46B that, in an opposite manner to that of the receiving summing
node 46A, distributes the transmit signals of the first and second
elements 18 for transmission. Among other things, the summing nodes
46 may be implemented as a compact Wilkinson power divider/summer,
which, as its name suggests, distributes/divides and/or sums
signals. Indeed, the summing nodes 46 may be implemented by other
active components and thus, a Wilkinson power divider/summer is but
one example.
[0057] In addition to connecting with the side arms, each summing
node 46A also connects with a main arm (aka "common arm") that
itself may have an amplifier and/or active gain controller (not
shown). In illustrative embodiments, the gain of the amplifier in
the main arm is greater than those in the side arms. The main arm
also has a switch 48 that switches between the transmit mode to the
receive mode.
[0058] Illustrative embodiments preferably do not have switches on
the side arms. To that end, the transmit and receive sides of each
vector modulator 34 preferably are physically coupled with adjacent
sides of its element 18. Specifically, if the elements 18 are sized
so that they are about half a wavelength from side-to-side, then
opposite sides will be about 180 degree out of phase with each
other. Adjacent sides, however, are about 90 degrees out of phase
with each other. In this manner, the transmit arms 44 may be
considered to be polarized a first way (e.g., "vertically
polarized"), while the receive arms 36 may be considered to be
polarized a second, orthogonal way (e.g., "horizontally
polarized").
[0059] Accordingly, the receive arms 36 in FIG. 5 connect with a
top portion of their respective elements 18, while the transmit
arms 44 of FIG. 5 connect with a side (orthogonal) portion of their
respective elements 18. Indeed, other embodiments may polarize the
transmit and receive arms 36 differently. As such, the specific
polarization discussed above is but one example and not intended to
limit various embodiments.
[0060] When coupled as shown, illustrative embodiments avoid the
need for a switch on the side arms by using a duplexing/diplexing
signal for transmit and receive (noted above). For example,
illustrative embodiments may use time division diplex waveforms or
frequency division diplex waveforms to both transmit and receive
signals. In that case, to permit asymmetric transmit and receive
data transmission, the transmit and receive signals may be
allocated to different time slots in the same frequency band. For
example, one or more of the elements 18 may couple with a frequency
diplexer (not shown) that splits its relevant signal into a first
frequency signal and a second frequency signal. Each of the
generated frequency signals is then routed to its own independent
circuit that either receives or transmits to or from the element
18.
[0061] The duplex/diplex waveforms may be generated in a number of
different ways. In some embodiments, the integrated circuits 14 are
configured to produce those waveforms. In other embodiments, one or
more diplexers or duplexers on the substrate 16 at least in part
produce those waveforms. FIG. 3B schematically shows one such
diplexer or duplexer, identified by reference number 27. This
diplexer/duplexer 27 communicates with other components, such as
the integrated circuits 14, using the transmission lines (e.g.,
traces, vias, lines, etc.) on the substrate 16.
[0062] During operation, the switch 48 in the main arm may be in
the transmit mode. Accordingly, the main arm receives a transmit
signal through the switch. Next, that signal is distributed to the
two transmit arms 44 through the transmitting summing node 46B. In
this capacity, the transmitting summing node 46B acts like a
distribution node as it distributes the signal to be transmitted to
each side arm. Next, each side arm in the respective vector
modulators 34 then shift and amplify its received signal as needed,
and transmit that conditioned signal through its respective element
18 to the orbiting satellite 12.
[0063] After the transmission process is completed, the switch 48
on the main arm may be actuated to the receive mode. Accordingly,
each receive arm 36 shifts and amplifies the signal received by its
respective element E1 or E2. The receiving summing node 46A then
sums or combines these two conditioned signals to produce a
combined signal that is forwarded to other components through the
switch 48 in the main arm.
[0064] Of course, it should be noted that the specific
configuration of elements 18 in FIG. 5 is but one of a wide variety
of different configuration to accomplish the desired effect.
Accordingly, when implementing various embodiments, those skilled
in the art can add other components, remove components, or
rearrange the noted components. The specific configuration of FIG.
5 therefore is intended to be illustrative and not intended to
limit various embodiments the invention.
[0065] FIG. 6 shows a process of forming the phased array 10A/AESA
system 10 in accordance with illustrative embodiments of the
invention. It should be noted that this process is substantially
simplified from a longer process that normally would be used to
form the AESA system 10. Accordingly, the process of forming the
AESA system 10 is expected to have many steps, such as testing
steps, soldering steps, or passivation steps, which those skilled
in the art may use. In addition, some of the steps may be performed
in a different order than that shown, or at the same time. Those
skilled in the art therefore can modify the process as appropriate.
Moreover, as noted above and below, the discussed materials and
structures are merely examples. Those skilled in the art can select
the appropriate materials and structures depending upon the
application and other constraints. Accordingly, discussion of
specific materials and structures is not intended to limit all
embodiments.
[0066] The process of FIG. 6 begins at step 600, which forms the
array of elements 18 on the substrate 16/printed circuit board 16.
As noted above, the elements 18 preferably are formed from metal
deposited onto the substrate 16 in a triangular lattice. This step
also may form pads 28 and lines 26 on the printed circuit board 16
to extend to the elements 18 (from the pads 28). As discussed
below, these lines 26 electrically connect the integrated circuits
14 with the elements 18.
[0067] In preferred embodiments, the elements 18 are spaced apart
from each other as a function of the wavelength of the signals
expected to be transmitted and received by the AESA system 10. For
example, the distances between the elements 18 may be spaced apart
a distance equal to between 40-60 percent of the wavelength of the
relevant signals. Some embodiments, however, may vary the spacing
of the elements 18. See, for example, co-pending provisional U.S.
Patent Application No. 62/376,442, filed on Aug. 18, 2016 and
entitled, "Hybrid Laminated Phased Array," for further spacing and
other details of similar embodiments. The disclosure of that
provisional patent application (U.S. Patent application Ser. No.
62/376,442) is incorporated herein, in its entirety, by
reference.
[0068] Those skilled in the art can select the appropriate numbers
of elements 18, based upon the application. Specifically, a given
application may require a specified minimum equivalent
isotropically radiated power ("EIRP") for transmitting signals. In
addition, that same application may have a specified minimum G/T
for receiving signals. Thus, step 600 may form the array to have a
minimum number of elements 18 to meet either or both the EIRP and
the G/T requirements of the application. For example, after
establishing the feed loss and the noise figure of the receive
amplifier 40 of the vector receive arms 36, one in the art can set
the array size to a desired G/T. Of course, the phased array 10A
may have more elements 18 beyond that minimum number.
[0069] Other embodiments may use other requirements for selecting
the appropriate number of elements 18. Accordingly, discussion of
the specific means for selecting the appropriate number of elements
18, and their spacing, is for descriptive purposes only and not
intended to limit various embodiments of the invention.
[0070] At step 602, the process mounts the integrated circuits 14
to the printed circuit board 16/substrate 16. To that end, as noted
above, when using WLCSP integrated circuits 14, illustrative
embodiments may use conventional flip-chip mounting processes. Such
a process directly electrically connects the integrated circuits 14
to the elements 18 (step 604). To that end, such embodiments may
deposit solder paste (e.g., powdered solder and flux) on the pads
28 of the printed circuit board 16, and position the integrated
circuits 14 on their respective board pads 28. Then, the printed
circuit board 16 may be heated (e.g., using a reflow oven or
process) to physically and electrically couple the pads 28 with the
solder 30.
[0071] Some embodiments that do not use flip-chip mounted WLCSP
integrated circuits 14, however, may require the additional step of
step 604 to electrically connect the integrated circuits 14 to the
elements 18. For example, a wirebond operation may be required to
solder wirebonds between the integrated circuits 14 and the
elements 18.
[0072] The process concludes by adding the polarizer 20 (step 606)
and securing the radome 22 (step 608) to the apparatus in a
conventional manner.
[0073] Accordingly, contrary to the conventional wisdom, the
inventors recognized that despite the possibility of reducing the
element area, which is generally undesirable, they could mount
WLCSP integrated circuits 14 to the front side of the printed
circuit board 16 to produce more cost efficient satellite
communication AESA system 10. Moreover, as noted, the AESA system
10 can have improved G/T and/or EIRP values despite the tradeoff
incurred by the loss of element area.
[0074] Although the above discussion discloses various exemplary
embodiments of the invention, it should be apparent that those
skilled in the art can make various modifications that will achieve
some of the advantages of the invention without departing from the
true scope of the invention.
* * * * *