U.S. patent application number 15/486888 was filed with the patent office on 2017-08-03 for trench having thick dielectric selectively on bottom portion.
The applicant listed for this patent is Texas Instruments Incorporated. Invention is credited to HIDEAKI KAWAHARA, CHRISTOPHER BOGUSLAW KOCON, YUNLONG LIU, YUFEI XIONG, HONG YANG.
Application Number | 20170222041 15/486888 |
Document ID | / |
Family ID | 55962346 |
Filed Date | 2017-08-03 |
United States Patent
Application |
20170222041 |
Kind Code |
A1 |
KAWAHARA; HIDEAKI ; et
al. |
August 3, 2017 |
TRENCH HAVING THICK DIELECTRIC SELECTIVELY ON BOTTOM PORTION
Abstract
A method of fabricating a semiconductor device includes etching
a semiconductor substrate having a top surface to form a trench
having sidewalls and a bottom surface that extends from the top
surface into the semiconductor substrate. A dielectric liner of a
first dielectric material is formed on the bottom surface and
sidewalls of the trench to line the trench. A second dielectric
layer of a second dielectric material is deposited to at least
partially fill the trench. The second dielectric layer is partially
etched to selectively remove the second dielectric layer from an
upper portion of the trench while preserving the second dielectric
layer on a lower portion of the trench. The trench is filled with a
fill material which provides an electrical conductivity that is at
least that of a semiconductor.
Inventors: |
KAWAHARA; HIDEAKI; (PLANO,
TX) ; YANG; HONG; (RICHARDSON, TX) ; KOCON;
CHRISTOPHER BOGUSLAW; (MOUNTAIN TOP, PA) ; XIONG;
YUFEI; (CHENGDU, CN) ; LIU; YUNLONG; (CHENGDU,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Texas Instruments Incorporated |
Dallas |
TX |
US |
|
|
Family ID: |
55962346 |
Appl. No.: |
15/486888 |
Filed: |
April 13, 2017 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14548029 |
Nov 19, 2014 |
9653342 |
|
|
15486888 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/28008 20130101;
H01L 28/60 20130101; H01L 21/823487 20130101; H01L 29/4236
20130101; H01L 29/4916 20130101; H01L 21/30604 20130101; H01L
21/76224 20130101; H01L 21/823481 20130101; H01L 29/41766 20130101;
H01L 29/7802 20130101; H01L 29/66734 20130101; H01L 21/765
20130101; H01L 29/1095 20130101; H01L 29/7813 20130101; H01L 29/945
20130101; H01L 29/0649 20130101; H01L 29/42368 20130101; H01L
29/407 20130101; H01L 27/088 20130101; H01L 29/66727 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 21/28 20060101 H01L021/28; H01L 29/40 20060101
H01L029/40; H01L 49/02 20060101 H01L049/02; H01L 21/306 20060101
H01L021/306; H01L 21/8234 20060101 H01L021/8234; H01L 29/06
20060101 H01L029/06; H01L 29/423 20060101 H01L029/423; H01L 29/49
20060101 H01L029/49; H01L 29/10 20060101 H01L029/10; H01L 21/762
20060101 H01L021/762; H01L 27/088 20060101 H01L027/088 |
Claims
1. A semiconductor device, comprising: a semiconductor substrate
having at least one trench including sidewalls and a bottom surface
that extends from a top surface of said semiconductor substrate
into said semiconductor substrate; a dielectric liner comprising a
first dielectric material on said bottom surface and said sidewalls
of said trench to line said trench; a second dielectric layer
comprising a second dielectric material on a lower portion of said
trench but not on a top portion of said trench, and a fill material
filling said trench that provides an electrical conductivity that
is at least that of a semiconductor.
2. The semiconductor device of claim 1, wherein said trench is a
trench isolation structure for said semiconductor device.
3. The semiconductor device of claim 1, wherein said trench is a
trench capacitor for said semiconductor device.
4. The semiconductor device of claim 1, wherein said semiconductor
substrate is a first doping type having a body region of a second
doping type formed in said semiconductor substrate, and wherein
said trench is associated with a metal-oxide-semiconductor
field-effect transistor (MOSFET) transistor that utilizes said body
region.
5. The semiconductor device of claim 4, wherein said MOSFET
transistor is a planar MOSFET transistor and said trench is a field
plate associated with said planar MOSFET transistor.
6. The semiconductor device of claim 4, wherein said MOSFET
transistor is a trench gate MOSFET transistor and wherein said
trench is a trench gate for said trench gate MOSFET transistor.
7. The semiconductor device of claim 1, wherein said fill material
comprises polysilicon.
8. The semiconductor device of claim 1, wherein said semiconductor
substrate comprises an epitaxial layer on a bulk substrate
material, and wherein said trench extends into said bulk substrate
material.
9. The semiconductor device of claim 1, wherein said second
dielectric material has a k-value.gtoreq.5.
10. A semiconductor device, comprising: a semiconductor substrate
having at least one trench including sidewalls and a bottom
surface; a dielectric liner comprising a first dielectric material
on said bottom surface and said sidewalls of said trench to line
said trench; a silicon nitride layer on the dielectric liner in a
lower portion of the trench but not on a top portion of the trench,
and a conductive material filling said trench, wherein the
conductive material is directly on the silicon nitride layer at the
bottom of the trench and wherein the dielectric liner separates the
conductive material from the sidewalls of the trench including the
top portion of the trench.
11. The semiconductor device of claim 10, wherein said
semiconductor substrate comprises an epitaxial layer on a bulk
substrate material, and wherein said trench extends into said bulk
substrate material.
12. The semiconductor device of claim 10, wherein said conductive
material comprises polysilicon.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application
Ser. No. 14/548,029, filed Nov. 19, 2014, the contents of which is
herein incorporated by reference in its entirety.
FIELD
[0002] Disclosed embodiments relate to filled dielectrically lined
trench structures for semiconductor devices.
BACKGROUND
[0003] Some trench structures include a dielectric liner filled
with a doped semiconductor or an electrical conductor. For certain
uses, the dielectric liner needs to support significant electrical
field strengths, for example, when trenches are used for trench
field type metal-oxide-semiconductor field-effect transistors
(MOSFETs) or trench gate type MOSFETs which both operate at
significant operating voltages. One way to sustain higher breakdown
voltages for such trench structures is to increase the thickness
the dielectric liner or use a relatively high refractive index
liner material.
SUMMARY
[0004] This Summary is provided to introduce a brief selection of
disclosed concepts in a simplified form that are further described
below in the Detailed Description including the drawings provided.
This Summary is not intended to limit the claimed subject matter's
scope.
[0005] Disclosed embodiments recognize for dielectrically lined
trench structures although increasing the thickness the dielectric
liner or using a relatively high refractive index liner material
raises the operating voltage the trench dielectric can sustain,
there is trade-off for some devices. For example, for trench
gate-type MOSFETs and trench field plate type planar gate MOSFETs
there is a tradeoff between breakdown voltage and ON-state
resistance attributed to the charge balance between the trench
dielectric liner and the substrate material (e.g., silicon).
Typically, reduced dielectric (e.g. oxide) thickness is preferred
for a charge balance improvement but may cause reliability or a
high E-field concern especially at the trench bottom corner.
Increased dielectric thickness can reduce such kinds of risk, but
introduces the difficulty to keep charge balance for an appropriate
breakdown voltage. Disclosed trench structures includes both a
conventional dielectric trench liner comprising a first dielectric
material (e.g., silicon oxide) a second dielectric material (e.g.,
SiN) at only the bottom of the trench to increase total dielectric
thickness only at the bottom of the trench.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Reference will now be made to the accompanying drawings,
which are not necessarily drawn to scale, wherein:
[0007] FIG. 1 is a flow chart that shows steps in an example method
for fabricating a semiconductor device including forming trenches
having a thick dielectric selectively on its bottom portion,
according to an example embodiment.
[0008] FIG. 2A is a cross section portion of a conventional trench
field plate FET.
[0009] FIG. 2B is a cross section portion of a disclosed trench
field plate FET including a trench having a thick dielectric
selectively on its bottom portion, according to an example
embodiment.
[0010] FIG. 2C is a cross section portion of a disclosed trench
field plate FET including a trench having a thick dielectric
selectively on its bottom portion that extends through an epitaxial
layer into the underlying substrate, according to an example
embodiment.
[0011] FIG. 2D is a cross section portion of a conventional trench
gate FET.
[0012] FIG. 2E is a cross section portion of a disclosed trench
gate FET including a trench having a thick dielectric selectively
on its bottom portion, according to an example embodiment.
[0013] FIG. 3A depicts a cross sectional view of an example trench
gate MOSFET including a plurality of transistor cells each
including a disclosed trench having a thick dielectric selectively
on its bottom portion, according to an example embodiment.
[0014] FIG. 3B depicts a cross sectional view of an example planar
gate trench MOSFET including a plurality of active transistor cells
each including a disclosed trench having a thick dielectric
selectively on its bottom portion, according to an example
embodiment.
DETAILED DESCRIPTION
[0015] Example embodiments are described with reference to the
drawings, wherein like reference numerals are used to designate
similar or equivalent elements. Illustrated ordering of acts or
events should not be considered as limiting, as some acts or events
may occur in different order and/or concurrently with other acts or
events. Furthermore, some illustrated acts or events may not be
required to implement a methodology in accordance with this
disclosure.
[0016] FIG. 1 is a flow chart that shows steps in an example method
100 for fabricating a semiconductor device including forming
trenches having a thick dielectric selectively on its bottom
portion, according to an example embodiment. Step 101 comprises
etching a semiconductor substrate having a top surface to form a
trench having sidewalls and a bottom surface that extends from the
top surface into the semiconductor substrate. The substrate can be
an epitaxial layer on a bulk semiconductor (e.g., silicon or
comprising silicon), but can also be solely a bulk semiconductor.
The trench depth is generally from 2 .mu.m to 50 .mu.m.
[0017] Step 102 comprises forming a dielectric liner comprising a
first dielectric material on the bottom surface and sidewalls of
the trench to line the trench. The dielectric liner can be
thermally grown or deposited such as by low pressure chemical vapor
deposition (LPCVD).
[0018] Step 103 comprises depositing a second dielectric layer
comprising a second dielectric material to at least partially fill
the trench. The trench filling is optionally a complete trench
filling. The second dielectric material generally has a
k-value.gtoreq.5. Silicon nitride is an example a second dielectric
material, others examples include SiON, SiC, or other dielectric
materials such as HfO.sub.2, ZrO.sub.2, Al.sub.2O.sub.3 and
HfSiO.sub.3.
[0019] Step 104 comprises partially etching the second dielectric
layer to selectively remove the second dielectric layer from an
upper portion of the trench while preserving the second dielectric
layer on a lower portion of the trench. Wet or dry (e.g., plasma)
processing can be used for this etch back process, and there is
generally no need for a masking pattern. The length of the upper
portion of the trench without the second dielectric layer is
generally .gtoreq.a length of the lower portion of the trench with
the second dielectric layer. A typical length ratio of the upper
portion without the second dielectric layer to the lower portion
with the second dielectric layer is >10:1.
[0020] Step 105 comprises filling the trench with a fill material
which provides an electrical conductivity that is at least that of
a semiconductor. In the case of a semiconductor fill material, the
semiconductor may later in the process be doped. Examples of fill
materials include polysilicon, and silicides such as tungsten
silicide. The fill material is generally deposited and is then
planarized to remove overburden fill materials, such as by chemical
mechanical polishing (CMP). The fabrication process is then
completed including implants, masking levels, depositions and
diffusions forming gates, sources, drain, interconnects and bond
pads, and passivation.
[0021] FIG. 2A is a cross section portion of a conventional trench
field plate FET formed on an epitaxial semiconductor layer (epi
layer) 180 on an n+ substrate 196. The FET shown includes a gate
electrode 270 on a gate dielectric 271 that is on a top surface
180a of the epi layer 180. A silicide layer 272 is shown on the
gate electrode 270 which will generally be present when the gate
electrode 270 comprises polysilicon. The surface 180a of the epi
layer 180 over the FET is shown covered with a dielectric film 190.
The trench is shown including a dielectric liner 140 comprising a
first dielectric material that is filled by a filler material 170.
A source 250 and a body region 260 are shown formed in the epi
layer 180. A source metal layer 195 is shown contacting the source
250, the body region 260, and the filler material 170.
[0022] FIG. 2B is a cross section portion of a disclosed trench
field plate FET including a trench having a thick dielectric
selectively on its bottom portion, according to an example
embodiment. A second dielectric layer 141 comprising a second
dielectric material is shown only on a lower portion of the trench.
The source metal layer 195 is again shown contacting the source
250, the body region 260, and the filler material 170.
[0023] FIG. 2C is a cross section portion of a disclosed trench
field plate FET including a trench having a thick dielectric
selectively on its bottom portion that extends through the epi
layer 180 into the underlying substrate 196, according to an
example embodiment. The source metal layer 195 is again shown
contacting the source 250, the body region 260, and the filler
material 170.
[0024] FIG. 2D is a cross section portion of a conventional trench
gate FET. The FET shown includes the filler material 170 as its
gate electrode and the dielectric liner 140 as its gate dielectric
layer. A source 150 and a body region 160 are shown formed in the
epi layer 180. A source metal layer 195 is shown contacting the
source 150 and body region 160. Although not shown in FIG. 2D or
FIG. 2E described below, the filler material 170 is contacted by
another metal (or polysilicon) pattern through vias cut in the
dielectric film 190 shown in FIG. 3A that is over the filler
material 170.
[0025] FIG. 2E is a cross section portion of a disclosed trench
gate FET including a trench having a thick dielectric selectively
on its bottom portion, according to an example embodiment. A second
dielectric layer 141 comprising a second dielectric material is
shown only on a lower portion of the trench.
[0026] FIG. 3A depicts a cross sectional view of an example trench
gate MOSFET 300 (trench gate MOSFET 300) shown as being an
n-channel device (NMOS) including a plurality of transistor cells
(cells) 110 each including a trench having thick dielectric
selectively on its bottom portion, according to an example
embodiment. Although generally described herein as being NMOS
devices, disclosed MOSFET devices may also be PMOS. Moreover, in a
practical device, there may be hundreds or thousands of cells
hooked electrically in parallel. The trench portion of any of the
cells 110 shown may be used for a trench isolation structure, field
plate, or as a trench capacitor for a given semiconductor device.
Although not shown in FIG. 3A, gate contacts and metal connections
to the gate contacts are provided to provide electrical contact to
the gate electrodes 170 of the cells 110.
[0027] Trench gate MOSFET 100 is formed on a substrate 196 shown as
an n+substrate that provides a drain for the device having an n-
epitaxial semiconductor layer 180 thereon which provides an n-
drain drift region. The n+ substrate 196/semiconductor layer 180
can comprise silicon; alternatively, the n+ substrate 196/epitaxial
semiconductor layer 180 may comprise other semiconductor materials
such as germanium, silicon carbide, gallium nitride, gallium
arsenide, etc. A p- doped body region 160 is formed in the
semiconductor layer 180, where n+ doped source regions 150 are
formed at the surface 180a of the semiconductor layer 180 within
the body regions 160.
[0028] Conductor filled dielectric lined gate trenches 170/140
provide the gate structure for the respective cells 110. The gate
trench walls are lined with a dielectric film 140 (or liner)
comprising a first dielectric material that functions as a gate
dielectric. The trenches include a thick dielectric selectively on
their bottom provided by the second dielectric layer 141 shown. In
this embodiment, the dielectric film 140 can be silicon dioxide.
Alternatively, the dielectric film 140 may comprise other
dielectric material such as silicon nitride, or other dielectrics.
The dielectric lined trenches are filled with polysilicon or other
electrically conductive material such as tungsten to form the gate
electrode 170 for the cells 110.
[0029] The gate trenches can be etched from the surface 180a of the
epitaxial semiconductor layer 180. In this embodiment, the five
depicted gate trenches can be processed concurrently with a pattern
step and then an etch step. The trench gate MOSFET 300 in this
embodiment can be formed by a process flow for conventional trench
MOSFETs such as including ion implantation or dopant diffusion to
form the body regions 160 and the source regions 150.
[0030] The surface 180a of the semiconductor layer 180 is shown
covered with a dielectric film 190. In this embodiment, the
dielectric film 190 can comprise silicon oxide or silicon
oxynitride. Alternatively, the dielectric film 190 may comprise
other dielectric materials as known in the art of semiconductor
device fabrication.
[0031] As shown in FIG. 3A, the cells 110 also include source/body
contact holes 112 which are formed through the top surface 180a of
the semiconductor layer 180 between the gate trenches through the
source regions 150 and the body regions 160. Although the
source/body contact holes 112 are shown in FIG. 3A extending into
the semiconductor layer 180, disclosed embodiments also include the
option of having planar source/body contacts.
[0032] Once filled with an electrical conductor shown as source
metal layer 195 the contact holes 112 short the source regions 150
to the body regions 160 of each of the cells 110. Source metal
layer 195 can be more generally any electrically conductive
material such as tungsten or doped polysilicon, which in operation
is generally grounded.
[0033] The backside 196a of the n+ substrate 196 of the trench gate
MOSFET 300 in FIG. 3A is shown covered with a separate metal film
197. This metal film 197 makes a low resistance ohmic contact to
the n+ substrate 196 which provides the drain region, which in
operation is connected to Vds. Alternatively, metal film 197 may be
omitted and the backside 196a of the n+ substrate 196 may instead
be mounted to a die pad of a leadframe. The gate electrodes 170 of
the active transistor cells 110 are separately tied together by
another metal or doped polycrystalline element (not shown) which is
connected to the gate electrode terminal of the device package.
[0034] When trench gate MOSFET 300 is an enhancement device,
provided the device is properly biased between gate and source, an
inversion channel forms in the mesa region between the source
region 150 and the drain drift region 180', adjacent to the
dielectric film 140 that lines the trench walls. When an
appropriate potential difference is established between the source
terminal and the drain terminal, electrical current flows
vertically through the channel. If the body region is doped more
heavily with n-type dopant (PMOS), the current is carried through
the channel by holes; if it is doped more heavily with p-type
dopant (NMOS) as shown in FIG. 3A, electrons.
[0035] FIG. 3B depicts a simplified cross-section view of an
example planar gate trench MOSFET device 350 (planar gate trench
MOSFET 350) including a plurality of transistor cells (cells) 210
each including a trench having thick dielectric selectively on its
bottom portion, according to an example embodiment. The planar gate
trench MOSFET 350 includes dielectric lined trenches with a
polysilicon filler 240 lined by a dielectric liner 140 comprising a
first dielectric material having a thick dielectric selectively on
the bottom of the trench provided by the second dielectric layer
141 shown to provide field plates (sometimes referred to as "RESURF
trenches) on both sides of the gate stacks for the cells 210. The
cells 210 are shown having a gate stack comprising a gate electrode
270 on a gate dielectric 271. Although not shown in FIG. 3B, gate
contacts and metal connections are provided to provide electrical
contact to the gate electrodes 270 of the cells 210. An n+ doped
source region 250 is on the top surface 180a of the semiconductor
layer 180 between the gate stacks and the trenches, and the
substrate 196 is shown as an n+ substrate which provides a drain
for the device having an epi layer 180 thereon that provides a
drain drift region 180'. Although a single gate is shown for each
of the cells 210, the respective cells 210 may also have a split
dual-gate. The planar gate trench MOSFET 350 in this embodiment can
be formed by a process flow for conventional MOSFETs such as
including ion implantation or diffusion to form the p-doped body
regions 260 and source regions 250.
[0036] The surface 180a includes a dielectric layer 190 thereon. In
this embodiment, the dielectric film material can be silicon
dioxide. Alternatively, the dielectric film 190 may comprise other
dielectric material such as silicon nitride or other dielectrics.
The source metal layer 195 is shown contacting the polysilicon
filler 240 in the dielectric lined trenches as well as the adjacent
source 250 and body region 260.
[0037] The gate electrodes 270 for the active transistor cells 210
are separately tied together by another metallic or polysilicon
element which is generally connected to the gate terminal of the
device package. When the planar gate trench MOSFET 350 is an
enhancement device, provided the device is properly biased, an
inversion channel forms in the body region 260 under the gate 270.
Electrical current flows through the channel when an electric field
gradient is established between the source and the drain. If the
body region is doped more heavily with n-type dopant (PMOS), the
current is carried through the channel by holes; if it is doped
more heavily with p-type dopant (NMOS), electrons.
[0038] Advantages of disclosed trench structures include enhancing
the charge balance for specific ON-resistance (Rsp)-breakdown
voltage (BV) trade-off without any degradation of reliability or
high E-field concern at the bottom of trench. As an example, for
trench field MOSFETs, the output capacitance (Coss) can be reduced
more than 20% without any performance degradation in Rsp, BV, or
threshold voltage (Vt). For trench gate FETs, disclosed trenches
reduce the gate to drain charge (Qgd) 50%, and Coss can be reduced
10% while keeping the same range of Rsp, BV and Vt.
[0039] Moreover, disclosed trenches increase the integrity between
the substrate (e.g., silicon) and fill material (e.g., polysilicon)
for trench gate FETs, and improve the operating voltage (Vop) for
trench capacitors at the trench bottom where typically reliability
is concerned due to a higher electric E-field. As noted above,
disclosed trenches may also be used for isolation trenches, for
example for shallow trench isolation (STI) and DEEP trench
isolation.
[0040] Disclosed embodiments can be used to form semiconductor die
that may be integrated into a variety of assembly flows to form a
variety of different devices and related products. The
semiconductor die may include various elements therein and/or
layers thereon, including barrier layers, dielectric layers, device
structures, active elements and passive elements including source
regions, drain regions, bit lines, bases, emitters, collectors,
conductive lines, conductive vias, etc. Moreover, the semiconductor
die can be formed from a variety of processes including bipolar,
Insulated Gate Bipolar Transistor (IGBT), CMOS, BiCMOS and
MEMS.
[0041] Those skilled in the art to which this disclosure relates
will appreciate that many other embodiments and variations of
embodiments are possible within the scope of the claimed invention,
and further additions, deletions, substitutions and modifications
may be made to the described embodiments without departing from the
scope of this disclosure.
* * * * *