U.S. patent application number 13/996972 was filed with the patent office on 2017-07-27 for method and apparatus of instruction that merges and sorts smaller sorted vectors into larger sorted vector.
The applicant listed for this patent is Jatin CHHUGANI, Nadathur Rajagopalan SATISH. Invention is credited to Jatin CHHUGANI, Changkyu CK KIM, Nadathur Rajagopalan SATISH.
Application Number | 20170212727 13/996972 |
Document ID | / |
Family ID | 49260934 |
Filed Date | 2017-07-27 |
United States Patent
Application |
20170212727 |
Kind Code |
A1 |
CHHUGANI; Jatin ; et
al. |
July 27, 2017 |
METHOD AND APPARATUS OF INSTRUCTION THAT MERGES AND SORTS SMALLER
SORTED VECTORS INTO LARGER SORTED VECTOR
Abstract
A semiconductor chip is described that includes an instruction
execution unit having a functional unit, said functional unit
having minimum and maximum comparison circuitry followed by
interleaving circuitry, said minimum and maximum comparison
circuitry to respectively identify minimums and maximums of same
positioned elements from two different sets of sorted elements,
said interleaving circuitry to interleave said minimums and
maximums to help form a third sorted set composed of elements from
said different sets and being larger than each of said different
sets.
Inventors: |
CHHUGANI; Jatin; (Mountain
View, CA) ; KIM; Changkyu CK; (San Jose, CA) ;
SATISH; Nadathur Rajagopalan; (Santa Clara, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
CHHUGANI; Jatin
SATISH; Nadathur Rajagopalan |
Mountain View
Santa Clara |
CA
CA |
US
US |
|
|
Family ID: |
49260934 |
Appl. No.: |
13/996972 |
Filed: |
March 30, 2012 |
PCT Filed: |
March 30, 2012 |
PCT NO: |
PCT/US2012/031645 |
371 Date: |
November 10, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 9/30036 20130101;
G06F 9/3005 20130101; G06F 7/32 20130101; G06F 9/3867 20130101;
G06F 7/36 20130101; G06F 9/30014 20130101; G06F 9/30021 20130101;
G06F 9/30032 20130101; G06F 9/3012 20130101 |
International
Class: |
G06F 7/36 20060101
G06F007/36; G06F 9/38 20060101 G06F009/38; G06F 9/30 20060101
G06F009/30 |
Claims
1. A semiconductor chip, comprising: an instruction execution unit
having a functional unit, said functional unit having minimum and
maximum comparison circuitry followed by interleaving circuitry,
said minimum and maximum comparison circuitry to respectively
identify minimums and maximums of same positioned elements from two
different sets of sorted elements, said interleaving circuitry to
interleave said minimums and maximums to help form a third sorted
set composed of elements from said different sets and being larger
than each of said different sets.
2. The semiconductor chip of claim 1 wherein said execution unit
comprises multiple stages of minimum and maximum comparison
circuitry followed by interleaving circuitry.
3. The semiconductor chip of claim 2 wherein said execution unit
comprises a multiplexer to select an output from different ones of
said stages as a function of the size of said sets.
4. The semiconductor chip of claim 2 wherein said size of said sets
are variable across different instructions executed by said
functional unit and include the following possible sizes: 4
elements, 8 elements and 16 elements.
5. The semiconductor chip of claim 2 wherein said size of said sets
are specified in a respective immediate operand of said different
instructions.
6. The semiconductor chip of claim 1 wherein said execution unit
includes a ROM storing micro-code that controls a number of loops
through said minimum and maximum comparison circuitry and
interleaving circuitry that said execution unit executes as a
function of said size of said sets.
7. The semiconductor chip of claim 2 wherein said size of said sets
are specified in a respective immediate operand of said different
instructions.
8. A method, comprising: performing the following with a single
instruction with logic circuitry in an instruction pipeline of a
semiconductor chip: i) producing a next set of minimums by flowing
same positioned elements of two sets of elements into minimum
comparison logic circuitry and producing a next set of maximums by
flowing said same positioned elements of two sets of elements into
maximum comparison logic circuitry; ii) producing a set of
interleaved elements by flowing said next set of minimums and said
next set of maximums through interleaving circuitry, said set of
interleaved elements corresponding to the next two sets of elements
operated upon by any repetition of i) above; repeating i) and ii)
above as a function of the number of said elements in said two sets
of elements.
9. The method of claim 8 wherein said repeating is effected by
running flows through successive and different respective stages of
minimum comparison logic circuitry, maximum comparison logic
circuitry and interleaving circuitry.
10. The method of claim 9 wherein said method further comprising
selecting respective interleaved elements produced by one of said
stages and flowing said respective interleaved elements through
multiplexer circuitry.
11. The method of claim 8 wherein said repeating is effected by
looping flows through same minimum comparison circuitry, maximum
comparison circuitry, and interleaving circuitry.
12. The method of claim 8 wherein determining the number of
repetitions of i) and ii) above is accomplished with a look-up
table implemented with ROM circuitry associated with said execution
unit.
13. The method of claim 8 wherein said method further comprises
running a received sorted set through pre-shuffling logic circuitry
before a first instance of i) is performed.
14. A machine readable medium containing program code that when
executed by a computing system causes the computing system to
perform a method, comprising: executing a first instruction to form
a first sorted set; executing a second instruction to form a second
sorted set; and, executing a third instruction to form a third
sorted set by combining and sorting the elements of the first and
second sorted sets.
15. The machine readable medium of claim 14 wherein said third
instruction includes an immediate operand from which a width of
said first and second sorted sets is determinable.
16. The machine readable medium of claim 14 wherein said third
instruction defines respective register locations for both said
first and second sorted sets.
17. The machine readable medium of claim 14 wherein said third
instruction defines a register location for one of said first and
second sorted sets, and, defines a memory location for the other of
said first and second sorted sets.
18. A machine readable medium containing program code that when
executed by a computing system causes the computing system to
perform a method, comprising: executing an instruction that accepts
first and second unsorted sets and forms a third sorted set by
combining and sorting elements of the first and second sorted
sets.
19. The machine readable medium of claim 18 wherein said third
instruction includes an immediate operand from which a width of
said first and second unsorted sets is determinable.
20. The machine readable medium of claim 18 wherein said
instruction defines respective register locations for both said
first and second unsorted sets.
Description
FIELD OF INVENTION
[0001] The field of invention relates to generally to the computing
sciences and more specifically to an instruction that merges and
sorted smaller sorted vectors into a larger sorted vector.
BACKGROUND
[0002] Vector Instruction Execution Pipeline
[0003] FIG. 1 shows a high level diagram of a processing core 100
implemented with logic circuitry on a semiconductor chip. The
processing core includes a pipeline 101. The pipeline consists of
multiple stages each designed to perform a specific step in the
multi-step process needed to fully execute a program code
instruction. These typically include at least: 1) instruction fetch
and decode; 2) data fetch; 3) execution; 4) write-back. The
execution stage performs a specific operation identified by an
instruction that was fetched and decoded in prior stage(s) (e.g.,
in step 1) above) upon data identified by the same instruction and
fetched in another prior stage (e.g., step 2) above). The data that
is operated upon is typically fetched from (general purpose)
register storage space 102. New data that is created at the
completion of the operation is also typically "written back" to
register storage space (e.g., at stage 4) above).
[0004] The logic circuitry associated with the execution stage is
typically composed of multiple "execution units" or "functional
units" 103_1 to 103_N that are each designed to perform its own
unique subset of operations (e.g., a first functional unit performs
integer math operations, a second functional unit performs floating
point instructions, a third functional unit performs load/store
operations from/to cache/memory, etc.). The collection of all
operations performed by all the functional units corresponds to the
"instruction set" supported by the processing core 100.
[0005] Two types of processor architectures are widely recognized
in the field of computer science: "scalar" and "vector". A scalar
processor is designed to execute instructions that perform
operations on a single set of data, whereas, a vector processor is
designed to execute instructions that perform operations on
multiple sets of data. FIGS. 2A and 2B present a comparative
example that demonstrates the basic difference between a scalar
processor and a vector processor.
[0006] FIG. 2A shows an example of a scalar AND instruction in
which a single operand set, A and B, are ANDed together to produce
a singular (or "scalar") result C (i.e., AB=C). By contrast, FIG.
2B shows an example of a vector AND instruction in which two
operand sets, A/B and D/E, are respectively ANDed together in
parallel to simultaneously produce a vector result C, F (i.e.,
A.AND.B=C and D.AND.E=F). As a matter of terminology, a "vector" is
a data element having multiple "elements". For example, a vector
V=Q, R, S, T, U has five different elements: Q, R, S, T and U. The
"size" of the exemplary vector V is five (because it has five
elements).
[0007] FIG. 1 also shows the presence of vector register space 107
that is different than general purpose register space 102.
Specifically, general purpose register space 102 is nominally used
to store scalar values. As such, when, any of execution units
perform scalar operations they nominally use operands called from
(and write results back to) general purpose register storage space
102. By contrast, when any of the execution units perform vector
operations they nominally use operands called from (and write
results back to) vector register space 107. Different regions of
memory may likewise be allocated for the storage of scalar values
and vector values.
[0008] Note also the presence of masking logic 104_1 to 104_N and
105_1 to 105_N at the respective inputs to and outputs from the
functional units 103_1 to 103_N. In various implementations, for
vector operations, only one of these layers is actually
implemented--although that is not a strict requirement (although
not depicted in FIG. 1, conceivably, execution units that only
perform scalar and not vector operations need not have any masking
layer). For any vector instruction that employs masking, input
masking logic 104_1 to 104_N and/or output masking logic 105_1 to
105_N may be used to control which elements are effectively
operated on for the vector instruction. Here, a mask vector is read
from a mask register space 106 (e.g., along with input operand
vectors read from vector register storage space 107) and is
presented to at least one of the masking logic 104, 105 layers.
[0009] Over the course of executing vector program code each vector
instruction need not require a full data word. For example, the
input vectors for some instructions may only be 8 elements, the
input vectors for other instructions may be 16 elements, the input
vectors for other instructions may be 32 elements, etc. Masking
layers 104/105 are therefore used to identify a set of elements of
a full vector data word that apply for a particular instruction so
as to effect different vector sizes across instructions. Typically,
for each vector instruction, a specific mask pattern kept in mask
register space 106 is called out by the instruction, fetched from
mask register space and provided to either or both of the mask
layers 104/105 to "enable" the correct set of elements for the
particular vector operation.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The present invention is illustrated by way of example and
not limitation in the figures of the accompanying drawings, in
which like references indicate similar elements and in which:
[0011] FIG. 1 (prior art) shows an embodiment of an instruction
execution pipeline;
[0012] FIG. 2 (prior art) shows an example of vector
processing;
[0013] FIG. 3 (prior art) pertains to a prior art merge and sorting
algorithm;
[0014] FIG. 4 shows an embodiment of instruction execution logic
circuitry for implementing the merge and sorting algorithm of FIG.
3 in a single instruction;
[0015] FIG. 5a, 5b shows various additional embodiments concerning
instruction execution logic circuitry for implementing the merge
and sorting algorithm of FIG. 3 in a single instruction;
[0016] FIG. 6 shows an embodiment of a micro-coded functional unit
for implementing the merge and sorting algorithm of FIG. 3 in a
single instruction;
[0017] FIG. 7a shows an instruction execution pipeline and
corresponding object code that supports an instruction that accepts
sorted sets as input operands;
[0018] FIG. 7b shows an instruction execution pipeline and
corresponding object code that supports an instruction that accepts
unsorted sets as input operands.
[0019] FIGS. 8A-8B are block diagrams illustrating a generic vector
friendly instruction format and instruction templates thereof
according to embodiments of the invention;
[0020] FIG. 9 is a block diagram illustrating an exemplary specific
vector friendly instruction format according to embodiments of the
invention;
[0021] FIG. 10 is a block diagram of a register architecture
according to one embodiment of the invention;
[0022] FIG. 11A is a block diagram illustrating both an exemplary
in-order pipeline and an exemplary register renaming, out-of-order
issue/execution pipeline according to embodiments of the
invention;
[0023] FIG. 11B is a block diagram illustrating both an exemplary
embodiment of an in-order architecture core and an exemplary
register renaming, out-of-order issue/execution architecture core
to be included in a processor according to embodiments of the
invention;
[0024] FIGS. 12A-B illustrate a block diagram of a more specific
exemplary in-order core architecture, which core would be one of
several logic blocks (including other cores of the same type and/or
different types) in a chip;
[0025] FIG. 13 is a block diagram of a processor that may have more
than one core, may have an integrated memory controller, and may
have integrated graphics according to embodiments of the
invention;
[0026] FIG. 14 is a block diagram of a system in accordance with
one embodiment of the present invention;
[0027] FIG. 15 is a block diagram of a first more specific
exemplary system in accordance with an embodiment of the present
invention;
[0028] FIG. 16 is a block diagram of a second more specific
exemplary system in accordance with an embodiment of the present
invention;
[0029] FIG. 17 is a block diagram of a SoC in accordance with an
embodiment of the present invention; and
[0030] FIG. 18 is a block diagram contrasting the use of a software
instruction converter to convert binary instructions in a source
instruction set to binary instructions in a target instruction set
according to embodiments of the invention.
DETAILED DESCRIPTION
[0031] Prior Art Merge Algorithm
[0032] Various software operations seek to merge two smaller sorted
sets into a larger sorted set. FIG. 3 shows a prior art software
process that is used for that purpose. Referring to FIG. 3, two
separate input sorted sets 301, 302 are merged by way of the merger
process depicted in FIG. 3 to ultimately form larger sorted set
303. A sorted set is a set of values that have been ranked
according to some criteria. The most basic criteria, which is
depicted in FIG. 3, is a numerical ranking. That is, elements in a
set are sorted based on their numerical values relative to another.
As observed in FIG. 3, the elements of input sorted sets 301, 302
and output sorted set 303 are ranked in numerical order with
smaller values aligned to the left and higher values aligned to the
right.
[0033] The larger output sorted set 303 is produced from the two
smaller input sorted sets 301, 302 according to the sequence of
procedures outlined n FIG. 3. First, one of the input sorted sets
(in this case input sorted set 302) has its respective elements
reversed or flipped as observed in set 311. Next, elements of set
301 and set 311 that are in the same location in their respective
set are compared. Two comparisons are made for each pair of same
positioned elements. A first comparison takes the minimum of the
pair and places it into the same corresponding position in a
resulting set 312. For example, the first element in set 312 is a 2
which corresponds to the minimum of the first element in set 301
(2) and the first element in set 311 (7).
[0034] A second comparison takes the maximum of the same positioned
elements in sets 301 and 311 and places it into the same
corresponding position in set 313. For example, the first element
in set 313 corresponds to the maximum of the first element in set
301 (2) and the first element in set 311 (7). Similar processes are
used for the other element positions of sets 312 and 313.
[0035] The values in the resulting sets 312, 313 are then
interleaved to produce resulting sets 318, 319. The interleaving
process essentially shuffles the elements in resulting sets 312,
313 such that the first element of set 312 is chosen as the first
element in set 318, then, the first element of set 313 is chosen
for the next element in set 318, then, the second element in set
312 is chosen as the third element for set 318 Continuing with the
process, the second element of set 312 is chosen for inclusion in
set 318, then, the second element of set 313 is chosen as the
fourth element for set 318. The interleaving process continues in
like manner for set 319.
[0036] The two processes described above, "min/max" (which produced
sets 312 and 313 from sets 301 and 311) and interleaving (which
produced sets 318, 319 from sets 312, 313), are repeated for a
sufficient number of cycles 320, 321 until the final result is
reached 303. Generally, the total number of cycles that is
sufficient is a function of the number of elements in the initial
sorted sets 301, 303. Specifically, N min/max and interleaving
cycles are performed where N=log.sub.2(2X) and where X is the
number of elements in each of the input sorted sets. In the
observed example of FIG. 3, X=4 (i.e., there are four elements in
each of input sorted sets 301 and 302), therefore
N=log.sub.2(2(4))=log.sub.2(8)=3. Thus three min/max and
interleaving cycles are observed in the overall sequence of FIG. 3
before the final, larger sorted set is presented at the output
303.
[0037] To date the above described merger algorithm has been
implemented in software such that each newly calculated element in
any intermediate or the resultant set consumes multiple CPU
instructions. As such, computing the entire algorithm can consume
hundreds if not thousands of CPU instructions.
[0038] Hardware Implementation of Merge Algorithms
[0039] In order to greatly speed up the construction of a larger
sorted set from smaller sorted sets, FIG. 4 shows an embodiment of
a logic circuit design for an execution unit 400 within an
instruction execution pipeline that implements a merger algorithm
with a single instruction. FIG. 4 shows a design for an X=4
implementation. A more generic and expansive discussion of the
logic design is provided in FIG. 4.
[0040] As observed in FIG. 4, two vector input operands from input
operand registers 401, 402 that correspond to two smaller sorted
sets are presented to the execution unit logic circuitry 400. With
each input operand being implemented as a vector, the elements of
each vector are received in a sorted state (e.g., numerically
increasing). Inverted shuffle logic 403 inverts one of the vector
operands to effectively perform the inverted shuffle that,
correspondingly, produced set 311 of FIG. 3.
[0041] A first stage of min/max comparison logic 404 then performs
min/max comparisons between identically positioned elements in the
set in register 401 and the set produced by logic 403. In the
embodiment of FIG. 4, comparison units 404_1 through 404_4 present
the respective minimum values of these identically positioned
values at the "left hand" inputs to interleaving logic 405. By
contrast, comparison units 404_5 through 404_8 present the
respective maximum values of these identically positioned values at
the "right hand" inputs to interleaving logic 405. The interleaving
logic 405 interleaves the results of the minimum comparison results
with the results of the maximum comparison results in a manner akin
to the technique used to produce sets 318, 319 in FIG. 3.
[0042] The execution logic circuitry 400 includes two following
stages of min/max comparison and interleaving logic 406, 407, 408,
409 to effectuate three stages of min/max comparisons and
interleaving for an X=4, N=3 system.
[0043] FIG. 5a shows a more generic depiction of the execution
logic circuitry. According to the depiction of FIG. 5a, N stages of
min/max comparison logic circuitry and interleaving circuitry are
chained in series for a pair of sorted input sets each of width X.
In an embodiment, the same execution logic circuitry can support
the merge operation for different values of X. That is, the size of
the input sorted sets is also taken as an input variable.
[0044] For example, FIG. 5b shows an embodiment of a design for an
execution unit that supports a value of X that can be any of 4, 8
or 16, where, the specific value of X for the particular
instruction is specified in an immediate operand.
[0045] As observed in FIG. 5b, the value of X received through the
immediate operand affects the length of the hardware channels.
According to the embodiment of FIG. 5b, the logic circuitry has a
total of five min/max and interleaving stages chained in series
that corresponds to the maximum value of X supported by the
instruction execution logic circuitry. That is, the circuitry is
designed to support the necessary number of min/max and
interleaving stages (i.e., log.sub.2(2(16))=5) needed for the
largest sized input sorted set (16) it can receive.
[0046] The specific value of X received through the immediate
operand for any particular instruction determines how many of the
stages are actually utilized in determining the output value of the
instruction. For example, if the immediate value specifies X=16,
then, all five stages are utilized to calculate the output. By
contrast, if the immediate operand specifies X=8, the output is
"tapped" from the output of the fourth stage rather than the fifth.
Likewise, if X=4 the output is "tapped" from the output of the
third stage. A multiplexer 550 accepts the value of X at its
channel select input and selects the output of the correct stage
for presentation as the formal result of the instruction.
[0047] In the specific embodiment of FIG. 5b, the value of X is
received through an immediate operand. The applicable value of N is
determined from the received value of X by logic 560 and applied to
the channel select input of multiplexer 550. Although logic 560 may
be designed to calculate log.sub.2(2(X)) outright, it may
alternatively be implemented as a look-up circuit that just reads
(e.g., from read-only-memory (ROM) circuitry) the correct value of
N for a given input value of X. In an alternate embodiment, N is
received through the immediate operand.
[0048] With respect to data channel width, similarly, the number of
min/max stages and the width of the interleaving stage is designed
to support the maximum value of X. For example, if the instruction
execution logic is to support a maximum value of 16, each min/max
stage includes 16 minimum comparison logic circuits and 16 maximum
comparison logic circuits. Similarly, each interleaving stage is
designed to interleave two input sets each as wide as 16 elements
and produce an output as wide as 32 elements. If the immediate
operand specifies X=16, all of this circuitry is utilized. If the
immediate operand specifies a lesser value of X (e.g., X=8 or X=4),
then, smaller portions of this circuitry are utilized. Notably, the
pair of signal lines flow through each of the stages has a width of
the maximum value of X (16).
[0049] Also with respect to data width, the pre-shuffle logic 570
can be implemented as a configurable network the effects the
correct shuffle pattern as a function of X. That is, in order to
support three different values of X, pre shuffle logic 570 should
support three different shuffle patterns. For example, focusing
briefly on the leftmost element output of the pre-shuffle logic
570, note that the correct shuffle pattern should select the fourth
element of the second sorted set input for X=4, or, the eighth
element of the second sorted set input for X=8, or, the sixteenth
element of the second sorted set input for X=16.
[0050] Another data width consideration for an execution unit that
supports multiple values of X is the consolidation of valid data
values from the left and right flows through the multiple stages.
That is, as observed in FIGS. 4, 5a and 5b, the processing through
the stages can be viewed as having a "left side" flow and a "right
side" flow. According to one perspective, the flows are designed in
hardware to support maximum data width (e.g., if maximum X=16, the
hardware includes 16 elements in both the left and right side
flows).
[0051] For values of X less than the maximum, there are unused
hardware blocks and unused individual element channels within the
flows that accumulate from the right. For example, if X=8 for an
execution unit that supports a maximum of X=16, and if the
underlying machine orders least significant elements to the left,
within the min/max comparison stage: 1) the eight leftmost minimum
comparison units will be used and the eight rightmost minimum
comparison units will be unused; and, 2) the eight leftmost maximum
comparison units will be used and the eight rightmost maximum
comparison units will be unused. Similarly, if X=8 and the unit
supports a maximum X=16, the eight leftmost elements in both the
left and right side flows will be used/valid, while, the eight
rightmost elements in both the left and right side flows will be
unused/invalid.
[0052] As such, "left-combining" logic 580 is used to leftwise
combine/accumulate the used/valid elements from the two flows so
that all used/valid elements from the two flows are aligned on the
left in order and all unused/invalid elements from the two flows
are aligned on the right. For example, if X=8 in an execution unit
that supports a maximum X=16, the "left-combining" logic 580 will
create a 32 element data structure that includes: 1) the 8
valid/used elements from the left flow oriented on the left; 2) the
8 valid/used elements from the right flow appended to the 8
valid/used element from the left flow; and, 3) 32 invalid/unused
elements on the right.
[0053] In implementation, "left-combining" logic 58 may be
implemented as a configurable network like pre-shuffle logic 570
but with different pre-configured input/output patterns.
[0054] An output masking layer 590 may be used to "zero out" the
invalid/unused elements at the output of left combining logic 580.
For example, if X=8 and the maximum allowed value of X=16, the
sixteen "leftmost" values presented at the output of left combining
logic 580 are presented as the formal resultant of the instruction,
and, the remaining 16 elements of the multiplexer output to the
"right" are zeroed (i.e., given a value of 0). Alternatively, the
masking layer may not be used or implemented and the overlying
software is responsible for understanding how many elements are
used/valid.
[0055] Another approach to implementing the instruction execution
logic is observed in FIG. 6. The approach of FIG. 6 employs less
than the maximum depth of stages required for the maximum value of
X and uses micro-ops to control a looping through of the limited
hardware the proper number of times for the specific applicable
value of X. For example, as seen in FIG. 6, the instruction
execution logic is implemented with only a single min/max stage and
a single interleaving stage. The microcode stored in the ROM 601
determines the correct number of stages that are to be executed as
a function of X (e.g., 3 loops if X=4; 4 loops if X=5; 5 loops if
X=16) and controls the data flow and looping (via loop control
logic 602) through the single stage hardware. A left combining
logic stage and output masking layer can still operate as described
just above.
[0056] Note that in the execution unit embodiments discussed above
with respect to FIGS. 4, 5a, 5b and 6, the first and second input
sorted sets may both be stored in register space, or one set in
register space and another in memory depending on instruction
format, be read from their respective storage locations and
presented to the execution unit (as such, these storage locations
may be said to be coupled to the execution unit). Likewise, the
resultant produced by the execution unit may be stored in register
space. The immediate operand originates from the instruction. The
instruction pipeline may have register space reserved for the
storage of immediate operands and associated logic for coupling
their contents to the execution unit.
[0057] FIG. 7a shows a first instruction execution pipeline 700
having execution units that support both a separate sorting
instruction and a separate merging instruction. FIG. 7a also shows
exemplary program code 701 that can be executed with the pipeline
700 of FIG. 7a. As observed in the program flow of FIG. 7a, a first
sorting instruction is executed to order a first set and create, as
its resultant, a first input operand for a subsequent merging
instruction. That is, the first instruction accepts a first vector
of elements with no relative ordering amongst themselves, and,
provides as the resultant the same elements but ordered
numerically. A second sorting instruction performs the same
operation with a second vector of elements. The third instruction
is a merging instruction implemented with, for example, any of the
hardware designs discussed above, and, accepts the resultants of
the two previous sorting instructions to create a larger ordered
set.
[0058] FIG. 7b shows a larger execution unit design that performs,
in a single instruction, both the sorting of two original unsorted
vectors, and, merges them to provide as a resultant a larger sorted
vector. As such, the execution unit can accept two unsorted vectors
as input operands and provide, through execution of a single
instruction, an ordered set that is twice as large as the two input
vectors. Sorting logic is understood in the art and need not be
repeated here. The execution unit of FIG. 7b may be designed to
support different set widths (e.g., through specification of an
immediate operand).
[0059] A compiler can be designed to produce object code conforming
to either of the flow diagrams of FIGS. 7a and 7b depending on the
targeted processor and corresponding instruction execution pipeline
design/technology.
[0060] FIGS. 8A-8B are block diagrams illustrating a generic vector
friendly instruction format and instruction templates thereof
according to embodiments of the invention. FIG. 8A is a block
diagram illustrating a generic vector friendly instruction format
and class A instruction templates thereof according to embodiments
of the invention; while FIG. 8B is a block diagram illustrating the
generic vector friendly instruction format and class B instruction
templates thereof according to embodiments of the invention.
Specifically, a generic vector friendly instruction format 800 for
which are defined class A and class B instruction templates, both
of which include no memory access 805 instruction templates and
memory access 820 instruction templates. The term generic in the
context of the vector friendly instruction format refers to the
instruction format not being tied to any specific instruction
set.
[0061] While embodiments of the invention will be described in
which the vector friendly instruction format supports the
following: a 64 byte vector operand length (or size) with 32 bit (4
byte) or 64 bit (8 byte) data element widths (or sizes) (and thus,
a 64 byte vector consists of either 16 doubleword-size elements or
alternatively, 8 quadword-size elements); a 64 byte vector operand
length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data
element widths (or sizes); a 32 byte vector operand length (or
size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8
bit (1 byte) data element widths (or sizes); and a 16 byte vector
operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16
bit (2 byte), or 8 bit (1 byte) data element widths (or sizes);
alternative embodiments may support more, less and/or different
vector operand sizes (e.g., 256 byte vector operands) with more,
less, or different data element widths (e.g., 128 bit (16 byte)
data element widths).
[0062] The class A instruction templates in FIG. 6A include: 1)
within the no memory access 805 instruction templates there is
shown a no memory access, full round control type operation 610
instruction template and a no memory access, data transform type
operation 815 instruction template; and 2) within the memory access
820 instruction templates there is shown a memory access, temporal
825 instruction template and a memory access, non-temporal 830
instruction template. The class B instruction templates in FIG. 8B
include: 1) within the no memory access 805 instruction templates
there is shown a no memory access, write mask control, partial
round control type operation 812 instruction template and a no
memory access, write mask control, vsize type operation 817
instruction template; and 2) within the memory access 820
instruction templates there is shown a memory access, write mask
control 827 instruction template.
[0063] The generic vector friendly instruction format 600 includes
the following fields listed below in the order illustrated in FIGS.
8A-8B. In conjunction with the discussions above, in an embodiment,
referring to the format details provided below in FIGS. 8A-B and 7,
either a non memory access instruction type 805 or a memory access
instruction type 820 may be utilized. Addresses for the read
mask(s), input vector operand(s) and destination may be identified
in register address field 844 described below. In a further
embodiment the read mask and the write masks are encoded in the
EVEX.kkk field.
[0064] Format field 840--a specific value (an instruction format
identifier value) in this field uniquely identifies the vector
friendly instruction format, and thus occurrences of instructions
in the vector friendly instruction format in instruction streams.
As such, this field is optional in the sense that it is not needed
for an instruction set that has only the generic vector friendly
instruction format.
[0065] Base operation field 842--its content distinguishes
different base operations.
[0066] Register index field 844--its content, directly or through
address generation, specifies the locations of the source and
destination operands, be they in registers or in memory. These
include a sufficient number of bits to select N registers from a
P.times.Q (e.g. 32.times.512, 16.times.128, 32.times.1024,
64.times.1024) register file. While in one embodiment N may be up
to three sources and one destination register, alternative
embodiments may support more or less sources and destination
registers (e.g., may support up to two sources where one of these
sources also acts as the destination, may support up to three
sources where one of these sources also acts as the destination,
may support up to two sources and one destination).
[0067] Modifier field 846--its content distinguishes occurrences of
instructions in the generic vector instruction format that specify
memory access from those that do not; that is, between no memory
access 805 instruction templates and memory access 820 instruction
templates. Memory access operations read and/or write to the memory
hierarchy (in some cases specifying the source and/or destination
addresses using values in registers), while non-memory access
operations do not (e.g., the source and destinations are
registers). While in one embodiment this field also selects between
three different ways to perform memory address calculations,
alternative embodiments may support more, less, or different ways
to perform memory address calculations.
[0068] Augmentation operation field 850--its content distinguishes
which one of a variety of different operations to be performed in
addition to the base operation. This field is context specific. In
one embodiment of the invention, this field is divided into a class
field 868, an alpha field 852, and a beta field 854. The
augmentation operation field 850 allows common groups of operations
to be performed in a single instruction rather than 2, 3, or 4
instructions.
[0069] Scale field 860--its content allows for the scaling of the
index field's content for memory address generation (e.g., for
address generation that uses 2.sup.scale*index+base).
[0070] Displacement Field 862A--its content is used as part of
memory address generation (e.g., for address generation that uses
2.sup.scale*index+base+displacement).
[0071] Displacement Factor Field 862B (note that the juxtaposition
of displacement field 862A directly over displacement factor field
862B indicates one or the other is used)--its content is used as
part of address generation; it specifies a displacement factor that
is to be scaled by the size of a memory access (N)--where N is the
number of bytes in the memory access (e.g., for address generation
that uses 2.sup.scale*index+base+scaled displacement). Redundant
low-order bits are ignored and hence, the displacement factor
field's content is multiplied by the memory operands total size (N)
in order to generate the final displacement to be used in
calculating an effective address. The value of N is determined by
the processor hardware at runtime based on the full opcode field
874 (described later herein) and the data manipulation field 854C.
The displacement field 862A and the displacement factor field 862B
are optional in the sense that they are not used for the no memory
access 805 instruction templates and/or different embodiments may
implement only one or none of the two.
[0072] Data element width field 864--its content distinguishes
which one of a number of data element widths is to be used (in some
embodiments for all instructions; in other embodiments for only
some of the instructions). This field is optional in the sense that
it is not needed if only one data element width is supported and/or
data element widths are supported using some aspect of the
opcodes.
[0073] Write mask field 870--its content controls, on a per data
element position basis, whether that data element position in the
destination vector operand reflects the result of the base
operation and augmentation operation. Class A instruction templates
support merging-writemasking, while class B instruction templates
support both merging- and zeroing-writemasking. When merging,
vector masks allow any set of elements in the destination to be
protected from updates during the execution of any operation
(specified by the base operation and the augmentation operation);
in other one embodiment, preserving the old value of each element
of the destination where the corresponding mask bit has a 0. In
contrast, when zeroing vector masks allow any set of elements in
the destination to be zeroed during the execution of any operation
(specified by the base operation and the augmentation operation);
in one embodiment, an element of the destination is set to 0 when
the corresponding mask bit has a 0 value. A subset of this
functionality is the ability to control the vector length of the
operation being performed (that is, the span of elements being
modified, from the first to the last one); however, it is not
necessary that the elements that are modified be consecutive. Thus,
the write mask field 870 allows for partial vector operations,
including loads, stores, arithmetic, logical, etc. While
embodiments of the invention are described in which the write mask
field's 870 content selects one of a number of write mask registers
that contains the write mask to be used (and thus the write mask
field's 870 content indirectly identifies that masking to be
performed), alternative embodiments instead or additional allow the
mask write field's 870 content to directly specify the masking to
be performed.
[0074] Immediate field 872--its content allows for the
specification of an immediate. This field is optional in the sense
that is it not present in an implementation of the generic vector
friendly format that does not support immediate and it is not
present in instructions that do not use an immediate.
[0075] Class field 868--its content distinguishes between different
classes of instructions. With reference to FIGS. 8A-B, the contents
of this field select between class A and class B instructions. In
FIGS. 8A-B, rounded corner squares are used to indicate a specific
value is present in a field (e.g., class A 868A and class B 868B
for the class field 868 respectively in FIGS. 8A-B).
[0076] Instruction Templates of Class A
[0077] In the case of the non-memory access 805 instruction
templates of class A, the alpha field 852 is interpreted as an RS
field 852A, whose content distinguishes which one of the different
augmentation operation types are to be performed (e.g., round
852A.1 and data transform 852A.2 are respectively specified for the
no memory access, round type operation 810 and the no memory
access, data transform type operation 815 instruction templates),
while the beta field 854 distinguishes which of the operations of
the specified type is to be performed. In the no memory access 805
instruction templates, the scale field 860, the displacement field
862A, and the displacement scale filed 862B are not present.
[0078] No-Memory Access Instruction Templates--Full Round Control
Type Operation
[0079] In the no memory access full round control type operation
810 instruction template, the beta field 854 is interpreted as a
round control field 854A, whose content(s) provide static rounding.
While in the described embodiments of the invention the round
control field 854A includes a suppress all floating point
exceptions (SAE) field 856 and a round operation control field 858,
alternative embodiments may support may encode both these concepts
into the same field or only have one or the other of these
concepts/fields (e.g., may have only the round operation control
field 858).
[0080] SAE field 856--its content distinguishes whether or not to
disable the exception event reporting; when the SAE field's 856
content indicates suppression is enabled, a given instruction does
not report any kind of floating-point exception flag and does not
raise any floating point exception handler.
[0081] Round operation control field 858--its content distinguishes
which one of a group of rounding operations to perform (e.g.,
Round-up, Round-down, Round-towards-zero and Round-to-nearest).
Thus, the round operation control field 858 allows for the changing
of the rounding mode on a per instruction basis. In one embodiment
of the invention where a processor includes a control register for
specifying rounding modes, the round operation control field's 850
content overrides that register value.
[0082] No Memory Access Instruction Templates--Data Transform Type
Operation
[0083] In the no memory access data transform type operation 815
instruction template, the beta field 854 is interpreted as a data
transform field 854B, whose content distinguishes which one of a
number of data transforms is to be performed (e.g., no data
transform, swizzle, broadcast).
[0084] In the case of a memory access 820 instruction template of
class A, the alpha field 852 is interpreted as an eviction hint
field 852B, whose content distinguishes which one of the eviction
hints is to be used (in FIG. 8A, temporal 852B.1 and non-temporal
852B.2 are respectively specified for the memory access, temporal
825 instruction template and the memory access, non-temporal 830
instruction template), while the beta field 854 is interpreted as a
data manipulation field 854C, whose content distinguishes which one
of a number of data manipulation operations (also known as
primitives) is to be performed (e.g., no manipulation; broadcast;
up conversion of a source; and down conversion of a destination).
The memory access 820 instruction templates include the scale field
860, and optionally the displacement field 862A or the displacement
scale field 862B.
[0085] Vector memory instructions perform vector loads from and
vector stores to memory, with conversion support. As with regular
vector instructions, vector memory instructions transfer data
from/to memory in a data element-wise fashion, with the elements
that are actually transferred is dictated by the contents of the
vector mask that is selected as the write mask.
[0086] Memory Access Instruction Templates--Temporal
[0087] Temporal data is data likely to be reused soon enough to
benefit from caching. This is, however, a hint, and different
processors may implement it in different ways, including ignoring
the hint entirely.
[0088] Memory Access Instruction Templates--Non-Temporal
[0089] Non-temporal data is data unlikely to be reused soon enough
to benefit from caching in the 1 st-level cache and should be given
priority for eviction. This is, however, a hint, and different
processors may implement it in different ways, including ignoring
the hint entirely.
[0090] Instruction Templates of Class B
[0091] In the case of the instruction templates of class B, the
alpha field 852 is interpreted as a write mask control (Z) field
852C, whose content distinguishes whether the write masking
controlled by the write mask field 870 should be a merging or a
zeroing.
[0092] In the case of the non-memory access 805 instruction
templates of class B, part of the beta field 854 is interpreted as
an RL field 857A, whose content distinguishes which one of the
different augmentation operation types are to be performed (e.g.,
round 857A.1 and vector length (VSIZE) 857A.2 are respectively
specified for the no memory access, write mask control, partial
round control type operation 812 instruction template and the no
memory access, write mask control, VSIZE type operation 817
instruction template), while the rest of the beta field 854
distinguishes which of the operations of the specified type is to
be performed. In the no memory access 805 instruction templates,
the scale field 860, the displacement field 862A, and the
displacement scale filed 862B are not present.
[0093] In the no memory access, write mask control, partial round
control type operation 810 instruction template, the rest of the
beta field 854 is interpreted as a round operation field 859A and
exception event reporting is disabled (a given instruction does not
report any kind of floating-point exception flag and does not raise
any floating point exception handler).
[0094] Round operation control field 859A--just as round operation
control field 858, its content distinguishes which one of a group
of rounding operations to perform (e.g., Round-up, Round-down,
Round-towards-zero and Round-to-nearest). Thus, the round operation
control field 859A allows for the changing of the rounding mode on
a per instruction basis. In one embodiment of the invention where a
processor includes a control register for specifying rounding
modes, the round operation control field's 850 content overrides
that register value.
[0095] In the no memory access, write mask control, VSIZE type
operation 817 instruction template, the rest of the beta field 854
is interpreted as a vector length field 859B, whose content
distinguishes which one of a number of data vector lengths is to be
performed on (e.g., 128, 256, or 512 byte).
[0096] In the case of a memory access 820 instruction template of
class B, part of the beta field 854 is interpreted as a broadcast
field 857B, whose content distinguishes whether or not the
broadcast type data manipulation operation is to be performed,
while the rest of the beta field 854 is interpreted the vector
length field 859B. The memory access 820 instruction templates
include the scale field 860, and optionally the displacement field
862A or the displacement scale field 862B.
[0097] With regard to the generic vector friendly instruction
format 800, a full opcode field 874 is shown including the format
field 840, the base operation field 842, and the data element width
field 864. While one embodiment is shown where the full opcode
field 874 includes all of these fields, the full opcode field 874
includes less than all of these fields in embodiments that do not
support all of them. The full opcode field 874 provides the
operation code (opcode).
[0098] The augmentation operation field 850, the data element width
field 864, and the write mask field 870 allow these features to be
specified on a per instruction basis in the generic vector friendly
instruction format.
[0099] The combination of write mask field and data element width
field create typed instructions in that they allow the mask to be
applied based on different data element widths.
[0100] The various instruction templates found within class A and
class B are beneficial in different situations. In some embodiments
of the invention, different processors or different cores within a
processor may support only class A, only class B, or both classes.
For instance, a high performance general purpose out-of-order core
intended for general-purpose computing may support only class B, a
core intended primarily for graphics and/or scientific (throughput)
computing may support only class A, and a core intended for both
may support both (of course, a core that has some mix of templates
and instructions from both classes but not all templates and
instructions from both classes is within the purview of the
invention). Also, a single processor may include multiple cores,
all of which support the same class or in which different cores
support different class. For instance, in a processor with separate
graphics and general purpose cores, one of the graphics cores
intended primarily for graphics and/or scientific computing may
support only class A, while one or more of the general purpose
cores may be high performance general purpose cores with out of
order execution and register renaming intended for general-purpose
computing that support only class B. Another processor that does
not have a separate graphics core, may include one more general
purpose in-order or out-of-order cores that support both class A
and class B. Of course, features from one class may also be
implement in the other class in different embodiments of the
invention. Programs written in a high level language would be put
(e.g., just in time compiled or statically compiled) into an
variety of different executable forms, including: 1) a form having
only instructions of the class(es) supported by the target
processor for execution; or 2) a form having alternative routines
written using different combinations of the instructions of all
classes and having control flow code that selects the routines to
execute based on the instructions supported by the processor which
is currently executing the code.
[0101] Exemplary Specific Vector Friendly Instruction Format
[0102] FIG. 9 is a block diagram illustrating an exemplary specific
vector friendly instruction format according to embodiments of the
invention. FIG. 9 shows a specific vector friendly instruction
format 900 that is specific in the sense that it specifies the
location, size, interpretation, and order of the fields, as well as
values for some of those fields. The specific vector friendly
instruction format 900 may be used to extend the x86 instruction
set, and thus some of the fields are similar or the same as those
used in the existing x86 instruction set and extension thereof
(e.g., AVX). This format remains consistent with the prefix
encoding field, real opcode byte field, MOD R/M field, SIB field,
displacement field, and immediate fields of the existing x86
instruction set with extensions. The fields from FIG. 8 into which
the fields from FIG. 9 map are illustrated.
[0103] It should be understood that, although embodiments of the
invention are described with reference to the specific vector
friendly instruction format 900 in the context of the generic
vector friendly instruction format 800 for illustrative purposes,
the invention is not limited to the specific vector friendly
instruction format 900 except where claimed. For example, the
generic vector friendly instruction format 800 contemplates a
variety of possible sizes for the various fields, while the
specific vector friendly instruction format 900 is shown as having
fields of specific sizes. By way of specific example, while the
data element width field 864 is illustrated as a one bit field in
the specific vector friendly instruction format 900, the invention
is not so limited (that is, the generic vector friendly instruction
format 800 contemplates other sizes of the data element width field
864).
[0104] The generic vector friendly instruction format 800 includes
the following fields listed below in the order illustrated in FIG.
9A.
[0105] EVEX Prefix (Bytes 0-3) 902--is encoded in a four-byte
form.
[0106] Format Field 840 (EVEX Byte 0, bits [7:0])--the first byte
(EVEX Byte 0) is the format field 840 and it contains 0x62 (the
unique value used for distinguishing the vector friendly
instruction format in one embodiment of the invention).
[0107] The second-fourth bytes (EVEX Bytes 1-3) include a number of
bit fields providing specific capability.
[0108] REX field 905 (EVEX Byte 1, bits [7-5])--consists of a
EVEX.R bit field (EVEX Byte 1, bit [7]--R), EVEX.X bit field (EVEX
byte 1, bit [6]--X), and 657BEX byte 1, bit[5]--B). The EVEX.R,
EVEX.X, and EVEX.B bit fields provide the same functionality as the
corresponding VEX bit fields, and are encoded using is complement
form, i.e. ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B.
Other fields of the instructions encode the lower three bits of the
register indexes as is known in the art (rrr, xxx, and bbb), so
that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX.R, EVEX.X,
and EVEX.B.
[0109] REX' field 810--this is the first part of the REX' field 810
and is the EVEX.R' bit field (EVEX Byte 1, bit [4]--R') that is
used to encode either the upper 16 or lower 16 of the extended 32
register set. In one embodiment of the invention, this bit, along
with others as indicated below, is stored in bit inverted format to
distinguish (in the well-known x86 32-bit mode) from the BOUND
instruction, whose real opcode byte is 82, but does not accept in
the MOD R/M field (described below) the value of 11 in the MOD
field; alternative embodiments of the invention do not store this
and the other indicated bits below in the inverted format. A value
of 1 is used to encode the lower 16 registers. In other words,
R'Rrrr is formed by combining EVEX.R', EVEX.R, and the other RRR
from other fields.
[0110] Opcode map field 915 (EVEX byte 1, bits [3:0]--mmmm)--its
content encodes an implied leading opcode byte (0F, 0F 38, or 0F
3).
[0111] Data element width field 864 (EVEX byte 2, bit [7]--W)--is
represented by the notation EVEX.W. EVEX.W is used to define the
granularity (size) of the datatype (either 32-bit data elements or
64-bit data elements).
[0112] EVEX.vvvv 920 (EVEX Byte 2, bits [6:3]--vvvv)--the role of
EVEX.vvvv may include the following: 1) EVEX.vvvv encodes the first
source register operand, specified in inverted (1s complement) form
and is valid for instructions with 2 or more source operands; 2)
EVEX.vvvv encodes the destination register operand, specified in is
complement form for certain vector shifts; or 3) EVEX.vvvv does not
encode any operand, the field is reserved and should contain 1111b.
Thus, EVEX.vvvv field 920 encodes the 4 low-order bits of the first
source register specifier stored in inverted (1s complement) form.
Depending on the instruction, an extra different EVEX bit field is
used to extend the specifier size to 32 registers.
[0113] EVEX.U 868 Class field (EVEX byte 2, bit [2]--U)--If
EVEX.0=0, it indicates class A or EVEX.U0; if EVEX.0=1, it
indicates class B or EVEX.U1.
[0114] Prefix encoding field 925 (EVEX byte 2, bits
[1:0]--pp)--provides additional bits for the base operation field.
In addition to providing support for the legacy SSE instructions in
the EVEX prefix format, this also has the benefit of compacting the
SIMD prefix (rather than requiring a byte to express the SIMD
prefix, the EVEX prefix requires only 2 bits). In one embodiment,
to support legacy SSE instructions that use a SIMD prefix (66H,
F2H, F3H) in both the legacy format and in the EVEX prefix format,
these legacy SIMD prefixes are encoded into the SIMD prefix
encoding field; and at runtime are expanded into the legacy SIMD
prefix prior to being provided to the decoder's PLA (so the PLA can
execute both the legacy and EVEX format of these legacy
instructions without modification). Although newer instructions
could use the EVEX prefix encoding field's content directly as an
opcode extension, certain embodiments expand in a similar fashion
for consistency but allow for different meanings to be specified by
these legacy SIMD prefixes. An alternative embodiment may redesign
the PLA to support the 2 bit SIMD prefix encodings, and thus not
require the expansion.
[0115] Alpha field 852 (EVEX byte 3, bit [7]--EH; also known as
EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N;
also illustrated with .alpha.)--as previously described, this field
is context specific.
[0116] Beta field 854 (EVEX byte 3, bits [6:4]--SSS, also known as
EVEX.s.sub.2-0, EVEX.r.sub.2-0, EVEX.rr1, EVEX.LL0, EVEX.LLB; also
illustrated with .beta..beta..beta.)--as previously described, this
field is context specific.
[0117] REX' field 810--this is the remainder of the REX' field and
is the EVEX.V' bit field (EVEX Byte 3, bit [3]--V') that may be
used to encode either the upper 16 or lower 16 of the extended 32
register set. This bit is stored in bit inverted format. A value of
1 is used to encode the lower 16 registers. In other words, V' VVVV
is formed by combining EVEX.V', EVEX.vvvv.
[0118] Write mask field 870 (EVEX byte 3, bits [2:0]--kkk)--its
content specifies the index of a register in the write mask
registers as previously described. In one embodiment of the
invention, the specific value EVEX kkk=000 has a special behavior
implying no write mask is used for the particular instruction (this
may be implemented in a variety of ways including the use of a
write mask hardwired to all ones or hardware that bypasses the
masking hardware).
[0119] Real Opcode Field 930 (Byte 4) is also known as the opcode
byte. Part of the opcode is specified in this field.
[0120] MOD R/M Field 940 (Byte 5) includes MOD field 942, Reg field
944, and R/M field 946. As previously described, the MOD field's
942 content distinguishes between memory access and non-memory
access operations. The role of Reg field 944 can be summarized to
two situations: encoding either the destination register operand or
a source register operand, or be treated as an opcode extension and
not used to encode any instruction operand. The role of R/M field
946 may include the following: encoding the instruction operand
that references a memory address, or encoding either the
destination register operand or a source register operand.
[0121] Scale, Index, Base (SIB) Byte (Byte 6)--As previously
described, the scale field's 850 content is used for memory address
generation. SIB.xxx 954 and SIB.bbb 956--the contents of these
fields have been previously referred to with regard to the register
indexes Xxxx and Bbbb.
[0122] Displacement field 862A (Bytes 7-10)--when MOD field 942
contains 10, bytes 9-10 are the displacement field 862A, and it
works the same as the legacy 32-bit displacement (disp32) and works
at byte granularity.
[0123] Displacement factor field 862B (Byte 7)--when MOD field 942
contains 01, byte 7 is the displacement factor field 862B. The
location of this field is that same as that of the legacy x86
instruction set 8-bit displacement (disp8), which works at byte
granularity. Since disp8 is sign extended, it can only address
between -128 and 127 bytes offsets; in terms of 64 byte cache
lines, disp8 uses 8 bits that can be set to only four really useful
values -128, -64, 0, and 64; since a greater range is often needed,
disp32 is used; however, disp32 requires 4 bytes. In contrast to
disp8 and disp32, the displacement factor field 862B is a
reinterpretation of disp8; when using displacement factor field
862B, the actual displacement is determined by the content of the
displacement factor field multiplied by the size of the memory
operand access (N). This type of displacement is referred to as
disp8*N. This reduces the average instruction length (a single byte
of used for the displacement but with a much greater range). Such
compressed displacement is based on the assumption that the
effective displacement is multiple of the granularity of the memory
access, and hence, the redundant low-order bits of the address
offset do not need to be encoded. In other words, the displacement
factor field 862B substitutes the legacy x86 instruction set 8-bit
displacement. Thus, the displacement factor field 862B is encoded
the same way as an x86 instruction set 8-bit displacement (so no
changes in the ModRM/SIB encoding rules) with the only exception
that disp8 is overloaded to disp8*N. In other words, there are no
changes in the encoding rules or encoding lengths but only in the
interpretation of the displacement value by hardware (which needs
to scale the displacement by the size of the memory operand to
obtain a byte-wise address offset).
[0124] Immediate field 872 operates as previously described.
[0125] Full Opcode Field
[0126] FIG. 9B is a block diagram illustrating the fields of the
specific vector friendly instruction format 900 that make up the
full opcode field 874 according to one embodiment of the invention.
Specifically, the full opcode field 874 includes the format field
840, the base operation field 842, and the data element width (W)
field 864. The base operation field 842 includes the prefix
encoding field 925, the opcode map field 915, and the real opcode
field 930.
[0127] Register Index Field
[0128] FIG. 9C is a block diagram illustrating the fields of the
specific vector friendly instruction format 900 that make up the
register index field 844 according to one embodiment of the
invention. Specifically, the register index field 844 includes the
REX field 905, the REX' field 910, the MODR/M.reg field 944, the
MODR/M.r/m field 946, the VVVV field 920, xxx field 954, and the
bbb field 956.
[0129] Augmentation Operation Field
[0130] FIG. 9D is a block diagram illustrating the fields of the
specific vector friendly instruction format 900 that make up the
augmentation operation field 850 according to one embodiment of the
invention. When the class (U) field 868 contains 0, it signifies
EVEX.U0 (class A 868A); when it contains 1, it signifies EVEX.U1
(class B 868B). When U=0 and the MOD field 942 contains 11
(signifying a no memory access operation), the alpha field 852
(EVEX byte 3, bit [7]--EH) is interpreted as the rs field 852A.
When the rs field 852A contains a 1 (round 852A.1), the beta field
854 (EVEX byte 3, bits [6:4]--SSS) is interpreted as the round
control field 854A. The round control field 854A includes a one bit
SAE field 856 and a two bit round operation field 858. When the rs
field 852A contains a 0 (data transform 852A.2), the beta field 854
(EVEX byte 3, bits [6:4]--SSS) is interpreted as a three bit data
transform field 854B. When U=0 and the MOD field 942 contains 00,
01, or 10 (signifying a memory access operation), the alpha field
852 (EVEX byte 3, bit [7]--EH) is interpreted as the eviction hint
(EH) field 852B and the beta field 854 (EVEX byte 3, bits
[6:4]--SSS) is interpreted as a three bit data manipulation field
854C.
[0131] When U=1, the alpha field 852 (EVEX byte 3, bit [7]--EH) is
interpreted as the write mask control (Z) field 852C. When U=1 and
the MOD field 942 contains 11 (signifying a no memory access
operation), part of the beta field 854 (EVEX byte 3, bit
[4]--S.sub.0) is interpreted as the RL field 857A; when it contains
a 1 (round 857A.1) the rest of the beta field 854 (EVEX byte 3, bit
[6-5]--S.sub.2-1) is interpreted as the round operation field 859A,
while when the RL field 857A contains a 0 (VSIZE 857.A2) the rest
of the beta field 854 (EVEX byte 3, bit [6-5]--S.sub.2-1) is
interpreted as the vector length field 859B (EVEX byte 3, bit
[6-5]--L.sub.1-0). When U=1 and the MOD field 942 contains 00, 01,
or 10 (signifying a memory access operation), the beta field 854
(EVEX byte 3, bits [6:4]--SSS) is interpreted as the vector length
field 859B (EVEX byte 3, bit [6-5]--L.sub.1-0) and the broadcast
field 857B (EVEX byte 3, bit [4]--B).
[0132] Exemplary Register Architecture
[0133] FIG. 10 is a block diagram of a register architecture 1000
according to one embodiment of the invention. In the embodiment
illustrated, there are 32 vector registers 1010 that are 512 bits
wide; these registers are referenced as zmm0 through zmm31. The
lower order 256 bits of the lower 16 zmm registers are overlaid on
registers ymm0-16. The lower order 128 bits of the lower 16 zmm
registers (the lower order 128 bits of the ymm registers) are
overlaid on registers xmm0-15. The specific vector friendly
instruction format 900 operates on these overlaid register file as
illustrated in the below tables.
TABLE-US-00001 Adjustable Vector Length Class Operations Registers
Instruction A (FIG. 8A; 810, 815, 825, zmm registers Templates that
U = 0) 830 (the vector do not include length is 64 byte) the vector
length B (FIG. 8B; 812 zmm registers field 859B U = 1) (the vector
length is 84 byte) Instruction B (FIG. 8B; 817, 827 zmm, ymm, or
Templates that U = 1) xmm registers do include the (the vector
vector length length is 64 byte, field 859B 32 byte, or 16 byte)
depending on the vector length field 859B
[0134] In other words, the vector length field 859B selects between
a maximum length and one or more other shorter lengths, where each
such shorter length is half the length of the preceding length; and
instructions templates without the vector length field 859B operate
on the maximum vector length. Further, in one embodiment, the class
B instruction templates of the specific vector friendly instruction
format 900 operate on packed or scalar single/double-precision
floating point data and packed or scalar integer data. Scalar
operations are operations performed on the lowest order data
element position in an zmm/ymm/xmm register; the higher order data
element positions are either left the same as they were prior to
the instruction or zeroed depending on the embodiment.
[0135] Write mask registers 1015--in the embodiment illustrated,
there are 8 write mask registers (k0 through k7), each 64 bits in
size. In an alternate embodiment, the write mask registers 815 are
16 bits in size. As previously described, in one embodiment of the
invention, the vector mask register k0 cannot be used as a write
mask; when the encoding that would normally indicate k0 is used for
a write mask, it selects a hardwired write mask of 0xFFFF,
effectively disabling write masking for that instruction.
[0136] General-purpose registers 1025--in the embodiment
illustrated, there are sixteen 64-bit general-purpose registers
that are used along with the existing x86 addressing modes to
address memory operands. These registers are referenced by the
names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through
R15.
[0137] Scalar floating point stack register file (x87 stack) 1045,
on which is aliased the MMX packed integer flat register file
1050--in the embodiment illustrated, the x87 stack is an
eight-element stack used to perform scalar floating-point
operations on 32/64/80-bit floating point data using the x87
instruction set extension; while the MMX registers are used to
perform operations on 64-bit packed integer data, as well as to
hold operands for some operations performed between the MMX and XMM
registers.
[0138] Alternative embodiments of the invention may use wider or
narrower registers. Additionally, alternative embodiments of the
invention may use more, less, or different register files and
registers.
[0139] Exemplary Core Architectures, Processors, and Computer
Architectures
[0140] Processor cores may be implemented in different ways, for
different purposes, and in different processors. For instance,
implementations of such cores may include: 1) a general purpose
in-order core intended for general-purpose computing; 2) a high
performance general purpose out-of-order core intended for
general-purpose computing; 3) a special purpose core intended
primarily for graphics and/or scientific (throughput) computing.
Implementations of different processors may include: 1) a CPU
including one or more general purpose in-order cores intended for
general-purpose computing and/or one or more general purpose
out-of-order cores intended for general-purpose computing; and 2) a
coprocessor including one or more special purpose cores intended
primarily for graphics and/or scientific (throughput). Such
different processors lead to different computer system
architectures, which may include: 1) the coprocessor on a separate
chip from the CPU; 2) the coprocessor on a separate die in the same
package as a CPU; 3) the coprocessor on the same die as a CPU (in
which case, such a coprocessor is sometimes referred to as special
purpose logic, such as integrated graphics and/or scientific
(throughput) logic, or as special purpose cores); and 4) a system
on a chip that may include on the same die the described CPU
(sometimes referred to as the application core(s) or application
processor(s)), the above described coprocessor, and additional
functionality. Exemplary core architectures are described next,
followed by descriptions of exemplary processors and computer
architectures.
[0141] Exemplary Core Architectures
[0142] In-Order and Out-of-Order Core Block Diagram
[0143] FIG. 11A is a block diagram illustrating both an exemplary
in-order pipeline and an exemplary register renaming, out-of-order
issue/execution pipeline according to embodiments of the invention.
FIG. 11B is a block diagram illustrating both an exemplary
embodiment of an in-order architecture core and an exemplary
register renaming, out-of-order issue/execution architecture core
to be included in a processor according to embodiments of the
invention. The solid lined boxes in FIGS. 11A-B illustrate the
in-order pipeline and in-order core, while the optional addition of
the dashed lined boxes illustrates the register renaming,
out-of-order issue/execution pipeline and core. Given that the
in-order aspect is a subset of the out-of-order aspect, the
out-of-order aspect will be described.
[0144] In FIG. 11A, a processor pipeline 1100 includes a fetch
stage 1102, a length decode stage 1104, a decode stage 1106, an
allocation stage 1108, a renaming stage 1110, a scheduling (also
known as a dispatch or issue) stage 1112, a register read/memory
read stage 1114, an execute stage 1116, a write back/memory write
stage 1118, an exception handling stage 1122, and a commit stage
1124.
[0145] FIG. 11B shows processor core 11110 including a front end
unit 1130 coupled to an execution engine unit 1150, and both are
coupled to a memory unit 1170. The core 1190 may be a reduced
instruction set computing (RISC) core, a complex instruction set
computing (CISC) core, a very long instruction word (VLIW) core, or
a hybrid or alternative core type. As yet another option, the core
1190 may be a special-purpose core, such as, for example, a network
or communication core, compression engine, coprocessor core,
general purpose computing graphics processing unit (GPGPU) core,
graphics core, or the like.
[0146] The front end unit 1130 includes a branch prediction unit
1132 coupled to an instruction cache unit 1134, which is coupled to
an instruction translation lookaside buffer (TLB) 1136, which is
coupled to an instruction fetch unit 1138, which is coupled to a
decode unit 1140. The decode unit 1140 (or decoder) may decode
instructions, and generate as an output one or more
micro-operations, micro-code entry points, microinstructions, other
instructions, or other control signals, which are decoded from, or
which otherwise reflect, or are derived from, the original
instructions. The decode unit 1140 may be implemented using various
different mechanisms. Examples of suitable mechanisms include, but
are not limited to, look-up tables, hardware implementations,
programmable logic arrays (PLAs), microcode read only memories
(ROMs), etc. In one embodiment, the core 1190 includes a microcode
ROM or other medium that stores microcode for certain
macroinstructions (e.g., in decode unit 1140 or otherwise within
the front end unit 1130). The decode unit 1140 is coupled to a
rename/allocator unit 1152 in the execution engine unit 1150.
[0147] The execution engine unit 1150 includes the rename/allocator
unit 1152 coupled to a retirement unit 1154 and a set of one or
more scheduler unit(s) 1156. The scheduler unit(s) 1156 represents
any number of different schedulers, including reservations
stations, central instruction window, etc. The scheduler unit(s)
1156 is coupled to the physical register file(s) unit(s) 1158. Each
of the physical register file(s) units 1158 represents one or more
physical register files, different ones of which store one or more
different data types, such as scalar integer, scalar floating
point, packed integer, packed floating point, vector integer,
vector floating point, status (e.g., an instruction pointer that is
the address of the next instruction to be executed), etc. In one
embodiment, the physical register file(s) unit 1158 comprises a
vector registers unit, a write mask registers unit, and a scalar
registers unit. These register units may provide architectural
vector registers, vector mask registers, and general purpose
registers. The physical register file(s) unit(s) 1158 is overlapped
by the retirement unit 1154 to illustrate various ways in which
register renaming and out-of-order execution may be implemented
(e.g., using a reorder buffer(s) and a retirement register file(s);
using a future file(s), a history buffer(s), and a retirement
register file(s); using a register maps and a pool of registers;
etc.). The retirement unit 1154 and the physical register file(s)
unit(s) 1158 are coupled to the execution cluster(s) 1160. The
execution cluster(s) 1160 includes a set of one or more execution
units 1162 and a set of one or more memory access units 1164. The
execution units 1162 may perform various operations (e.g., shifts,
addition, subtraction, multiplication) and on various types of data
(e.g., scalar floating point, packed integer, packed floating
point, vector integer, vector floating point). While some
embodiments may include a number of execution units dedicated to
specific functions or sets of functions, other embodiments may
include only one execution unit or multiple execution units that
all perform all functions. The scheduler unit(s) 1156, physical
register file(s) unit(s) 1158, and execution cluster(s) 1160 are
shown as being possibly plural because certain embodiments create
separate pipelines for certain types of data/operations (e.g., a
scalar integer pipeline, a scalar floating point/packed
integer/packed floating point/vector integer/vector floating point
pipeline, and/or a memory access pipeline that each have their own
scheduler unit, physical register file(s) unit, and/or execution
cluster--and in the case of a separate memory access pipeline,
certain embodiments are implemented in which only the execution
cluster of this pipeline has the memory access unit(s) 1164). It
should also be understood that where separate pipelines are used,
one or more of these pipelines may be out-of-order issue/execution
and the rest in-order.
[0148] The set of memory access units 1164 is coupled to the memory
unit 1170, which includes a data TLB unit 1172 coupled to a data
cache unit 1174 coupled to a level 2 (L2) cache unit 1176. In one
exemplary embodiment, the memory access units 1164 may include a
load unit, a store address unit, and a store data unit, each of
which is coupled to the data TLB unit 1172 in the memory unit 1170.
The instruction cache unit 1134 is further coupled to a level 2
(L2) cache unit 1176 in the memory unit 1170. The L2 cache unit
1176 is coupled to one or more other levels of cache and eventually
to a main memory.
[0149] By way of example, the exemplary register renaming,
out-of-order issue/execution core architecture may implement the
pipeline 1100 as follows: 1) the instruction fetch 1138 performs
the fetch and length decoding stages 1102 and 1104; 2) the decode
unit 1140 performs the decode stage 1106; 3) the rename/allocator
unit 1152 performs the allocation stage 1108 and renaming stage
1110; 4) the scheduler unit(s) 1156 performs the schedule stage
1112; 5) the physical register file(s) unit(s) 1158 and the memory
unit 1170 perform the register read/memory read stage 1114; the
execution cluster 1160 perform the execute stage 1116; 6) the
memory unit 1170 and the physical register file(s) unit(s) 1158
perform the write back/memory write stage 1118; 7) various units
may be involved in the exception handling stage 1122; and 8) the
retirement unit 1154 and the physical register file(s) unit(s) 1158
perform the commit stage 1124.
[0150] The core 1190 may support one or more instructions sets
(e.g., the x86 instruction set (with some extensions that have been
added with newer versions); the MIPS instruction set of MIPS
Technologies of Sunnyvale, Calif.; the ARM instruction set (with
optional additional extensions such as NEON) of ARM Holdings of
Sunnyvale, Calif.), including the instruction(s) described herein.
In one embodiment, the core 1190 includes logic to support a packed
data instruction set extension (e.g., AVX1, AVX2, and/or some form
of the generic vector friendly instruction format (U=0 and/or U=1)
previously described), thereby allowing the operations used by many
multimedia applications to be performed using packed data.
[0151] It should be understood that the core may support
multithreading (executing two or more parallel sets of operations
or threads), and may do so in a variety of ways including time
sliced multithreading, simultaneous multithreading (where a single
physical core provides a logical core for each of the threads that
physical core is simultaneously multithreading), or a combination
thereof (e.g., time sliced fetching and decoding and simultaneous
multithreading thereafter such as in the Intel.RTM. Hyperthreading
technology).
[0152] While register renaming is described in the context of
out-of-order execution, it should be understood that register
renaming may be used in an in-order architecture. While the
illustrated embodiment of the processor also includes separate
instruction and data cache units 1134/1174 and a shared L2 cache
unit 1176, alternative embodiments may have a single internal cache
for both instructions and data, such as, for example, a Level 1
(L1) internal cache, or multiple levels of internal cache. In some
embodiments, the system may include a combination of an internal
cache and an external cache that is external to the core and/or the
processor. Alternatively, all of the cache may be external to the
core and/or the processor.
[0153] Specific Exemplary In-Order Core Architecture
[0154] FIGS. 12A-B illustrate a block diagram of a more specific
exemplary in-order core architecture, which core would be one of
several logic blocks (including other cores of the same type and/or
different types) in a chip. The logic blocks communicate through a
high-bandwidth interconnect network (e.g., a ring network) with
some fixed function logic, memory I/O interfaces, and other
necessary I/O logic, depending on the application.
[0155] FIG. 12A is a block diagram of a single processor core,
along with its connection to the on-die interconnect network 1202
and with its local subset of the Level 2 (L2) cache 1204, according
to embodiments of the invention. In one embodiment, an instruction
decoder 1200 supports the x86 instruction set with a packed data
instruction set extension. An L1 cache 1206 allows low-latency
accesses to cache memory into the scalar and vector units. While in
one embodiment (to simplify the design), a scalar unit 1208 and a
vector unit 1210 use separate register sets (respectively, scalar
registers 1212 and vector registers 1214) and data transferred
between them is written to memory and then read back in from a
level 1 (L1) cache 1206, alternative embodiments of the invention
may use a different approach (e.g., use a single register set or
include a communication path that allow data to be transferred
between the two register files without being written and read
back).
[0156] The local subset of the L2 cache 1204 is part of a global L2
cache that is divided into separate local subsets, one per
processor core. Each processor core has a direct access path to its
own local subset of the L2 cache 1204. Data read by a processor
core is stored in its L2 cache subset 1204 and can be accessed
quickly, in parallel with other processor cores accessing their own
local L2 cache subsets. Data written by a processor core is stored
in its own L2 cache subset 1204 and is flushed from other subsets,
if necessary. The ring network ensures coherency for shared data.
The ring network is bi-directional to allow agents such as
processor cores, L2 caches and other logic blocks to communicate
with each other within the chip. Each ring data-path is 1212-bits
wide per direction.
[0157] FIG. 12B is an expanded view of part of the processor core
in FIG. 12A according to embodiments of the invention. FIG. 12B
includes an L1 data cache 1206A part of the L1 cache 1204, as well
as more detail regarding the vector unit 1210 and the vector
registers 1214. Specifically, the vector unit 1210 is a 16-wide
vector processing unit (VPU) (see the 16-wide ALU 1228), which
executes one or more of integer, single-precision float, and
double-precision float instructions. The VPU supports swizzling the
register inputs with swizzle unit 1220, numeric conversion with
numeric convert units 1222A-B, and replication with replication
unit 1224 on the memory input. Write mask registers 1226 allow
predicating resulting vector writes.
[0158] Processor with Integrated Memory Controller and Graphics
[0159] FIG. 13 is a block diagram of a processor 1300 that may have
more than one core, may have an integrated memory controller, and
may have integrated graphics according to embodiments of the
invention. The solid lined boxes in FIG. 13 illustrate a processor
1300 with a single core 1302A, a system agent 1310, a set of one or
more bus controller units 1316, while the optional addition of the
dashed lined boxes illustrates an alternative processor 1300 with
multiple cores 1302A-N, a set of one or more integrated memory
controller unit(s) 1314 in the system agent unit 1310, and special
purpose logic 1308.
[0160] Thus, different implementations of the processor 1300 may
include: 1) a CPU with the special purpose logic 1308 being
integrated graphics and/or scientific (throughput) logic (which may
include one or more cores), and the cores 1302A-N being one or more
general purpose cores (e.g., general purpose in-order cores,
general purpose out-of-order cores, a combination of the two); 2) a
coprocessor with the cores 1302A-N being a large number of special
purpose cores intended primarily for graphics and/or scientific
(throughput); and 3) a coprocessor with the cores 1302A-N being a
large number of general purpose in-order cores. Thus, the processor
1300 may be a general-purpose processor, coprocessor or
special-purpose processor, such as, for example, a network or
communication processor, compression engine, graphics processor,
GPGPU (general purpose graphics processing unit), a high-throughput
many integrated core (MIC) coprocessor (including 30 or more
cores), embedded processor, or the like. The processor may be
implemented on one or more chips. The processor 1300 may be a part
of and/or may be implemented on one or more substrates using any of
a number of process technologies, such as, for example, BiCMOS,
CMOS, or NMOS.
[0161] The memory hierarchy includes one or more levels of cache
within the cores, a set or one or more shared cache units 1306, and
external memory (not shown) coupled to the set of integrated memory
controller units 1314. The set of shared cache units 1306 may
include one or more mid-level caches, such as level 2 (L2), level 3
(L3), level 4 (L4), or other levels of cache, a last level cache
(LLC), and/or combinations thereof. While in one embodiment a ring
based interconnect unit 1312 interconnects the integrated graphics
logic 1308, the set of shared cache units 1306, and the system
agent unit 1310/integrated memory controller unit(s) 1314,
alternative embodiments may use any number of well-known techniques
for interconnecting such units. In one embodiment, coherency is
maintained between one or more cache units 1306 and cores
1302-A-N.
[0162] In some embodiments, one or more of the cores 1302A-N are
capable of multi-threading. The system agent 1310 includes those
components coordinating and operating cores 1302A-N. The system
agent unit 1310 may include for example a power control unit (PCU)
and a display unit. The PCU may be or include logic and components
needed for regulating the power state of the cores 1302A-N and the
integrated graphics logic 1308. The display unit is for driving one
or more externally connected displays.
[0163] The cores 1302A-N may be homogenous or heterogeneous in
terms of architecture instruction set; that is, two or more of the
cores 1302A-N may be capable of execution the same instruction set,
while others may be capable of executing only a subset of that
instruction set or a different instruction set.
[0164] Exemplary Computer Architectures
[0165] FIGS. 14-17 are block diagrams of exemplary computer
architectures. Other system designs and configurations known in the
arts for laptops, desktops, handheld PCs, personal digital
assistants, engineering workstations, servers, network devices,
network hubs, switches, embedded processors, digital signal
processors (DSPs), graphics devices, video game devices, set-top
boxes, micro controllers, cell phones, portable media players, hand
held devices, and various other electronic devices, are also
suitable. In general, a huge variety of systems or electronic
devices capable of incorporating a processor and/or other execution
logic as disclosed herein are generally suitable.
[0166] Referring now to FIG. 14, shown is a block diagram of a
system 1400 in accordance with one embodiment of the present
invention. The system 1400 may include one or more processors 1410,
1415, which are coupled to a controller hub 1420. In one embodiment
the controller hub 1420 includes a graphics memory controller hub
(GMCH) 1490 and an Input/Output Hub (IOH) 1450 (which may be on
separate chips); the GMCH 1490 includes memory and graphics
controllers to which are coupled memory 1440 and a coprocessor
1445; the IOH 1450 is couples input/output (I/O) devices 1460 to
the GMCH 1490. Alternatively, one or both of the memory and
graphics controllers are integrated within the processor (as
described herein), the memory 1440 and the coprocessor 1445 are
coupled directly to the processor 1410, and the controller hub 1420
in a single chip with the IOH 1450.
[0167] The optional nature of additional processors 1415 is denoted
in FIG. 14 with broken lines. Each processor 1410, 1415 may include
one or more of the processing cores described herein and may be
some version of the processor 1300.
[0168] The memory 1440 may be, for example, dynamic random access
memory (DRAM), phase change memory (PCM), or a combination of the
two. For at least one embodiment, the controller hub 1420
communicates with the processor(s) 1410, 1415 via a multi-drop bus,
such as a frontside bus (FSB), point-to-point interface such as
QuickPath Interconnect (QPI), or similar connection 1495.
[0169] In one embodiment, the coprocessor 1445 is a special-purpose
processor, such as, for example, a high-throughput MIC processor, a
network or communication processor, compression engine, graphics
processor, GPGPU, embedded processor, or the like. In one
embodiment, controller hub 1420 may include an integrated graphics
accelerator.
[0170] There can be a variety of differences between the physical
resources 1410, 1415 in terms of a spectrum of metrics of merit
including architectural, microarchitectural, thermal, power
consumption characteristics, and the like.
[0171] In one embodiment, the processor 1410 executes instructions
that control data processing operations of a general type. Embedded
within the instructions may be coprocessor instructions. The
processor 1410 recognizes these coprocessor instructions as being
of a type that should be executed by the attached coprocessor 1445.
Accordingly, the processor 1410 issues these coprocessor
instructions (or control signals representing coprocessor
instructions) on a coprocessor bus or other interconnect, to
coprocessor 1445. Coprocessor(s) 1445 accept and execute the
received coprocessor instructions.
[0172] Referring now to FIG. 15, shown is a block diagram of a
first more specific exemplary system 1500 in accordance with an
embodiment of the present invention. As shown in FIG. 15,
multiprocessor system 1500 is a point-to-point interconnect system,
and includes a first processor 1570 and a second processor 1580
coupled via a point-to-point interconnect 1550. Each of processors
1570 and 1580 may be some version of the processor 1300. In one
embodiment of the invention, processors 1570 and 1580 are
respectively processors 1410 and 1415, while coprocessor 1538 is
coprocessor 1445. In another embodiment, processors 1570 and 1580
are respectively processor 1410 coprocessor 1445.
[0173] Processors 1570 and 1580 are shown including integrated
memory controller (IMC) units 1572 and 1582, respectively.
Processor 1570 also includes as part of its bus controller units
point-to-point (P-P) interfaces 1576 and 1578; similarly, second
processor 1580 includes P-P interfaces 1586 and 1588. Processors
1570, 1580 may exchange information via a point-to-point (P-P)
interface 1550 using P-P interface circuits 1578, 1588. As shown in
FIG. 15, IMCs 1572 and 1582 couple the processors to respective
memories, namely a memory 1532 and a memory 1534, which may be
portions of main memory locally attached to the respective
processors.
[0174] Processors 1570, 1580 may each exchange information with a
chipset 1590 via individual P-P interfaces 1552, 1554 using point
to point interface circuits 1576, 1594, 1586, 1598. Chipset 1590
may optionally exchange information with the coprocessor 1538 via a
high-performance interface 1539. In one embodiment, the coprocessor
1538 is a special-purpose processor, such as, for example, a
high-throughput MIC processor, a network or communication
processor, compression engine, graphics processor, GPGPU, embedded
processor, or the like.
[0175] A shared cache (not shown) may be included in either
processor or outside of both processors, yet connected with the
processors via P-P interconnect, such that either or both
processors' local cache information may be stored in the shared
cache if a processor is placed into a low power mode.
[0176] Chipset 1590 may be coupled to a first bus 1516 via an
interface 1596. In one embodiment, first bus 1516 may be a
Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI
Express bus or another third generation I/O interconnect bus,
although the scope of the present invention is not so limited.
[0177] As shown in FIG. 15, various I/O devices 1514 may be coupled
to first bus 1516, along with a bus bridge 1518 which couples first
bus 1516 to a second bus 1520. In one embodiment, one or more
additional processor(s) 1515, such as coprocessors, high-throughput
MIC processors, GPGPU's, accelerators (such as, e.g., graphics
accelerators or digital signal processing (DSP) units), field
programmable gate arrays, or any other processor, are coupled to
first bus 1516. In one embodiment, second bus 1520 may be a low pin
count (LPC) bus. Various devices may be coupled to a second bus
1520 including, for example, a keyboard and/or mouse 1522,
communication devices 1527 and a storage unit 1528 such as a disk
drive or other mass storage device which may include
instructions/code and data 1530, in one embodiment. Further, an
audio I/O 1524 may be coupled to the second bus 1520. Note that
other architectures are possible. For example, instead of the
point-to-point architecture of FIG. 15, a system may implement a
multi-drop bus or other such architecture.
[0178] Referring now to FIG. 16, shown is a block diagram of a
second more specific exemplary system 1600 in accordance with an
embodiment of the present invention Like elements in FIGS. 15 and
16 bear like reference numerals, and certain aspects of FIG. 15
have been omitted from FIG. 16 in order to avoid obscuring other
aspects of FIG. 16.
[0179] FIG. 16 illustrates that the processors 1570, 1580 may
include integrated memory and 110 control logic ("CL") 1572 and
1582, respectively. Thus, the CL 1572, 1582 include integrated
memory controller units and include I/O control logic. FIG. 16
illustrates that not only are the memories 1532, 1534 coupled to
the CL 1572, 1582, but also that I/O devices 1614 are also coupled
to the control logic 1572, 1582. Legacy I/O devices 1615 are
coupled to the chipset 1590.
[0180] Referring now to FIG. 17, shown is a block diagram of a SoC
1700 in accordance with an embodiment of the present invention.
Similar elements in FIG. 13 bear like reference numerals. Also,
dashed lined boxes are optional features on more advanced SoCs. In
FIG. 17, an interconnect unit(s) 1702 is coupled to: an application
processor 1710 which includes a set of one or more cores 202A-N and
shared cache unit(s) 1306; a system agent unit 1310; a bus
controller unit(s) 1316; an integrated memory controller unit(s)
1314; a set or one or more coprocessors 1720 which may include
integrated graphics logic, an image processor, an audio processor,
and a video processor; an static random access memory (SRAM) unit
1730; a direct memory access (DMA) unit 1732; and a display unit
1740 for coupling to one or more external displays. In one
embodiment, the coprocessor(s) 1720 include a special-purpose
processor, such as, for example, a network or communication
processor, compression engine, GPGPU, a high-throughput MIC
processor, embedded processor, or the like.
[0181] Embodiments of the mechanisms disclosed herein may be
implemented in hardware, software, firmware, or a combination of
such implementation approaches. Embodiments of the invention may be
implemented as computer programs or program code executing on
programmable systems comprising at least one processor, a storage
system (including volatile and non-volatile memory and/or storage
elements), at least one input device, and at least one output
device.
[0182] Program code, such as code 1730 illustrated in FIG. 17, may
be applied to input instructions to perform the functions described
herein and generate output information. The output information may
be applied to one or more output devices, in known fashion. For
purposes of this application, a processing system includes any
system that has a processor, such as, for example; a digital signal
processor (DSP), a microcontroller, an application specific
integrated circuit (ASIC), or a microprocessor.
[0183] The program code may be implemented in a high level
procedural or object oriented programming language to communicate
with a processing system. The program code may also be implemented
in assembly or machine language, if desired. In fact, the
mechanisms described herein are not limited in scope to any
particular programming language. In any case, the language may be a
compiled or interpreted language.
[0184] One or more aspects of at least one embodiment may be
implemented by representative instructions stored on a
machine-readable medium which represents various logic within the
processor, which when read by a machine causes the machine to
fabricate logic to perform the techniques described herein. Such
representations, known as "IP cores" may be stored on a tangible,
machine readable medium and supplied to various customers or
manufacturing facilities to load into the fabrication machines that
actually make the logic or processor.
[0185] Such machine-readable storage media may include, without
limitation, non-transitory, tangible arrangements of articles
manufactured or formed by a machine or device, including storage
media such as hard disks, any other type of disk including floppy
disks, optical disks, compact disk read-only memories (CD-ROMs),
compact disk rewritable's (CD-RWs), and magneto-optical disks,
semiconductor devices such as read-only memories (ROMs), random
access memories (RAMs) such as dynamic random access memories
(DRAMs), static random access memories (SRAMs), erasable
programmable read-only memories (EPROMs), flash memories,
electrically erasable programmable read-only memories (EEPROMs),
phase change memory (PCM), magnetic or optical cards, or any other
type of media suitable for storing electronic instructions.
[0186] Accordingly, embodiments of the invention also include
non-transitory, tangible machine-readable media containing
instructions or containing design data, such as Hardware
Description Language (HDL), which defines structures, circuits,
apparatuses, processors and/or system features described herein.
Such embodiments may also be referred to as program products.
[0187] Emulation (Including Binary Translation, Code Morphing,
Etc.)
[0188] In some cases, an instruction converter may be used to
convert an instruction from a source instruction set to a target
instruction set. For example, the instruction converter may
translate (e.g., using static binary translation, dynamic binary
translation including dynamic compilation), morph, emulate, or
otherwise convert an instruction to one or more other instructions
to be processed by the core. The instruction converter may be
implemented in software, hardware, firmware, or a combination
thereof. The instruction converter may be on processor, off
processor, or part on and part off processor.
[0189] FIG. 18 is a block diagram contrasting the use of a software
instruction converter to convert binary instructions in a source
instruction set to binary instructions in a target instruction set
according to embodiments of the invention. In the illustrated
embodiment, the instruction converter is a software instruction
converter, although alternatively the instruction converter may be
implemented in software, firmware, hardware, or various
combinations thereof. FIG. 18 shows a program in a high level
language 1802 may be compiled using an x86 compiler 1804 to
generate x86 binary code 1806 that may be natively executed by a
processor with at least one x86 instruction set core 1816. The
processor with at least one x86 instruction set core 1816
represents any processor that can perform substantially the same
functions as an Intel processor with at least one x86 instruction
set core by compatibly executing or otherwise processing (1) a
substantial portion of the instruction set of the Intel x86
instruction set core or (2) object code versions of applications or
other software targeted to run on an Intel processor with at least
one x86 instruction set core, in order to achieve substantially the
same result as an Intel processor with at least one x86 instruction
set core. The x86 compiler 1804 represents a compiler that is
operable to generate x86 binary code 1806 (e.g., object code) that
can, with or without additional linkage processing, be executed on
the processor with at least one x86 instruction set core 1816.
Similarly, FIG. 18 shows the program in the high level language
1802 may be compiled using an alternative instruction set compiler
1808 to generate alternative instruction set binary code 1810 that
may be natively executed by a processor without at least one x86
instruction set core 1814 (e.g., a processor with cores that
execute the MIPS instruction set of MIPS Technologies of Sunnyvale,
Calif. and/or that execute the ARM instruction set of ARM Holdings
of Sunnyvale, Calif.). The instruction converter 1812 is used to
convert the x86 binary code 1806 into code that may be natively
executed by the processor without an x86 instruction set core 1814.
This converted code is not likely to be the same as the alternative
instruction set binary code 1810 because an instruction converter
capable of this is difficult to make; however, the converted code
will accomplish the general operation and be made up of
instructions from the alternative instruction set. Thus, the
instruction converter 1812 represents software, firmware, hardware,
or a combination thereof that, through emulation, simulation or any
other process, allows a processor or other electronic device that
does not have an x86 instruction set processor or core to execute
the x86 binary code 1806.
* * * * *