U.S. patent application number 15/324011 was filed with the patent office on 2017-07-20 for semiconductor device.
This patent application is currently assigned to Mitsubishi Electric Corporation. The applicant listed for this patent is Mitsubishi Electric Corporation. Invention is credited to Kiyoshi ARAI, Yumie KITAJIMA, Tatunori YANAGIMOTO.
Application Number | 20170207179 15/324011 |
Document ID | / |
Family ID | 55398958 |
Filed Date | 2017-07-20 |
United States Patent
Application |
20170207179 |
Kind Code |
A1 |
KITAJIMA; Yumie ; et
al. |
July 20, 2017 |
SEMICONDUCTOR DEVICE
Abstract
An object of the present invention is to obtain a semiconductor
device having highly reliable bonding portions. The semiconductor
device according to the present invention includes an insulating
substrate on which a conductive pattern is formed, and an electrode
terminal and a semiconductor element which are bonded to the
conductive pattern, the electrode terminal and the conductive
pattern are bonded by ultrasonic bonding on a bonding face, and the
ultrasonic bonding is performed at a plurality of positions.
Inventors: |
KITAJIMA; Yumie; (Tokyo,
JP) ; YANAGIMOTO; Tatunori; (Tokyo, JP) ;
ARAI; Kiyoshi; (Tokyo, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Mitsubishi Electric Corporation |
Tokyo |
|
JP |
|
|
Assignee: |
Mitsubishi Electric
Corporation
Tokyo
JP
|
Family ID: |
55398958 |
Appl. No.: |
15/324011 |
Filed: |
August 28, 2014 |
PCT Filed: |
August 28, 2014 |
PCT NO: |
PCT/JP2014/072594 |
371 Date: |
January 5, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/29 20130101;
H01L 2224/8384 20130101; H01L 2224/45424 20130101; H01L 2924/12032
20130101; H01L 23/49558 20130101; H01L 23/562 20130101; H01L
2224/45147 20130101; H01L 2224/73265 20130101; H01L 2924/13091
20130101; H01L 21/4839 20130101; H01L 23/3735 20130101; H01L
2224/48091 20130101; H01L 2224/32245 20130101; H01L 2224/45015
20130101; H01L 24/48 20130101; H01L 2224/45147 20130101; H01L
2224/45124 20130101; H01L 2224/73265 20130101; H01L 2924/10253
20130101; H01L 2224/29139 20130101; H01L 2924/181 20130101; H01L
2224/45014 20130101; H01L 2224/48091 20130101; H01L 2224/291
20130101; H01L 24/45 20130101; H01L 2224/45124 20130101; H01L
25/072 20130101; H01L 2224/291 20130101; H01L 2224/45014 20130101;
H01L 2224/48247 20130101; H01L 2224/48137 20130101; H01L 2924/00012
20130101; H01L 2924/00012 20130101; H01L 2924/014 20130101; H01L
2924/00014 20130101; H01L 2924/00014 20130101; H01L 2224/48247
20130101; H01L 2924/00014 20130101; H01L 24/32 20130101; H01L 25/18
20130101; H01L 2924/181 20130101; H01L 24/73 20130101; H01L
2924/10272 20130101; H01L 23/49517 20130101; H01L 23/49811
20130101; H01L 2224/45015 20130101; H01L 2224/73265 20130101; H01L
21/4825 20130101; H01L 2924/13055 20130101; H01L 23/24 20130101;
H01L 24/83 20130101; H01L 2224/32225 20130101; H01L 2924/1033
20130101; H01L 2224/32245 20130101; H01L 2924/00014 20130101; H01L
2224/32225 20130101; H01L 2924/00012 20130101; H01L 2924/206
20130101; H01L 2924/2076 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; H01L 21/48 20060101 H01L021/48; H01L 23/495 20060101
H01L023/495 |
Claims
1. A semiconductor device comprising: an insulating substrate on
which a conductive pattern is formed; and an electrode terminal and
a semiconductor element that are bonded to the conductive pattern,
wherein the electrode terminal and the conductive pattern are
bonded together by ultrasonic bonding through at least one bonding
face, and the ultrasonic bonding is performed at a plurality of
positions.
2. The semiconductor device according to claim 1, wherein the at
least one bonding face is one bonding face, and the ultrasonic
bonding is performed at a plurality of positions on the one bonding
face.
3. The semiconductor device according to claim 1, wherein the at
least one bonding face is a plurality of bonding faces, a root of
the electrode terminal is divided, the divided root forms the
plurality of bonding faces, and each of the plurality of bonding
faces includes at least one position subjected to the ultrasonic
bonding.
4. The semiconductor device according to claim 3, wherein the
electrode terminal is a flat plate, and the root of the electrode
terminal is divided in the thickness direction or in the width
direction.
5. The semiconductor device according to claim 3, wherein the root
of the electrode terminal is divided into two, three, or four
branches.
6. The semiconductor device according to claim 4, wherein the root
of the electrode terminal is divided into two, three, or four
branches.
7. The semiconductor device according to claim 3, wherein branch
parts at the root of the electrode terminal are angled such that
the branch parts go away from each other in a plan view with
respect to the bonding faces.
8. The semiconductor device according to claim 4, wherein branch
parts at the root of the electrode terminal are angled such that
the branch parts go away from each other in a plan view with
respect to the bonding faces.
9. The semiconductor device according to claim 2, wherein with
respect to the plurality of positions on the bonding face subjected
to the ultrasonic bonding, vibration directions of the ultrasonic
bonding are different from each other.
10. The semiconductor device according to claim 1, wherein the
ultrasonic bonding is performed a plurality of times in such a
manner that the positions on the bonding face subjected to the
ultrasonic bonding are overlapped with each other in a plan
view.
11. A semiconductor device comprising: an insulating substrate on
which a conductive pattern is formed; and an electrode terminal and
a semiconductor element that are bonded to the conductive pattern,
wherein the electrode terminal and the conductive pattern are
bonded together by ultrasonic bonding through at least one bonding
face, the electrode terminal includes a projection and the
conductive pattern includes a depression on the bonding face, or
the electrode terminal includes a depression and the conductive
pattern includes a projection on the bonding face, and the
projection and the depression are engaged with each other.
12. The semiconductor device according to claim 11, wherein the
projection and the depression are overlap with the position
subjected to the ultrasonic bonding in a plan view.
13. The semiconductor device according to claim 12, wherein the
ultrasonic bonding is performed at a plurality of positions.
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor device,
particularly to a semiconductor device to which an electrode
terminal is bonded by ultrasonic bonding.
BACKGROUND ART
[0002] Nowadays, power semiconductor devices are necessary
equipment in many different fields from small-sized electronic
devices to automobiles, bullet trains, etc., and also to electric
power transmission and distribution. The use areas and application
fields have been increasing year by year, and in the fields of
automobiles, bullet trains, electric power, and the like, higher
current, higher breakdown voltage, and operation temperatures in a
wide range, especially durability under high operation temperatures
have been desired, not to mention high reliability and long
lifetime. Since conventional solder-bonding techniques cannot
ensure reliability of soldering materials under high temperatures,
it is becoming more and more difficult to fabricate the elements
that satisfy the conditions. As one of bonding techniques to solve
this problem, the ultrasonic bonding has been introduced.
[0003] Here, a semiconductor device in which a conductive pattern
is formed on a surface of an insulating substrate, and a
semiconductor element and an electrode terminal are bonded to the
conductive pattern is considered. Conventionally, the electrode
terminal and the conductive pattern are subjected to the ultrasonic
bonding at one position. When a power semiconductor element is used
under conditions of high temperatures for a long period of time, a
thermal stress is generated due to a difference in thermal
expansion coefficients between the electrode terminal and the
insulating substrate on which the conductive pattern is formed, and
a bonding portion sometimes peels off.
[0004] In addition, as the semiconductor device carries larger
current, it becomes necessary to increase a cross-sectional area of
the electrode terminal. In other words, an increase in the
thickness or the width of the electrode terminal requires an
increase in the size of the electrode terminal. The increase in
size of the electrode terminal causes an increase of the stiffness
of the terminal. This results in an increase of a stress applied to
the bonding portion accompanied by displacement of a package due to
the heat generated by operation of the power semiconductor element,
and thus a problem, such as reduction of bonding strength and
terminal peeling, may occur.
[0005] Further, due to an increase in the thickness of the
electrode terminal and the area of a bonding face, it becomes
harder to propagate the energy of the ultrasonic bonding to the
bonding face. To increase the bonding strength of the ultrasonic
bonding, a bonding load and an ultrasonic output are generally
increased as a countermeasure. However, the increase of these
elements may cause a problem, i.e., the insulating substrate
provided under the conductive pattern is damaged.
[0006] Accordingly, Patent Document 1 discloses a technique in
which slits are provided at a plurality of positions between signal
terminals that are subjected to the ultrasonic bonding, so that the
ultrasonic bonding is stably performed. In addition, Patent
Document 2 discloses a technique in which the ultrasonic bonding is
performed at a plurality of positions between metal ribbons and
electrode pads on a semiconductor chip to increase the area of the
bonding face.
PRIOR ART DOCUMENTS
Patent Documents
[0007] Patent Document 1: Japanese Patent Application Laid-Open No.
2010-10537
[0008] Patent Document 2: Japanese Patent Application Laid-Open No.
2012-146747
SUMMARY OF INVENTION
Problems to be Solved by the Invention
[0009] However, the above conventional arts include the following
problems to be solved. Although an initial bonding strength can be
sufficiently obtained by the technique according to Patent Document
1, the bonding is susceptible to a thermal stress caused by heat
from an electrode accompanied by use of a semiconductor module. As
a bonding part of the electrode is divided by a slit and each of
the parts is presumably bonded at one position, the plurality of
bonding portions may all peel off due to generation of the
stress.
[0010] According to Patent Document 2, an integral metal ribbon is
bonded by ultrasonic bonding at a plurality of portions, but an
unbonded portion between the bonded portions is floated from a
target element and forms a gap. This is because a bonding target is
a ribbon, which is thin in a thickness normally equal to or less
than 300 .mu.m, and the ribbon may split without a gap. The bonding
target according to the present invention is an electrode having
the thickness of 0.5 mm or more and hardly split, and thus it is
not necessary to provide a gap.
[0011] The present invention has been made to solve the above
problems, and an object is to obtain a semiconductor device having
highly reliable bonding portions.
Means for Solving the Problems
[0012] The semiconductor device according to the present invention
includes an insulating substrate on which a conductive pattern is
formed, and an electrode terminal and a semiconductor element that
are bonded to the conductive pattern, the electrode terminal and
the conductive pattern are bonded together by the ultrasonic
bonding through at least one bonding face, and the ultrasonic
bonding is performed at a plurality of positions.
[0013] In addition, the semiconductor device according to the
present invention includes an insulating substrate on which a
conductive pattern is formed, and an electrode terminal and a
semiconductor element that are bonded to the conductive pattern,
the electrode terminal and the conductive pattern are bonded
together by the ultrasonic bonding through at least one bonding
face, the electrode terminal includes a projection and the
conductive pattern includes a depression on the bonding face,
alternatively the electrode terminal includes a depression and the
conductive pattern includes a projection on the bonding face, and
the projection and the depression are engaged with each other.
Effects of the Invention
[0014] In the semiconductor device according to the present
invention, a plurality of ultrasonically bonding portions are
provided on the bonding face. With this structure, an area of each
bonding portion can be reduced. As a result, an absolute value of a
thermal stress applied to each bonding portion can be reduced, and
thus peeling of the bonding face can be suppressed. In addition,
since the total area of the bonding portions increases, a reliable
semiconductor device can be obtained.
[0015] Moreover, in the semiconductor device according to the
present invention, the projection and the depression are fit with
each other before performing the ultrasonic bonding, thereby
facilitating positioning of the electrode terminal with respect to
the conductive pattern. With this structure, at the time of
performing the ultrasonic bonding, the relative position between
the electrode terminal and the conductive pattern is settled, and
the energy of the ultrasonic bonding can be sufficiently obtained.
Since the ultrasonic bonding can be stably performed, a
semiconductor device having a high bonding reliability can be
obtained.
[0016] The object, features, aspects, and advantageous effects of
the present invention are clarified by the following detailed
description and the accompanied drawings.
BRIEF DESCRIPTION OF DRAWINGS
[0017] FIG. 1 is a plan view and a sectional view of a
semiconductor device according to a first embodiment.
[0018] FIG. 2 is a perspective view of an electrode terminal and a
conductive pattern of the semiconductor device according to the
first embodiment.
[0019] FIG. 3 is a perspective view of an electrode terminal and a
conductive pattern of a semiconductor device according to a second
embodiment.
[0020] FIG. 4 is a perspective view of an electrode terminal and a
conductive pattern of a semiconductor device according to a third
embodiment.
[0021] FIG. 5 is a perspective view of an electrode terminal and a
conductive pattern of a semiconductor device according to a fourth
embodiment.
[0022] FIG. 6 is a plan view and a sectional view of a
semiconductor device according to a fifth embodiment.
[0023] FIG. 7 is a perspective view of an electrode terminal and a
conductive pattern of the semiconductor device according to the
fifth embodiment.
[0024] FIG. 8 is a perspective view of an electrode terminal and a
conductive pattern of a semiconductor device according to a sixth
embodiment.
[0025] FIG. 9 is a perspective view of an electrode terminal and a
conductive pattern of a semiconductor device according to a seventh
embodiment.
[0026] FIG. 10 is a perspective view of an electrode terminal and a
conductive pattern of a semiconductor device according to an eighth
embodiment.
[0027] FIG. 11 is a perspective view of an electrode terminal and a
conductive pattern of a semiconductor device according to a ninth
embodiment.
[0028] FIG. 12 is a sectional view of the electrode terminal and
the conductive pattern of the semiconductor device according to the
ninth embodiment.
[0029] FIG. 13 a plan view and a sectional view of a semiconductor
device according to a tenth embodiment.
[0030] FIG. 14 is a sectional view of a semiconductor device
according to a prerequisite art.
[0031] FIG. 15 is a plan view of the semiconductor device and a
sectional view of an electrode terminal according to the
prerequisite art.
[0032] FIG. 16 is a perspective view of the electrode terminal and
a conductive pattern of the semiconductor device according to the
prerequisite art.
DESCRIPTION OF EMBODIMENTS
[0033] <Prerequisite Art>
[0034] Before describing embodiments of the present invention, a
prerequisite art for the present invention is described below. FIG.
14 is a sectional view of a semiconductor device (power module)
according to the prerequisite art. The semiconductor device
according to the prerequisite art includes an insulating substrate
1 or an insulating sheet, a Metal Oxide Semiconductor Field Effect
Transistor (MOSFET) chip 2, a Shottkey Barrier Diode (SBD) chip 3,
conductive patterns 4a, 4b, an electrode terminal 6, a wire 14, a
sealing member 9, an outsert case 10, and a base plate 11.
[0035] The insulating substrate 1 is bonded to the base plate 11
for heat dissipation through a bonding member 8. The conductive
patterns 4a, 4b formed from a conductive material are provided on
the insulating substrate 1. The MOSFET chip 2 and the SBD chip 3
are mounted on the conductive pattern 4a with the bonding
member.
[0036] The electrode terminal 6 is bonded to the conductive pattern
4b on the bonding face 7. The electrode of the MOSFET chip 2 and
the electrode of the SBD chip 3 are bonded with each other by the
wire 14. In addition, the electrode of the SBD chip 3 and the
conductive pattern 4b are bonded with each other by the wire
14.
[0037] The outsert case 10 is attached to the base plate 11 by an
adhesive agent 12. The outsert case 10 is filled with the
insulating sealing member 9 formed of silicone gel, elastomer, or
the like.
[0038] The conductive patterns 4a, 4b are formed by etching a
copper plate brazed to the insulating substrate 1. The copper plate
may be an aluminum plate. The surfaces of the conductive patterns
4a, 4b may be covered with nickel.
[0039] Although the insulating substrate 1 is formed by using an
insulating material formed from AlN, the insulating material may
also be Al.sub.2O.sub.3, Si.sub.3N.sub.4, or the like. Although the
MOSFET chip 2 is mounted as a semiconductor element, the
semiconductor element may also be an Insulated Gate Bipolar
Transistor (IGBT). In addition, the SBD chips 3 may be a Free Wheel
Diode (FWD). Note that the semiconductor element may be selected
from elements having Si, SiC, or GaN as a base material. Although
the wire 14 is an Al wire having 400 .mu.m in diameter, the wire 14
may also be a wire formed from an Al alloy, a plate-shaped Al
sheet, or a good conductive metal wire composed of Cu.
[0040] Although solder is generally used as the conductive bonding
member 8, a sintered body of fine Ag particles having a diameter of
about several nanometers may be used for coping with
high-temperature operations. In addition, in the case of a
semiconductor device handling a small current, a conductive
adhesive agent containing a conductive filler may be used.
[0041] Although the insulating substrate 1 is bonded to the base
plate 11 by the bonding member 8, the insulating substrate 1 may be
formed integrally with the base plate 11. The material of the base
plate 11 is a composite material formed from Al and ceramic, such
as Al-SiC. In addition, the base plate 11 may also be a copper
plate.
[0042] In FIG. 14, the bonding between the electrode terminal 6 and
the conductive pattern 4b is performed by soldering. The solder
bonding requires controlling of the maximum operation temperature
and the melting point of solder, and has difficulty in coping with
elevation of operation temperatures in the case where an SiC
element, which is operable at high temperatures, is mounted as a
semiconductor element.
[0043] Accordingly, in recent years, ultrasonic bonding has been
applied to the bonding between the electrode terminal 6 and the
conductive pattern 4b. The ultrasonic bonding is a technique in
which ultrasonic vibration is applied to the bonding face of the
materials that make contact with each other to generate frictional
heat at a bonding portion, while imposing a load on the bonding
face so that coupling metals are joined at the interface at an
atomic level.
[0044] FIG. 15 is a view schematically showing the ultrasonic
bonding. In addition, FIG. 16 is a perspective view of the bonding
portion of the electrode terminal 6 and the conductive pattern 4b.
As shown in FIG. 15, a tool 13 is pressed against an upper part of
the bonding face 7 between the electrode terminal 6 and the
conductive pattern 4b and is ultrasonically vibrated, for example
in the direction of the arrow shown in the figure. The tool 13
transmits ultrasonic waves to the bonding face 7. At the time of
the ultrasonic bonding, a recess 5 is formed on the upper surface
of the electrode terminal 6 against which the tool 13 is pressed.
Use of the ultrasonic bonding enables bonding in a short period of
time without using a material such as an adhesive agent, solder, or
the like. In addition, the use of the ultrasonic bonding also
enables coping with high-temperature operations.
[0045] According to the prerequisite art, as shown in FIG. 16, the
electrode terminal 6 and the conductive pattern 4b are bonded
together by the ultrasonic bonding at one position. When a power
semiconductor element is used under high-temperature conditions for
a long period of time, the bonding portion sometimes peels off
because of a thermal stress caused by a difference in thermal
expansion coefficients between the electrode terminal 6 and the
insulating substrate 1 on which the conductive pattern 4b is
formed.
[0046] In addition, as the semiconductor device carries larger
current, it becomes necessary to increase a cross-sectional area of
the electrode terminal 6. In other words, an increase in the
thickness or the width of the electrode terminal 6 requires an
increase in the size of the electrode terminal 6. The increase in
size of the electrode terminal 6 causes an increase of the
stiffness of the terminal. This results in an increase of a stress
applied to the bonding portion accompanied by displacement of a
package due to the heat generated by operation of the power
semiconductor element, and thus a problem, such as reduction of
bonding strength and terminal peeling, may occur.
[0047] Further, due to an increase in the thickness of the
electrode terminal and the area of a bonding face 7, it becomes
harder to propagate the energy of the ultrasonic bonding to the
bonding face 7. To increase the bonding strength of the ultrasonic
bonding, a bonding load and an ultrasonic output are generally
increased as a countermeasure. However, the increase of these
elements may cause a problem, i.e., the insulating substrate 1
provided under the conductive pattern 4 is damaged.
First Embodiment
[0048] <Structure>
[0049] FIG. 1 is a plan view and a front view of a structure of a
semiconductor device according to a first embodiment. FIG. 2 is a
perspective view of an electrode terminal 6 and a conductive
pattern 4b. In this first embodiment, like in the prerequisite art
(FIG. 14), conductive patterns 4a and 4b are disposed on the
insulating substrate 1, and semiconductor elements (a MOSFET chip 2
and an SBD chip 3) are bonded to the conductive pattern 4a. The
electrode terminal 6 is bonded on the conductive pattern 4b.
[0050] According to the prerequisite art, ultrasonic bonding is
performed at only one position on one bonding face between the
electrode terminal 6 and the conductive pattern 4b. Accordingly, a
recess 5 is formed by the ultrasonic bonding at one position on the
upper surface of a bonding portion of the electrode terminal 6.
[0051] On the other hand, according to this first embodiment, as
shown in FIG. 1, a plurality of bonding portions are provided on
one bonding face 7 of the electrode terminal 6 to which the
conductive pattern 4b is bonded. Accordingly, a plurality of
recesses 5a, 5b are formed by the ultrasonic bonding on the upper
surface of the bonding portion of the electrode terminal 6. The
bonding portions are spaced apart from each other. In other words,
an interval of 50 .mu.m or less is provided between the recesses 5a
and 5b. Alternatively, the bonding portions may be in contact with
each other.
[0052] <Operation>
[0053] In the semiconductor device configured as shown in FIG. 1,
when a semiconductor element comes into operation, a current flows
into the electrode terminal 6 and then the electrode terminal 6
generates heat. The generated heat causes the whole electrode
terminal 6 to expand, a stress, such as tensile stress, is applied
to the root of the electrode terminal 6 that is a bonding portion.
In addition, the thermal stress is generated on the bonding face 7
between the electrode terminal 6 and the conductive pattern 4b
because of a difference in thermal expansion coefficients between
the materials of the insulating substrate 1 and the electrode
terminal 6.
[0054] <Effects>
[0055] The semiconductor device according to this first embodiment
includes an insulating substrate 1 on which conductive patterns 4a,
4b are formed, and an electrode terminal 6 and a semiconductor
element that are bonded to the conductive patterns 4a, 4b, the
electrode terminal 6 and the conductive pattern 4b are bonded
together by the ultrasonic bonding through the bonding face 7, and
the ultrasonic bonding is performed at a plurality of
positions.
[0056] Accordingly, in this first embodiment, as shown in FIG. 1
and FIG. 2, a plurality of ultrasonically bonding portions are
provided on the bonding face 7. With this structure, an area of
each bonding portion can be reduced. As a result, an absolute value
of a thermal stress applied to each bonding portion can be reduced,
and thus peeling of the bonding face 7 can be suppressed. In
addition, since the total area of the bonding portions increases, a
highly reliable semiconductor device can be obtained.
[0057] In addition, the semiconductor device according to this
first embodiment includes one bonding face 7, and the ultrasonic
bonding is performed at a plurality of positions on the bonding
face 7.
[0058] Accordingly, even with one bonding face 7, this first
embodiment can provide a highly reliable semiconductor device by
performing the ultrasonic bonding at two positions.
Second Embodiment
[0059] <Structure>
[0060] FIG. 3 is a perspective view of an electrode terminal 6 and
a conductive pattern 4b according to a second embodiment. In this
second embodiment, the electrode terminal 6 is a flat plate. The
root of the electrode terminal 6 is divided into two branches in
the width direction. In other words, the root of the electrode
terminal 6 includes two branches 6a, 6b.
[0061] As shown in FIG. 3, the branches 6a, 6b are bent to form an
angle of 90.degree. with each other in a plan view. The branch 6a
is bonded to the conductive pattern 4b by ultrasonic bonding on the
bonding face 7a. In the same manner, the branch 6b is bonded by the
ultrasonic bonding to the conductive pattern 4b on the bonding face
7b. On the bonding faces 7a, 7b, the branches 6a, 6b are
respectively bonded by the ultrasonic bonding to the conductive
pattern 4b at one position. Recesses 5a, 5b are formed by the
ultrasonic bonding at the upper surfaces of the branches 6a,
6b.
[0062] <Operation>
[0063] In this second embodiment, the sectional areas of the
branches 6a and 6b of the electrode terminal 6 are assumed equal to
each other. In this case, when the current flowing in one electrode
terminal is defined as I [A], the current flowing in each of the
branches 6a, 6b is I/2 [A].
[0064] In addition, the area of the bonding face of each of the
branches 6a, 6b is half of that of the bonding face according to
the first embodiment. Accordingly, with respect to the mechanical
stress due to the expansion of the electrode terminal 6, the stress
applied to the branches 6a, 6b is also reduced by half.
[0065] <Effects>
[0066] The semiconductor device according to this second embodiment
includes a plurality of bonding faces 7a, 7b, the root of the
electrode terminal 6 is divided into branches, and the divided root
(i.e., branches 6a, 6b) forms the plurality of bonding faces 7a,
7b, and each of the bonding faces 7a, 7b includes at least one
position that is subjected to the ultrasonic bonding.
[0067] In this second embodiment, the root of the electrode
terminal 6 is divided into two branches, and the branches 6a, 6b
form two bonding faces 7a, 7b, respectively. Each of the bonding
faces 7a, 7b includes one position that is subjected to the
ultrasonic bonding. Accordingly, in this second embodiment, by
dividing the root of the electrode terminal 6 into two branches,
the current flowing in each terminal (branches 6a, 6b) becomes I/2
[A], and thus the heating value of each of the bonding faces is
reduced by half as compared to that of the first embodiment. This
enables the thermal stress applied to each bonding face to be
reduced by half.
[0068] In addition, since two bonding faces 7a, 7b are provided,
peeling of the bonding faces 7a, 7b can be suppressed as compared
to a case where one bonding face 7 is provided as in the
prerequisite art, even when a force to peel the electrode terminal
6 upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
[0069] In addition, in the semiconductor device according to this
second embodiment, the electrode terminal 6 is a flat plate, the
root of the electrode terminal 6 is divided in the thickness
direction or in the width direction.
[0070] According to the present embodiment, the root of the
electrode terminal 6 in the shape of a flat plate is divided into
two branches in the width direction. Accordingly, in fabrication of
the electrode terminal 6, the root of the electrode terminal 6 can
be divided into two branches by a press processing. Accordingly, a
semiconductor device which is easily processed and reduced in cost
can be obtained.
[0071] In addition, in the semiconductor device according to this
second embodiment, the root of the electrode terminal 6 is divided
into two, three, or four branches.
[0072] According to the present embodiment, the root of the
electrode terminal 6 is divided into two branches. Accordingly, in
this second embodiment, by dividing the root of the electrode
terminal 6 into two branches, the current flowing in each terminal
(branches 6c, 6d) is reduced by half, and thus the heating value of
each of the bonding faces is reduced by half as compared to that of
the first embodiment. This enables the thermal stress applied to
each bonding face to be reduced by half.
[0073] In addition, in the semiconductor device according to this
second embodiment, the branch parts at the root of the electrode
terminal 6 are separated from each other toward the bonding faces
7a, 7b in a plan view.
[0074] In the semiconductor device according to this second
embodiment, the branches 6a, 6b form an angle of 90.degree. with
each other in a plan view. Accordingly, peeling of the bonding
faces 7a, 7b can be suppressed as compared to a case where the
bonding face is provided only in one direction of the electrode
terminal 6, even when a force to peel the electrode terminal 6
upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
Third Embodiment
[0075] <Structure>
[0076] FIG. 4 is a perspective view of an electrode terminal 6 and
a conductive pattern 4b according to a third embodiment. In this
third embodiment, the electrode terminal 6 is a flat plate. The
root of the electrode terminal 6 is divided into two branches in
the thickness direction. In other words, the root of the electrode
terminal 6 includes two branches 6a, 6b.
[0077] As shown in FIG. 4, the branches 6a, 6b are bent in opposite
directions to form an angle of 180.degree. with each other in a
plan view. The branch 6a is bonded to the conductive pattern 4b by
ultrasonic bonding on the bonding face 7a. Similarly, the branch 6b
is bonded by the ultrasonic bonding to the conductive pattern 4b on
the bonding face 7b. Each of the branches 6a, 6b is bonded by the
ultrasonic bonding to the conductive pattern 4b at one position on
one of the bonding faces 7a, 7b. The total sum of the areas of the
bonding faces 7a, 7b according to this third embodiment is twice as
large as that of the bonding face 7 according to the prerequisite
art. The recesses 5a, 5b are formed by the ultrasonic bonding on
the upper surfaces of the branches 6a, 6b, respectively. In this
third embodiment, when the thickness of the electrode terminal 6 is
defined as w6, the thickness of the branch 6a is defined as w6a,
and the thickness of the branch 6b is defined as w6b, w6=w6a+w6b
and w6a=w6b are satisfied. Note that w6a and w6b may be arbitrary
values on condition that the thicknesses satisfy the relation,
w6=w6a+w6b.
[0078] <Operation>
[0079] In this third embodiment, the sectional areas of the
branches 6a and 6b of the electrode terminal 6 are assumed equal to
each other. In this case, when the current flowing in one electrode
terminal is defined as I [A], the current flowing in each of the
branches 6c, 6d is I/2[A]. At the bonding faces 7a, 7b, the
thicknesses of the branches 6a, 6b that are subjected to bonding
are less than those in the second embodiment. With this structure,
the stress applied to the branches 6a, 6b is reduced by half with
respect to the mechanical stress due to the expansion of the
electrode terminal 6.
[0080] <Effects>
[0081] In the semiconductor device according to this third
embodiment, the electrode terminal 6 is a flat plate, and the root
of the electrode terminal 6 is divided in the thickness direction
or in the width direction.
[0082] In this third embodiment, the root of the electrode terminal
6 in the shape of a flat plate is divided into two branches in the
thickness direction. Accordingly, since the thickness of the
electrode terminal 6 is reduced at the bonding portions, the
electrode is deformed largely due to the stress, and thus the
stress applied to the bonding portions can be reduced and a
semiconductor device having highly reliable bonding portions can be
obtained.
[0083] In addition, in the semiconductor device according to this
third embodiment, the root of the electrode terminal 6 is divided
into two, three, or four branches.
[0084] According to this third embodiment, the root of the
electrode terminal 6 is divided into two branches. Accordingly, in
this third embodiment, by dividing the root of the electrode
terminal 6 into two branches, the current flowing in each terminal
(branches 6c, 6d) is reduced by half, and thus the heating value of
each of the bonding faces is reduced by half as compared to that of
the first embodiment. This enables the thermal stress applied to
each bonding face to be reduced by half.
[0085] In addition, since two bonding faces 7a, 7b are provided by
dividing the root of the electrode terminal 6 into two branches,
peeling of the bonding faces 7a, 7b can be suppressed as compared
to a case where one bonding face 7 is provided as in the
prerequisite art, even when a force to peel the electrode terminal
6 upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
[0086] In addition, in the semiconductor device according to this
third embodiment, the branch parts at the root of the electrode
terminal 6 are angled such that the branch parts go away from each
other in a plan view with respect to the bonding faces 7a, 7b.
[0087] In the semiconductor device according to this third
embodiment, the branches 6a, 6b form an angle of 180.degree. with
each other in a plan view. Accordingly, peeling of the bonding
faces 7a, 7b can be suppressed as compared to a case where the
bonding face is provided only in one direction of the electrode
terminal 6, even when a force to peel the electrode terminal 6
upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
Fourth Embodiment
[0088] <Structure>
[0089] FIG. 5 is a perspective view of an electrode terminal 6 and
a conductive pattern 4b according to a fourth embodiment. In this
fourth embodiment, the electrode terminal 6 is a flat plate. The
root of the electrode terminal 6 is divided into two branches in
the width direction. In other words, the root of the electrode
terminal 6 includes two branches 6a, 6b.
[0090] As shown in FIG. 5, the branches 6a, 6b are bent in opposite
directions to form an angle of 180.degree. with each other in a
plan view. The branch 6a is bonded to the conductive pattern 4b by
ultrasonic bonding on the bonding face 7a. Similarly, the branch 6b
is bonded by the ultrasonic bonding to the conductive pattern 4b on
the bonding face 7b. Each of the branches 6a, 6b is bonded by the
ultrasonic bonding to the conductive pattern 4b at one position on
one of the bonding faces 7a, 7b. The recesses 5a, 5b are formed by
the ultrasonic bonding on the upper surfaces of the branches 6a,
6b, respectively.
[0091] <Effects>
[0092] In addition, in the semiconductor device according to this
fourth embodiment, the electrode terminal 6 is a flat plate, and
the root of the electrode terminal 6 is divided in the thickness
direction or in the width direction.
[0093] According to this fourth embodiment, the root of the
electrode terminal 6 in the shape of a flat plate is divided into
two branches in the width direction. Accordingly, in fabrication of
the electrode terminal 6, the root of the electrode terminal 6 can
be divided into two branches by a press processing. Accordingly, a
semiconductor device which is easily processed and reduced in cost
can be obtained.
[0094] In addition, in the semiconductor device according to this
fourth embodiment, the root of the electrode terminal 6 is divided
into two, three, or four branches.
[0095] According to this fourth embodiment, the root of the
electrode terminal 6 is divided into two branches. Accordingly, in
this fourth embodiment, by dividing the root of the electrode
terminal 6 into two branches, the current flowing in each terminal
(branches 6c, 6d) is reduced by half, and thus the heating value of
each of the bonding faces is reduced by half as compared to that of
the first embodiment. This enables the thermal stress applied to
each bonding face to be reduced by half.
[0096] In addition, since two bonding faces 7a, 7b are provided by
dividing the root of the electrode terminal 6 into two branches,
peeling of the bonding faces 7a, 7b can be suppressed as compared
to a case where one bonding face 7 is provided as in the
prerequisite art, even when a force to peel the electrode terminal
6 upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
[0097] In addition, in the semiconductor device according to this
fourth embodiment, the branch parts at the root of the electrode
terminal 6 are angled such that the branch parts go away from each
other in a plan view with respect to the bonding faces 7a, 7b.
[0098] In the semiconductor device according to this fourth
embodiment, the branches 6a, 6b form an angle of 180.degree. with
each other in a plan view. Accordingly, peeling of the bonding
faces 7a, 7b can be suppressed as compared to a case where the
bonding face is provided only in one direction of the electrode
terminal 6, even when a force to peel the electrode terminal 6
upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
Fifth Embodiment
[0099] <Structure>
[0100] FIG. 6 is a plan view and a front view of a structure of a
semiconductor device according to a fifth embodiment. FIG. 7 is a
perspective view of an electrode terminal 6 and a conductive
pattern 4b. Note that in FIG. 7, semiconductor elements (an MOSFET
chip 2, an SBD chip 3) are omitted for easy understanding. As shown
in FIG. 6, a plurality of conductive patterns 4a, 4b, 4c are formed
on the insulating substrate 1.
[0101] In this fifth embodiment, the electrode terminal 6 is a flat
plate. The root of the electrode terminal 6 is divided into four
branches. In other words, the root of the electrode terminal 6
includes four branches 6a, 6b, 6c, 6d. As shown in FIG. 7, opposing
branches 6a, 6c are bent in directions that are opposite to each
other. Similarly, opposing branches 6b, 6d are bent in directions
that are opposite to each other. In other words, the branch 6a and
the branch 6b, the branch 6b and the branch 6c, the branch 6c and
the branch 6d, and the branch 6d and the branch 6a respectively
form an angle of 90.degree. with each other in a plan view.
[0102] The branches 6a, 6b, 6c, 6d are bonded to the conductive
pattern 4a by ultrasonic bonding on the bonding faces 7a, 7b, 7c,
7d, respectively. Each of the branches 6a, 6b, 6c, 6d is bonded by
the ultrasonic bonding to the conductive pattern 4a at one position
on one of the bonding faces 7a, 7b, 7c, 7d. The recesses 5a, 5b,
5c, 5d are formed by the ultrasonic bonding on the upper surfaces
of the branches 6a, 6b, 6c, 6d, respectively.
[0103] As shown in FIG. 6, an SBD chip 3 is bonded to the
conductive pattern 4a at a position next to the branch 6a and the
branch 6b. In addition, an SBD chip 3 is bonded to the conductive
pattern 4a at a position next to the branch 6b and the branch 6c.
In addition, an MOSFET chip 2 is bonded to the conductive pattern
4a at a position next to the branch 6c and the branch 6d. An MOSFET
chip 2 is bonded to the conductive pattern 4a at a position next to
the branch 6d and the branch 6a.
[0104] <Operation>
[0105] In the semiconductor device configured as shown in FIG. 6
and FIG. 7, when a semiconductor element comes into operation, a
current flows into the electrode terminal 6 and then the electrode
terminal 6 generates heat. In the case where there is a difference
between the distances from each of the branches 6a, 6b, 6c, 6d to
the MOSFET chips 2 and the SBD chips 3 when a power semiconductor
element is in operation, the wiring resistance is varied depending
on the distance, and thus the amounts of the current flow become
unequal. This causes a deviation in the heating positions. Since
the heat makes the whole electrode terminal 6 expand, a stress such
as a tensile stress is applied to the root of the electrode
terminal 6, which is a bonding portion, and thus a difference in
the amount of the heating value generates a difference in the
stress applied to the branches 6a to 6d.
[0106] According to this fifth embodiment, the branches 6a to 6d
are disposed to extend in four directions, and the MOSFET chips 2
and the SBD chips 3 are disposed next to the branches, and thus a
difference between the distances from each of the branches 6a, 6b,
6c, 6d to the MOSFET chips 2 and the SBD chips 3 can be reduced.
With this structure, a deviation in the temperature rise caused by
an uneven current flow can be reduced, and thus the heat cycle
property is improved.
[0107] In addition, since the bonding faces 7a to 7d are provided
in four directions of the electrode terminal 6, peeling of the
bonding faces 7a to 7d can be suppressed as compared to a case
where one bonding face 7 is provided as in the prerequisite art,
even when a force to peel the electrode terminal 6 upward (stress
generated perpendicular to the bonding face) is generated.
Accordingly, a semiconductor device having highly reliable bonding
portions can be obtained, and thus the heat cycle property is
improved.
[0108] <Effects>
[0109] In the semiconductor device according to this fifth
embodiment, the root of the electrode terminal 6 is divided into
two, three, or four branches.
[0110] According to this fifth embodiment, the root of the
electrode terminal 6 are divided into four branches, and the
branches 6a to 6d are disposed to extend in four directions. The
MOSFET chips 2 and the SBD chips 3 are disposed next to the
branches, and thus a difference between the distances from each of
the branches 6a, 6b, 6c, 6d to the MOSFET chips 2 and the SBD chips
3 can be reduced. With this structure, a deviation in the
temperature rise caused by an uneven current flow can be
reduced.
[0111] In addition, in the semiconductor device according to this
fifth embodiment, the branch parts at the root of the electrode
terminal 6 are angled such that the branch parts go away from each
other in a plan view with respect to the bonding faces 7a, 7b.
[0112] In the semiconductor device according to this fifth
embodiment, the branches 6a, 6b, 6c, 6d form an angle of 90.degree.
with each other in a plan view. Accordingly, peeling of the bonding
faces 7a, 7b, 7c, 7d can be suppressed as compared to a case where
the bonding face is provided only in one direction of the electrode
terminal 6, even when a force to peel the electrode terminal 6
upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
Sixth embodiment
[0113] <Structure>
[0114] FIG. 8 is a perspective view of an electrode terminal 6 and
a conductive pattern 4b of a semiconductor device according to a
sixth embodiment. The semiconductor device may include the
electrode terminal 6 according to this sixth embodiment instead of
the electrode terminal 6 according to the fifth embodiment (FIG.
7).
[0115] The electrode terminal 6 according to this sixth embodiment
is a flat plate, and the root thereof is divided into three
branches. In other words, the root of the electrode terminal 6
includes three branches 6a, 6b, 6c. As shown in FIG. 8, the branch
6a and the branch 6b, and the branch 6b and the branch 6c are bent
to form an angle of 90.degree. with each other in a plan view.
[0116] The branches 6a, 6b, 6c are bonded to the conductive pattern
4a by ultrasonic bonding on the bonding faces 7a, 7b, 7c,
respectively. Each of the branches 6a, 6b, 6c is bonded by the
ultrasonic bonding to the conductive pattern 4a at one position on
one of the bonding faces 7a, 7b, 7c. The recesses 5a, 5b, 5c are
formed by the ultrasonic bonding on the upper surfaces of the
branches 6a, 6b, 6c, respectively.
[0117] As shown in FIG. 8, an SBD chip 3 is bonded to the
conductive pattern 4a at a position next to the branch 6a and the
branch 6b. In addition, an SBD chip 3 is bonded to the conductive
pattern 4a at a position next to the branch 6b and the branch 6c.
In addition, an MOSFET chip 2 is bonded to the conductive pattern
4a at a position opposite to the SBD chip 3 across the branch 6a.
In addition, an MOSFET chip 2 is bonded to the conductive pattern
4a at a position opposite to the SBD chip 3 across the branch
6c.
[0118] Note that although each of the branch 6a and the branch 6b,
the branch 6b and the branch 6c are bent to form an angle of
90.degree. with each other in a plan view, they may be bent to form
an arbitrary angle, for example an angle of 120.degree..
[0119] <Effects>
[0120] In the semiconductor device according to this sixth
embodiment, the root of the electrode terminal 6 is divided into
two, three, or four branches.
[0121] According to this sixth embodiment, the root of the
electrode terminal 6 is divided into three branches, and the
branches 6a to 6c are disposed to extend in three directions. The
MOSFET chips 2 and the SBD chips 3 are disposed next to the
branches, and thus a difference between the distances from each of
the branches 6a, 6b, 6c to the MOSFET chips 2 and the SBD chips 3
can be reduced. With this structure, a deviation in the temperature
rise caused by an uneven current flow can be reduced, and thus the
heat cycle property is improved.
[0122] In addition, since the bonding faces 7a to 7c are provided
in three directions of the electrode terminal 6, peeling of the
bonding faces 7a to 7c can be suppressed as compared to a case
where one bonding face 7 is provided as in the prerequisite art,
even when a force to peel the electrode terminal 6 upward (stress
generated perpendicular to the bonding face) is generated.
Accordingly, a semiconductor device having highly reliable bonding
portions can be obtained.
[0123] In addition, in fabrication of the electrode terminal 6, the
root of the electrode terminal 6 can be divided into three branches
by a press processing. Accordingly, a semiconductor device which is
easily processed and reduced in cost can be obtained.
[0124] In addition, in the semiconductor device according to this
sixth embodiment, the branch parts at the root of the electrode
terminal 6 are angled such that the branch parts go away from each
other in a plan view with respect to the bonding faces 7a, 7b,
7c.
[0125] In the semiconductor device according to this sixth
embodiment, the branches 6a, 6b, 6c form an angle of 90.degree.
with each other in a plan view. Accordingly, peeling of the bonding
faces 7a, 7b, 7c can be suppressed as compared to a case where the
bonding face is provided only in one direction of the electrode
terminal 6, even when a force to peel the electrode terminal 6
upward (stress generated perpendicular to the bonding face) is
generated. Accordingly, a semiconductor device having highly
reliable bonding portions can be obtained.
Seventh Embodiment
[0126] <Structure>
[0127] FIG. 9 is a perspective view of an electrode terminal 6 and
a conductive pattern 4b of a semiconductor device according to a
seventh embodiment. In the semiconductor device according to this
seventh embodiment, the electrode terminal 6 is bonded to the
conductive pattern 4b by ultrasonic bonding on one bonding face 7
in the same manner as the first embodiment (FIG. 1 and FIG. 2).
This bonding face 7 includes two bonding portions. In other words,
two recesses 5a, 5b are generated on the upper surfaces of the
roots of the electrode terminal 6 at the time of the ultrasonic
bonding.
[0128] In FIG. 9, the recess 5a is formed at the time of the
ultrasonic bonding in which a tool (see tool 13 in FIG. 14) is
vibrated in the x-direction. In addition, the recess 5b is formed
at the time of the ultrasonic bonding in which the tool is vibrated
in the y-direction. In other words, a plurality of positions
subjected to the ultrasonic bonding on the bonding face 7 are
vibrated in directions different from each other at the time of the
ultrasonic bonding.
[0129] <Effects>
[0130] In the semiconductor device according to this seventh
embodiment, with respect to the plurality of positions subjected to
the ultrasonic bonding on the bonding face 7, vibration directions
of the ultrasonic bonding are different from each other at the time
of the ultrasonic bonding.
[0131] Accordingly, in this seventh embodiment, the vibration
directions of the ultrasonic bonding are changed at each position
subjected to the ultrasonic bonding and thus directions with weak
bonding strength can be dispersed. In other words, the bonding face
7 that is bonded with more uniform strength can be obtained.
[0132] In addition, the vibration direction of the ultrasonic
bonding is set to a direction different from the direction in which
the insulating substrate 1 is vulnerable to vibration, and thus
generation of a crack on an insulating substrate 1 can be avoided.
In addition, the vibration direction of the ultrasonic bonding is
set to a direction in which the electrode terminal 6 is susceptible
to a thermal stress, and thus the bonding reliability improves.
Eighth Embodiment
[0133] <Structure>
[0134] FIG. 10 is a perspective view of an electrode terminal 6 and
a conductive pattern 4b of a semiconductor device according to an
eighth embodiment. In the semiconductor device according to this
eighth embodiment, the electrode terminal 6 is bonded to the
conductive pattern 4b by ultrasonic bonding on one bonding face 7
in the same manner as the first embodiment (FIG. 1 and FIG. 2).
This bonding face 7 includes two bonding portions. Two recesses 5a,
5b are generated on the roots of the electrode terminal 6 at the
time of the ultrasonic bonding. Here, the recess 5b is formed
inside the recess 5a in a plan view. In other words, the ultrasonic
bonding is performed twice in such a manner that a bonding portion
of the second ultrasonic bonding is overlapped with that of the
first ultrasonic bonding.
[0135] <Effects>
[0136] On the bonding face 7 of the semiconductor device according
to the present embodiment, the ultrasonic bonding is performed a
plurality of times in such a manner that positions subjected to the
ultrasonic bonding are overlapped with each other in a plan
view.
[0137] Accordingly, in this eighth embodiment, a plurality of
bonding portions subjected to the ultrasonic bonding are provided
on one bonding face 7 so as to overlap with each other, and thus a
position in which the bonding strength is increased can be provided
on the bonding face 7. For example, when an electrode terminal 1 is
bonded to a surface including a vicinity of an end surface of the
insulating substrate 1, a first ultrasonic bonding is performed
with an energy that does not damage the insulating substrate 1, and
then a second ultrasonic bonding is performed only around the
center of the insulating substrate 1. This prevents the ultrasonic
bonding from generating a crack on the insulating substrate 1, and
enables obtaining a desired bonding strength.
Ninth Embodiment
[0138] <Structure>
[0139] FIG. 11 is a perspective view of an electrode terminal 6 and
a conductive pattern 4b of a semiconductor device according to a
ninth embodiment. In addition, FIG. 12 is a sectional view taken
along line AB in FIG. 11.
[0140] In this ninth embodiment, coining is performed at the root
of the electrode terminal 6. As shown in FIG. 12, a depression 6e
is formed on the upper surface of the root of the electrode
terminal 6 and at the same time, a projection 6f is formed on the
lower surface of the root of the electrode terminal 6 by the
coining.
[0141] In addition, on the upper surface of an insulating substrate
1, a depression is provided at a position corresponding to the
projection 6f. This depression is formed by a mechanical processing
or by an etching. Since the conductive pattern 4b is formed on the
surface of the insulating substrate 1, a depression 41b is also
formed on the conductive pattern 4b at a position corresponding to
the depression on the insulating substrate 1, as shown in FIG.
12.
[0142] In fabrication processes, firstly, the electrode terminal 6
is disposed on the conductive pattern 4b. At this time, the
projection 6f of the electrode terminal 6 is engaged with the
depression 41b of the conductive pattern 4b. Then, a tool is
pressed against the upper surface of the electrode terminal 6, and
the electrode terminal 6 is bonded to the conductive pattern 4b by
ultrasonic bonding. By the ultrasonic bonding, a recess 5 is formed
on the upper surface of the root of the electrode terminal 6.
[0143] Note that although a projection is formed on the electrode
terminal 6 and a depression is formed on the conductive pattern 4b
according to the present embodiment, the depression may be formed
on the electrode terminal 6 and the projection may be formed on the
conductive pattern 4b to engage with the depression.
[0144] <Effects>
[0145] The semiconductor device according to this ninth embodiment
includes the insulating substrate 1 on which the conductive pattern
4b is formed, and an electrode terminal 6 and a semiconductor
element that are bonded to the conductive pattern 4b, the electrode
terminal 6 and the conductive pattern 4b are bonded by the
ultrasonic bonding on a bonding face 7, the electrode terminal 6
includes a projection 6f and the conductive pattern 4b includes the
depression 41b on the bonding face 7, or the electrode terminal 6
includes a depression and the conductive pattern 4b includes a
projection on the bonding face, and the projection 6f and the
depression 41b are engaged with each other.
[0146] In this ninth embodiment, the projection 6f is engaged with
the depression 41b. Since the projection 6f and the depression 41b
are engaged with each other before performing the ultrasonic
bonding, the electrode terminal 6 is easily positioned with respect
to the conductive pattern 4b. This stables a relative position of
the electrode terminal 6 and the conductive pattern 4b at the time
of the ultrasonic bonding, and thus the energy of the ultrasonic
bonding can be sufficiently obtained. Since the ultrasonic bonding
can be stably performed, a semiconductor device having a high
bonding reliability can be obtained.
Tenth Embodiment
[0147] (Description of Structure)
[0148] FIG. 13 is a plan view of a semiconductor device according
to a tenth embodiment, and a sectional view of the electrode
terminal 6 and the conductive pattern 4b.
[0149] The semiconductor device according to this tenth embodiment
has the same structure as that of the first embodiment (FIG. 1,
FIG. 2) except for the shape of a bonding face between the
electrode terminal 6 and the conductive pattern 4b.
[0150] A projection 6g is formed on the lower surface of the root
of the electrode terminal 6. In addition, a depression 42b is
formed on the surface of the conductive pattern 4b. The projection
6g has a shape that is engaged with the depression 42b. For
example, the projection 6g is formed by mechanical processing, and
the depression 42b is formed by etching.
[0151] In a fabrication process, firstly, the electrode terminal 6
is formed on the conductive pattern 4b. At this time, the
projection 6g of the electrode terminal 6 is engaged with the
depression 42b of the conductive pattern 4b. Then, a tool is
pressed against the upper surface of the electrode terminal 6, and
the electrode terminal 6 is bonded to the conductive pattern 4b by
ultrasonic bonding. At this time, the ultrasonic bonding is
performed at two positions. Two recesses 5a, 5b are formed on the
upper surface of the root of the electrode terminal 6 by the
ultrasonic bonding. In this tenth embodiment, the positions
subjected to the ultrasonic bonding, the projection 6g, and the
depression 42b overlap with each other in a plan view. In other
words, two recesses 5a, 5b on the upper surface of the electrode
terminal 6, the projection 6g, and the depression 42b overlap with
each other in a plan view.
[0152] Note that in this embodiment, although a projection is
formed on the electrode terminal 6 and a depression is formed on
the conductive pattern 4b, the depression may be formed on the
electrode terminal 6, a projection may be formed on the conductive
pattern 4b to engage with each other. In addition, a plurality of
the projections 6g and a plurality of the depressions 42b may be
formed. In addition, a corner between the projection 6g and the
depression 42b may be smooth.
[0153] <Effects>
[0154] In the semiconductor device according to this tenth
embodiment, the projection 6g and the depression 42b overlap with
the position subjected to the ultrasonic bonding in a plan
view.
[0155] In this tenth embodiment, the projection 6g is engaged with
the depression 42b. The projection 6g and the depression 42b are
engaged with each other before performing the ultrasonic bonding,
and thus the electrode terminal 6 is easily positioned with respect
to the conductive pattern 4b. With this structure, the relative
position of the electrode terminal 6 and the conductive pattern 4b
are stabled at the time of the ultrasonic bonding, and the energy
of the ultrasonic bonding can be sufficiently obtained. In
addition, since the depression and the projection are provided at a
position subjected to the ultrasonic bonding on the bonding face,
the area of the bonding face can be increased, and thus the bonding
strength can be increased. In view of the above, a semiconductor
device having a high bonding reliability can be obtained.
[0156] In addition, in the semiconductor device according to this
tenth embodiment, the ultrasonic bonding is performed at a
plurality of positions.
[0157] Accordingly, the area of each of the bonding portions can be
reduced. Therefore, an absolute value of a thermal stress at each
of the bonding portions can be reduced, peeling of the bonding face
7 can be suppressed. In addition, since the total area of the
bonding portions is increased, a highly reliable semiconductor
device can be obtained.
[0158] Although this invention is described in detail, the above
descriptions are examples in all aspects, and this invention is not
limited to that extent. Unlimited number of modifications that are
not exemplified can be estimated without deviating from the scope
of this invention.
REFERENCE SIGNS LIST
[0159] 1: insulating substrate,
[0160] 2: MOSFET chip
[0161] 3: SBD chip
[0162] 4a, 4b, 4c: conductive pattern
[0163] 5, 5a, 5b, 5c, 5d: recess
[0164] 6: electrode terminal
[0165] 6a, 6b, 6c, 6d: branch
[0166] 7, 7a, 7b, 7c, 7d: bonding face
[0167] 8: bonding member
[0168] 9: sealing member
[0169] 10: outsert case
[0170] 11: base plate
[0171] 12: adhesive agent
[0172] 13: tool
[0173] 14: metal wire.
* * * * *