U.S. patent application number 15/043627 was filed with the patent office on 2017-07-20 for semiconductor device and method for fabricating the same.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Hsuan-Sheng Lin, Huang-Ren Wei.
Application Number | 20170207096 15/043627 |
Document ID | / |
Family ID | 59314912 |
Filed Date | 2017-07-20 |
United States Patent
Application |
20170207096 |
Kind Code |
A1 |
Wei; Huang-Ren ; et
al. |
July 20, 2017 |
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Abstract
A method for fabricating semiconductor device is disclosed. The
method includes the steps of: providing a substrate; forming a
fin-shaped structure on the substrate; performing a first etching
process to remove part of the fin-shaped structure for forming a
trench; and performing a second etching process to extend the depth
of the trench and divide the fin-shaped structure into a first
portion and a second portion.
Inventors: |
Wei; Huang-Ren; (Tainan
City, TW) ; Lin; Hsuan-Sheng; (Chiayi City,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
59314912 |
Appl. No.: |
15/043627 |
Filed: |
February 15, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/30604 20130101;
H01L 21/3085 20130101; H01L 21/823431 20130101; H01L 21/823481
20130101; H01L 21/3065 20130101; H01L 29/0657 20130101; H01L
21/3081 20130101; H01L 29/66795 20130101 |
International
Class: |
H01L 21/308 20060101
H01L021/308; H01L 21/306 20060101 H01L021/306; H01L 29/06 20060101
H01L029/06 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 20, 2016 |
TW |
105101619 |
Claims
1-9. (canceled)
10. A semiconductor device, comprising: a substrate; a plurality of
first fin-shaped structures on the substrate, wherein the substrate
extending between and contacting sidewalls of the first fin-shaped
structures comprises a completely planar surface; a second
fin-shaped structure and a third fin-shaped structure adjacent to
two sides of the first fin-shaped structures; a first trench
between the first fin-shaped structures and the second fin-shaped
structure, wherein a bottom surface of the first trench is lower
than the completely planar surface between the first fin-shaped
structures; and a second trench between the first fin-shaped
structures and the third fin-shaped structure, wherein the bottom
surfaces of the first trench and the second trench are lower than
the completely planar surface between the first fin-shaped
structures, wherein the width of each of the first fin-shaped
structures is equal to a width of the first trench, wherein the
depths of the first trench and the second trench are equal.
11. The semiconductor device of claim 10, wherein the height of the
first fin-shaped structures and the height of the second fin-shaped
structure are the same.
12. The semiconductor device of claim 11, wherein the height of the
second fin-shaped structure and the height of the third fin-shaped
structure are the same.
13. The semiconductor device of claim 10, wherein the height of the
first fin-shaped structures and the height of the second fin-shaped
structure are different.
14. The semiconductor device of claim 13, wherein the height of the
second fin-shaped structure and the height of the third fin-shaped
structure are the same.
15. The semiconductor device of claim 10, wherein the bottom
surfaces of the first fin-shaped structures and the second
fin-shaped structure are coplanar.
16. The semiconductor device of claim 10, wherein the bottom
surface of the first trench is lower than the bottom surface of the
first fin-shaped structures.
17. The semiconductor device of claim 10, wherein the bottom
surfaces of the first trench and the second trench are coplanar.
Description
BACKGROUND OF THE INVENTION
[0001] 1.Field of the Invention
[0002] The invention relates to a method for fabricating
semiconductor device, and more particularly, to a method of using
two etching process to divide fin-shaped structure into two
parts.
[0003] 2.Description of the Prior Art
[0004] With the trend in the industry being towards scaling down
the size of the metal oxide semiconductor transistors (MOS),
three-dimensional or non-planar transistor technology, such as fin
field effect transistor technology (FinFET) has been developed to
replace planar MOS transistors. Since the three-dimensional
structure of a FinFET increases the overlapping area between the
gate and the fin-shaped structure of the silicon substrate, the
channel region can therefore be more effectively controlled. This
way, the drain-induced barrier lowering (DIBL) effect and the short
channel effect are reduced. The channel region is also longer for
an equivalent gate length, thus the current between the source and
the drain is increased. In addition, the threshold voltage of the
fin FET can be controlled by adjusting the work function of the
gate.
[0005] In current FinFET fabrication, fin-shaped structure may be
divided and insulating material is deposited to form shallow trench
isolation (STI). However, the STI formed between fin-shaped
structures often results in expansion and affects the formation of
gate structure thereafter. Hence, how to improve the current FinFET
fabrication and structure for resolving this issue has become an
important task in this field.
SUMMARY OF THE INVENTION
[0006] According to a preferred embodiment of the present
invention, a method for fabricating semiconductor device is
disclosed. The method includes the steps of: providing a substrate;
forming a fin-shaped structure on the substrate; performing a first
etching process to remove part of the fin-shaped structure for
forming a trench; and performing a second etching process to extend
the depth of the trench and divide the fin-shaped structure into a
first portion and a second portion.
[0007] According to another aspect of the present invention, a
semiconductor device is disclosed. The semiconductor device
includes: a substrate; a first fin-shaped structure on the
substrate; a second fin-shaped structure and a third fin-shaped
structure adjacent to two sides of the first fin-shaped structure;
a first trench between the first fin-shaped structure and the
second fin-shaped structure; and a second trench between the first
fin-shaped structure and the third fin-shaped structure.
[0008] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIGS. 1-2 are top views illustrating a method for
fabricating semiconductor device according to a preferred
embodiment of the present invention.
[0010] FIGS. 3-8 are cross-sectional views illustrating a method
for fabricating semiconductor device according to a preferred
embodiment of the present invention.
[0011] FIG. 9 illustrates a structural view of a semiconductor
device according to an embodiment of the present invention.
DETAILED DESCRIPTION
[0012] Referring to FIGS. 1-8, FIGS. 1-2 are top views illustrating
a method for fabricating a semiconductor device according to a
preferred embodiment of the present invention, and FIGS. 3-8 are
cross-sectional views illustrating a method for fabricating the
semiconductor device. As shown in FIG. 1, a substrate 12, such as a
silicon substrate or silicon-on-insulator (SOI) substrate is
provided, and a plurality of fin-shaped structures 14, 16, 18, 20,
22, 24, 26 are formed on the substrate 12.
[0013] The formation of the fin-shaped structures 14, 16, 18, 20,
22, 24, 26 could be accomplished by first forming a patterned mask
(now shown) on the substrate, 12, and an etching process is
performed to transfer the pattern of the patterned mask to the
substrate 12. Alternatively, the formation of the fin-shaped
structure 14, 16, 18, 20, 22, 24, 26 could also be accomplished by
first forming a patterned hard mask (not shown) on the substrate
12, and then performing an epitaxial process on the exposed
substrate 12 through the patterned hard mask to grow a
semiconductor layer. This semiconductor layer could then be used as
the corresponding fin-shaped structures 14, 16, 18, 20, 22, 24, 26.
Moreover, if the substrate 12 were a SOI substrate, a patterned
mask could be used to etch a semiconductor layer on the bottom
oxide layer without etching through the semiconductor layer for
forming the fin-shaped structure 14, 16, 18, 20, 22, 24, 26.
[0014] Next, a first fin-cut process is conducted by using a
photo-etching process to remove the fin-shaped structures 16 and 24
surrounded by the rectangular block along X-direction in FIG. 1.
The fin-shaped structures 18, 20, 22 and fin-shaped structures 14
and 26 are remained after the first fin-cut process. It should be
noted that despite two of the fin-shaped structures, such as
fin-shaped structures 16 and 24 are removed in this embodiment, the
quantity and location of the fin-shaped structures being removed
could all be adjusted according to the demand of the product.
[0015] Next, as shown in FIG. 2, a second fin-cut process is
conducted by using etching process to remove part of the fin-shaped
structures 18, 20, 22 marked by the elliptical dotted lines along
Y-direction in FIG. 2. This divides the fin-shaped structures 18,
20, 22 into two portions. It should be noted that in contrast to
the aforementioned first fin-cut process of using a single etching
process to remove the fin-shaped structures 16, 24 completely, two
etching processes are preferably conducted in the second fin-cut
process to form a trench in the fin-shaped structures 18, 20, 22
and divide the fin-shaped structures 18, 20, 22 into two
portions.
[0016] Referring to FIGS. 3-8, FIGS. 3-8 are detailed views
illustrating the process of dividing the fin-shaped structure 22
into two portions along the sectional line AA' of FIG. 2. It should
be noted that a hard mask 28 and a dielectric layer 30 are
preferably formed on each of the fin-shaped structures 14, 16, 18,
20, 22, 24, 26 before the first fin-cut process is conducted. For
instance, as shown in FIG. 3, the hard mask 28 is preferably an
oxide-nitride-oxide (ONO) stack including a silicon oxide layer 32,
a silicon nitride layer 34, and another silicon oxide layer 36, and
the dielectric layer 30 could be composed of organic dielectric
layer (ODL) or photoresist material, but not limited thereto.
[0017] Next, as shown in FIG. 4, a photo-etching process is
conducted on the dielectric layer 30 by first forming a patterned
resist (not shown) on the dielectric layer 30, and then using
etching to remove part of the dielectric layer 30 for forming an
opening to expose the surface of the silicon oxide layer 36
underneath.
[0018] Next, as shown in FIG. 5, after stripping the photoresist, a
first etching process is conducted by using the patterned
dielectric layer 30 as mask to remove part of the hard mask 28 and
part of the fin-shaped structure 22 for forming a trench 38 while
forming a passivation layer 40 on the dielectric layer 30 and hard
mask 28. Preferably, a first etchant used to form the trench 38 and
passivation layer 40 in the first etching process is selected from
the group consisting of Cl.sub.2, O.sub.2, and SiCl.sub.4.
[0019] Specifically, the first etching process and the formation of
the passivation layer 40 are accomplished in-situly, or viewing
from another perspective, as part of the dielectric layer 30, part
of the hard mask 28, and part of the fin-shaped structure 22 are
removed by the first etchant to form the trench 38, a passivation
layer 40 is slow built-up or accumulated on the top surface of the
dielectric layer 30 and sidewalls of the hard mask 28.
[0020] Preferably, the silicon atom from the SiCl.sub.4 component
of first etchant is specifically utilized to react with oxides from
the dielectric layer 30 and hard mask 28 to form polymers
preferably composed of SiO.sub.2, and these polymers essentially
become the passivation layer 40 used for protecting the dielectric
layer 30 and hard mask 28 in this embodiment.
[0021] Next, as shown in FIG. 6, a second etching process is
conducted by using a second etchant to extend the depth of the
trench 38 further downward and divide the fin-shaped structure 22
into a first portion 42 and a second portion 44 . Preferably, the
second etchant is selected from the group consisting of Cl.sub.2
and O.sub.2. More specifically, the second etching process of this
embodiment preferably uses the passivation layer 40 as mask to
further etch the fin-shaped structure 22 that has already been
partially removed during the first etching process. This extends
the depth of the trench 38 further downward till reaching the
substrate 12 and divides the fin-shaped structures 22 into two
parts, including a first portion 42 and a second portion 44.
[0022] Typically, etchant used in fin-shaped structure removal is
selected from the group consisting of Cl.sub.2 and O.sub.2. This
recipe however not only consumes a great portion of dielectric
layer and hard mask atop the fin-shaped structure while the
fin-shaped structure is divided in half, but also unable to
maintain the width of the trench. This causes the trench width
within top portion of the fin-shaped structure to be significantly
larger than trench width in the hard mask, thereby affecting the
deposition of insulating material afterwards and the critical
dimension of the device.
[0023] In other to resolve this issue, the passivation layer 40
formed during the aforementioned first etching process is
preferably used to protect the top surface and sidewalls of the
dielectric layer 30 as well as the sidewalls of the hard mask 28 so
that these two elements are affected by the second etchant used
during the second etching process.
[0024] Next, as shown in FIG. 7, a shallow trench isolation (STI)
formation could be conducted by first depositing an insulating
material 50 composed of silicon oxide into the trench 38 and fill
the space surrounding the fin-shaped structure 22, and then using a
planarizing process, such as chemical mechanical polishing (CMP)
process to remove part of the insulating material 40, part of the
passivation layer 40, and the dielectric layer 30 and stop of the
hard mask 28 surface. It should be noted that at this stage, part
of the passivation layer 40 is still remained on the sidewalls of
the hard mask 28.
[0025] Next, as shown in FIG. 8, an etching back process is
conducted to remove part of the insulating material 50 once more
and the remaining passivation layer 40 so that the top surface of
the remaining insulating material 50 is lower than the top surface
of the hard mask 28. This forms a STI 52 in the trench 38 and
around the divided first portion 42 and second portion 44. Next,
another etching process is conducted to fully remove the hard mask
28. This completes the fabrication of a semiconductor device
according to a preferred embodiment of the present invention.
[0026] Referring to FIG. 9, FIG. 9 illustrates a structural view of
FIG. 2 along the sectional line BB' after the aforementioned second
etching process is completed. As shown in FIG. 9, the semiconductor
device includes a substrate 12, fin-shaped structures 14, 18, 20,
22, 26 on the substrate 12, a trench 46 between the fin-shaped
structures 14 and 18, and a trench 48 between the fin-shaped
structures 22 and 26 . Despite three fin-shaped structures 18, 20,
22 are disposed between the trenches 46 and 48 and only one
fin-shaped structure 14 and one fin-shaped structure 26 are
disposed on other sides of the trenches 46 and 48, the quantity of
the fin-shaped structures 14, 18, 20, 22, 26 is not limited to the
ones disclosed in this embodiment, but could all be adjusted
according to the demand of the product. Also, for simplicity
purpose, the hard mask on top of each of the fin-shaped structures
14, 18, 20, 22, 26 is not shown in the figure.
[0027] In this embodiment, since the location of the fin-shaped
structures 16 and 24 shown in FIG. 1 has been etched twice by the
aforementioned first fin-cut process and the second fin-cut
process, the original location of the fin-shaped structures 16, 24
after the second fin-cut process would form trenches 46 and 48
instead of a surface even with the substrate 12 surface or the
bottom surface of fin-shaped structures 14, 18, 20, 22, 26.
[0028] Overall, the fin-shaped structures 18, 20, 22 between the
two trenches 46 and 48 preferably share same height, the heights of
the fin-shaped structures 18, 20, 22 are equivalent to the heights
of the fin-shaped structures 14, 26, and the height of the
fin-shaped structure 14 is also equivalent to the height of the
fin-shaped structure 26. However, according to another embodiment
of the present invention, the height of the fin-shaped structures
18, 20, 22 could also be different from the fin-shaped structures
14, 26 while the fin-shaped structures 14, 26 share same height,
which is also within the scope of the present invention.
[0029] In addition, the bottom surface of the fin-shaped structures
18, 20, 22 is even with the bottom surface of the fin-shaped
structures 14, 26 as the bottom surfaces of the fin-shaped
structures 14, 18, 20, 22, 26 are all even with the top surface of
the substrate 12, the bottom surface of each of the trenches 46, 48
is lower than the bottom surface of the fin-shaped structures 14,
18, 20, 22, 26, and the bottom surface of the trench 46 is even
with the bottom surface of the trench 48.
[0030] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *