U.S. patent application number 15/134438 was filed with the patent office on 2017-07-20 for memory device and operating method for resistive memory cell.
The applicant listed for this patent is MACRONIX INTERNATIONAL CO., LTD.. Invention is credited to Dai-Ying Lee, Ming-Hsiu Lee, Tien-Yen Wang, Chao-I Wu.
Application Number | 20170206960 15/134438 |
Document ID | / |
Family ID | 59297929 |
Filed Date | 2017-07-20 |
United States Patent
Application |
20170206960 |
Kind Code |
A1 |
Wu; Chao-I ; et al. |
July 20, 2017 |
MEMORY DEVICE AND OPERATING METHOD FOR RESISTIVE MEMORY CELL
Abstract
A memory device and an operating method for a resistive memory
cell are provided. The memory device includes the resistive memory
cell. The resistive memory cell includes a first electrode, a
second electrode and a memory film between the first electrode and
the second electrode. The first electrode includes a bottom
electrode portion and a sidewall electrode portion extending
upwardly from the bottom electrode portion and between the memory
film and the bottom electrode portion. A width of the sidewall
electrode portion and a width of the memory film are smaller than a
width of the bottom electrode portion.
Inventors: |
Wu; Chao-I; (Hsinchu City,
TW) ; Lee; Dai-Ying; (Hsinchu County, TW) ;
Lee; Ming-Hsiu; (Hsinchu City, TW) ; Wang;
Tien-Yen; (Zhubei City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
MACRONIX INTERNATIONAL CO., LTD. |
Hsinchu |
|
TW |
|
|
Family ID: |
59297929 |
Appl. No.: |
15/134438 |
Filed: |
April 21, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62280713 |
Jan 20, 2016 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 13/0064 20130101;
H01L 45/1233 20130101; H01L 45/04 20130101; H01L 45/1253 20130101;
H01L 45/1633 20130101; G11C 13/0069 20130101; H01L 27/2436
20130101; G11C 2213/52 20130101; G11C 2013/0066 20130101; H01L
45/145 20130101; G11C 13/0002 20130101; G11C 13/0007 20130101 |
International
Class: |
G11C 13/00 20060101
G11C013/00; H01L 45/00 20060101 H01L045/00 |
Claims
1. A memory device, comprising: a resistive memory cell comprising
a first electrode, a second electrode and a memory film between the
first electrode and the second electrode; and a conductive layer,
wherein the first electrode comprises a bottom electrode portion
and a sidewall electrode portion extending upwardly from the bottom
electrode portion, and between the memory film and the bottom
electrode portion, a width of the sidewall electrode portion and a
width of the memory film are smaller than a width of the bottom
electrode portion, the first electrode is on the conductive layer,
a width L1 of the sidewall electrode portion is smaller than a
width L2 of the conductive layer.
2. The memory device according to claim 1, wherein a height H1 of
the memory film is smaller than a height H2 of the first
electrode.
3. The memory device according to claim 2, wherein
0<H1/H2<0.1.
4. (canceled)
5. The memory device according to claim 1, wherein
0<L1/L2<0.5.
6. The memory device according to claim 1, wherein the width L1 of
the sidewall electrode portion is 10 .ANG.-200 .ANG., the width L2
of the conductive layer is 1000 .ANG.-5000 .ANG..
7. The memory device according to claim 1, wherein the sidewall
electrode portion and the memory film have the same width.
8. The memory device according to claim 1, further comprising a
memory material on the memory film, wherein the memory film and the
memory material have different materials.
9. The memory device according to claim 1, further comprising a
memory material on the memory film, wherein a width of the memory
material is bigger than the width of the memory film.
10. The memory device according to claim 1, further comprising an
electrode material, wherein the electrode material is between the
second electrode and the memory film and has a material different
from a material of the second electrode.
11. The memory device according to claim 10, wherein the electrode
material and the second electrode have the same width.
12. The memory device according to claim 1, wherein the bottom
electrode portion and the sidewall electrode portion have an
included angle therebetween, the included angle is 45-90
degrees.
13. The memory device according to claim 1, wherein the first
electrode has a L shape.
14. The memory device according to claim 1, wherein the first
electrode and the memory film form a L shape.
15. The memory device according to claim 1, further comprising a
transistor, wherein the first electrode is electrically connected
to a source/drain of the transistor through the conductive
layer.
16-20. (canceled)
Description
[0001] This application claims the benefit of U.S. provisional
application Ser. No. 62/280,713, filed Jan. 20, 2016, the subject
matter of which is incorporated herein by reference.
BACKGROUND
[0002] Technical Field
[0003] The disclosure relates to a memory cell and an operating
method for the same, and particularly to a resistive memory cell
and an operating method for the same.
[0004] Description of the Related Art
[0005] Along with the advance in semi-conductor technology,
electronic elements are kept being miniaturized, such that
electronic products possess more and more functions when the size
remains unchanged or become even smaller. As there are more and
more information to be processed, the demand for the memory having
larger capacity but smaller size is ever increasing.
[0006] Electric currently, the read-write memory stores data by
means of a transistor structure assisted by a memory cell. However,
the technology for manufacturing such memory has come to a
bottleneck in terms of scalability. Therefore, more advanced memory
structures, such as phase change random access memory (PCRAM),
magnetic random access memory (MRAM), and resistive random access
memory (RRAM), are presented. The RRAM, having the advantages of
fast read-write speed, non-destructive access, tolerance against
extreme temperatures and compatibility with electric current
manufacturing process of complementary metal oxide semiconductor
(CMOS), is a new memory technology with great potential to replace
the electric current storage media.
SUMMARY
[0007] The present disclosure provides a memory device and an
operating method for a resistive memory cell.
[0008] According to an embodiment, a memory device includes the
resistive memory cell. The resistive memory cell includes a first
electrode, a second electrode and a memory film between the first
electrode and the second electrode. The first electrode includes a
bottom electrode portion and a sidewall electrode portion extending
upwardly from the bottom electrode portion and between the memory
film and the bottom electrode portion. A width of the sidewall
electrode portion and a width of the memory film are smaller than a
width of the bottom electrode portion.
[0009] According to another embodiment, a memory device comprises a
resistive memory cell comprising a first electrode, a second
electrode and a memory film between the first electrode and the
second electrode. The first electrode comprises a titanium nitride.
The memory film comprises a titanium oxynitride. The second
electrode comprises a titanium nitride.
[0010] According to yet another embodiment, a method for operating
a resistive memory cell comprises the following steps. A writing
step comprises writing the resistive memory cell with a pulse of a
first width or shots of a first number of times. After the writing
step, it is verified if the resistive memory cell reaches a
predetermined resistance or electric current. It is verified if the
first width or the first number of times reaches a maximum width or
a maximum number of times, if the resistive memory cell does not
reach the predetermined resistance or electric current. The
resistive memory cell is written with a pulse of a second width or
shots of a second number of times, if the first width or the first
number of times does not reach the maximum width or the maximum
number of times. The second number of times is bigger than the
first number of times. The second width is bigger than the first
width.
[0011] The above and other embodiments of the disclosure will
become better understood with regard to the following detailed
description of the non-limiting embodiment(s). The following
description is made with reference to the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 illustrates a cross-section view of a resistive
memory cell according to an embodiment.
[0013] FIG. 2A illustrates a cross-section view of a resistive
memory cell according to an embodiment.
[0014] FIG. 2B illustrates a cross-section view of a resistive
memory cell according to an embodiment.
[0015] FIG. 3 to FIG. 13 illustrate a process flow for
manufacturing a memory device according to some embodiments.
[0016] FIG. 14 shows a relation of a resistance and a probability
of the resistive memory cell in a set state and in a reset state
according to an embodiment.
[0017] FIG. 15 shows a relation of a cycling count and a cell
resistance of a resistive memory cell in a set state and in a reset
state.
[0018] FIG. 16 shows a result of an incremental step pulse
programming (ISPP) method for a resistive memory cell.
[0019] FIG. 17 shows characteristics of writing timing and
resistance of a resistive memory cell in a reset state.
[0020] FIG. 18 shows characteristics of writing timing and
resistance of a resistive memory cell in a set state.
[0021] FIG. 19 illustrates an operating method for a resistive
memory cell according to an embodiment.
[0022] FIG. 20 shows results of operating a resistive memory cell
in an embodiment and a comparative example.
DETAILED DESCRIPTION
[0023] The present disclosure provides a memory device and a method
for operating a resistive memory cell. The resistive memory cell
can have a large and stable switching window, and good
reliability.
[0024] The illustrations may not be necessarily be drawn to scale,
and there may be other embodiments of the present disclosure which
are not specifically illustrated. Thus, the specification and the
drawings are to be regard as an illustrative sense rather than a
restrictive sense. Moreover, the descriptions disclosed in the
embodiments of the disclosure such as detailed construction,
manufacturing steps and material selections are for illustration
only, not for limiting the scope of protection of the disclosure.
The steps and elements in details of the embodiments could be
modified or changed according to the actual needs of the practical
applications. The disclosure is not limited to the descriptions of
the embodiments.
[0025] According to embodiments, the resistive memory cell
comprises a first electrode, a second electrode and a memory film
between the first electrode and the second electrode. A material
film may be between the memory film and the second electrode. In
embodiments, the resistive memory cell can reach excellent
electrical characteristic through designs of materials and
structures.
[0026] FIG. 1 illustrates a cross-section view of the resistive
memory cell according to an embodiment. The resistive memory cell
comprises a first electrode 102, a memory film 104 on the first
electrode 102, a material film 106 on the memory film 104, and a
second electrode 108 on the material film 106.
[0027] In an embodiment, the material film 106 comprises
compositions of a memory material. In embodiments, compositions for
the memory film 104 and memory material for the material film 106
comprise a material having various resistance (high and low
resistance states), changeable by adjusting a voltage bias applied
the memory film 104 and memory material for the material film 106.
Compositions of the memory film 104 may be different from the
compositions of the material film 106. In an embodiment, for
example, the resistive memory cell is a resistive random access
memory (RRAM, ReRAM), of which the first electrode 102 comprises a
titanium nitride (TiN), the memory film 104 comprises a titanium
oxynitride (TiOxNy), the material film 106 comprises a titanium
oxide (TiOx), the second electrode 108 comprises a titanium
nitride. According to the material designs, the resistive memory
cell can have a large switching window, and good reliability. For
example, the memory retention can maintain longer than 3 hours at
250.degree. C.
[0028] In another embodiment, the material film 106 comprises an
electrode material. A material of the second electrode 108 may be
different from a material of the material film 106. In an
embodiment, for example, the resistive memory cell is a resistive
random access memory, of which the first electrode 102 comprises a
titanium nitride (TiN), the memory film 104 comprises a titanium
oxynitride (TiOxNy), the material film 106 comprises a titanium
(Ti), and the second electrode 108 comprises a titanium nitride.
According to the material designs, the resistive memory cell can
have a large switching window, and good reliability. For example,
the memory retention can maintain longer than 3 hours at
250.degree. C.
[0029] In some embodiments, the material film 106 of titanium oxide
may be an oxidized film formed from the deposited titanium material
film 106 exposed to the atmosphere air. In some embodiments, the
material film 106 of titanium oxide is formed by performing an
additional oxidation step to the titanium material film 106.
[0030] In present disclosure, materials of the resistive memory
cell are not limited to the foregoing examples. In other
embodiments, the first electrode 102, the second electrode 108 and
the electrode material of the material film 106 may use suitable
kinds of conductive materials, for example a metal or a metal
nitride, comprising a transition metal or a transition metal, such
as Ta, TaN, Hf, HfN, etc. In various embodiments, the memory film
104 and the memory material of the material film 106 may use
suitable kinds of memory materials, for example a metal oxide or a
metal oxynitride for a resistive memory material. For example, the
metal oxide may comprise a transition metal containing oxide such
as TaOx, HfOx, etc. For example, the metal oxynitride may comprise
a transition metal containing oxynitride, such as TaOxNy, HfOxNy,
etc.
[0031] FIG. 2A and FIG. 2B illustrate cross-section views of the
resistive memory cells according to other embodiments. The
resistive memory cells of FIG. 2A and FIG. 2B are different from
the resistive memory cell of FIG. 1 in the following illustrating.
The first electrode 102 comprises a bottom electrode portion 110
and a sidewall electrode portion 112 extending upwardly from the
bottom electrode portion 110. The sidewall electrode portion 112 is
between the memory film 104 and the bottom electrode portion 110. A
width of the sidewall electrode portion 112 and a width of the
memory film 104 are smaller than a width of the bottom electrode
portion 110, and may be smaller than a width of the material film
106 and a width of the second electrode 108. The sidewall electrode
portion 112 and the memory film 104 may have the same width
substantially. The material film 106 and the second electrode 108
may have the same width substantially. In embodiments, a height H1
of the memory film 104 is smaller than a height H2 of the first
electrode 102. For example, 0<H1/H2<0.1. The first electrode
102 and the memory film 104 may form a L shape. In embodiments, the
bottom electrode portion 110 and the sidewall electrode portion 112
of the first electrode 102, forming a L shape, have an included
angle of 45 degrees to 90 degrees.
[0032] FIG. 3 to FIG. 13 illustrate a process flow for
manufacturing the memory device according to some embodiments.
[0033] Referring to FIG. 3, a substrate structure 128 is provided,
comprising a semiconductor substrate 130, and a transistor 131, a
dielectric layer 133 and a conductive layer 136 formed on the
semiconductor substrate 130. The semiconductor substrate 130 may
comprise silicon, or other suitable semiconductor materials. The
transistor 131 comprises a source/drain 132 and a gate structure
134. The source/drain 132 may comprise a heavily-doped region
formed by doping the semiconductor substrate 130, such as a N+
region. The gate structure 134 may comprise a gate dielectric layer
135 and a gate electrode layer 137 on the gate dielectric layer
135. The gate dielectric layer 135 may comprise an oxide such as
silicon oxide, or other suitable dielectric materials. The gate
electrode layer 137 may comprise polysilicon, or other suitable
conductive materials.
[0034] The conductive layer 136 passing through the dielectric
layer 133 may comprise a metal plug, electrically connected to the
source/drain 132. The dielectric layer 133 may comprise an oxide, a
nitride, an oxynitride, such as silicon oxide, silicon nitride,
silicon oxynitride, or other suitable dielectric materials. The
conductive layer 136 may comprise a metal, such as W, or other
suitable conductive materials. In an embodiment, the substrate
structure 128 shown in FIG. 3 may be a flatted structure through a
chemical mechanical polishing (CMP) process.
[0035] Referring to FIG. 4, a hard mask layer 138 is formed on the
substrate structure 128. In an embodiment, the hard mask layer 138
comprises SiN. In other embodiments, the hard mask layer 138 may
use other suitable materials. In an embodiment, for example, the
hard mask layer 138 may have a thickness of 1000 .ANG. to 2000
.ANG., such as 1500 .ANG..
[0036] Referring to FIG. 5A, the hard mask layer 138 is patterned
to form an opening 140 therein. An included angle of the opening
140 is not limited to 90 degrees as shown in FIG. 5A. In other
embodiments, the included angle of the opening 140 may be bigger
than 90 degrees as shown in FIG. 5B.
[0037] Referring to FIG. 6, a first electrode 102A is formed on an
upper surface of the hard mask layer 138, and on a sidewall of the
hard mask layer 138 and upper surfaces of the dielectric layer 133
and the conductive layer 136 exposed by the opening 140. In an
embodiment, for example, the first electrode 102A may have a
thickness of 50 .ANG. to 200 .ANG., such as 100 .ANG..
[0038] Referring to FIG. 7, the first electrode 102A is patterned
to remain a first electrode 102E having a stair shape covering the
conductive layer 136 and portions of the hard mask layer 138 and
the dielectric layer 133 adjacent to the conductive layer 136, and
to expose a portion of the dielectric layer 133 and a portion of
the hard mask layer 138 adjacent to the dielectric layer 133.
[0039] Referring to FIG. 8, a sacrificial layer 142 is formed on
the hard mask layer 138 and the first electrode 102B, and in the
opening 140. In an embodiment, the sacrificial layer 142 may
comprise an oxide, such as a deposited TEAS. In other embodiments,
the sacrificial layer 142 may use other suitable materials.
[0040] Referring to FIG. 9, upper portions of the sacrificial layer
142 and the first electrode 102E are removed to remain the
sacrificial layer 142 and the first electrode 102 having a L shape
in the opening 140. In an embodiment, the removing step may use a
CMP method that may stop on the hard mask layer 138.
[0041] Referring to FIG. 10, an exposed upper portion of the first
electrode 102 is oxidized to form the memory film 104 of an oxide.
The height (H1 in FIG. 2A, FIG. 2B) of the memory film 104 may be
controlled by an oxidation process. The oxidation comprises a
chemical vapor deposition (CVD) method or a physical vapor
deposition (PVD) method. In an embodiment, for example, the first
electrode 102 comprises titanium nitride (TiN), and the memory film
104 comprises titanium oxynitride (TiOxNy) formed through the
oxidation step.
[0042] Referring to FIG. 11, the material film 106 is formed on the
memory film 104, the sacrificial layer 142 and the hard mask layer
138. In an embodiment, the material film 106 may have a thickness
of 5 .ANG. to 50 .ANG., such as 10 .ANG.. The second electrode 108
is formed on the material film 106. In an embodiment, the second
electrode 108 may have a thickness of 50 .ANG. to 500 .ANG., such
as 400 .ANG..
[0043] Referring to FIG. 12A, the sacrificial layer 142, the hard
mask layer 138, the material film 106 and the second electrode 108
are patterned.
[0044] Referring to FIG. 12A and FIG. 12B, the first electrode 102
of the resistive memory cell is electrically connected to the
source/drain 132, for example the drain, of the transistor 131
through the conductive layer 136. In an embodiment, for example,
widths of the patterned material film 106 and second electrode 108
are 5000 .ANG.. In embodiments, a width L1 of the sidewall
electrode portion 112 of the first electrode 102 is smaller than a
width L2 of the conductive layer 136. For example,
0<L1/L2<0.5. In an embodiment, for example, the width L1 of
the sidewall electrode portion 112 is 10 .ANG. to 200 .ANG., such
as 100 .ANG.. The width L2 of the conductive layer 136 is 1000
.ANG. to 5000 .ANG., such as 3000 .ANG..
[0045] Referring to FIG. 13, a conductive layer 144 is formed on
the conductive layer 136 and the second electrode 108. The
conductive layer 144 may comprise a metal (such as M1) routing.
[0046] FIG. 14 shows a relation of a resistance and a probability
of the resistive memory cell in a set state and in a reset state
according to an embodiment. It is shown that the resistive memory
cell has a large switching window, i.e. a large resistance gap, and
thus the set state and the reset state of the resistive memory cell
can be recognized easily.
[0047] In the present disclosure, the inventors find that after
cycling operating, a resistive memory cell (not limited to the
resistive memory cell structure disclosed herein) would have a
resistance switching window instability problem (as shown in FIG.
15), which would result in switching fail and reliability
degrading. In addition, it is hard to monitor the failure cells
during the operating, and the problem can be solved by a
conventional incremental step pulse programming (ISPP) method (as
shown in FIG. 16). The inventors develops a method for operating a
memory device according to the discovered characteristics of write
timing and resistance (in the reset state as shown in FIG. 17, and
in the set state as shown in FIG. 18), which may be used for
monitoring degradation behavior of the operated resistive memory
cell.
[0048] The following disclose the operating method for a memory
device according to embodiments, which may be used for monitoring
degradation behavior or healthy status for the resistive memory
cell. The operating method comprises an algorithm with degradation
awareness scheme, which can improve the reliability of the
resistive memory cell.
[0049] FIG. 19 illustrates the operating method for the resistive
memory cell in an array of memory cells according to an embodiment.
The method starts in a step 270. In a step 272, a condition for
writing the resistive memory cell is loaded.
[0050] In a step 274, a setting up step is performed, comprising
setting up a width of a pulse or a number of times of shots for
writing the resistive memory cell. In an embodiment, the width of
the pulse or the number of times of the shots is set to a first
width or a first number of times. For example, the number N of
times of the shots means there are N writing pulses.
[0051] In a step 276, a writing step is performed, comprising
writing the resistive memory cell with the pulse of the first width
or the shots of the first number of times, set in the step 274. In
embodiments, during the writing step 276, no verifying step is
performed. For example, no verifying step is performed between the
shots.
[0052] After the writing step 276, a step 278 is performed, which
is a verifying step, comprising verifying if the written resistive
memory cell reaches a predetermined resistance or electric current.
The method proceeds to a step 280, verifying the first width of the
pulse or the first number of times of the shots reaches a maximum
width or a maximum number of times, if the resistive memory cell
does not reach the predetermined resistance or electric current.
The method proceeds to a step 282: increasing the width of the
writing pulse or the number of times of the writing shots, i.e.
increasing the width from the first width to a second width of the
writing pulse, or increasing the number of times from the first
number of time to a second number of times of the writing shots, if
in the step 280 it is verified that the maximum width or the
maximum number of times is not reached. Then, the process as shown
in FIG. 19 can be performed with the setting up step 274 performed
with the second width or the second number of times obtained in the
step 282. In an embodiment, an awareness scheme as indicated by a
dotted line involving the step 280 and the step 282 may be used to
motor the degradation condition for the resistive memory cell.
[0053] In the step 278, if the resistive memory cell is verified to
reach the predetermined resistance or electric current, the method
proceeds to an end step 284. In addition, in the step 280 if it is
verified that the maximum width or the maximum number of times is
reached, the method proceeds to a step 286, logging the writing
fail, and then proceeds to the end step 284.
[0054] FIG. 20 shows operating results of the resistive memory
cells of embodiment (indicated with solid lines) and comparative
examples (indicated with dotted lines). The operating method of
embodiment comprises the awareness scheme comprising the steps 280
and 282 as shown in FIG. 19. The operating method of comparative
omits the steps 280 and 282. As found in FIG. 20, by using the
operating method according to embodiments, the resistive memory
cell can maintain a stable resistance switching window after
cycling operation.
[0055] According to embodiments, the resistive memory cell can have
a large switching window and good reliability. In addition, using
the operating method according to embodiments, the resistive memory
cell can have a stable switching window.
[0056] While the disclosure has been described by way of example
and in terms of the exemplary embodiment(s), it is to be understood
that the disclosure is not limited thereto. On the contrary, it is
intended to cover various modifications and similar arrangements
and procedures, and the scope of the appended claims therefore
should be accorded the broadest interpretation so as to encompass
all such modifications and similar arrangements and procedures.
* * * * *