U.S. patent application number 15/346573 was filed with the patent office on 2017-07-06 for system and method for tin plating metal electrodes.
This patent application is currently assigned to SolarCity Corporation. The applicant listed for this patent is SolarCity Corporation. Invention is credited to Christoph G. Erben, Zhi-Wen Sun.
Application Number | 20170194517 15/346573 |
Document ID | / |
Family ID | 57234875 |
Filed Date | 2017-07-06 |
United States Patent
Application |
20170194517 |
Kind Code |
A1 |
Erben; Christoph G. ; et
al. |
July 6, 2017 |
SYSTEM AND METHOD FOR TIN PLATING METAL ELECTRODES
Abstract
Systems and methods for fabricating a photovoltaic structure are
provided. During fabrication, a patterned mask is formed on a first
surface of a multilayer body of the photovoltaic structure, with
openings of the mask corresponding to grid line locations of a
first grid. Subsequently, a core layer of the first grid is
deposited in the openings of the patterned mask, and a protective
layer is deposited on an exposed surface of the core layer. The
patterned mask is then removed to expose the sidewalls of the core
layer. Heat is applied to the protective layer such that the
protective layer reflows to cover both the exposed surface and
sidewalls of the core layer.
Inventors: |
Erben; Christoph G.; (Los
Gatos, CA) ; Sun; Zhi-Wen; (Sunnyvale, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SolarCity Corporation |
San Mateo |
CA |
US |
|
|
Assignee: |
SolarCity Corporation
San Mateo
CA
|
Family ID: |
57234875 |
Appl. No.: |
15/346573 |
Filed: |
November 8, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14985238 |
Dec 30, 2015 |
9496429 |
|
|
15346573 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 31/022433 20130101;
H01L 31/022441 20130101; H01L 31/1864 20130101; H01L 31/0682
20130101; H01L 31/1884 20130101; H01L 31/022425 20130101; Y02E
10/547 20130101 |
International
Class: |
H01L 31/0224 20060101
H01L031/0224; H01L 31/18 20060101 H01L031/18 |
Claims
1. A system for fabricating electrode grids on a photovoltaic
structure, comprising: a masking tool configured to form a
patterned mask on a first surface of the photovoltaic structure,
wherein openings of the patterned mask correspond to grid line
locations of a first grid on the photovoltaic structure; a first
plating tool configured to deposit a first core layer of the first
grid in openings of the patterned mask; a second plating tool
configured to deposit a first protective layer on an exposed
surface of the first core layer while the patterned mask covers
sidewalls of the first core layer; a mask-removing tool configured
to remove the patterned mask subsequent to the deposition of the
first protective layer; and a thermal reflow tool configured to
apply heat to the first protective layer such that the first
protective layer reflows to cover both the exposed surface and
sidewalls of the first core layer.
2. The system of claim 1, wherein the first core layer comprises
Cu.
3. The system of claim 1, wherein a thickness of the first core
layer is between 10 and 100 microns.
4. The system of claim 1, wherein the first protective layer
comprises one or more metallic materials selected from a group
consisting of: tin; tin-lead alloy; tin-zinc alloy; tin-bismuth
alloy; tin-indium alloy; tin-silver-copper alloy; tin-lead-zinc
alloy; and tin-lead-copper alloy.
5. The system of claim 4, wherein the first protective layer
comprises tin, tin-lead alloy, or both.
6. The system of claim 1, wherein the first protective layer has a
melting point that is below 250.degree. C.
7. The system of claim 1, wherein, while depositing the first
protective layer, the second plating tool is configured to control
a thickness of the first protective layer to be between 0.3 and 10
microns.
8. The system of claim 1, wherein the reflow oven is configured to
reflow the first protective layer in a way such that a thickness of
the first protective layer is between 0.1 and 5 microns after the
reflow.
9. The system of claim 1, further comprising: a third plating tool
configured to deposit, over a second patterned mask on a second
surface of the photovoltaic structure, a second core layer of a
second grid; a fourth plating tool configured to deposit a second
protective layer on an exposed surface the second core layer while
the second patterned mask is covering sidewalls of the second core
layer; and a second thermal reflow tool configured to apply heat,
after the second patterned mask layer is removed, to the second
protective layer such that the second protective layer reflows to
cover both the exposed surface and sidewalls of the second core
layer.
10. The system of claim 9, wherein the first and second thermal
reflow tools are configured to reflow both protective layers
simultaneously.
11. The system of claim 9, wherein the first and second thermal
reflow tools are configured to reflow the first and second
protective layers sequentially.
12. The system of claim 1, wherein while applying the heat, the
first thermal reflow tool is configured to maintain the first
protective layer at a predetermined temperature for a predetermined
time period.
13. The system of claim 12, wherein the predetermined time period
is between 10 seconds and 2 minutes.
14. The system of claim 12, wherein the predetermined temperature
is 10 to 20.degree. C. higher than the first protective layer's
melting point.
15. The system of claim 1, wherein the first thermal reflow tool
includes one selected from a group consisting of: an oven; a hot
plate; an infrared lamp; a hot air blower; and a heated tunnel.
16. The system of claim 1, wherein the patterned mask includes one
of: a patterned layer of photoresist; a patterned layer of silicon
oxide; and a patterned layer of silicon nitride.
17-20. (canceled)
Description
CROSS-REFERENCE TO OTHER APPLICATIONS
[0001] This application/patent is a continuation application of
application Ser. No. 14/985,238, Attorney Docket Number P182-1NUS,
entitled "System and Method for Tin Plating Metal Electrodes," by
inventors Christoph G. Erben and Zhi-Wen Sun, filed 30 Dec. 2015,
the disclosure of which is incorporated herein by reference in
their entirety for all purposes.
FIELD OF THE INVENTION
[0002] This is related to fabrication of photovoltaic structures,
including fabrication of photovoltaic structures with tin-plated
metallic electrodes.
DEFINITIONS
[0003] "Solar cell" or "cell" is a photovoltaic structure capable
of converting light into electricity. A cell may have any size and
any shape, and may be created from a variety of materials. For
example, a solar cell may be a photovoltaic structure fabricated on
a silicon wafer or one or more thin films on a substrate material
(e.g., glass, plastic, or any other material capable of supporting
the photovoltaic structure), or a combination thereof.
[0004] A "photovoltaic structure" can refer to a solar cell, a
segment, or a solar cell strip. A photovoltaic structure is not
limited to a device fabricated by a particular method. For example,
a photovoltaic structure can be a crystalline silicon-based solar
cell, a thin film solar cell, an amorphous silicon-based solar
cell, a poly-crystalline silicon-based solar cell, or a strip
thereof.
[0005] "Finger lines," "finger electrodes," and "fingers" refer to
elongated, electrically conductive (e.g., metallic) electrodes of a
photovoltaic structure for collecting carriers.
[0006] A "busbar," "bus line," or "bus electrode" refers to an
elongated, electrically conductive (e.g., metallic) electrode of a
photovoltaic structure for aggregating current collected by two or
more finger lines. A busbar is usually wider than a finger line,
and can be deposited or otherwise positioned anywhere on or within
the photovoltaic structure. A single photovoltaic structure may
have one or more busbars.
BACKGROUND
[0007] The negative environmental impact of fossil fuels and their
rising cost have resulted in a need for cleaner, cheaper
alternative energy sources. Among different forms of alternative
energy sources, solar power has been favored for its cleanness and
wide availability.
[0008] A solar cell converts light into electricity using the
photovoltaic effect. Most solar cells include one or more p-n
junctions, which can include heterojunctions or homojunctions. In a
solar cell, light is absorbed near the p-n junction and generates
carriers. The carriers diffuse into the p-n junction and are
separated by the built-in electric field, thus producing an
electrical current across the device and external circuitry. An
important metric in determining a solar cell's quality is its
energy-conversion efficiency, which is defined as the ratio between
power converted (from absorbed light to electrical energy) and
power collected when the solar cell is connected to an electrical
circuit. High efficiency solar cells are essential in reducing the
cost to produce solar energy.
[0009] One important factor affecting the energy-conversion
efficiency of a solar cell is its internal resistance. Reducing
resistive loss can increase the energy outputted by the solar cell,
and hence the solar cell's efficiency. It has been shown that
electrode grids based on electroplated Cu have significantly lower
resistivity than conventional screen-printed Ag grids. In addition
to having lower resistivity, electroplated Cu grids also cost less
than the Ag grids. However, unlike Ag, Cu can be susceptible to
oxidation and corrosion. When exposed to moisture, Cu grids may
oxidize, resulting in increased resistivity and decreased strength.
Therefore, Cu grids of solar cells are often coated with a
corrosion-resistive protection layer. Conventional approaches for
coating Cu grids with such a corrosion-resistive protection layer
can generate hazardous waste.
SUMMARY
[0010] One embodiment of the invention can provide a system for
fabricating a photovoltaic structure. During fabrication, the
system can form a multilayer body of the photovoltaic structure and
a first grid on a first surface of the multilayer body. While
forming the first grid, the system can form a patterned mask on the
first surface of the multilayer body, with openings of the
patterned mask corresponding to grid line locations of the first
grid. The system can further deposit, using a plating technique, a
core layer of the first grid in the openings of the patterned mask;
deposit, using a plating technique, a protective layer on an
exposed surface of the core layer while the patterned mask covering
sidewalls of the core layer; remove the patterned mask to expose
the sidewalls of the core layer; and apply heat to the protective
layer such that the protective layer reflows to cover both the
exposed surface and sidewalls of the core layer.
[0011] In one embodiment, the patterned mask can include a
photoresist mask or a SiO.sub.2 mask.
[0012] In one embodiment, the core layer can be a metallic layer
that includes Cu.
[0013] The thickness of the core layer can be between 10 and 100
microns, for example.
[0014] The protective layer can be a metallic layer that includes
one or more of: tin, tin-lead alloy, tin-zinc alloy, tin-bismuth
alloy, tin-indium alloy, tin-silver-copper alloy, tin-lead-zinc
alloy, and tin-lead-copper alloy.
[0015] In a further variation, the protective layer can be a
metallic layer that includes one or more of: tin and tin-lead
alloy.
[0016] The thickness of the protective layer, before the protective
layer reflows, can be between 1 and 10 microns, for example.
[0017] The thickness of the protective layer, after the protective
layer reflows, can be between 0.1 and 2 microns, for example.
[0018] The multilayer body can include, for example, at least a
base layer, an emitter layer positioned on a first side of the base
layer, and a surface field layer positioned on a second side of the
base layer.
[0019] In a further variation, the multilayer body can further
include at least one of: a passivation layer positioned between the
base layer and the emitter layer, a second passivation layer
positioned between the base layer and the surface field layer, a
transparent conductive oxide layer positioned on the emitter layer,
and a second transparent conductive oxide layer positioned on the
surface field layer.
[0020] In a variation of this embodiment, the system can further
form a second grid on a second surface of the multilayer body,
which may be formed simultaneously with the first grid.
[0021] The above described embodiments and their variations can be
combined in any suitable manner.
BRIEF DESCRIPTION OF THE FIGURES
[0022] FIG. 1A shows an exemplary high-efficiency photovoltaic
structure.
[0023] FIG. 1B shows an amplified view of a metal line on a surface
of a photovoltaic structure.
[0024] FIGS. 2A-2O show exemplary intermediate photovoltaic
structures after certain fabrication steps, according to an
embodiment of the present invention.
[0025] FIGS. 3A-3G show exemplary intermediate photovoltaic
structures after certain fabrication steps, according to an
embodiment of the present invention.
[0026] FIG. 4 shows an exemplary fabrication system, according to
an embodiment of the present invention.
[0027] In the figures, like reference numerals refer to the same
figure elements.
DETAILED DESCRIPTION
[0028] The following description is presented to enable any person
skilled in the art to make and use the embodiments, and is provided
in the context of a particular application and its requirements.
Various modifications to the disclosed embodiments will be readily
apparent to those skilled in the art, and the general principles
defined herein may be applied to other embodiments and applications
without departing from the spirit and scope of the present
disclosure. Thus, the invention is not limited to the embodiments
shown, but is to be accorded the widest scope consistent with the
principles and features disclosed herein.
[0029] Systems and methods for fabricating low-cost high-efficiency
photovoltaic structures are provided. To ensure high-efficiency and
to reduce fabrication cost, a photovoltaic structure can use
electroplated Cu grids as electrodes on one or both surfaces.
Because Cu is susceptible to oxidation and corrosion, it can be
desirable to coat the Cu grid, including both its top surface and
sidewalls, with a protective layer. Tin, due to its anti-corrosion
property and low melting point, is often used to provide corrosion
protection and solderbility (if needed) to electroplated Cu grids.
In some embodiments, depositing a tin layer over a Cu grid can be
achieved via a tin plating process followed by the thermal reflow
of the tin layer. More specifically, during fabrication, a thick
tin-containing metallic layer can be plated onto the top surface of
an electroplated Cu grid while the sidewalls of the Cu grid are
still covered by the plating mask (e.g., a photoresist or SiO.sub.2
mask). Subsequently, the plating mask can be removed to expose the
sidewalls of the Cu grid, and the tin-containing metallic layer can
then be heated, causing the tin-containing metal to reflow. As a
result, the sidewalls of the Cu grid can now be covered by a
tin-containing metallic layer. Compared to the conventional
tin-immersion technique that generates toxic waste, this novel
fabrication process is advantageous, because it is environmental
friendly and can reduce fabrication cost.
Fabrication Processes
[0030] FIG. 1A shows an exemplary high-efficiency photovoltaic
structure. Photovoltaic structure 100 can include substrate 102,
surface-field layer 104, emitter layer 106, and electrode grids 108
and 110. In the example shown in FIG. 1A, substrate 102 can include
a lightly doped or substantially intrinsic crystalline Si (c-Si)
layer; surface-field layer 104 can include a heavily doped
amorphous Si (a-Si) layer; and emitter layer 106 can include a
heavily doped a-Si layer.
[0031] Surface-field layer 104 can face the majority of incident
light (as indicated by the sun), and hence can also be called the
front surface-field (FSF) layer. Substrate 102 can either be doped
with n-type dopants (e.g., phosphorus) or p-type dopants (e.g.,
boron). The doping types of FSF layer 104 and emitter layer 106 can
be determined by the doping type of substrate 102. For an n-type
doped substrate, FSF layer 104 can be doped with n-type dopants to
act as an electron collector; and emitter layer 106 can be doped
with p-type dopants to act as a hole collector. On the other hand,
for a p-type doped substrate, FSF layer 104 can be doped with
p-type dopants to act as a hole collector; and emitter layer 106
can be doped with n-type dopants to act as an electron
collector.
[0032] Electrode grids 108 and 110 are responsible for collecting
current. To ensure low electrical resistivity while resisting
oxidation and corrosion, electrode grids 108 and 110 can include an
electroplated Cu core and a protective layer covering the top
surface and sidewalls of the Cu core. FIG. 1B shows an amplified
view of a grid line on a surface of a photovoltaic structure. Grid
line 120 (e.g., a finger line or a busbar) can be positioned on
surface 130 of a photovoltaic structure. Grid line 120 can include
core layer 122 and protective layer 124. If the shape of the prism
is substantially rectangular (as shown in FIG. 1B), core layer 122
can have a top surface, a bottom surface, and four sidewalls. The
bottom surface can be in contact with surface 130 of the
photovoltaic structure, and the top surface and sidewalls covered
by protective layer 124. Protective layer 124 typically can contain
metallic materials that can resist corrosion, such as Ag and Sn
(tin), or non-metallic materials, such as certain
corrosion-resisting organic materials. Tin sometimes can be
preferred over Ag due to its lower cost and soldering ability.
[0033] Conventional approaches for depositing protective layer 124
often involves a metal immersion process, during which Ag or Sn
ions displace Cu ions on the top surface and sidewalls of Cu core
122. During the immersion-tin process, a complexing agent, such as
thiourea (SC(NH.sub.2).sub.2) and its derivatives, is needed,
because the redox potential of Cu is greater than that of Sn. More
specifically, Thiourea can reduce the redox potential of Cu from
+0.34 V to -0.39 V, which is lower than the redox potential of Sn
(-0.14 V), making it possible for Sn ions to replace the Cu
ions.
[0034] However, this immersion-tin approach faces a significant
challenge. More specifically, thiourea is a hazardous material
(e.g., it is suspected to be a carcinogen) and needs to be handled
with care. Not only does the working environment need to be
carefully controlled to prevent possible human exposure, the waste
solution generated by the emersion-tin process also needs to be
carefully treated. The treatment of the thiourea-containing waste
can be an expensive process, which can then add to the fabrication
cost of the solar panels.
[0035] To reduce fabrication cost, embodiments of the present
invention can deposit a protective layer over the electroplated Cu
grid without using thiourea. Instead of using an immersion process
that relies on displacement of metal ions, a
plating-followed-by-thermal-reflow process can be used to form a
protective layer surrounding the electroplated Cu finger lines or
busbars.
[0036] FIGS. 2A-2O show exemplary intermediate photovoltaic
structures after certain fabrication steps, according to an
embodiment of the present invention. FIG. 2A shows substrate 200.
In some embodiments, substrate 200 can include a solar grade Si
(SG-Si) wafer, which can be epitaxially grown or prepared using a
Czochralski (CZ) or Float Zone (FZ) method. The thickness of
substrate 200 can be between 80 and 300 microns, and typically
between 110 and 180 microns. The resistivity of the SG-Si wafer can
range from 0.5 ohm-cm to 10 ohm-cm, for example. Substrate 200 can
be intrinsic or lightly doped with n- or p-type dopants. In some
embodiments, substrate 200 can be doped with n-type dopants and can
have a doping concentration ranging from 1.times.10.sup.10/cm.sup.3
to 1.times.10.sup.16/cm.sup.3. In further embodiments, substrate
200 can have a graded doping profile. The preparation operation can
include typical saw damage etching that removes approximately 10
.mu.m of silicon and, optionally, surface texturing. The surface
texture can have various patterns, including but not limited to:
hexagonal-pyramid, inverted pyramid, cylinder, cone, ring, and
other irregular shapes. In one embodiment, the surface-texturing
operation can result in a random pyramid textured surface.
Afterwards, substrate 200 can go through extensive surface
cleaning.
[0037] FIG. 2B shows that a tunneling/passivation layer can be
formed on both surfaces of Si substrate 200 to form
tunneling/passivation layers 202 and 204, respectively. A
tunneling/passivation layer can include a single layer or a
multilayer structure. In some embodiments, a tunneling/passivation
multilayer structure can include a tunneling layer and one or more
passivation layers. In further embodiments, the tunneling layer can
include a thin oxide layer, and the passivation layer(s) can
include wide bandgap materials, such as intrinsic hydrogenated
amorphous Si (a-Si:H). Various oxidation techniques can be used to
form the thin oxide layer, including, but not limited to: wet
oxidation using oxygen or ozone bubbling at low temperatures, dry
oxidation at relatively high temperatures (around or below
400.degree. C.) (also known as thermal oxidation), low-pressure
radical oxidation, atomic layer deposition (ALD) of a SiO.sub.2
layer, plasma-enhanced chemical-vapor deposition (PECVD) of a
SiO.sub.2 layer, etc. The thin oxide layer can also include native
oxide. The thickness of the thin oxide layer can be between 1 and
50 angstroms, preferably between 1 and 10 angstroms. In some
embodiments, the tunneling layer can also function as a passivation
layer, and no additional passivation layer is needed.
[0038] The intrinsic a-Si:H passivation layer can be formed using a
chemical-vapor deposition (CVD) technique, such as PECVD. To ensure
superior passivation results and a low interface defect density
(D.sub.it), the intrinsic a-Si:H passivation layer may have graded
H content levels. At the interface to the tunneling layer or
substrate 200, the intrinsic a-Si:H passivation layer can have a
low H content level to ensure a low D.sub.it, whereas other
portions of the intrinsic a-Si:H passivation layer can have a
higher H content level to provide a wider bandgap, and hence better
passivation effects. Forming an intrinsic a-Si:H layer having
graded H content levels can involve adjusting the H flow rate
during the CVD process.
[0039] FIG. 2C shows that emitter layer 206 can be deposited on
tunneling/passivation layer 202. The doping type of emitter layer
206 can be opposite to that of substrate 200. For n-type doped
substrate, emitter layer 206 can be p-type doped. Emitter layer 206
can include doped a-Si or hydrogenated a-Si (a-Si:H). The thickness
of emitter layer 206 can be between 2 and 50 nm, preferably between
4 and 8 nm. In some embodiments, emitter layer 206 can have a
graded doping profile. The doping profile of emitter layer 206 can
be optimized to ensure good ohmic contact, minimum light
absorption, and a large built-in electrical field. In some
embodiments, the doping concentration of emitter layer 206 can
range from 1.times.10.sup.15/cm.sup.3 to
5.times.10.sup.20/cm.sup.3. In further embodiments, the region
within emitter layer 206 that is adjacent to tunneling/passivation
layer 202 can have a lower doping concentration, and the region
that is away from tunneling/passivation layer 202 can have a higher
doping concentration. The lower doping concentration at the
interface between tunneling/passivation layer 202 and emitter layer
206 can ensure a reduced interface defect density, and the higher
doping concentration on the other side can prevent emitter layer
depletion.
[0040] The crystal structure of emitter layer 206 can either be
nanocrystalline, which can enable higher carrier mobility; or
protocrystalline, which can enable good absorption in the
ultra-violet (UV) wavelength range and good transmission in the
infrared (IR) wavelength range. Both crystalline structures need to
preserve the large bandgap of the a-Si. For higher film
conductivity and better moisture barrier performance, the finishing
surface of emitter layer 206 (the surface away from
tunneling/passivation layer 202) should have a nanocrystalline
structure. Various deposition techniques can be used to deposit
emitter layer 206, including, but not limited to: atomic layer
deposition, PECVD, hot wire CVD, etc. In some embodiments,
depositions of an intrinsic a-Si:H passivation layer and emitter
layer 206 can be performed within the same CVD environment.
[0041] FIG. 2D shows that TCO layer 208 can be deposited on emitter
layer 206 using a physical vapor deposition (PVD) process, such as
sputtering or evaporation. Materials used to form TCO layer 208 can
include, but are not limited to: tungsten doped indium oxide (IWO),
indium-tin-oxide (ITO), GaInO (GIO), GaInSnO (GITO), ZnInO (ZIO),
ZnInSnO (ZITO), tin-oxide (SnO.sub.x), aluminum doped zinc-oxide
(ZnO:Al or AZO), gallium doped zinc-oxide (ZnO:Ga), and their
combinations. If emitter layer 206 is p-type doped, TCO layer 208
can have a relatively high work function (e.g., between 5 and 6 eV)
to ensure that the work function of TCO layer 208 matches that of
p-type doped a-Si. Examples of high work function TCO can include,
but are not limited to: GaInO (GIO), GaInSnO (GITO), ZnInO (ZIO),
ZnInSnO (ZITO), their combinations, as well as their combination
with ITO.
[0042] In FIG. 2E, a layer stack that includes surface field layer
210 and TCO layer 212 can be formed on the surface of
tunneling/passivation layer 204. Surface field layer 210 can have
the same doping type as that of substrate 200. For an n-type doped
substrate, surface field layer 210 can also be n-type doped. Other
than the conductive doping type, surface field layer 210 can be
similar to emitter layer 206 by having similar material make up,
thickness, doping profile, and crystal structure. For example, like
emitter layer 206, surface field layer 210 can include doped a-Si
or a-Si:H, and can have a thickness between 2 and 50 nm, preferably
between 4 and 8 nm. Alternatively, surface field layer 210 can also
include crystalline Si (c-Si). In some embodiments, the doping
concentration of surface field layer 210 can range from
1.times.10.sup.15/cm.sup.3 to 5.times.10.sup.20/cm.sup.3. The
doping profile of surface field layer 210 can also be similar to
that of emitter layer 206. Various deposition techniques can be
used to deposit surface field layer 210, including, but not limited
to: atomic layer deposition, PECVD, hot wire CVD, etc. In some
embodiments, depositions of an intrinsic a-Si:H passivation layer
and surface field layer 210 can be performed within the same CVD
environment.
[0043] TCO layer 212 can be deposited on surface field layer 210
using a physical vapor deposition (PVD) process, such as sputtering
or evaporation. Materials used to form TCO layer 212 can include,
but are not limited to: tungsten doped indium oxide (IWO),
indium-tin-oxide (ITO), GaInO (GIO), GaInSnO (GITO), ZnInO (ZIO),
ZnInSnO (ZITO), tin-oxide (SnO.sub.x), aluminum doped zinc-oxide
(ZnO:Al or AZO), gallium doped zinc-oxide (ZnO:Ga), and their
combinations. If surface field layer 210 is n-type doped, TCO layer
212 can have a relatively low work function (e.g., less than 4 eV).
Examples of low work function TCO materials include, but are not
limited to: AZO, IWO, ITO, F:SnO.sub.2, IZO, IZWO, and their
combinations.
[0044] FIG. 2F shows that thin metallic layers 214 and 226 can be
deposited onto TCO layers 208 and 212, respectively. Thin metallic
layers 214 and 226 can be deposited using a physical vapor
deposition (PVD) technique, such as sputtering deposition or
evaporation. Thin metallic layers 214 and 226 can be a single layer
that includes Cu, Ni, Ag, NiV, Ti, Ta, W, TiN, TaN, WN, TiW, NiCr,
and their combinations. In some embodiments, thin metallic layers
214 and 226 can also be a metallic stack that includes a layer of
one or more of the aforementioned metals directly deposited on the
TCO layer and/or a metallic seed layer having the same material
makeup (e.g., Cu) as that of the subsequently electroplated
metallic grid. The thickness of thin metallic layers 214 and 226
can be between 20 nm and 500 nm. Thin metallic layers 214 and 226
can improve the adhesion between TCO layer 208 and an electroplated
metallic grid. In some embodiments, thin metallic layers 214 and
226 can be deposited using separate PVD processes. Alternatively,
thin metallic layers 214 and 226 can be deposited using a single
PVD process.
[0045] FIG. 2G shows that a patterned mask 216 can be formed on top
of thin metallic layer 214. Windows (or openings) within mask 216
(e.g., windows 218 and 220) correspond to the locations of the
designed metallic grid. Patterned mask 216 can include a patterned
photoresist layer, which can be formed using a photolithography
technique. In one embodiment, patterning the photoresist can start
with screen-printing photoresist on top of metallic layer 214,
covering the entire wafer surface. The photoresist can then be
baked to remove solvent. An optical mask can be laid on the
photoresist, and the wafer can be exposed to UV light. After the UV
exposure, the optical mask can removed, and the photoresist can be
developed in a photoresist developer. Windows 218 and 220 can be
formed after the photoresist is developed. In addition to printing,
the photoresist can also be applied onto thin metallic layer 214 by
spraying, dip coating, or curtain coating. Dry film resist can also
be used.
[0046] Alternatively, patterned mask 216 can include a patterned
layer of silicon oxide (SiO.sub.2). In one embodiment, a patterned
SiO.sub.2 mask can be formed by first depositing a layer of
SiO.sub.2 using a low-temperature PECVD process. In a further
embodiment, a patterned SiO.sub.2 mask can be formed by dip-coating
the surface of a wafer using silica slurry, followed by
screen-printing an etchant that includes hydrofluoric acid or
fluorides. Other materials (e.g., SiN.sub.x) can also be possible
to form patterned mask 216, as long as the masking material is
electrically insulating. In some embodiments, patterned mask 216
can have a thickness of tens of microns (e.g., between 20 and 100
microns), and windows 218 and 220 can have a width between 10 and
3000 microns. If a window is used to define a finger line, its
width can be between 20 and 80 microns; and if a window is used to
define a busbar, its width can be between 500 and 3000 microns.
[0047] FIG. 2H shows that metallic or non-metallic materials can be
deposited into the windows of patterned mask 216 to form core layer
222. If core layer 222 includes metallic materials (e.g., Cu), it
can be formed using a plating technique, which can include
electroplating and/or electroless plating. In some embodiments, the
photovoltaic structure, including thin metallic layer 214 and
patterned mask 216, can be submerged in an electrolyte solution
that permits the flow of electricity. During plating, thin metallic
layer 214 can be coupled to the cathode of the plating power
supply, and the anode of the plating power supply can include a
metallic target (e.g., a Cu target). Because mask 216 is
electrically insulating and the windows within mask 216 are
electrically conductive, metallic ions will be selectively
deposited into the windows in mask 216, forming a metallic grid
with a designed pattern. To deposit a Cu grid, a Cu plate or a
basket of copper chunks can be used as the anode, and the
photovoltaic structure can be submerged in an electrolyte suitable
for Cu plating (e.g., a CuSO.sub.4 solution). To prevent plating on
the other side of the photovoltaic structure, a layer of insulating
material (e.g., photoresist) can be used to cover the surface of
thin metallic layer 226. To ensure a well-defined aspect ratio, it
is desirable to have the thickness of mask 216 to be greater than
or equal to the desired thickness of metallic core layer 222. In
some embodiments, the thickness of metallic core layer 222 can
between 10 and 100 microns, preferably between 30 and 50 microns.
Note that, high aspect-ratios grid lines are important to obtain
low-resistance electrodes while reducing shading loss.
[0048] FIG. 2I shows that additional materials can be deposited on
top of core layer 222 to form protective layer 224, while patterned
mask 216 remains intact. Materials used to form protective layer
224 can include materials that are corrosion resistive and have a
relatively low melting point. It is preferable to use metallic
materials with a melting point lower than 250.degree. C. to
preserve the electronic quality of the a-Si:H emitter and surface
field layers. Tin, due to its low melting point (around 230.degree.
C.) and its anti-corrosion ability, can often be used to form
protective layer 224. Other materials, including but not limited
to: tin-lead alloy, tin-zinc alloy, tin-bismuth alloy, tin-indium
alloy, silver-lead alloy, tin-silver-copper alloy, tin-lead-zinc
alloy, tin-lead-copper alloy, etc., can also be used to form
protective layer 224. In some embodiments, metallic protective
layer 224 can be formed using a plating process similar to the one
used to form metallic core layer 222.
[0049] Because patterned mask 216 is largely electrically
insulating, during plating, metallic ions forming metallic
protective layer 224 can only attach to metallic core layer 222,
covering its top surface. The thickness of the plated metallic
protective layer 224 can be between 0.3 and 10 microns, preferably
between 3 and 7 microns, more preferably around 5 microns. A
sufficient amount of protective material needs to be deposited here
in order to provide, at a later time, sufficient coverage to the
sidewalls of the core layer.
[0050] FIG. 2J shows that patterned mask 216 can be removed. If
mask 216 includes photoresist, a photoresist stripper can be used
to strip off photoresist mask 216. If mask 216 includes SiO.sub.2,
hydrofluoric acid or buffered hydrofluoric acid can be used to etch
off SiO.sub.2 mask 216. Note that, after mask 216 is removed,
sidewalls of metallic core layer 222 are exposed.
[0051] FIG. 2K shows that, using metallic protective layer 224 as a
mask, thin metallic layer 214 can be selectively etched to expose
the underneath TCO layer 208, making it possible for light to reach
the junctions. Etching thin metallic layer 224 can be optional if
thin metallic layer 214 is extremely thin to be transparent.
[0052] FIG. 2L shows that heat can be applied to the photovoltaic
structure to cause protective layer 224 to reflow. More
specifically, heat can be applied to protective layer 224, raising
its temperature to a predetermined value such that protective layer
224 reflows (i.e., it melts and starts to flow). As a result of the
thermal reflow, protective layer 224 can now cover both the top
surface and sidewalls of core layer 222. Protective layer 224 can
also cover sidewalls of thin metallic layer 214, preventing thin
metallic layer 214 from being exposed to the environment.
[0053] Various heating techniques can be used to generate the
thermal reflow, including but not limited to: placing the
photovoltaic structure into an oven, placing the photovoltaic
structure onto a hot plate, using an infrared lamp, blowing hot
air, etc. In some embodiments, the heating device can include a
conveyor system to allow a larger number of wafers to be processed
inline. For example, a conveyor can carry wafers through a heated
tunnel, and thermal reflow of protective layer 224 can occur while
the wafers passing through the heated tunnel. The temperature of
the environment can be carefully controlled to ensure the reflow of
protective layer 224 without causing damage to other layers.
Similarly, the thermal profile (e.g., the temperature
rising/cooling rate) also needs to be well controlled to reduce
thermal stress. For example, the temperature can be controlled to
ramp up slowly to a predetermined value that is above the melting
point of protective layer 224. The predetermined temperature can be
10 to 20.degree. C. higher than the melting point. Once melted, due
to surface tension, protective layer 224 can wet the underneath
core layer 222, covering its sidewalls. The time duration that
protective layer 224 remains above its melting point can be
referred to as the wetting time and can depend on the time it takes
for protective layer 224 to completely wet the sidewalls of
metallic core layer 222. If the wetting time is kept too short, the
sidewalls of metallic core layer 22 may not be sufficiently
covered. On the other hand, excessive wetting time can result in
intermetallic structures or large grain structures being formed in
protective layer 224. This can then cause protective layer 224 to
become brittle and weaker. In some embodiments, the wetting time
can be between 10 seconds and 2 minutes, preferably between 30
seconds and 1 minute.
[0054] After wetting, protective layer 224 needs to cool down to
below the melting point. A relatively rapid cooling down process
can be needed to reduce the possibility of large grain structures
being formed. In some embodiments, water-cooling or
refrigerated-cooling can be included as part of the thermal reflow
operation. After the thermal reflow, the thickness of protective
layer 224 can be between 0.1 and 5 microns, preferably between 0.5
and 1 micron. Note that, after reflow, protective layer 224 needs
to be sufficiently thick in order to provide adequate
anti-corrosion protection to the underneath metallic (e.g., Cu)
layer.
[0055] In FIG. 2M, the backside grid that comprises core layer 228
and protective layer 230 can be formed on top of thin metallic
layer 226 using processes similar to the ones shown by FIGS. 2G-2J.
If plating is used for depositions of core layer 228 and protective
layer 230, the front side of the photovoltaic structure needs to be
protected (e.g., by using photoresist).
[0056] FIG. 2N shows that thin metallic layer 226 can be
selectively etched using a process similar to the one shown in FIG.
2K. As a result, TCO layer 212 can be partially exposed.
[0057] FIG. 2O shows that heat can be applied to protective layer
230, causing it to reflow to cover the sidewalls of core layer 228.
The thermal reflow process of protective layer 230 can be similar
to the one used in operation 2L.
[0058] In the example shown in FIGS. 2A-2O, the top and bottom
grids are formed one after the other, i.e., the top grid is formed,
including performing the thermal reflow, before materials forming
the bottom grid are plated. In practice, it can also be possible to
combine metallization processes on both sides of the photovoltaic
structure. For example, it can be possible to simultaneously
plating both sides of the photovoltaic structure. In addition, it
can also be possible to perform thermal reflow on both sides of the
photovoltaic structure. The fabrication throughput can be
significantly improved if electrode grids on both sides of the
photovoltaic structures can be formed simultaneously.
[0059] FIGS. 3A-3G show exemplary intermediate photovoltaic
structures after certain fabrication steps, according to an
embodiment of the present invention. FIG. 3A shows a multilayer
body of a photovoltaic structure. The multilayer body can be
prepared using processes similar to those shown by FIGS. 2A-2F. The
multilayer body can include base layer 300, tunneling/passivation
layers 302 and 304, surface field layer 306, emitter layer 308, TCO
layers 310 and 312, and Cu seed layers 314 and 316.
[0060] FIG. 3B shows that patterned photoresist masks 318 and 320
can be formed on Cu seed layers 314 and 316, respectively. Forming
these two patterned masks can involve depositing and exposing
photoresist on each side of the photovoltaic structure in sequence,
and then simultaneously developing photoresist on both sides.
[0061] FIG. 3C shows that the photovoltaic structure can be
submerged into an electrolyte solution suitable for Cu plating
(e.g., CuSO.sub.4) to simultaneously form Cu core layers 322 and
324 on metallic seed layers 314 and 316, respectively. Note that,
because photoresist is electrically insulating, Cu ions can only be
deposited at locations that correspond to windows of masks 318 and
320. During plating, Cu seed layers 314 and 316 both can be
electrically coupled to the plating cathode.
[0062] FIG. 3D shows that the photovoltaic structure can be
submerged into an electrolyte solution suitable for tin plating
(e.g., a solution containing SnSO.sub.4) to simultaneously form tin
layers 326 and 328 on Cu core layers 322 and 324, respectively.
[0063] FIG. 3E shows that photoresist masks 318 and 320 can be
removed simultaneously using a photoresist stripper, exposing the
sidewalls of Cu core layers 322 and 324.
[0064] FIG. 3F shows that, using tin layers 326 and 328 as masks,
Cu seed layers 314 and 316 can be selectively etched to expose TCO
layers 310 and 312. If wet etching is used, Cu seed layers 314 and
316 can be etched simultaneously by submerging the photovoltaic
structure into the etching solution.
[0065] FIG. 3G shows that the photovoltaic structure can be heated
to a temperature slightly above the melting point of tin (e.g., to
about 240.degree. C.), causing tin layers 326 and 328 to reflow to
cover the sidewalls of Cu core layers 322 and 324. Cu seed layers
314 and 316 can also be buried by reflowed tin layers 326 and 328,
respectively. To allow simultaneous reflow of both tin layers 326
and 328, the photovoltaic structure may need to be mounted onto a
vertically oriented wafer carrier to ensure even heating to both
surfaces. In cases where the heat is applied via radiation, heating
elements may be arranged in a way such that both surfaces of the
photovoltaic structures experience substantially even heating.
Fabrication System
[0066] FIG. 4 shows an exemplary fabrication system, according to
an embodiment of the present invention.
[0067] Fabrication system 400 can include wet station 402, CVD tool
404, PVD tool 406, photolithography tool 408, plating baths 410 and
412, and thermal reflow oven 414. Wet station 402 (also known as a
wet bench) can include a number of baths, each containing a
particular solution, used for the various wet processes (e.g.,
surface cleaning and texturing, wet oxidation, wet etching, etc).
For large-scale fabrications, wet station 402 can process Si
substrates in batches, with each batch including tens or hundreds
of Si substrates. During fabrication, crystalline Si wafers can
first undergo a number of wet processes at wet station 402,
including surface cleaning, saw-damage removing, surface texturing,
and wet oxidation.
[0068] The substrates emerging from wet station 402 can have a thin
oxide layer formed on both surfaces, and can be sent to CVD tool
404 for material deposition. In some embodiments, CVD tool 404 can
be used to deposit one or more passivation layer(s), an emitter
layer, and a surface field layer. CVD tool 404 can be a combined
CVD system that includes both static-processing CVD modules and
inline-processing CVD modules. The static-processing modules can be
used to deposit layers having higher surface quality requirements,
and the inline-processing modules can be used to deposit layers
having lower surface quality requirements. In some embodiments,
photovoltaic structures may need to go through CVD tool two times
to complete fabrications on both sides.
[0069] Photovoltaic structures emerging from CVD tool 404 can be
transported, sometimes via an automated conveyor system, to PVD
tool 406, which can be used to deposit a TCO layer and one or more
thin metallic layers on each side of the photovoltaic structures.
In some embodiments, PVD tool 406 can be configured to sequentially
deposit a TCO layer and one or more thin metallic layers, without
breaking vacuum. For example, PVD tool 406 can include a
multiple-target sputtering tool (e.g., an RF magnetron sputtering
tool). The multiple targets inside the deposition chamber can
include an ITO target and one or more metallic targets. In some
embodiments, a target can be a rotary target electrically coupled
to a periodically tuned capacitor to ensure uniform target
depletion. PVD tool 406 can also be configured to include a
vertically oriented wafer carrier to enable simultaneous material
deposition on both sides of the photovoltaic structures.
[0070] Photovoltaic structures emerging from PVD tool 406 can
include a complete layer stack on both sides, and can be
transported to photolithography tool 408. Optionally, before being
sent to photolithography tool 408, the photovoltaic structures can
go through a rapid annealing process at a temperature greater than
200.degree. C. to anneal both the TCO and the one or more metallic
layers. Photolithography tool 408 can deposit a patterned
photoresist mask on one or both sides of the photovoltaic
structures. The mask pattern can correspond to the pattern of a
subsequently formed metallic grid, with windows in the mask
corresponding to locations of the metal lines.
[0071] Plating baths 410 and 412 each can contain an electrolyte
solution suitable for electroplating a certain metallic material.
For example, plating bath 410 can be used to plate the core layer
of a metallic grid, and plating bath 412 can be used to plate the
protective layer of the metallic grid. The core layer of the
metallic grid can include metallic materials with low resistivity,
such as Cu. Accordingly, plating bath 410 can contain an
electrolyte solution that includes Cu ions. The protective layer of
the metallic grid can include corrosion-resisting, low-melting
point metallic materials, such as tin, tin-lead alloy, tin-zinc
alloy, tin-bismuth alloy, tin-indium alloy, silver-lead alloy,
tin-silver-copper alloy, tin-lead-zinc alloy, tin-lead-copper
alloy, etc. Accordingly, plating bath 412 can contain an
electrolyte solution that includes Sn ions and other appropriated
metal ions. Photovoltaic structures with a patterned mask on one or
both sides can be submerged into plating baths 410 and 412
sequentially, resulting in the sequential deposition of the core
layer and the protective layer of an electrode grid on the one or
both sides. To ensure high throughput, plating baths 410 and 412
can both be equipped with a cathode that can move from one end of a
plating bath to the other end during plating; and photovoltaic
structures can be attached to the moving cathode using custom
designed jigs. The custom designed jig can establish electrical
connections to both surfaces of the wafers, thus allowing
simultaneous plating on both sides of the photovoltaic structures.
It can also be possible to use to the same moving cathode in both
plating baths, thus eliminating the need to unload and load the
photovoltaic structures between plating operations.
[0072] Photovoltaic structures emerging from the plating baths can
be sent back to photolithography tool 408 for the removal of the
photoresist mask to expose the sidewalls of the core layer of the
metallic grids. Alternatively, the removal of the photoresist mask
can be performed at wet station 402. Afterwards, the photovoltaic
structures can also be sent to wet station 402 for selective
etching of the one or more thin metallic layers to expose the
underneath TCO layer(s). Subsequent to the wet etching, the
photovoltaic structures can be cleaned and dried before being sent
to thermal reflow oven 414. Thermal reflow oven 414 can include a
conveyor system (e.g., a conveyor belt) and a number of
heating/cooling zones. Photovoltaic structures can be loaded onto
the conveyor and move through the different heating/cooling zones.
When the protective layer of the metallic grid reaches its melting
point, it can reflow to cover the sidewalls of the core layer. The
thermal profile of the protective layer can be controlled by
adjusting the temperature setting in each heating/cooling zone and
the speed of the conveyor. The fabrication of the metallic grid can
be completed once the photovoltaic structures are sufficiently
cooled and the protective layer re-solidified. If metallic grids on
both sides are completed, the photovoltaic structures can be sent
to a packaging tool, which can divide the standard photovoltaic
structures into smaller strips, cascading the smaller strips into
strings, and placing the strings into a protective frame to obtain
a solar panel. If only one side of the photovoltaic structures has
a completed metallic grid, the photovoltaic structures can be sent
back to photolithography tool 408 to continue the fabrication of a
metallic grid on the other side.
[0073] Variations to the fabrication system shown in FIG. 4 are
also possible. For example, an alternative fabrication system may
have two CVD tools to allow material depositions on different sides
of the photovoltaic structures to be performed in different CVD
tools. This way, the photovoltaic structures do not need to go
through the same CVD tool twice, thus reducing the wait time and
further increasing the fabrication throughput. The fabrication
system can also include one or more annealing stations that can
anneal the TCO layers and/or the metallic seed layers. In addition
to using a plating bath, the protective layer can also be deposited
using a PVD tool, which can be the same PVD tool used for the TCO
and/or metallic seed layer deposition or a different PVD tool.
[0074] The foregoing descriptions of various embodiments have been
presented only for purposes of illustration and description. They
are not intended to be exhaustive or to limit the invention to the
forms disclosed. Accordingly, many modifications and variations
will be apparent to practitioners skilled in the art. Additionally,
the above disclosure is not intended to limit the invention.
* * * * *