U.S. patent application number 15/413273 was filed with the patent office on 2017-06-22 for pixel structure and display device.
This patent application is currently assigned to Xiamen Tianma Micro-Electronics Co., Ltd.. The applicant listed for this patent is Tianma Micro-Electronics Co., Ltd., Xiamen Tianma Micro-Electronics Co., Ltd.. Invention is credited to Xuexin Lan.
Application Number | 20170179165 15/413273 |
Document ID | / |
Family ID | 58167574 |
Filed Date | 2017-06-22 |
United States Patent
Application |
20170179165 |
Kind Code |
A1 |
Lan; Xuexin |
June 22, 2017 |
PIXEL STRUCTURE AND DISPLAY DEVICE
Abstract
The present application discloses a pixel structure and a
display device. The pixel structure includes: a scan line having a
branch structure; and a semiconductor pattern intersecting with the
scan line and the branch structure. The semiconductor pattern
includes: a first channel region disposed below the scan line; a
second channel region disposed below the branch structure; and
doping regions respectively disposed at two sides of the first
channel region and at two sides of the second channel region.
Wherein, the width of the second channel region is less than the
width of the first channel region. The pixel structure may improve
the display performance of the display screen.
Inventors: |
Lan; Xuexin; (Xiamen,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Xiamen Tianma Micro-Electronics Co., Ltd.
Tianma Micro-Electronics Co., Ltd. |
Xiamen
Shenzhen |
|
CN
CN |
|
|
Assignee: |
Xiamen Tianma Micro-Electronics
Co., Ltd.
Xiamen
CN
Tianma Micro-Electronics Co., Ltd.
Shenzhen
CN
|
Family ID: |
58167574 |
Appl. No.: |
15/413273 |
Filed: |
January 23, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/78696 20130101;
H01L 29/78672 20130101; G02F 2202/104 20130101; H01L 29/78648
20130101; H01L 27/1255 20130101; G02F 1/136286 20130101; G02F
1/1368 20130101; H01L 29/78645 20130101; H01L 27/1233 20130101;
H01L 27/124 20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12; G02F 1/1362 20060101 G02F001/1362; G02F 1/1368 20060101
G02F001/1368; H01L 29/786 20060101 H01L029/786 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 12, 2016 |
CN |
201610816672.9 |
Claims
1. A pixel structure, comprising: a scan line having a branch
structure; and a semiconductor pattern intersecting with the scan
line and the branch structure, wherein the semiconductor pattern
comprises: a first channel region corresponding to the scan line; a
second channel region corresponding to the branch structure; and
doping regions respectively disposed at two sides of the first
channel region and at two sides of the second channel region,
wherein a width of the second channel region is less than a width
of the first channel region.
2. The pixel structure according to claim 1, wherein the branch
structure is an L-shaped branch.
3. The pixel structure according to claim 2, wherein the L-shaped
branch comprises a first portion and a second portion, the first
portion extends perpendicularly from the scan line, and the second
portion intersects perpendicularly with the semiconductor
pattern.
4. The pixel structure according to claim 2, wherein the
semiconductor pattern comprises a linear portion, the second
portion of the L-shaped branch intersects with the first portion of
the L-shaped branch, and the second portion of the L-shaped branch
intersects perpendicularly with the linear portion of the
semiconductor pattern.
5. The pixel structure according to claim 1, wherein the branch
structure extends perpendicularly from the scan line.
6. The pixel structure according to claim 5, wherein the
semiconductor pattern comprises at least a first portion and a
second portion, the first portion intersects perpendicularly with
the scan line, and the second portion intersects perpendicularly
with the branch structure.
7. The pixel structure according to claim 1, wherein the width of
the second channel region is one fifth to four fifth of the width
of the first channel region.
8. The pixel structure according to claim 1, wherein the
semiconductor pattern comprises a polysilicon pattern.
9. The pixel structure according to claim 1, wherein the width of
the pixel structure is less than 15 um.
10. The pixel structure according to claim 1, wherein the pixel
structure has a pixel storage capacitance less than 150 fF.
11. A display device, comprising a pixel structure according to
claim 1.
12. The display device according to claim 11, wherein the branch
structure is an L-shaped branch.
13. The display device according to claim 12, wherein the L-shaped
branch comprises a first portion and a second portion, the first
portion extends perpendicularly from the scan line, and the second
portion extends perpendicularly from the semiconductor pattern.
14. The display device according to claim 12, wherein the
semiconductor pattern comprises a linear portion, the second
portion of the L-shaped branch intersects with the first portion of
the L-shaped branch, and the second portion of the L-shaped branch
intersects perpendicularly with the linear portion of the
semiconductor pattern.
15. The display device according to claim 11, wherein the branch
structure extends perpendicularly from the scan line.
16. The display device according to claim 15, wherein the
semiconductor pattern comprises at least a first portion and a
second portion, the first portion intersects perpendicularly with
the scan line, and the second portion intersects perpendicularly
with the branch structure.
17. The display device according to claim 11, wherein the width of
the second channel region is 1/5 to 4/5 of the width of the first
channel region.
18. The display device according to claim 11, wherein the
semiconductor pattern comprises a polysilicon pattern.
19. The display device according to claim 11, wherein the width of
the pixel structure is less than 15 um.
20. The display device according to claim 11, wherein the pixel
structure has a pixel storage capacitance less than 150 fF.
Description
CROSS REFERENCE
[0001] This application is based upon and claims priority to
Chinese Patent Application No. 201610816672.9, filed on Sep. 12,
2016, the entire contents thereof are incorporated herein by
reference.
TECHNICAL FIELD
[0002] The present disclosure relates to the technical field of
crystal displays, and more particularly to a pixel structure and a
display device.
BACKGROUND
[0003] With the rapid development of display technology, high PPI
(Pixels Per Inch), and even ultra-high PPI has become an inevitable
trend. Image resolution is generally expressed in PPI (number of
pixels per inch), and the higher the PPI value is, the higher the
density of the display screen (pixels) for displaying an image is.
The higher the PPI of the display is, the more detail a displayed
image will contain, and the higher the fidelity will be. However,
with the improvement of the PPI of the screen, more and more
closely pixels will be arranged, the size of each pixel has to
become smaller and smaller, which not only poses great challenges
to the design of the device, but also leads to many
difficulties.
[0004] Among many technical problems that restrict the high PPI
technology, insufficient charging capacity is one of the reasons
that challenge the high PPI technology. The main factors that
restrict the high-PPI charging capacity may be: a heavy load of a
LCD panel, a short pixel charging time, existence of a feed-through
voltage and a limited width-to-length ratio of the pixel, and so
on, in which the feed-through is important to the high PPI
technology with a small pixel storage capacitance (less than 32 fF)
as shown in FIG. 1.
[0005] There are several methods for reducing the feed-through
voltage of the pixel: reducing a width of the pixel structure and a
width of a channel of the pixel structure, reducing a capacitance
of a gate oxide layer in the pixel structure, reducing a voltage
difference of a thin-film transistor (TFT) when the liquid crystal
screen is turned on and turned off, and increasing the storage
capacitance of the pixel structure, and so on. However, for a
high-PPI product, since a pitch between pixels is very small, it is
difficult to increase the storage capacitance of the pixel
structure. While reducing the width of the channel of the pixel
structure or reducing the voltage difference of the thin-film
transistor (TFT) when the liquid crystal screen is turned on and
turned off means further reducing the charging capability. Reducing
the capacitance of the gate oxide layer of the pixel structure
means increasing the thickness of the film or reducing the
dielectric coefficient. This goes away from the trend of
miniaturization of the device, and this will reduce the current of
the device in a turned-on state. As a result, it will reduce the
charging capacity. Reducing the width of the channel of the pixel
structure can reduce the feed-through voltage and improve the
charging capability. However, it will bring about other problems
such as increased gate delay and unequal charging capability on the
left side and on the right side of the panel.
[0006] Therefore, a method and a structure for reducing a
feed-through voltage are demanded.
[0007] The above-mentioned information disclosed in the background
section is only for the purpose of enhancing the understanding of
the background of the invention and thus it may include information
which does not constitute prior art known to those of ordinary
skill in the art.
SUMMARY
[0008] The present disclosure provides a pixel structure, which can
lower the feed-through voltage without increasing gate delay. It
may improve the charge capacity of the device and it may improve
the display performance of the display screen.
[0009] Other characteristics and advantages of the present
disclosure may become apparent from the following detailed
description, and may be partly learned by practicing the present
disclosure.
[0010] According to one aspect of the present disclosure, there is
provided a pixel structure, including a scan line having a branch
structure; and a semiconductor pattern intersecting with the scan
line and the branch structure. The semiconductor pattern includes:
a first channel region corresponding to the scan line; a second
channel region corresponding to the branch structure; and doping
regions respectively disposed at two sides of the first channel
region and at two sides of the second channel region, wherein a
width of the second channel region is less than a width of the
first channel region.
[0011] According to the pixel structure of the present disclosure,
the feed-through voltage may be lowered without increasing gate
delay. Moreover, the charge capacity of the device may be enhanced,
and it may improve the display performance of the display
screen.
[0012] It should be understood that the above general description
and the detailed description below are merely illustrative, rather
than limiting the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The above and other objectives, features and advantages of
the present disclosure will become more apparent from exemplary
embodiments thereof which are described in detail with reference to
accompanying drawings.
[0014] FIG. 1 schematically illustrates a graph of how a
feed-through voltage influences charging capability of a pixel.
[0015] FIG. 2 is a schematic diagram of a pixel structure according
to an exemplary embodiment in accordance with the present
disclosure.
[0016] FIG. 3 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0017] FIG. 4 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0018] FIG. 5 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0019] FIG. 6 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0020] FIG. 7 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0021] FIG. 8 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0022] FIG. 9 is a schematic cross sectional view of a pixel
structure according to an exemplary embodiment in accordance with
the present disclosure.
[0023] FIG. 10 is a simulation circuit diagram of a pixel structure
according to an exemplary embodiment in accordance with the present
disclosure.
[0024] FIG. 11 is a simulation circuit diagram of a pixel structure
according to another exemplary embodiment in accordance with the
present disclosure.
[0025] FIG. 12 is a graph of positive-frame charging of a
simulation circuit of a pixel as shown in FIGS. 6 and 7 according
to an exemplary embodiment in accordance with the present
disclosure.
[0026] FIG. 13 is a graph of negative-frame charging of a
simulation circuit of a pixel as shown in FIGS. 6 and 7 according
to an exemplary embodiment in accordance with the present
disclosure.
DETAILED DESCRIPTION
[0027] Now, the exemplary embodiments will be described fully with
reference to the accompanying drawings. However, the exemplary
embodiments may be implemented in various forms, and should not be
understood as being limited to the examples set forth herein.
Instead, these embodiments are provided to make the present
disclosure more thorough and complete, and to fully convey the
concept of the exemplary embodiments to those skilled in the art.
The accompanying drawings are merely schematic illustration of the
present disclosure, and may not be depicted in scale. Like
reference numbers throughout the drawings represent same or similar
components, and the description thereof will be omitted.
[0028] In addition, the features, structures or characteristics
described herein may be combined in one or more embodiments with a
proper manner. In the description below, many specific details are
given for through understanding of the embodiments described in the
present disclosure. However, it should be appreciated by those
skilled in the art that, the technical solution of the present
disclosure may be practiced without one or more of the particular
details, or may utilize other components, device, etc. In other
situations, structures, devices, materials which are well known
will not be illustrated or described in detail to avoid obscuring
the aspects of the present disclosure.
[0029] FIG. 2 is a schematic diagram of a pixel structure according
to an exemplary embodiment in accordance with the present
disclosure.
[0030] As shown in FIG. 2, a pixel structure 200 according to an
exemplary embodiment includes a scan line 210, a data line 220
intersecting with the scan line 210, a semiconductor pattern 230
and a transparent pixel electrode 240. The pixel structure 200 may
be disposed on a substrate (not shown). In FIG. 2, the
semiconductor pattern 230 is disposed below the scan line 210, and
the data line 220 is disposed below the scan line 210. However, the
present disclosure is not limited thereto.
[0031] The semiconductor pattern 230 also includes a
drain-electrode contact 233 and a source-electrode contact 234.
[0032] As shown in FIG. 2, the scan line 210 has a branch structure
211. The branch structure 211 extends vertically from the scan line
210. However, the present disclosure is not limited thereto.
[0033] The semiconductor pattern 230 intersects respectively with
the scan line 210 and the branch structure 211. The semiconductor
pattern 230 includes a first channel region 231 which corresponds
to the scan line 210, a second channel region 232 which corresponds
to the branch structure 211, doping regions 235A, 235B and 235C
respectively on the two sides of the first channel region 231 and
on the two sides of the second channel region 232.
[0034] As shown in FIG. 2, the first channel region 231, the second
channel region 232 and the doping regions 235A, 235B and 235C as
well as the portions of the scan line 210 and the branch structure
211 to which the first channel region 231, the second channel
region 232 correspond may be configured to form a multi-channel
(multi-gate) thin-film transistor 230.
[0035] According to an exemplary embodiment, an asymmetric double
gate (or multi-gate) structure is provided. For example, as shown
in FIG. 2, the branch structure 211 intersecting with the
semiconductor pattern 230 has a width L2 less than a width L1 of
the scan line 210. Since the first channel region 231 corresponds
to the scan line 210, the first channel region 231 has a width
equal to the width L1 of the scan line 210. In the present
embodiment, L1 represents the width of the first channel region 231
or the width of the scan line 210. Since the second channel region
232 corresponds to the branch structure 211, the second channel
region 232 has a width equal to the width L2 of the branch
structure 211. In the present embodiment, L2 represents the width
of the second channel region 232 or the width of the branch
structure 211. That is, the width of the second channel region 232
is less than the width of the first channel region 231. Therefore,
the width of another channel region may be reduced without changing
the width of the scan line. By so doing, the stray capacitance may
be reduced and the feed-through voltage may be lowered without
increasing gate delay.
[0036] In embodiments in accordance with the present disclosure,
the width mentioned herein is merely for easy description, rather
than limiting the present disclosure. In the embodiments of the
present disclosure, the terms "length" and "width" may be
interchangeable.
[0037] In some embodiments, the width of the second channel region
232 is L2 as shown in FIG. 2, which may be 1/5 to 4/5 of L1 as
shown in FIG. 2, where L1 is the width of the first channel region
231. This can achieve desirable balance between performance and
cost. It should be understood that the present disclosure is not
limited thereto, and the width of the second channel region 232 may
be smaller. As long as the manufacturing technology permits and
won't cause the TFT device to fail, the width of the second channel
region 232 may be even smaller.
[0038] In some embodiments, the semiconductor pattern 230 may be
made of polysilicon material, for example. That is , the
semiconductor pattern 230 may be a polysilicon pattern.
[0039] In an exemplary embodiment, as shown in FIG. 2, the pixel
structure 200 may also include the drain-electrode contact 233 and
the source-electrode contact 234. The data line 220 may be
electrically connected to the source-electrode contact 234. The
transparent pixel electrode 240 may be electrically connected to
the drain-electrode contact 233.
[0040] In an exemplary embodiment, as shown in FIG. 2, the
semiconductor pattern 230 may also include a capacitor electrode
237.
[0041] In an exemplary embodiment, the width L2 of the second
channel region 232 is smaller than the width L1 of the first
channel region 231. This may effectively reduce the stray
capacitance in the pixel structure. Therefore, the pixel structure
in the exemplary embodiment may be applicable to situation where
the pixel structure has a small width and the pixel storage
capacitance is low. For example, in some embodiments, the width of
the pixel structure may be less than 15 um. As another example, in
some embodiments, the value of the pixel storage capacitance may be
less than 150 fF. This is difficult to be achieved with
conventional technology. Therefore, the pixel structure of this
embodiment in accordance with the present disclosure is applicable
to high PPI technology which has low pixel storage capacitance. It
can effectively improve the charging capacity of a high-PPI display
screen, and in turn, may improve the overall performance of the
display.
[0042] FIG. 3 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0043] As shown in FIG. 3, a pixel structure 300 includes a scan
line 310, a data line 320, a semiconductor pattern 330 and a
transparent pixel electrode 340.
[0044] The pixel structure of the exemplary embodiment as shown in
FIG. 3 is substantially the same with the pixel structure as shown
in FIG. 2, except that the semiconductor pattern 330 and the
extending directions of the scan line 310 and the branch structure
311 are different from those shown in FIG. 2. In this regard, the
semiconductor pattern 330 includes: a first channel region 331
which corresponds to the scan line 310 and a second channel region
332 which corresponds to the branch structure 311.
[0045] FIG. 4 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure.
[0046] As shown in FIG. 4, a pixel structure 400 includes a scan
line 410, a data line 420, a semiconductor pattern 430 and a
transparent pixel electrode 440. FIG. 4 differs from FIG. 2 in that
the branch structure 411 is of an "L" shape and the semiconductor
pattern 430 includes a linear portion Q. In FIG. 4, a second part
L2 of the L-shaped branch structure 411 intersects with a first
part L1 of the L-shaped branch structure 411, and the second part
L2 of the L-shaped branch structure 411 perpendicularly intersects
with a linear part Q of the semiconductor pattern 430. However, the
present disclosure is not limited thereto. The semiconductor
pattern 430 intersects with the scan line 410 and the branch
structure 411 respectively. In this regard, the semiconductor
pattern 430 includes: a first channel region 431 which corresponds
to the scan line 410 and a second channel region 432 which
corresponds to the branch structure 411. Description of the parts
in FIG. 4 which are the same as in FIG. 2 will not be repeated.
[0047] FIG. 5 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure. As shown in FIG. 5, a pixel structure 500 includes a
scan line 510, a data line 520, a semiconductor pattern 530 and a
transparent pixel electrode 540. Description of the parts in FIG. 5
which are the same as in FIG. 2 will not be repeated.
[0048] FIG. 5 differs from FIG. 2 in that the semiconductor pattern
530 contains an L-shaped structure. One side of the L-shaped
structure contained in the semiconductor pattern 530 intersects
with the scan line 510, and the other side of the L-shaped
structure contained in the semiconductor pattern 530 intersects
with the branch structure 511. In this regard, the semiconductor
pattern 530 includes: a first channel region 531 which corresponds
to the scan line 510 and a second channel region 532 which
corresponds to the branch structure 511.
[0049] FIG. 6 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure. As shown in FIG. 6, a pixel structure 600 includes a
scan line 610, a data line 620, a semiconductor pattern 630 and a
transparent pixel electrode 640. Description of the parts in FIG. 6
which are the same as in FIG. 2 will not be repeated.
[0050] FIG. 6 differs from FIG. 2 in that a second part L2 of an
L-shaped branch structure 611 intersects with a first part L1 of
the branch structure 611, and the second part L2 of the L-shaped
branch structure 611 intersects with the semiconductor pattern 630.
The semiconductor pattern 630 intersects with the scan line 610 and
the branch structure 611 respectively. In this regard, the
semiconductor pattern 630 includes: a first channel region 631
which corresponds to the scan line 610 and a second channel region
632 which corresponds to the branch structure 611. The first
channel region 631 and the second channel region 632 are all below
the data line 620. However, the present disclosure is not limited
thereto.
[0051] FIG. 7 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure. As shown in FIG. 7, a pixel structure 700 includes a
scan line 710, a data line 720, a semiconductor pattern 730 and a
transparent pixel electrode 740. Description of the parts in FIG. 7
which are the same as in FIG. 2 will not be repeated.
[0052] As shown in FIG. 7, the scan line 710 has branch structures
711 and 712. Each of the branch structure 711 and the branch
structure 712 perpendicularly extends from the scan line 710.
However, the present disclosure is not limited thereto.
[0053] The semiconductor pattern 730 intersects with the scan line
710, the branch structures 711 and 712 respectively. In this
regard, the semiconductor pattern 730 includes: a first channel
region 731 which corresponds to the scan line 710, a second channel
region 732 which corresponds to the branch structure 711, and a
third channel region 733 which corresponds to the branch structure
712. Wherein the width of the scan line 710 is the width L1'' of
the first channel region; the width of the branch structure 711 is
the width L2'' of the second channel region; the width of the
branch structure 712 is the width L3'' of the third channel region.
Doping regions 735A and 735B are respectively disposed at the two
sides of the first channel region 731; doping regions 735B and 735C
are respectively disposed at the two sides of the second channel
region 732; and doping regions 735C and 735D are respectively
disposed at the two sides of the third channel region 733.
[0054] As shown in FIG. 7, the first channel region 731, the second
channel region 732, the third channel region 733 and the doping
regions 735A, 735B, 735C and 735D and the portions of the scan line
710, the branch structure 711 and the branch structure 712 which
respectively correspond to the first channel region 731, the second
channel region 732 and the third channel region 733, may be
configured to form a multi-channel (multi-gate) thin-film
transistor 730.
[0055] According to the exemplary embodiment, an asymmetric
multi-gate structure is provided. For example, as shown in FIG. 7,
at least one of the branch structure 711 and the branch structure
712 which respectively intersect with the semiconductor pattern 730
has a width less than a width L1'' of the scan line 710. That is to
say, at least one of the width L2'' of the second channel region
732 and the width L3'' of the third channel region 733 is less than
the width of the first channel region 731. In this way, the width
of at least one channel region may be reduced without changing the
width of the scan line. By so doing, the stray capacitance may be
reduced and the feed-through voltage may be lowered without
increasing gate delay.
[0056] FIG. 8 is a schematic diagram of a pixel structure according
to another exemplary embodiment in accordance with the present
disclosure. As shown in FIG. 8, a pixel structure 800 includes a
scan line 810, a data line 820, a semiconductor pattern 830 and a
transparent pixel electrode 840. Description of the parts in FIG. 8
which are the same as in FIG. 7 will not be repeated.
[0057] FIG. 8 differs from FIG. 7 in that the scan line 810 has a
branch structure 811 and a branch structure 812. In the embodiment,
the branch structure 812 is an L-shaped branch structure, and each
of the branch structure 811 and the branch structure 812 extends
perpendicularly from the scan line 810. However, the present
disclosure is not limited thereto. A second portion L2 of the
L-shaped branch structure 812 intersects with a first portion L1 of
the branch structure 812. The second portion L2 of the L-shaped
branch structure 812 perpendicularly intersects with a linear
portion of the semiconductor pattern 830. The semiconductor pattern
830 intersects with the scan line 810, the branch structure 811 and
the branch structure 812, respectively. In this regard, the
semiconductor pattern 830 includes: a first channel region 831
which corresponds to the scan line 810, a second channel region 832
which corresponds to the branch structure 811, and a third channel
region 833 which corresponds to the branch structure 812.
[0058] FIG. 9 is a schematic cross sectional view of a pixel
structure according to an exemplary embodiment in accordance with
the present disclosure. As shown in FIG. 9A, in the cross sectional
view of the pixel, the pixel includes a scan-line layer 902, an
insulator layer 904 and an active source layer 906. In an exemplary
embodiment, the scan-line layer may include a scan line 9021 and a
branch structure 9023 of the scan line. As shown in FIG. 9B, in a
cross sectional view of the pixel, the pixel includes a scan-line
layer 902', an insulator layer 904' and an active source layer
906'. In an exemplary embodiment, in the cross sectional view, the
scan-line layer may also include a scan line 9021' and a branch
structure 9023' of the scan line.
[0059] FIG. 10 is a simulation circuit diagram of a pixel structure
according to an exemplary embodiment in accordance with the present
disclosure.
[0060] As shown in a circuit diagram 100 of FIG. 10, Data is a
negative frame voltage, C1 is a pixel storage capacitance, and TFT1
and TFT2 are equivalent circuits formed by the semiconductor
circuit in the pixel structure of the present disclosure.
[0061] With reference to the example shown in FIG. 2, for example,
it may be assumed that a turned-on voltage VGH of the thin film
transistor (TFT) is 10V, a turned-off voltage VGL of the thin film
transistor (TFT) is -7V, a negative frame voltage Data is -5V, and
a pixel storage capacitance is 0.32 fF. The width of the scan line
210, i.e. the width L1 of the first channel region 231 as discussed
above is 2 um. The width of the branch structure 211 of the scan
line, i.e. the width L2 of the second channel region 232 as
discussed above is 3 um, 2 um and 1 um respectively. Results of
positive frame voltage simulation in the embodiment of FIG. 6 are
as shown in the following table, and as shown in FIG. 13:
TABLE-US-00001 Voltage after Width of Second Voltage when fully
Feed-Through Charge Channel charged Voltage Loss Rate 3 um 5.00 V
4.789 V 95.78% 2 um 5.00 V 4.804 V 96.08% 1 um 5.00 V 4.821 V
96.42%
[0062] With reference to the example shown in FIG. 3, for example,
it may be assumed that a turned-on voltage VGH of the thin film
transistor (TFT) is 10V, a turned-off voltage VGL of the thin film
transistor (TFT) is -7V, a negative frame voltage Data is -5V, and
a pixel storage capacitance is 0.32 fF. The width of the scan line
310, i.e. the width L1' of the first channel region 331 as
discussed above is 2 um. The width of the branch structure 311 of
the scan line, i.e. the width L2' of the second channel region 332
as discussed above is 3 um, 2 um and 1 um respectively. Results of
positive frame voltage simulation in the embodiment of FIG. 6 are
as shown in the following table, and as shown in FIG. 12:
TABLE-US-00002 Voltage after Width of Second Voltage when fully
Feed-Through Charge Channel charged Voltage Loss Rate 3 um 5.00 V
4.789 V 95.78% 2 um 5.00 V 4.826 V 96.52% 1 um 5.00 V 4.856 V
97.12%
[0063] In positive frame voltage simulation of the pixel structure,
the design objective is to reduce a feed-through voltage as far as
possible, that is, to make the voltage value after the feed-through
voltage loss close to a standard voltage value 5V.
[0064] It can be seen from the results, when in the pixel
structure, the branch structure of the scan line has a different
width of the scan line, it may influence the positive frame charge
capacity of the entire pixel. The wider of the branch structure of
the scan line, the weaker the charge capability of the entire pixel
structure will be, and it means that the resulted voltage after the
pixel structure is charged is more deviated from 5V. In the present
embodiment, the result of positive frame voltage simulation of such
pixel structure, according to the embodiment in which the width of
the scan line is larger than the width of branch structure of the
scan line (that is, the embodiment in which the width of the first
channel region is larger than the width of the second channel
region), it can effectively lower the feed-through voltage and it
can enhance the charge capability of the device.
[0065] FIG. 11 is a simulation circuit diagram of another pixel
structure according to an exemplary embodiment in accordance with
the present disclosure.
[0066] In the circuit diagram 120 as shown in FIG. 11, Data is a
negative frame voltage, C2 is a pixel storage capacitance, TFT1 and
TFT2 are equivalent circuits constituted by the semiconductor
circuit in the pixel structure disclosed by the present
disclosure.
[0067] With reference to the example as shown in FIG. 2, for
example, it may be assumed that a turned-on voltage VGH of the thin
film transistor (TFT) is 10V, a turned-off voltage VGL of the thin
film transistor (TFT) is -7V, a negative frame voltage Data is -5V,
and a pixel storage capacitance is 0.32 fF. The width of the scan
line 210, i.e. the width L1 of the first channel region 231 as
discussed above is 2 um. The width of the branch structure 211 of
the scan line, i.e. the width L2 of the second channel region 232
as discussed above is 3 um, 2 um and 1 um respectively. Results of
negative frame voltage simulation in the embodiment of FIG. 7 are
as shown in the following table, and as shown in FIG. 13:
TABLE-US-00003 Voltage after Width of Second Voltage when fully
Feed-Through Charge Channel charged Voltage Loss Rate 3 um -5.00
-5.228 104.56% 2 um -5.00 -5.169 103.38% 1 um -5.00 -5.110
102.20%
[0068] With reference to the example as shown in FIG. 3, for
example, it may be assumed that a turned-on voltage VGH of the thin
film transistor (TFT) is 10V, a turned-off voltage VGL of the thin
film transistor (TFT) is -7V, a negative frame voltage Data is -5V,
and a pixel storage capacitance is 32 fF. The width of the scan
line 310, i.e. the width L1' of the first channel region 331 as
discussed above is 2 um. The width of the branch structure 311 of
the scan line, i.e. the width L2' of the second channel region 332
as discussed above is 3 um, 2 um and 1 um respectively. Results of
negative frame voltage simulation in the embodiment of FIG. 7 are
as shown in the following table, and as shown in FIG. 13:
TABLE-US-00004 Voltage after Width of Second Voltage when fully
Feed-Through Charge Channel charged Voltage Loss Rate 3 um -5.00
-5.228 104.56% 2 um -5.00 -5.142 102.84% 1 um -5.00 -5.084
101.68%
[0069] In negative frame voltage simulation of the pixel structure,
the design objective is to reduce a feed-through voltage, that is,
to make the voltage value after the feed-through voltage loss close
to a standard voltage value -5V.
[0070] It can be seen from the results, when in the pixel
structure, the branch structure of the scan line has a different
width of the scan line. It may influence the negative frame charge
capacity of the entire pixel. The wider of the branch structure of
the scan line, the weaker the charge capability of the entire pixel
structure will be, and it means that the resulted voltage after the
pixel structure is charged is more deviated from -5V. In the
present embodiment, the result of negative frame voltage simulation
of such pixel structure, according to the embodiment in which the
width of the scan line is larger than the width of branch structure
of the scan line (that is, the embodiment in which the width of the
first channel region is larger than the width of the second channel
region), it can effectively lower the feed-through voltage and it
can enhance the charge capability of the device.
[0071] From the above detailed description, it should be understood
by those skilled in the art that, the pixel structure according to
the embodiments of the present disclosure may have one or more of
the following advantages.
[0072] According to various embodiments in accordance with the
present disclosure, the feed-through voltage may be lowered without
increasing gate delay. Moreover, the charge capacity of the device
may be enhanced, and it may improve the display performance of the
display screen.
[0073] The exemplary embodiments described in the present
disclosure have been illustrated and described in detail as above.
It should be understood that, the present disclosure is not limited
to the detailed structure, the configuration and implementation
described herein. Instead, the present disclosure intends to cover
various modifications and equivalents falling within the spirit and
scope of the appended claims.
* * * * *