U.S. patent application number 15/448280 was filed with the patent office on 2017-06-22 for compressing detected current and preceding instructions with the same operation code and operand patterns.
The applicant listed for this patent is FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITED. Invention is credited to Makiko Ito, Mitsuru Tomono, Hiroya Uehara.
Application Number | 20170177370 15/448280 |
Document ID | / |
Family ID | 47262615 |
Filed Date | 2017-06-22 |
United States Patent
Application |
20170177370 |
Kind Code |
A1 |
Tomono; Mitsuru ; et
al. |
June 22, 2017 |
COMPRESSING DETECTED CURRENT AND PRECEDING INSTRUCTIONS WITH THE
SAME OPERATION CODE AND OPERAND PATTERNS
Abstract
A processor accesses memory storing a compressed instruction
sequence that includes compression information indicating that an
instruction that with respect to the preceding instruction, has
identical operation code and operand continuity is compressed. The
processor includes a fetcher that fetches a bit string from the
memory and determines whether the bit string is a non-compressed
instruction, where if so, transfers the given bit string and if
not, transfers the compression information; and a decoder that upon
receiving the non-compressed instruction, holds in a buffer,
instruction code and an operand pattern of the non-compressed
instruction and executes processing to set to an initial value, the
value of an instruction counter that indicates a count of
consecutive instructions having identical operation code and
operand continuity, and upon receiving the compression information,
restores the instruction code based on the instruction code held in
the buffer, the instruction counter value, and the operand
pattern.
Inventors: |
Tomono; Mitsuru; (Kawasaki,
JP) ; Uehara; Hiroya; (Yokohama, JP) ; Ito;
Makiko; (Kawasaki, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
FUJITSU LIMITED
FUJITSU SEMICONDUCTOR LIMITED |
Kawasaki-shi
Yokohama-shi |
|
JP
JP |
|
|
Family ID: |
47262615 |
Appl. No.: |
15/448280 |
Filed: |
March 2, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13481221 |
May 25, 2012 |
9619235 |
|
|
15448280 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 9/30185 20130101;
G06F 9/30178 20130101; G06F 9/3016 20130101; G06F 9/30072 20130101;
G06F 9/30032 20130101; G06F 9/3802 20130101; G06F 9/30145 20130101;
G06F 9/3816 20130101 |
International
Class: |
G06F 9/30 20060101
G06F009/30; G06F 9/38 20060101 G06F009/38 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 1, 2011 |
JP |
2011-123851 |
Claims
1. A processor having access to a memory storing therein a sequence
of compressed instruction groups including compression information
indicating that an instruction having operation code identical to
that of the preceding instruction and having operand continuity
with the preceding instruction has been compressed, the processor
comprising: a fetcher that fetches a given bit string from the
memory and judges a combination pattern of the compression
information in the given bit string and a non-compressed
instruction, where concerning a non-compressed instruction, further
identifies the non-compressed instruction in the given bit string
and transfers the non-compressed instruction, and concerning the
compression information, further transfers the compression
information, and a decoder that upon receiving the non-compressed
instruction transferred thereto from the fetcher, holds in a
buffer, instruction code and an operand pattern of the
non-compressed instruction and executes setting processing of
setting to an initial value, the value of an instruction counter
that indicates a consecutive count of consecutive instructions
having identical operation code and operands with regularity, and
upon receiving the compression information transferred thereto from
the fetcher, restores the instruction code based on the instruction
code held in the buffer, the value of the instruction counter, and
the operand pattern.
2. A computer-readable medium storing therein a compression program
that causes a computer to execute a process, the process
comprising: acquiring a test subject from an instruction group
under test that is among a sequence of instruction groups;
determining whether operation code of the acquired test subject and
operation code of a preceding instruction are identical, and
whether operands of the test subject and operands of the preceding
instruction have continuity, the preceding instruction being an
instruction at a position that corresponds to that of the test
subject, in the instruction group that precedes the instruction
group under test; and compressing the test subject when at the
determining identicalness and continuity are determined.
3. The computer-readable medium according to claim 2, wherein the
compressing, when identicalness and continuity are determined,
includes appending to the test subject, compression information
indicating that the test subject is compressed, and deleting the
operation code and the operands of the test subject.
4. The computer-readable medium according to claim 2, the process
further comprising setting for the test subject, compression
information indicating that the test subject is not compressed and
storage information indicating that the test subject is an
instruction that is to be stored, the setting being performed when
identicalness and continuity are not determined at the
determining.
5. The computer-readable medium according to claim 4, wherein the
determining, when identicalness and continuity are not determined,
includes determining whether the test subject is to be stored,
based on the operation code type of the test subject, and the
setting, when storage is determined, includes setting for the test
subject, the compression information indicating that the test
subject is not compressed and the storage information indicating
that the test subject is an instruction that is to be stored, and
when storage is not determined, includes setting for the test
subject, compression information indicating that the test subject
is not compressed and the storage information indicating that the
test subject is not an instruction that is to be stored.
6. The computer-readable medium according to claim 2, the process
further comprising storing a compression information group obtained
from test subjects of the instruction group under test, and
subsequent to the compression information group, storing a
non-compressed test subject that is in the instruction group under
test, is not compressed, and for which the storage information has
been set.
7. The computer-readable medium according to claim 6, wherein the
storing includes shortening by concatenating storage results
obtained for each instruction group under test.
8. A compression apparatus comprising: an acquirer that acquires a
test subject from an instruction group under test that is among a
sequence of instruction groups; a determiner that determines
whether operation code of the acquired test subject and operation
code of a preceding instruction are identical, and whether operands
of the test subject and operands of the preceding instruction have
continuity, the preceding instruction being an instruction at a
position that corresponds to the that of the test subject, in the
instruction group that precedes the instruction group under test;
and a compressor that compresses the test subject when
identicalness and continuity are determined by the determiner.
9. A compression method executed by a computer, the compression
method comprising: acquiring a test subject from an instruction
group under test that is among a sequence of instruction groups;
determining whether operation code of the acquired test subject and
operation code of a preceding instruction are identical, and
whether operands of the test subject and operands of the preceding
instruction have continuity, the preceding instruction being an
instruction at a position that corresponds to that of the test
subject, in the instruction group that precedes the instruction
group under test; and compressing the test subject when at the
determining identicalness and continuity are determined.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Divisional of U.S. patent application
Ser. No. 13/481,221, filed May 25, 2012, which is based upon and
claims the benefit of priority of the prior Japanese Patent
Application No. 2011-123851, filed on Jun. 1, 2011, the entire
contents of which are incorporated herein by reference.
FIELD
[0002] The embodiments discussed herein are related to a processor
that executes an instruction, a processor that compresses an
instruction, a computer product, a compression apparatus, and a
compression method.
BACKGROUND
[0003] Conventionally, technologies have been disclosed that upon a
compression determination instruction, issue an exclusive
instruction to transition to a compression mode, and perform
transition to a compression mode and a non-compression mode (see,
for example, Japanese Laid-Open Patent Publication Nos. 2001-142696
and 2003-050696). During the compression mode, these technologies
use a memory address that is different from that of the instruction
memory (called a dictionary address, which is stored in compressed
instruction code), refer to the dictionary memory, and restore an
instruction.
[0004] Further, technology has been disclosed that stores a portion
of the previous operation code and a portion of the operand, and by
compensating deficient portions of compressed code by the stored
code, restore the compressed code (see, for example, Japanese
Laid-Open Patent Publication No. 2004-355477). This technology, for
example, when the size of the instruction code is 32 bits,
compresses the code to 16 bits.
[0005] Technology that compresses and curtails frequent no
operation instructions in Very Long Instruction Words (VLIWs) and
thereby reduces the instruction code size has been disclosed (for
example, Japanese Laid-Open Patent Publication No. H7-182169).
[0006] Nonetheless, with the technologies according to Japanese
Laid-Open Patent Publication Nos. 2001-142696 and 2003-050696,
since the memory that is called dictionary memory, which is also
different from the instruction memory, is used, a problem arises in
that the number of memory accesses increases by the number of
accesses to the dictionary memory and power consumption
increases.
[0007] With the technology according to Japanese Laid-Open Patent
Publication No. 2004-355477, since a portion of the preceding
instruction code has to be stored for each instruction code, a
problem arises in that compression efficiency is low. Further, with
the technology according to Japanese Laid-Open Patent Publication
No. H7-182169, only no operation instructions can be compressed.
Thus, the instruction code compression efficiency is low and a
problem arises in that curtailing of the memory access frequency is
not sufficient as compared to before compression.
SUMMARY
[0008] According to an aspect of an embodiment, a processor has
access to a memory storing therein a compressed instruction
sequence that includes compression information indicating that an
instruction having operation code identical to that of the
preceding instruction and having operand continuity with the
preceding instruction has been compressed. The processor includes a
fetcher that fetches a given bit string from the memory and
determines whether the given bit string is a non-compressed
instruction, where upon determining the given bit string to be a
non-compressed instruction, further transfers the given bit string
and upon determining the given bit string to not be a
non-compressed instruction, further transfers the compression
information located at the head of the given bit string; and a
decoder that upon receiving the non-compressed instruction
transferred thereto from the fetcher, holds in a buffer,
instruction code and an operand pattern of the non-compressed
instruction and executes setting processing of setting to an
initial value, the value of an instruction counter that indicates a
consecutive count of consecutive instructions having identical
operation code and operands with regularity, and upon receiving the
compression information transferred thereto from the fetcher,
restores the instruction code based on the instruction code held in
the buffer, the value of the instruction counter, and the operand
pattern.
[0009] The object and advantages of the invention will be realized
and attained by means of the elements and combinations particularly
pointed out in the claims.
[0010] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are not restrictive of the invention, as
claimed.
BRIEF DESCRIPTION OF DRAWINGS
[0011] FIG. 1 is a diagram depicting the flow of instruction
compression and instruction execution.
[0012] FIG. 2 is a diagram of the structure of an instruction
IS.
[0013] FIG. 3 is a block diagram of a hardware configuration of a
compression apparatus according to a first embodiment.
[0014] FIG. 4 is a block diagram depicting an example of a
functional configuration of the compression apparatus according to
a first example.
[0015] FIG. 5 is a diagram of an example of a storage determining
table T.
[0016] FIG. 6 is a diagram depicting an example of compression
processing according to the first example.
[0017] FIG. 7 is a first part of a flowchart depicting a procedure
of compression processing by the compression apparatus according to
the first example.
[0018] FIG. 8 is a second part of a flowchart depicting the
compression procedure by the compression apparatus.
[0019] FIG. 9 is a diagram of one example of a sequence of
instruction groups according to a second example.
[0020] FIG. 10 is a block diagram depicting an example of a
functional configuration of the compression apparatus according to
the second example.
[0021] FIGS. 11A, 11B, and 11C depict an example of compression
processing according to the second example.
[0022] FIG. 12 is a flowchart depicting an example of a procedure
of compression processing by the compression apparatus according to
the second example.
[0023] FIG. 13 is a first part of a flowchart depicting an example
of a procedure of test-subject compression processing (step S1205)
depicted in FIG. 12.
[0024] FIG. 14 is a second part of a flowchart of the example of
the procedure of the test-subject compression processing (step
S1205) depicted in FIG. 12.
[0025] FIG. 15 is a block diagram depicting an example of a
hardware configuration of a processor depicted in FIG. 1.
[0026] FIG. 16 is a diagram of a first configuration example of an
operand updater.
[0027] FIG. 17 is a diagram of a second configuration example of
the operand updater.
[0028] FIG. 18 is a diagram of a third configuration example of the
operand updater.
[0029] FIG. 19 is a flowchart of processing by the processor.
[0030] FIGS. 20 to 36 are diagrams of an example of pipeline
processing according to a third embodiment.
[0031] FIGS. 37 to 42 are diagrams of an example of recovery
processing for recovery from an interrupt.
[0032] FIGS. 43 to 55 are diagrams of an example of pipeline
processing according to a fourth embodiment.
[0033] FIGS. 56 to 64 are diagrams of an example of recovery
processing for recovery from an interrupt.
DESCRIPTION OF EMBODIMENTS
[0034] Preferred embodiments of the present invention will be
explained with reference to the accompanying drawings.
[0035] FIG. 1 is a diagram depicting the flow of instruction
compression and instruction execution. In the present embodiment,
instruction sequences are compressed by a compression program
installed on a computer. An instruction sequence is a set of
consecutive instructions, for example, stored in order of address
in a storage device. In FIG. 1, as an example, instructions IS1 to
IS6 are regarded as an instruction sequence. For the sake of
convenience, herein an instruction in an instruction sequence is
indicated as an "instruction IS".
[0036] FIG. 2 is a diagram of the structure of an instruction IS.
In FIG. 2, instruction IS1 is taken as an example. An instruction
IS is information where a compression bit and a storage bit are
appended to operation code and operands. As an example, the
instruction width is assumed to be 32 bits.
[0037] The compression bit is compression information that
indicates whether the instruction IS is to be compressed. For
example, when the compression bit is "1", compression is indicated
and when the compression bit is "0", no-compression is indicated.
Before compression, the compression bit is assumed to indicate
no-compression ("0"). The storage bit is storage information that
indicates whether the instruction IS to be stored as a restoration
source instruction. For example, when the storage bit is "1",
storage is indicated and when the storage bit is "0", no-storage is
indicated. Before compression, the storage bit is assumed to
indicate no-storage ("0").
[0038] In FIG. 1, a compression apparatus 101 is a computer on
which a compression program is installed. The compression apparatus
101 compresses instruction sequences ISs. The compression apparatus
101 performs compression, when 2 instructions having consecutive
addresses further have the same operation code and operands that
have continuity. For example, both operation codes among the
consecutive instructions IS1, IS2 are ADD and the operands increase
by 1. Consequently, instruction IS2 is compressed.
[0039] Similarly, the instruction IS3 is also compressed.
Compression between the instructions IS3 and IS4; the instructions
IS4 and IS5; and the instructions IS5 and IS6 is not performed.
Further, with regard to the instruction IS6, instruction IS5 is
disregarded and consequent to the relation with the instruction
IS4, compression is performed. Details of the compression are
described hereinafter.
[0040] Furthermore, an instruction group that has been compressed
by the compression apparatus 101 is referred to as a compressed
instruction group iss. A compressed instruction group iss includes
both (non-compressed) instructions that are restoration sources and
compressed instructions that can be restored by referring to a
restoration source instruction. A processor 102, by fetching a
compressed instruction group iss, restores the compressed
instructions and executes the instructions. Details of the
execution will be described hereinafter. The processor 102 may be a
central processing unit (CPU) in the compression apparatus 101 or
may be a CPU of a computer different from the compression apparatus
101. The processor 102 may further be a digital signal processor
(DSP).
[0041] A first embodiment will be described. In the first
embodiment, the instruction compression depicted in FIG. 1 will be
described.
[0042] FIG. 3 is a block diagram of a hardware configuration of the
compression apparatus 101 according to the first embodiment. As
depicted in FIG. 3, the compression apparatus 101 includes a CPU
301, a read-only memory (ROM) 302, a random access memory (RAM)
303, a magnetic disk drive 304, a magnetic disk 305, an optical
disk drive 306, an optical disk 307, a display 308, an interface
(I/F) 309, a keyboard 310, a mouse 311, a scanner 312, and a
printer 313, respectively connected by a bus 300.
[0043] The CPU 301 governs overall control of the compression
apparatus 101. The ROM 302 stores therein programs such as a boot
program. The RAM 303 is used as a work area of the CPU 301. The
magnetic disk drive 304, under the control of the CPU 301, controls
the reading and writing of data with respect to the magnetic disk
305. The magnetic disk 305 stores therein data written under
control of the magnetic disk drive 304.
[0044] The optical disk drive 306, under the control of the CPU
301, controls the reading and writing of data with respect to the
optical disk 307. The optical disk 307 stores therein data written
under control of the optical disk drive 306, the data being read by
a computer.
[0045] The display 308 displays, for example, data such as text,
images, functional information, etc., in addition to a cursor,
icons, and/or tool boxes. A cathode ray tube (CRT), a
thin-film-transistor (TFT) liquid crystal display, a plasma
display, etc., may be employed as the display 308.
[0046] The I/F 309 is connected to a network 314 such as a local
area network (LAN), a wide area network (WAN), and the Internet
through a communication line and is connected to other apparatuses
through the network 314. The I/F 309 administers an internal
interface with the network 314 and controls the input/output of
data from/to external apparatuses. For example, a modem or a LAN
adaptor may be employed as the I/F 309.
[0047] The keyboard 310 includes, for example, keys for inputting
letters, numerals, and various instructions and performs the input
of data. Alternatively, a touch-panel-type input pad or numeric
keypad, etc. may be adopted. The mouse 311 is used to move the
cursor, select a region, or move and change the size of windows. A
track ball or a joy stick may be adopted provided each respectively
has a function similar to a pointing device.
[0048] The scanner 312 optically reads an image and takes in the
image data into the compression apparatus 101. The scanner 312 may
have an optical character reader (OCR) function as well. The
printer 313 prints image data and text data. The printer 313 may
be, for example, a laser printer or an ink jet printer.
[0049] Instructions include regular instructions and instruction
groups that include multiple instructions such as a VLIW. In a
first example, a case will be described where an instruction
sequence that is subsequent to a regular instruction is compressed.
In a second example, a case will be described where a sequence of
instruction groups subsequent to an instruction group that includes
multiple instructions, is compressed.
[0050] FIG. 4 is a block diagram depicting an example of a
functional configuration of the compression apparatus 101 according
to the first example. The compression apparatus 101 includes an
acquirer 401, a determiner 402, a compressor 403, and a setter 404.
These functions (the acquirer 401 to the setter 404) forming a
controller, for example, are realized by executing on the CPU 301,
a program stored in a storage device such as the ROM 302, the RAM
303, the magnetic disk 305, and the optical disk 307 depicted in
FIG. 3, or by the I/F 309.
[0051] The acquirer 401 acquires a given instruction as a test
subject from among an instruction sequence. For example, the
acquirer 401 reads in an instruction sequence such as that in FIG.
1, sequentially according to address, one instruction at a time.
For example, beginning with the instruction IS1 at the head address
0xF000, the acquirer 401 acquires the instructions in the sequence
of IS1, IS2, IS3, IS4, IS5, IS6.
[0052] The determiner 402 determines whether the operation code of
the test subject acquired by the acquirer 401 and the operation
code of the instruction preceding the test subject are identical;
and determines whether operands of the test subject and operands of
the preceding instruction have continuity. The test subject is the
instruction IS read in at the current reading. The preceding
instruction is the instruction IS that was read in at the reading
immediately preceding the current reading. For example, if the test
subject is the instruction IS2, the preceding instruction is the
instruction IS1. When the test subject is the instruction IS1,
there is no preceding instruction. Continuity among operands is a
state in which like operands vary in a regular manner.
[0053] An operand pattern is embedded in the operation code. The
operand pattern indicates the operand structure and includes the
operand type, the operand count, and the starting position of the
head operand. For example, in the case of the instruction IS1, the
operand type is register and the operand count is 3. Further,
assuming that operation code is 12 bits, the starting position of
the head operand is the 15th bit from the head of the instruction
IS1. This operand pattern, for example, is assumed to be embedded
in the upper bit string of the operation code.
[0054] At the determiner 402, when the operand patterns of the test
subject and of the preceding instruction are identical and the
operand values are consecutive, continuity is determined. When the
operand patterns of the test subject and of the preceding
instruction are not identical, non-continuity is determined without
checking the operand values.
[0055] For example, in the case of the instructions IS1, IS2, the
operands of the instruction IS1 are r0, r16 and r32; and the
operands of the instruction IS2 are r1, r17 and r33. Thus, since
the register addresses increase by 1 between the instructions IS1
and IS2, the operands have continuity. "+1" indicating the increase
by 1 is stored in a continuity buffer. Similarly, between the
instructions IS2 and IS3, and the instructions IS1 and IS2, the
register addresses increase by 1 and the continuity buffer values
match. Therefore, the successive operands have continuity. When
there is no continuity, the continuity buffer is initialized.
[0056] In this manner, when the register numbers and memory
addresses vary with continuity, there is continuity among operands.
In the example depicted in FIG. 1, for the instructions IS1 to IS3,
the operation codes are determined to be identical and continuity
among the operands is determined.
[0057] When the storage bit of the test subject instruction IS is
"0" (no-storage), the continuity buffer is maintained as is. For
example, the instruction IS5 subsequent to the instruction IS4 is
no operation instruction (NOP) and as described hereinafter, the
storage bit of the instruction IS5 is set as "0". In this case,
when the instruction IS6 is restored by the processor 102, since
the storage bit of the instruction IS5 is "0" and is not restored,
by further tracing back to the instruction IS4, it is determined
whether the operation codes of the instructions IS4 and IS6 are
identical and whether the operands have continuity.
[0058] Operand continuity is not limited to regular increases of
the register numbers and addresses, etc., and may be increments by
a variable as well as decrements. If the magnitude of
increase/decrease is the same for each instruction, the magnitude
of increase/decrease need not be 1. Further, if the register
numbers are the same, continuity is determined because, for
example, in the case of values set to specify an instruction
operation, the same register (register number) may be specified. In
this case, the magnitude of increase/decrease is 0. In the case of
immediate value as well, if the magnitude of increase/decrease is
the same, continuity is determined. Further, when changes are by a
constant rule (for example, corresponds to expressions depicted in
FIG. 16), continuity is determined. Additionally, when immediate
values are the same value, continuity is determined.
[0059] When identicalness and continuity are not determined, the
determiner 402, based on the operation code type of the test
subject, may determine whether the test subject is an instruction
that is to be stored as a restoration source instruction. Among the
instructions are system instructions without operands like HALT,
RET, RFE, EXTW, and NOP. Such system instructions are not used as
restoration sources for compressed instructions.
[0060] FIG. 5 is a diagram of an example of a storage determining
table T. As depicted in FIG. 5, the storage determining table T
includes a storage flag for each operation code. Thus, according to
the operation code of the test subject, whether the test subject is
to be stored as a restoration source instruction can be determined.
For example, when the operation code of the instruction IS1 is ADD,
the storage flag is "1" (storage) and consequently, it is
determined that the test subject is to be stored as a restoration
source instruction.
[0061] When the operation code of the test subject is HALT, the
storage flag is "0" (no-storage) and consequently, it is determined
that the test subject is not to be stored as a restoration source
instruction. The storage determining table T is stored in a storage
device such as the ROM 302, the RAM 303, the magnetic disk 305, and
the optical disk 307 depicted in FIG. 3.
[0062] The compressor 403, when identicalness and continuity have
been determined by the determiner 402, compresses the test subject.
For example, the compressor 403, when identicalness and continuity
have been determined by the determiner, appends to the test
subject, compression information indicating that the test subject
is to be compressed, and deletes the instruction code in the test
subject. For example, in the case of compression, the compressor
403 sets the compression bit of the test subject to "1"
(compression), making the test subject a compressed instruction. In
other words, in the case of compression, the storage bit and the
instruction code are completely deleted, leaving only the
compression bit. As a result, for example, an instruction of a
given bit width (e.g., 32 bits, 64 bits, 128 bits, etc.) can be
compressed to 1 bit.
[0063] The setter 404, when non-identicalness and non-continuity
have been determined by the determiner 402, sets for the test
subject, compression information indicating that the test subject
is not to be compressed and storage information indicating that the
test subject is to be stored as an instruction not subject to
compression. For example, when non-identicalness and non-continuity
have been determined by the determiner 402, the setter 404 sets the
test subject to not be subject to compression. Therefore, the
setter 404 sets the compression bit of the test subject to "0"
(no-compression). Further, since the test subject is not to be
compressed, the setter 404 sets the storage bit of the test subject
to "1" (storage). As a result, when the subsequent instruction is
compressed, the non-compressed test subject becomes the restoration
source of the subsequent instruction.
[0064] Further, when non-identicalness and non-continuity have been
determined by the determiner 402 and storage has been determined by
the determiner 402, the setter 404 sets, for test subject,
compression information indicating that the test subject is not to
be compressed and further sets storage information indicating that
the test subject is to be stored as a restoration source
instruction. For example, the setter 404 sets the compression bit
of the test subject to "0" (no-compression) and further sets the
storage bit of the test subject to "1" (storage). Consequently,
when the subsequent instruction is compressed, the non-compressed
test subject becomes the restoration source of the subsequent
instruction.
[0065] On the other hand, when non-identicalness, non-continuity,
and no-storage are determined by the determiner 402, the setter 404
sets for the test subject, information indicating that the test
subject is not to be compressed and further sets information
indicating that the test subject is not to be stored as a
restoration source instruction. For example, the setter 404 sets
the compression bit of the test subject to "0" (no-compression) and
sets the storage bit of the test subject to "0" (no-storage),
whereby the non-compressed test subject does not become a
restoration source of the subsequent instruction.
[0066] FIG. 6 is a diagram depicting an example of compression
processing according to the first example. FIG. 5 depicts an
example of compression of the instruction group depicted in FIG. 1.
The compression apparatus 101 reads in the instruction IS1 of
address 0xF000. Since there is no instruction preceding the
instruction IS1, the compression bit of the instruction IS1 is "0"
(no-compression). Further, since the operation code of the
instruction IS1 is ADD, the storage bit of the instruction IS1 is
"1" (storage). Thus, for the instruction IS1, after compression,
the storage bit changes from "0" to "1".
[0067] The instruction IS2 has the same operation code as the
preceding instruction IS1 and operand continuity. Consequently, the
compression bit becomes "1" and all else is deleted. The
instruction IS3 has the same operation code as the preceding
instruction IS2 and operand continuity. Consequently, the
compression bit becomes "1" and all else is deleted.
[0068] The instruction IS4 does not have the same operation code as
the preceding instruction IS3. Consequently, the compression bit is
set to "0". Further, the operation code of the instruction IS4 is
STORE and thus, the instruction IS4 is to be stored as a
restoration source instruction. Therefore, the storage bit is set
to "1". Hence, for the instruction IS4, after compression, the
storage bit changes from "0" to "1".
[0069] The instruction IS5 does not have the same operation code as
the preceding instruction IS4. Consequently, the compression bit is
set to "0". Further, the instruction IS5 is a NOP instruction and
thus, is not to be stored as a restoration source instruction.
Therefore, the storage bit is set to "0". Thus, for the instruction
IS5, after compression, the same command as before compression is
stored.
[0070] The instruction IS6 does not have the same operation code as
the preceding instruction IS5, but the storage bit of the preceding
instruction IS5 is set to "0" and consequently, the instruction IS4
is regarded as the preceding instruction. In this case, the
instruction IS6 has the same operation code as the preceding
instruction IS4 and operand continuity. Consequently, the
compression bit of the instruction IS6 becomes "1" and all else is
deleted. In this manner, in the present embodiment, the more
consecutive test subjects having the same operation code as the
preceding instruction and operand continuity there are, the higher
the compression efficiency is. In this case, the updated operand
becomes 0x0001. However, depending on the data size and/or memory
size handled by the instruction, the value of the instruction
counter 14 may be multiplied by a coefficient by a decoder block
(156).
[0071] FIG. 7 is a first part of a flowchart depicting a procedure
of compression processing by the compression apparatus 101
according to the first example. The compression apparatus 101
determines whether an instruction is present in an instruction
group (step S701). If no instruction is present (step S701: NO),
the compression processing ends. On the other hand, if an
instruction is present (step S701: YES), the compression apparatus
101, via the acquirer 401, acquires a test subject (step S702) and
via the determiner 402, determines whether the test subject has the
same operation code as the preceding instruction (step S703). A
case where the operation codes are identical (step S703: YES) is
described with in FIG. 8.
[0072] If the operation codes are not identical (step S703: NO),
the compression apparatus 101, via the determiner 402, refers to
the storage bit of the preceding instruction and determines whether
the preceding instruction is an instruction that is not to be
stored as a restoration source instruction (step S704). If the
preceding instruction is an instruction that is not to be stored as
a restoration source instruction (step S704: YES), the preceding
instruction is a system instruction without an operand.
Accordingly, the operation codes of the test subject and of the
instruction immediately before the preceding instruction (the
preceding instruction when the preceding instruction of the current
test subject was the test subject) may be identical and there may
be operand continuity. Therefore, the compression apparatus 101,
via the setter 404, changes the preceding instruction to the
instruction immediately before the preceding instruction (step
S705), and returns to step S703.
[0073] At step S705, for example, if the test subject is the
instruction IS6 depicted in FIG. 6, the preceding instruction is
the NOP instruction IS5. Since an NOP is not to be stored as a
restoration source instruction, the instruction IS4, which was 1
instruction before the preceding instruction IS5 (NOP), is regarded
as the preceding instruction.
[0074] If the preceding instruction is not an instruction that is
not to be stored as a restoration source instruction (step S704:
NO), i.e., is an instruction to be stored as a restoration source
instruction, the compression apparatus 101, via the setter 404,
initializes the continuity buffer (step S706), and sets the
compression bit of the test subject to "0" (step S707).
[0075] The compression apparatus 101, via the determiner 402,
determines whether the test subject is to be stored as a
restoration source instruction (step S708). For example, in the
storage determining table T, if the storage flag corresponding to
the operation code of the test subject is "1", storage as a
restoration source instruction is indicated; and if "0", such
storage is not indicated.
[0076] If the test subject is to be stored as a restoration source
instruction (step S708: YES), the compression apparatus 101, via
the setter 404, sets the storage bit of the test subject to "1"
(step S709). The compression apparatus 101 stores to a compression
buffer, a non-compressed instruction having a compression bit of
"0", a storage bit of "1", an operation code identical to that of
the test subject and operands (step S710); and then, returns to
step S701.
[0077] At step S708, if the test subject is not to be stored as a
restoration source instruction (step S708: NO), the compression
apparatus 101, via the setter 404, sets the storage bit of the test
subject to "0" (step S711). The compression apparatus 101 stores to
the compression buffer, a non-compressed instruction having a
compression bit of "0", a storage bit of "0", an operation code
that is identical to that of the test subject and operands (step
S712). In other words, the compression apparatus 101 stores the
test subject as is and returns to step S701.
[0078] FIG. 8 is a second part of a flowchart depicting the
compression procedure by the compression apparatus 101. At step
S703 depicted in FIG. 7, if the operation codes are identical (step
S703: YES), the compression apparatus 101, via the determiner 402,
determines whether the operand patterns of the preceding
instruction of and of the test subject are identical (step S801).
If the operand patterns are not identical (step S801: NO), the
operands are not consecutive and the test subject is excluded as a
compression subject. Consequently, the compression apparatus 101
transitions to step S706 depicted in FIG. 7, and via the setter
404, initializes the continuity buffer.
[0079] If the operand patterns are identical (step S801: YES), the
compression apparatus 101 detects differences between the operands
of the preceding instruction and the operands of the test subject
(step S802). For example, when the preceding instruction is the
instruction IS1 and the test subject is the instruction IS2, the
difference is "+1". Similarly, when the preceding instruction is
the instruction IS2 and the test subject is the instruction IS3,
the difference is "+1".
[0080] The compression apparatus 101, via the determiner 402,
determines whether the detected difference and the value of the
continuity buffer are identical (step S804). When the detected
difference and the continuity buffer value are not identical (step
S804: NO), the continuity buffer is initialized and the compression
apparatus 101, via the setter 404, updates the continuity buffer to
the detected difference (step S803), and transitions to step
S707.
[0081] When the detected difference and the continuity buffer value
are identical (step S804: YES), such as when the preceding
instruction is the instruction IS2 and the test subject is the
instruction IS3, the compression apparatus 101, via the compressor
403, sets the compression bit of the test subject to "1" (step
S805). Thereafter, the compression apparatus 101, via the
compressor 403, deletes the bit string (storage bit, instruction
code) subsequent to the compression bit of the test subject (step
S806). Thus, the compression apparatus 101 stores to the
compression buffer, a compressed instruction that includes only the
compression bit (=1) (step S807), and transitions to step S701.
[0082] Thus, the compression apparatus 101 enables high compression
of an instruction group by compressing instructions (test subjects)
that with respect to the preceding instruction, have the same
operation code and operand continuity. For example, when there are
M successive m-bit instructions meeting the compression conditions,
in an uncompressed state, there are (mxM) bits. Whereas, after
compression by the compression apparatus 101, only the head
instruction is not compressed and the subsequent instructions are
compressed to 1 bit (i.e., the compression bit).
[0083] Therefore, the compressed size becomes (m+M-1) bits. Thus,
when the size is reduced by compression, since the maximum amount
of compressed instructions equivalent to the bus width can be
fetched collectively, the number of accesses to the memory can be
reduced and power consumption can be reduced. Further, system
instructions such as NOPs have no operands and consequently, such
instructions are not subject to storage as a restoration source
instruction, enabling the instructions to be excluded from
restoration sources and thereby, enabling improvement of the
restoration processing efficiency.
[0084] The second example will be described. In the second example,
compression of an instruction sequence group of consecutive
instruction groups executed in parallel such as a VLIW will be
described.
[0085] FIG. 9 is a diagram of one example of a sequence of
instruction groups according to the second example. Here, a VLIW
will be described as an example. In a sequence of instruction
groups Vs, multiple VLIW instructions having multiple instructions
(4 in FIG. 9) such as those depicted in FIG. 1 are present.
Further, in the sequence of instruction groups Vs, an instruction
at the same position in each of the instruction sequences is framed
by a bold line. For example, in the instruction sequence V1 to V4
of the sequence of instruction groups Vs, the head instruction A1
at address 0x0000, the head instruction A2 at address 0x0010, the
head instruction A3 at address 0x0020, and the head instruction A4
at address 0x0030 are instructions at the same position. Further,
in the sequence of instruction groups Vs depicted in FIG. 9, as an
example, 1 instruction has 32 bits as in the first example, and
since 1 group is assumed to be configured by a sequence of 4
instructions, 1 group has 128 bits. The structure of the
instruction is identical to that depicted in FIG. 2.
[0086] FIG. 10 is a block diagram depicting an example of a
functional configuration of the compression apparatus 101 according
to the second example. As depicted in FIG. 10, the compression
apparatus 101 includes an acquirer 1001, a determiner 1002, a
compressor 1003, a setter 1004, and a storer 1005. These functions
(the acquirer 1001 to the setter 1004) forming a controller, for
example, are realized by executing on the CPU 301, a program stored
in storage device such as the ROM 302, the RAM 303, the magnetic
disk 305, and the optical disk 307 depicted in FIG. 3, or by the
I/F 309.
[0087] The acquirer 1001 acquires a given instruction as a test
subject from an instruction group under test, among the sequence of
instruction groups. For example, from the head address 0x0000 of
the sequence of instruction groups, the acquirer 1001 sequentially
acquires instruction groups V1, V2, V3, and V4. Further, when the
instruction group V1 is acquired, the acquirer 1001 sequentially
acquires an instruction A1, an instruction B1, an instruction C1,
and an instruction D1. After the acquisition of the instruction D1,
the instruction group V2 at the next address 0x0010 is assumed to
be acquired.
[0088] The determiner 1002 executes determination processing
identical to the determiner 402 of the first example. However, in
the second example, since instructions are handled in units of
instruction groups, the preceding instruction of the test subject
is not the immediately preceding instruction, but rather the
instruction at the same position in the preceding instruction
group. For example, the preceding instruction of the instruction B2
at address 0x0010 is not the instruction A1 at address 0x0010, but
rather the instruction B1 at the same position in the preceding
instruction group V1. Further, the compressor 1003 executes
compression processing that is identical to that of the compressor
403 of the first example.
[0089] The setter 1004 executes setting processing identical to the
setter 404 of the first example. However, similar to the determiner
1002, the preceding instruction of the test subject is not the
instruction immediately preceding instruction, but rather the
instruction at the same position in the preceding instruction
group. In the second example, a continuity buffer is set for each
position of the instructions in the instruction groups. For
example, the instructions A1 to A4 are at different positions in
the instruction group and thus, a continuity buffer is prepared for
each position. In other words, in the example depicted in FIG. 9, 4
continuity buffers are set.
[0090] The storer 1005 stores a compression information group
obtained from the test subjects of the instruction group under test
and subsequent to the compression information group, further stores
non-compressed test subjects among the instruction group under test
and for which storage information has been set. In the first
example, compressed instructions and non-compressed instructions
are written to the compression buffer simply in the order of
writing. However, in the second example, for each instruction
group, the compression bits of the instructions in the instruction
group are collectively placed at the head. A string of compression
bits collected in this manner is referred to as a "compression
information group".
[0091] The storer 1005 establishes an area for the compression
information group in the compression buffer, and from the head
instruction of the instruction group under test, writes the
compression bits. When the compression bit is "0" (no-compression),
the non-compressed instruction including the storage bit, operation
code, and operands is written subsequent to the compression
information group.
[0092] In this manner, the storer 1005, for each instruction group,
writes a compression information group and 0 or more non-compressed
instructions to the compression buffer. However, if even 1
instruction is compressed in the instruction groups, empty areas
arise and by performing shifts according to the empty areas, the
compressed sequence of instruction groups can be shortened. By such
shortening, the number of fetches performed can be reduced,
enabling increased processing speed at the processor 102 and
reduced power consumption.
[0093] FIGS. 11A, 11B, and 11C are diagrams of an example of the
compression processing according to the second example. FIGS. 11A
to 11C depict an example where the sequence of instruction groups
depicted in FIG. 9 is compressed. FIG. 11A depicts the sequence of
instruction groups before compression; FIG. 11B depicts the
sequence of instruction groups after compression; and FIG. 11C
depicts the compressed sequence of instruction groups after
shortening.
[0094] In FIG. 11A, the compression apparatus 101 reads in the
instruction group V1 at address 0x0000, decodes the instruction
group V1, and reads in the instruction A1. Since the instruction
group V1 has no preceding instruction group, the instruction A1 has
no preceding instruction. Consequently, the compression bit of
instruction A1 is "0" (no-compression). In FIG. 11B, the head bit
of a compression information group C1 of the instruction group V1
is set to "0". Since the instruction group V1 is the head
instruction group, the subsequent instructions B1, C1, D1 have the
same results.
[0095] In FIG. 11A, the compression apparatus 101, upon completing
the compression processing for the instruction group V1 at address
0x0000, reads in (as the instruction group under test) the
instruction group V2 at the next address 0x0010, decodes the
instruction group V2, and reads in the instruction A2. Since the
preceding instruction group of the instruction group V2 is the
instruction group V1, the preceding instruction of the instruction
A2 is the instruction A1. Since the instruction A2 satisfies the
compression conditions (same operation code and operand continuity)
of the determiner 1002, the compression apparatus 101 sets the
compression bit of the instruction A2 to "1" (compression).
Accordingly, as depicted in FIG. 11B, the head bit of a compression
information group C2 of the instruction group V1 is set to "1", and
the storage bit, the operation code, and the operands are deleted.
The subsequent instructions B2, C2, and D2 of the instruction group
V2 have the same results.
[0096] For the instruction group V3 at address 0x0020, the
instructions A3 and C3 are compressed, while the instructions F and
NOP are not. Similarly, for the instruction group V4 at address
0x0030, the instructions A4 and D3 are compressed, while the
instructions B3 and NOP are not. Although the preceding instruction
of the instruction D3 is the NOP of the instruction group V3, in
the case of an NOP, since the continuity buffer holds the
difference of the instruction therebefore (i.e., the instruction
D2), the instruction D3 is compressed.
[0097] By shortening the state depicted in FIG. 11B to the state
depicted in FIG. 11C, the shortened sequence of compressed
instruction groups sys is stored at addresses 0xF100 to 0xF120,
where address 0xF130 is an empty area. Accordingly, in the state
depicted in FIG. 11A, assuming the bus width is 128, 4 memory
accesses are required. However, in the state depicted in FIG. 11C,
the memory access count is 3, thereby enabling a reduction of the
memory access count.
[0098] FIG. 12 is a flowchart depicting an example of a procedure
of compression processing by the compression apparatus 101
according to the second example. The compression apparatus 101
determines whether an instruction group is present in a sequence of
instruction groups (step S1201). If an instruction group is present
(step S1201: YES), the compression apparatus 101, via the acquirer
1001, acquires an instruction group as an instruction group under
test (step S1202); and establishes in the compression buffer, a
compression information group area of N-bits, where N=the number of
instructions in the instruction group under test (in the example
depicted in FIG. 9, N=4) (step S1203). The compression apparatus
101 sets an index i, which indicates the position of the
instruction in the instruction group under test, as i=1 (step
S1204). In the example depicted in FIG. 9, from the left i=1, 2, 3,
4(=N).
[0099] Subsequently, the compression apparatus 101 executes
test-subject compression processing (step S1205). In the
test-subject compression processing (step S1205), compression
processing of the test subject, which is the i-th instruction of
the instruction group under test, is executed. Contents of the
compression processing are described with reference to FIGS. 13 and
14.
[0100] When the test-subject compression processing (step S1205) is
executed, the compression apparatus 101 increments i (step S1206),
and determines whether i>N is true (step S1207). If i>N is
not true (step S1207: NO), the compression apparatus 101 returns to
the test-subject compression processing (step S1205). On the other
hand, if i>N is true (step S1207: YES), the compression
apparatus 101 returns to step S1201.
[0101] At step S1201, if no instruction group is present (step
S1201: NO), the compression apparatus 101, via the storer 1005,
bit-shifts the compressed instruction group stored in the
compression buffer, and thereby shortens the compressed instruction
group (the bit-shifting being performed according to the empty
areas as depicted in FIG. 11C) (step S1208), ending the compression
processing.
[0102] FIG. 13 is a first part of a flowchart depicting an example
of a procedure of the test-subject compression processing (step
S1205) depicted in FIG. 12. In FIG. 13, the compression apparatus
101, via the determiner 1002, determines whether test subject has
the same operation code as the preceding instruction (step S1301).
If the operation code is the same (step S1301: YES), the processing
described with reference to FIG. 14 is performed.
[0103] On the other hand, if the operation code is not the same
(step S1301: NO), the compression apparatus 101, via the determiner
1002, refers to the storage bit of the preceding instruction, and
determines whether the preceding instruction is an instruction that
is not to be stored as a restoration source instruction (step
S1302). If the preceding instruction is an instruction that is not
to be stored as a restoration source instruction (step S1302: YES),
the preceding instruction is a system instruction without operands
and consequently, the test subject and the instruction at the same
position in the instruction group before the instruction group
preceding the instruction group under test may have the same
operation code and operand continuity. Therefore, the compression
apparatus 101, via the setter 1004, changes the preceding
instruction to the instruction at the same position in the
instruction group therebefore (step S1303), and returns to step
S1301.
[0104] For example, if the test subject is the instruction D3
depicted in FIG. 11A, the preceding instruction is an NOP of the
instruction group V3. Since an NOP is not stored as a restoration
instruction, the instruction D2 at the same position in the
instruction group V2, which is the instruction group before that of
the preceding instruction (NOP), is regarded as the preceding
instruction.
[0105] Further, if the preceding instruction is not an instruction
that is not to be stored as a restoration source (step S1302: NO),
i.e., is an instruction to be stored as a restoration source
instruction, the compression apparatus 101, via the setter 1004,
initializes the continuity buffer of the i-th position (step
S1304), and sets the compression bit of the test subject to "0"
(step S1305).
[0106] The compression apparatus 101, via the determiner 1002,
determines whether the test subject is an instruction that is to be
stored as a restoration source instruction (step S1306). For
example, the compression apparatus 101 refers to the storage
determining table T and if the storage flag concerning the
operation code for the test subject is "1", determines that the
instruction is to be stored and if "0", determines that the
instruction is not to be stored as a restoration resource
instruction.
[0107] If the instruction is to be stored as a restoration source
instruction (step S1306: YES), the compression apparatus 101 sets
the storage bit of the test subject to "1" (step S1307). The
compression apparatus 101, via the storer 1005, stores the
compression bit "0" to the i-th bit position in the compression
information group area in the compression buffer. Further, for
storage bits of "1", the compression apparatus 101, via the storer
1005, stores subsequent to the compression information group in the
compression buffer, the operation code and operands that are
identical to those of the test subject (step S1308). Thus, a
non-compressed instruction concerning the test subject is stored
and the compression apparatus 101 returns to step S1206.
[0108] At step S1306, if the instruction is not to be stored as a
restoration source instruction (step S1306: NO), the compression
apparatus 101 sets the storage bit of the test subject to "0" (step
S1309). The compression apparatus 101 stores the compression bit
"0" to the i-th bit position in the compression information group
area of the compression buffer. For storage bits of "0", the
compression apparatus 101 stores subsequent to the compression
information group in the compression buffer, the operation code and
operands that are identical to those of the test subject (step
S1310). Thus, a non-compressed instruction concerning the test
subject is stored and the compression apparatus 101 returns to step
S1206.
[0109] FIG. 14 is a second part of a flowchart of the example of
the procedure of the test-subject compression processing (step
S1205) depicted in FIG. 12. In FIG. 14, when the operation code is
the same at step S1301 depicted in FIG. 13 (step S1301: YES), the
compression apparatus 101, via the determiner 1002, determines
whether the operand patterns of the preceding instruction and the
test subject are identical (step S1401). If the operand patterns
are not identical (step S1401: NO), the operands have no continuity
and the test subject is not be subject to compression. Therefore,
the compression apparatus 101 transitions to step S1304 in FIG. 12
and via the setter 1004, initializes the i-th position continuity
buffer.
[0110] On the other hand, if the operand patterns are identical
(step S1401: YES), the compression apparatus 101 detects
differences between the operands of the preceding instruction and
the operands of the test subject (step S1402). For example, in the
case of the preceding instruction A1 and the test subject
instruction A2, the difference is "+1". Similarly, in the case of
the preceding instruction A2 and the test subject instruction A3,
the difference is "+1".
[0111] The compression apparatus 101, via the determiner 1002,
determines whether the detected difference and the continuity
buffer value are identical (step S1403). When the detected
difference and the i-th position continuity buffer value are not
identical (step S1403: NO), the compression apparatus 101 updates
the i-th position continuity buffer to the detected difference
(step S1404) and transitions to step S1305.
[0112] When the detected difference and the i-th position
continuity buffer value are identical (step S1403: YES), such as in
the case of the preceding instruction A2 and the test subject
instruction A3, the compression apparatus 101, via the compressor
1003, sets the compression bit of the test subject to "1" (step
S1405). The compression apparatus 101, via the compressor 1003,
deletes the bit string (storage bit, instruction code) subsequent
to the compression bit of the test subject (step S1406), whereby
the compression apparatus 101 stores to the i-th position of the
compression information group area of the compression buffer, a
compressed instruction formed of merely the compression bit (=1)
(step S1407). Thereafter, the compression apparatus 101 transitions
to step S1206.
[0113] Thus, by compressing a test subject that, with respect to
the preceding instruction, has the same operation code and operand
continuity, the compression apparatus 101 enables high compression
of a sequence of instruction groups. For example, M consecutive
instruction groups of N instructions of m-bits and satisfying the
compression conditions, is (m.times.N.times.m) bits in a
non-compressed state; whereas, subsequent to compression by the
compression apparatus 101, the head instruction group alone is not
subject to compression and the instructions of the subsequent
instruction group are compressed to 1 bit (compression bit).
[0114] Consequently, the compressed size becomes
(m.times.N+(M-1).times.N) bits. Thus, when the size is reduced by
compression, since the maximum amount of compressed instructions
equivalent to the bus width can be fetched collectively, the number
of accesses to the memory can be reduced and power consumption can
be reduced. Further, system instructions such as NOPs have no
operands and consequently, such instructions are not subject to
storage as a restoration source instruction, enabling the
instructions to be excluded from restoration sources and thereby,
enabling improvement of the restoration processing efficiency.
[0115] A second embodiment will be described. In the second
embodiment, the instruction execution depicted in FIG. 1 will be
described. In the second embodiment, the processor 102 depicted in
FIG. 1, while reading in an instruction sequence, performs
execution processes concerning non-compressed instructions; and for
compressed instructions, restores each instruction by referring to
the restoration source instruction and executes the instruction. In
this manner, by fetching a compressed instruction sequence, the
number of fetches performed, i.e., the number of memory access can
be reduced and power consumption can be reduced.
[0116] FIG. 15 is a block diagram depicting an example of a
hardware configuration of the processor 102 depicted in FIG. 1. The
processor 102 is connected to an instruction RAM 151 and a data RAM
152, via a bus, enabling access thereto. The bus width, for
example, is assumed to be 32 bits. The instruction RAM 151 stores
therein the compressed instruction sequence iss depicted in FIG. 6,
the compressed instruction sequence group vs depicted in FIG. 11B,
or the compressed instruction sequence group sys depicted in FIG.
11C. The processor 102 is further connected to other surrounding
modules (not depicted) such as an input apparatus, an output
apparatus, a communication apparatus, a DSP, another CPU, enabling
access respectively thereto.
[0117] The processor 102 includes a controller 153, a recovery
register group 154, a fetch controller 155, a decoder 156, an
executing unit 157, a memory access unit 158, a data register 159,
and an interrupt controller 1510.
[0118] The controller 153 is connected to the interrupt controller
1510, the fetch controller 155, the decoder 156, the executing unit
157, the memory access unit 158, the recovery register group 154,
and the data register 159 (hereinafter, collectively referred to as
"connection destinations"). The controller 153 controls the
connection destinations, and transfers data from a given connection
destination to another connection destination. Further, the
controller 153 controls a pipeline between the fetch controller
155, the decoder 156, the executing unit 157, and the memory access
unit 158.
[0119] The recovery register group 154 is configured by an upper
recovery register 1541, an intermediate recovery register 1542, and
a lower recovery register 1543 connected in series. The upper
recovery register 1541 is connected to the fetch controller 155 and
the decoder 156; the intermediate recovery register 1542 is
connected to the executing unit 157; and the lower recovery
register 1543 is connected to the memory access unit 158.
[0120] The recovery registers respectively include a program
counter 11, 21, 31; an instruction buffer 12, 22, 32; a bit field
information (BFI) register 13, 23, 33; and an instruction counter
14, 24, 34. The program counters 11, 21, 31 hold therein values
that are counted by the fetch controller 155 and transferred from
upstream. The instruction buffers 12, 22, 32 hold therein
instruction codes obtained by the decoder 156. The BFI registers
13, 23, 33 hold therein the operand patterns of the instruction
codes obtained by the decoder 156. The instruction counters 14, 24,
34 indicate the number of consecutive times that the operation
codes are identical and the operands are regularly consecutive. The
value held by the upper recovery register 1541 is taken on by the
intermediate recovery register 1542; the value held by the
intermediate recovery register 1542 is taken on by the lower
recovery register 1543.
[0121] The fetch controller 155 includes a prefetch buffer 1551, a
fetch buffer 1552, and a program counter 1553. Here, the bit width
of the prefetch buffer 1551 and the fetch buffer 1552 is equivalent
to the bus width. The fetch controller 155 prefetches from the
instruction RAM 151, data of the bus width and stores the data to
the prefetch buffer 1551.
[0122] When the fetch buffer 1552 has empty areas, the fetch
controller 155 sequentially transfers to the fetch buffer 1552,
data that remains in the prefetch buffer 1551, the transferring
being from the head data (first in, first out). When the head bit
of the data held by the fetch buffer 155 is "0" (i.e., compression
bit=0), the fetch controller 155 determines the instruction to be a
non-compressed instruction. In this case, the fetch controller 155
transfers to the decoder 156, a bit string of a number of bits
equivalent to the non-compressed instruction.
[0123] On the other hand, when the head bit of the data held in the
fetch buffer 1552 is "1" (i.e., compression bit=1), the fetch
controller 155 determines the instruction to be a compressed
instruction. In this case, the fetch controller 155 transfers to
the decoder 156, bits of a number equivalent to the compressed
instruction (the bit value is compression information="1",
indicating compression).
[0124] The program counter 1553 counts the position of the
compressed instruction sequence fetched from the instruction RAM
151. For example, at the fetch controller 155, if a non-compressed
instruction is determined, the program counter 1553 increments the
value of the program counter 1553 by the bit length of the
non-compressed instruction (for example, in the case of 32 bits, by
32). On the other hand, at the fetch controller 155, if a
compressed instruction is determined, the program counter 1553
increments the value of the program counter 1553 by the bit length
of the compressed instruction (for example, in the case of 1, by
1).
[0125] When data is transferred from the fetch buffer 1552, the
fetch controller 155 shifts the remaining data toward the head.
When the fetch buffer 1552 is empty, the fetch controller 155
fetches data equivalent to the bit width of the prefetch buffer
1551. When the value of the program counter 1553 is updated, the
fetch controller 155 transfers to the upper program counter 11, the
updated value of the program counter 1553.
[0126] The decoder 156 is connected to the upper recovery register
1541 in the recovery register group 154, enabling access thereto.
The upper recovery register 1541 includes the upper program counter
11, the upper instruction buffer 12, the upper BFI register 13, and
the upper instruction counter 14. When the value of the program
counter 1553 in the fetch controller 155 is updated and
transferred, the decoder 156 updates the value of the upper program
counter 11 to the updated value of the program counter 1553.
[0127] The decoder 156 interprets the instruction transferred from
the fetch controller 155 and passes the instruction to the
executing unit 157. The instruction transferred from the fetch
controller 155 includes 2 types, a non-compressed instruction and a
compressed instruction. For example, when the head bit of data
transferred from the fetch controller 155 is "0" (i.e., compression
bit=0), the decoder 156 determines the instruction to be a
non-compressed instruction. On the other hand, when the head bit of
data transferred from the fetch controller 155 is "1" (i.e.,
compression bit=1), the decoder determines the instruction to be a
compressed instruction.
[0128] If the transferred instruction is determined to be a
non-compressed instruction, the decoder 156 extracts the
instruction code from the non-compressed instruction and transfers
the extracted instruction code to the executing unit 157. For
example, if the instruction IS1 at address 0xF100 and depicted in
FIG. 5 is transferred, the instruction code (operation code ADD,
operands r0, r16, r32) excluding the head 2 bits "01" is
transferred to the executing unit 157.
[0129] If the transferred instruction is determined to be a
non-compressed instruction, the decoder 156, according to the
storage bit, which is the second bit from the head, determines
whether storage to the upper instruction buffer 12 is to be
performed with respect to the transferred instruction. If the
instruction is determined to not be subject to storage (storage
bit=0), storage to the upper instruction buffer 12 and the upper
BFI register 13 is not performed.
[0130] On the other hand, if the transferred instruction is
determined to be subject to storage, the decoder 156 interprets the
operand pattern of the instruction code and writes the operand
pattern to the upper BFI register 13. For example, if the operand
pattern is written to the upper bit of the operation code, the
operand pattern is written to the upper BFI register 13. For
example, in the case of the instruction IS1 at address 0xF100 and
depicted in FIG. 6, the operand pattern written to the upper BFI
register 13 is information indicating that the type of operand is
register, the operand count is 3, the starting position of the head
operand is the 15th bit from the head of the instruction code.
[0131] Further, if the transferred instruction is to be subject to
storage, the decoder 156 writes the instruction code to the upper
instruction buffer 12. For example, if the instruction IS1 at
address 0xF100 and depicted in FIG. 6 is transferred, the
instruction code (operation code ADD, operands r0, r16, r32)
exclusive of the head 2 bits "01", is written to the upper
instruction buffer 12.
[0132] Further, if the transferred instruction is determined to be
subject to storage, the decoder 156 sets the instruction counter to
the initial value. For example, the decoder 156 sets the initial
value as 1. The instruction counter is incremented by 1 each time a
compressed instruction is transferred, and returns to the initial
value if a non-compressed instruction is transferred.
[0133] Further, if the transferred instruction is determined to be
a compressed instruction, the decoder 156, for example, in the case
of 1-bit compression information, restores the instruction to the
original instruction based on the current values of the upper BFI
register 13, the upper instruction buffer 12, and the upper
instruction counter 14. For example, if the head bit (left end) "1"
at address 0xF120 depicted in FIG. 6 is transferred, the
instruction code (operation code ADD and operands r1, r17, r33) in
the instruction IS2 is restored.
[0134] Similarly, if the second bit "1" from the head (left end) at
address 0xF120 depicted in FIG. 6 is transferred, the instruction
code (operation code ADD and operands r2, r18, r34) in the
instruction IS3 is restored. Details of the restoration processing
will be described hereinafter. The decoder 156 transfers the
restored instruction to the executing unit 157. If the decoder 156
has restored an instruction, after transferring the instruction to
the executing unit 157, the decoder increments the instruction
counter by 1.
[0135] If a non-compressed instruction or a restored instruction is
transferred to the executing unit 157, the decoder 156 transfers
the values of the upper recovery register 1541 to the intermediate
recovery register 1542, whereby the values of the intermediate
recovery register 1542 are updated, enabling the instruction code
transferred to the executing unit 157 and the values of the
intermediate recovery register 1542 to be synchronized.
[0136] The executing unit 157 executes the instruction code
transferred thereto from the decoder 156 and writes the instruction
code to the data register 159 specified by the operands. The
executing unit 157 transfers the instruction code to the memory
access unit 158. Here, the executing unit 157, via the controller
153, transfers each value in the intermediate recovery register
1542 to the lower recovery register 1543. As a result, the values
of the lower recovery register 1543 are updated, enabling the
instruction code transferred to the memory access unit 158 and the
value of the lower recovery register 1543 to be synchronized.
[0137] If the instruction code transferred from the executing unit
157 includes the address of the data RAM 152, which is the access
destination, the memory access unit 158 accesses the data RAM 152.
For example, if the operation code of the transferred instruction
code is LOAD, data is read in from the address of the data RAM 152
indicated in the instruction code and is written to the data
register 159 specified by the operand. If the operation code of the
transferred instruction code is STORE, the value of the data
register 159 specified by the data operand is written to the data
RAM 152 address indicated in the instruction code.
[0138] The interrupt controller 1510 detects an interrupt signal
from a surrounding module. The interrupt controller 1510 informs
the controller 153 of the detected interrupt signal, whereby the
controller 153 preferentially causes execution of the interrupting
instruction with respect to the fetch controller 155, the decoder
156, the executing unit 157 and the memory access unit 158. In this
case, the memory access unit 158 causes the values of the lower
recovery register 1543 to be saved in a stack area 1520 of the data
RAM 152.
[0139] The interrupt controller 1510 detects an interrupt
processing completion signal from a surrounding module. The
interrupt controller 1510 informs the controller 153 of the
detected interrupt signal, whereby the controller 153 causes, with
respect to the fetch controller 155, the decoder 156, the executing
unit 157, and the memory access unit 158, the execution of recovery
processing for recovering the state before the interrupt. For
example, the instruction code at the time of the interrupt at the
memory access unit 158 is recovered at the decoder 156 by using the
values of the lower register, stored to the stack area 1520 of the
data RAM 152. The recovery processing of restoring the state before
an interrupt will be described in detail hereinafter.
[0140] An operand updater in the decoder 156 will be described in
detail. According to the operand pattern held in the upper the BFI
register 13, the operand updater extracts the operands held in the
upper instruction buffer 12, 1 operand at a time. From the
extracted operands and the value of the instruction counter, the
operand updater updates the extracted operands. The contents of the
updating processing, for example, are as follows.
Operand=Operand OP X (1)
X=IC or (IC OP K) (2)
OP=+ or - or * or / or >> or << (3)
Where, K=coefficient
[0141] In equation 1, the left-hand term "Operand" is the updated
operand, the right-hand term "Operand" is the operand before
updating. In equations 1 and 2, "OP" is an operation, and as
prescribed by equation 3, is an arithmetic operator and a shift
operation is performed. "X" is a variable and "IC" is the value of
the upper instruction counter 14. "X" is the value "IC" of the
upper instruction counter 14 or a value resulting from an operation
involving a constant K and the value "IC" of the upper instruction
counter 14.
[0142] For example, when the operand (register number, variable)
increases by 1 for each instruction, the value of the instruction
counter increases by 1, whereby "OP" is OP="+", and X=IC is set. As
a result, equation 1 becomes as follows.
Operand=Operand+IC (4)
[0143] When the operand (register number, variable) increases by 2
for each instruction, the value of the instruction counter
increases by 1, whereby "OP" is OP="+", and K=1 is set. As a
result, equation 1 becomes as follows.
Operand=Operand+IC+1 (5)
[0144] When the operand (register number, variable) decreases by 1
for each instruction, the value of the instruction counter
increases by 1, whereby in equation 2, OP="*" and K=-1 is set, and
in equation 1, "OP" is set as OP="+". As a result, equation 1
becomes as follows.
Operand=Operand+{IC*(-1)} (6)
[0145] The way that the operand regularly changes for each
instruction, i.e., concerning the combination of "OP" and "K", is
specified by the instruction code. Such circuit configuration can
be built from combinational circuits. Hereinafter, an example will
be described in detail.
[0146] FIG. 16 is a diagram of a first configuration example of the
operand updater. In FIG. 16, an operand updater 1600 is configured
by equations A to Z, an equation setting register 1601, a
coefficient register 1602, and a selector 1603. Each of the
equations A to Z is configured by combinational circuits. When
there is an equation changing instruction, equation-setting code
that selects any equation from among the equations A to Z is
written to the equation setting register 1601. When there is a
coefficient changing instruction, a value K is written to the
coefficient register 1602.
[0147] In each of the equations A to Z, the operand before updating
(right-hand term Operand of equation 1), the value IC of the upper
instruction counter 14, and the value K of the coefficient register
1602 are input. The equation-setting code written in the equation
setting register 1601 is input to the selector 1603. Output from
the selector is the updated operand (left-hand term Operand of
equation 1).
[0148] For example, as a non-compressed instruction, an equation
changing instruction and a coefficient changing instruction are in
the compressed instruction sequence depicted in FIG. 6, at the
address before 0xF100; the value of the operand (selection code
specifying the equation to be used from among the equations A to Z)
of the equation changing instruction is held in the equation
setting register 1601; and the value K=0 of the operand of the
coefficient changing instruction is held in the coefficient
register 1602.
[0149] For example, in the case of the instruction IS1 at 0xF100,
equation A is assumed to be equation 4. The selection code of
equation A is held in the equation setting register 1601. As a
result, the value IC of the instruction counter, the register
number r0, which is the operand before updating, and the
coefficient K=0 are input, and according to equation 4, the updated
operand becomes r1. The same is true concerning r16 and r32.
[0150] FIG. 17 is a diagram of a second configuration example of
the operand updater 1600. FIG. 16 depicts an example where an
equation changing instruction and a coefficient changing
instruction are included in a compressed instruction sequence. FIG.
17 depicts an example where the operation code (or a portion
thereof) of a restoration source instruction is the selection code
of the equations A to Z. For example, when the operation code is
ADD, selection code selecting equation A is set. When the operation
code is STORE, selection code selecting equation B is set by a
selector 1703. In such a configuration, instructions equivalent to
the equation changing instructions become unnecessary, enabling
efficient compression to be facilitated.
[0151] FIG. 18 is a diagram of a third configuration example of the
operand updater 1600. FIG. 18 depicts an example of a configuration
enabling selection of an equation setting method of setting any one
among the configuration example depicted in FIG. 16 and the
configuration example depicted in FIG. 17. Since the configuration
example depicted in FIG. 16 can be selected, the configuration
example can be selected even in a case where the operation codes
differ and the operations are the same.
[0152] For example, the operand updater 1600 includes an equation
setting method selection register 1801, and selectors 1802, 1803.
When there is an equation-setting method changing instruction,
selection code selecting any one of the operation code and the
equation-setting code written in the equation setting register, is
written in the equation setting method selection register 1801.
According to the selection code written in the equation setting
method selection register 1801, a selector 1802 selects any one
among the operation code and the equation-setting code written in
the equation setting register. According to a selection signal from
the selector 1802, a selector 1803 selects the corresponding
equation from among the equations A to Z and updates the operand.
In each of the configuration examples depicted in FIGS. 16 to 18,
the operand updater 1600 can handle the regular changes of the
operands, for each instruction.
[0153] FIG. 19 is a flowchart of processing by the processor 102.
The processor 102, via the fetch controller 155, performs
prefetching (step S1901) and fetching (step S1902). The processor
102, via the fetch controller 155, refers to the head bit of the
fetch buffer, and determines whether a bit string in the fetch
buffer is a compressed instruction or a non-compressed instruction
(step S1903). If the bit string is a non-compressed instruction
(step S1903: NO), the processor 102, via the prefetch buffer 1551,
increments the value of the program counter by the number of
non-compressed instructions (step S1904).
[0154] Thereafter, the processor 102, via the decoder 156,
determines whether the non-compressed instruction is to be stored
as a restoration source instruction (step S1905). For example, the
processor 102 refers to the storage bit (the second bit from the
head) and if the storage bit is "1", determines that the
non-compressed instruction is to be stored as a restoration source
instruction, and if the storage bit is "0", determines that the
non-compressed instruction is not to be stored as a restoration
source instruction.
[0155] If the non-compressed instruction is not to be stored as a
restoration source instruction (step S1905: NO), the processor 102,
via the decoder 156, decodes the non-compressed instruction (step
S1906) and transitions to step S1914. On the other hand, if the
non-compressed instruction is to be stored as a restoration source
instruction (step S1905: YES), the processor 102, via the decoder
156, stores to the upper instruction buffer 12, the instruction
code in the non-compressed instruction (step S1907). Thereafter,
the processor 102, via the decoder 156, decodes the non-compressed
instruction (step S1908), stores the operand pattern of the
non-compressed instruction to the upper BFI register 13,
initializes the upper instruction counter 14 (step S1909), and
transitions to step S1914.
[0156] At step S1903, if the bit string is a compressed instruction
(step S1903: YES), the processor 102, via the fetch controller 155,
increments the value of the program counter by the number of
compressed instructions (step S1910). The processor 102, via the
decoder 156, acquires the instruction code held in the upper
instruction buffer 12 (step S1911).
[0157] Thereafter, the processor 102 acquires the operand pattern
from the upper BFI register 13 and thereby, identifies the operand
to be updated and based on the value of the upper instruction
counter 14, updates each of the operands to be updated, via the
operand updater 1600 (step S1912). The processor 102, via the
decoder 156, combines the operation code in the instruction code
acquired from the upper instruction buffer 12 and the updated
operand; and thereby, restores the compressed instruction to the
instruction before compression (step S1913). The processor 102
transitions to step S1914.
[0158] The processor 102, at step S1914, determines whether the bit
length of the bit string prefetched by the fetch controller 155 is
at least a given size (step S1914), and if the bit length is the
given size or greater (step S1914: YES), returns to step S1902 and
performs fetching (step S1902).
[0159] On the other hand, if the bit length is not the given size
or greater (step S1914: NO), the processor 102 returns to step
S1901 and performs prefetching (step S1901). Thus, by the operation
of the fetch controller 155 and the decoder 156, a non-compressed
instruction is normally decoded and transferred to the executing
unit 157; and a compressed instruction is restored to the original
instruction and transferred to the executing unit 157.
[0160] Pipeline processing according to the second embodiment will
be described. In the pipeline processing, instruction fetching by
the fetch controller 155, register read by the decoder 156,
execution by the executing unit 157, and memory access by the
memory access unit (stage before commit) are executed. In the
pipeline processing, as described above, at the register read stage
by the decoder 156, the operand is updated, the instruction code
before compression is restored, and recovery processing in the case
of an interrupt is executed. In a third embodiment, pipeline
processing of a compressed instruction sequence compressed by the
first example will be described; and in a fourth embodiment,
pipeline processing of a sequence of compressed instruction groups
compressed by the second example will be described.
[0161] FIGS. 20 to 36 are diagrams of an example of pipeline
processing according to the third embodiment. In FIG. 20, the fetch
controller 155 prefetches and holds in the prefetch buffer 1551,
the bit string (instruction IS1) at address 0xF100 of the
instruction RAM 151.
[0162] In FIG. 21, the fetch controller 155 fetches from the
prefetch buffer 1551 and holds in the fetch buffer, the bit string
(instruction IS1) of address 0xF100 of the instruction RAM 151. The
fetch controller 155, prefetches and holds in the prefetch buffer
1551, which has become empty consequent to the fetching, the bit
string at address 0xF104 of the instruction RAM 151.
[0163] In FIG. 22, the fetch controller 155 determines whether the
bit string (instruction IS1) of address 0xF100 and held in the
fetch buffer is a non-compressed instruction. For example, the
fetch controller 155 determines whether the head bit of the fetch
buffer (compression bit) is "0" (no-compression) or "1"
(compression). In the case of the bit string of address 0xF100,
since the head bit is "0", the bit string of address 0xF100 is
determined to be a bit string of a non-compressed instruction. In
this case, the fetch controller 155 transfers the entire bit string
in the fetch buffer to the decoder 156.
[0164] The fetch controller 155 updates the program counter by the
number of transferred bits. In this case, since the transferred bit
string is 32 bits, the value of the program counter becomes "32".
The fetch controller 155 transfers the updated value "32" of the
program counter to the upper program counter 11 of the decoder
156.
[0165] The decoder 156, upon receiving the non-compressed
instruction transferred from the fetch controller 155, refers to
the storage bit, which is the second bit from the head of
non-compressed instruction. In this case, since the value of the
storage bit is "1" (storage), the decoder 156 holds in the upper
instruction buffer 12, the instruction code ISC1 (operation code:
ADD, operand: r0, r16, r32) in the non-compressed instruction. The
decoder 156 holds the operand pattern D1 of the instruction code
ISC1 in the upper BFI register 13. The decoder 156, since a
non-compressed instruction has been transferred thereto, sets the
upper instruction counter 14 to the initial value of "1". The
decoder 156 sets the program counter value transferred from the
fetch controller 155 as the value of the upper program counter
11.
[0166] In FIG. 23, the fetch controller 155 fetches from the
prefetch buffer 1551 and holds in the fetch buffer 1552 that has
become empty, the bit string of address 0xF104. The fetch
controller 155 prefetches and holds in the prefetch buffer 1551,
which has become empty consequent to the fetching, the bit string
at address 0xF10C in the instruction RAM 151.
[0167] The decoder 156 transfers the instruction code ISC1 and the
values of the upper recovery register 1541 to the executing unit
157. The executing unit 157 updates the intermediate recovery
register 1542 to the values of the upper recovery register 1541. By
referring to the data register 159 and the data RAM 152, the
executing unit 157 executes the instruction code ISC1 transferred
from the decoder 156.
[0168] In FIG. 24, the fetch controller 155 determines whether the
bit string of address 0xF104 and held in the fetch buffer is a
non-compressed instruction. In the case of the bit string of
address 0xF104, since the head bit is "1", the head bit of the bit
string of address 0xF104 is a compressed instruction. In this case,
the fetch controller 155 transfers the head bit (=1) of the fetch
buffer to the decoder 156.
[0169] The fetch controller 155 updates the program counter by the
number of transferred bits. In this case, since the transferred bit
string is the head bit (1 bit), the value of the program counter
becomes "33". The fetch controller 155 transfers the updated value
"33" of the program counter to the upper program counter 11 of the
decoder 156.
[0170] The decoder 156, upon receiving the compressed instruction
transferred from the fetch controller 155, reads out the
instruction code ISC1 held in the upper instruction buffer 12, the
operand pattern D1 held in the BFI register, and the value "1" of
the instruction counter. The decoder 156, via the operand updater
1600, updates the operands of the read instruction code ISC1,
whereby, the decoder 156 restores the original instruction code
ISC2 (operation code: ADD, operands: r1, r17, r33).
[0171] The executing unit 157 transfers the instruction code ISC1
and the values of the intermediate recovery register 1542 to the
memory access unit 158. The memory access unit 158 updates the
lower recovery register 1543 to the values of the intermediate
recovery register 1542. The memory access unit 158 accesses the
data RAM 152, according to the operation code of the transferred
instruction code. In the case of the instruction code ISC1, since
the data RAM 152 address is not in the operands, the data RAM 152
is not accessed.
[0172] In FIG. 25, the decoder 156 transfers the restored
instruction code ISC2 and the values of the upper recovery register
1541 to the executing unit 157. The decoder 156, after the
transfer, increments the value of the upper instruction counter 14
by 1. The executing unit 157 updates the intermediate recovery
register 1542 to the values of the upper recovery register 1541.
Accordingly, the values of the upper recovery register 1541 and the
values of the intermediate recovery register 1542 only differ for
the value "2" of the upper instruction counter 14 and the value "1"
of the intermediate counter 24. By referring to the data register
159 and the data RAM 152, the executing unit 157 executes the
instruction code ISC2 transferred from the decoder 156.
[0173] In FIG. 26, since 1 bit has become empty consequent to the
transfer of the 1-bit compressed instruction as depicted in FIG.
24, the fetch controller 155 shifts the bit string (31 bits)
remaining in the fetch buffer by 1 bit, and fetches and holds in
the empty area (1 bit), the head bit of the prefetch buffer 1551.
At the memory access unit 158, when the instruction code ISC1 is
processed, processing (writeback) other than commit stage
processing is performed.
[0174] In FIG. 27, the fetch controller 155 determines whether the
bit string in the fetch buffer is a non-compressed instruction. In
the case of this bit string, since the head bit is "1", the head
bit of the bit string held in the fetch buffer is determined to be
a compressed instruction. In this case, the fetch controller 155
transfers the head bit (=1) in the fetch buffer to the decoder
156.
[0175] The fetch controller 155 updates the program counter by the
number of transferred bits. In this case, since the transferred bit
string is the head bit (1 bit), the value of the program counter
becomes "34". The fetch controller 155 transfers the updated
program counter value "34" to the upper program counter 11 of the
decoder 156.
[0176] The decoder 156, upon receiving the compressed instruction
transferred from the fetch controller 155, reads out the
instruction code ISC1 held in the upper instruction buffer 12, the
operand pattern D1 held in the BFI register, and the instruction
counter value "2". The decoder 156, via the operand updater 1600,
updates the operands of the read instruction code ISC1, whereby the
decoder 156 restores the original instruction code ISC3 (operation
code: ADD, operands: r2, r18, r34).
[0177] The executing unit 157 transfers the instruction code ISC2
and the value of the intermediate recovery register 1542 to the
memory access unit 158. The memory access unit 158 updates the
lower recovery register 1543 to the values of the intermediate
recovery register 1542. The memory access unit 158 accesses the
data RAM 152, according to the operation code of the transferred
instruction code. In the case of the instruction code ISC2, since
the data RAM 152 address is not included in the operands, the data
RAM 152 is not accessed.
[0178] In FIG. 28, the decoder 156 transfers the restored
instruction code ISC3 and the value of the upper recovery register
1541 to the executing unit 157. The decoder 156, after the
transfer, increments the value of the upper instruction counter 14
by 1. The executing unit 157 updates the intermediate recovery
register 1542 to the values of the upper recovery register 1541.
Accordingly, the values of the upper recovery register 1541 and the
values of the intermediate recovery register 1542 only differ for
the value of "3" for the upper instruction counter 14 and the value
of "2" for the intermediate instruction counter 24. By referring to
the data register 159 and the data RAM 152, the executing unit 157
executes the instruction code ISC3 transferred from the decoder
156.
[0179] In FIG. 29, since 1 bit has become empty consequent to the
transfer of the 1-bit compressed instruction as depicted in FIG.
28, the fetch controller 155 shifts the bit string (31 bits)
remaining in the fetch buffer by 1 bit, and fetches and holds in
the empty area (1 bit), the head bit of the prefetch buffer 1551.
At the memory access unit 158, when the instruction code ISC2 is
processed, processing (writeback) other than commit stage
processing is performed.
[0180] In FIG. 30, the fetch controller 155 determines whether the
bit string in the fetch buffer is a non-compressed instruction. In
the case of this bit string, since the head bit is "0", the bit
string in the fetch buffer 1552 is determined to be a bit string of
a non-compressed instruction. In this case, the fetch controller
155 transfers the entire bit string in the fetch buffer to the
decoder 156.
[0181] The fetch controller 155 updates the program counter 1553 by
the number of bits transferred. In this case, since the transferred
bit string is 32 bits, the value of the program counter 1553
becomes "66". The fetch controller 155 transfers the updated
program counter value "66" to the upper program counter 11 of the
decoder 156.
[0182] The decoder 156, upon receiving the non-compressed
instruction transferred from the fetch controller 155, refers to
the storage bit, which is the second bit from the head of the
non-compressed instruction. In this case, since the value of the
storage bit is "1" (storage), the instruction code ISC4 (operation
code: STORE, operands: r32, 0x0000) in the non-compressed
instruction are held in the upper instruction buffer 12. The
decoder 156 holds the operand pattern D4 of the instruction code
ISC4 in the upper BFI register 13. The decoder 156, since a
non-compressed instruction has been transferred thereto, sets the
instruction counter 14 to the initial value of "1". The decoder 156
sets the program counter value "66" transferred thereto from the
fetch controller 155, as the upper program counter 11 value
"66".
[0183] In FIG. 31, the fetch controller 155 fetches the 30-bit bit
string in the prefetch buffer 1551 (see FIG. 30). The fetch
controller 155 prefetches and holds in the prefetch buffer 1551,
which has become empty, the bit string "001" at address 0xF160 in
the instruction RAM 151. Since 2 bits have become empty in the
fetch buffer, the fetch controller 155 fetches and holds in the
fetch buffer, the first 2 bits "00" among the 3 bits in prefetch
buffer. As a result, the instruction IS5 is fetched and held in the
fetch buffer.
[0184] The decoder 156 transfers the instruction code ISC4 and the
value of the upper recovery register 1541 to the executing unit
157. The executing unit 157 updates the intermediate recovery
register 1542 to the values of the upper recovery register 1541. By
referring to the data register 159 and the data RAM 152, the
executing unit 157 executes the instruction code ISC4 transferred
from the decoder 156. At the memory access unit 158, when the
instruction code ISC3 is processed, processing (writeback) other
than commit stage processing is performed.
[0185] In FIG. 32, the fetch controller 155 determines whether the
bit string (instruction IS5) of address 0xF160 and held in the
fetch buffer 1552 is a non-compressed instruction. In the case of
the bit string of address 0xF160, since the head bit is "0", the
bit string of address 0xF160 is determined to be a bit string of a
non-compressed instruction (instruction IS5). In this case, the
fetch controller 155 transfers the entire bit string (instruction
IS5) in the fetch buffer 1552 to the decoder 156.
[0186] The fetch controller 155 updates the program counter by the
number of transferred bits. In this case, since the transferred bit
string is 32 bits, the program counter value becomes "98". The
fetch controller 155 transfers the updated program value "98" to
the upper program counter 11 of the decoder 156.
[0187] The decoder 156, upon receiving the non-compressed
instruction transferred from the fetch controller 155, refers to
the storage bit, which is the second bit from the head of the
non-compressed instruction (instruction IS5). In this case, since
the value of the storage bit is "0" (no-storage), the instruction
code ISC5 (NOP) in the non-compressed instruction is not held in
the upper instruction buffer 12. Similarly, the operand pattern of
the instruction code ISC5 (NOP) is not held in the upper BFI
register 13.
[0188] Thus, for system instruction code such as the instruction
code ISC5 (NOP), by excluding system instruction code from operand
updating processing, operands can be updated from the value of the
upper recovery register 1541 and the subsequent instruction code.
The decoder 156, since a non-compressed instruction has been
transferred thereto, sets the upper instruction counter 14 to the
initial value of "1". The decoder 156 sets the program counter
value "98" from the fetch controller 155, as the upper program
counter 11 value "98".
[0189] The executing unit 157 transfers the instruction code ISC4
and the value of the intermediate recovery register 1542 to the
memory access unit 158. The memory access unit 158 updates the
lower recovery register 1543 to the values of the intermediate
recovery register 1542. The memory access unit 158 accesses the
data RAM 152, according to the operation code of the transferred
instruction code. In the case of the instruction code ISC4, since
the data RAM 152 address 0x0000 is in the operands, the data RAM
152 address 0x0000 is accessed (STORE).
[0190] In FIG. 33, the fetch controller 155 fetches and holds in
the fetch buffer 1552, which has become empty, the bit string (1
bit) in the prefetch buffer 1551. The decoder 156 transfers the
instruction code ISC5 and the values of the upper recovery register
1541 to the executing unit 157. The executing unit 157 updates the
intermediate recovery register 1542 to the values of the upper
recovery register 1541. The executing unit 157, since the
instruction code ISC5 transferred from the decoder 156 is NOP, does
nothing. At the memory access unit 158, when the instruction code
ISC4 is processed, processing (writeback) other than commit stage
processing is performed.
[0191] In FIG. 34, the fetch controller 155 determines whether the
bit string in the fetch buffer 1552 is a non-compressed
instruction. In the case of this bit string, since the head bit is
"1", the head bit of the bit string held in the fetch buffer 1552
is determined to be a compressed instruction. In this case, the
fetch controller 155 transfers the head bit (=1) in the fetch
buffer 1552 to the decoder 156.
[0192] The fetch controller 155 updates the program counter 1553 by
the number of transferred bits. In this case, since the transferred
bit string is the head bit (1 bit), the value of the program
counter 1553 becomes "99". The fetch controller 155 transfers the
updated program counter 1553 value "99" to the upper program
counter 11 of the decoder 156.
[0193] The decoder 156, upon receiving the compressed instruction
transferred from the fetch controller 155, reads out the
instruction code ISC4 held in the upper instruction buffer 12, the
operand pattern D4 held in the upper BFI register 13, and the value
"1" of the instruction counter 14. The decoder 156, via the operand
updater 1600, updates the operand of the read instruction code
ISC4, whereby the decoder 156 restores the original instruction
code ISC6 (operation code: STORE, operands: r33, 0x0001). In this
case, the updated operand becomes 0x0001. However, depending on the
data size and/or memory size handled by the instruction, the value
of the instruction counter 14 may be multiplied by a coefficient by
the decoder block (156).
[0194] The executing unit 157 transfers the instruction code ISC5
(NOP) and the values of the intermediate recovery register 1542 to
the memory access unit 158. The memory access unit 158 updates the
lower recovery register 1543 to the values of the intermediate
recovery register 1542. The memory access unit 158 accesses the
data RAM 152, according to the transferred operation code of the
instruction code. In the case of instruction code ISC5, since the
instruction code is NOP nothing is done.
[0195] In FIG. 35, the decoder 156 transfers the restored
instruction code ISC6 and the value of the upper recovery register
1541 to the executing unit 157. The decoder 156, after the
transfer, increments the value of the upper instruction counter 14
by 1. The executing unit 157 updates the intermediate recovery
register 1542 to the values of the upper recovery register 1541.
Accordingly, the values of the upper recovery register 1541 and the
values of the intermediate recovery register 1542 differ for the
value "2" of the upper instruction counter 14 and the value "1" of
the intermediate counter 24. By referring to the data register 159
and the data RAM 152, the executing unit 157 executes the
instruction code ISC6 transferred from the decoder 156.
[0196] In FIG. 36, the executing unit 157 transfers the instruction
code ISC6 and the values of the intermediate recovery register 1542
to the memory access unit 158. The memory access unit 158 updates
the lower recovery register 1543 to the values of the intermediate
recovery register 1542. The memory access unit 158 accesses the
data RAM 152, according to the operation code of the transferred
instruction code. In the case of the instruction code ISC6, since
the data RAM 152 address 0x0001 is in the operands, the data RAM
152 address 0x0001 is accessed (STORE). At the memory access unit
158, when the instruction code ISC6 is processed, processing
(writeback) other than commit stage processing is performed.
[0197] Thus, the compressed instruction sequence iss is pipeline
processed, whereby the compressed instruction is restored by the
decoder 156. Accordingly, the processor 102 can execute the same
instructions as the instruction sequence before compression.
Further, since the compressed instruction sequence iss includes
compressed instructions, the number of fetches from the instruction
RAM 151 can be reduced. In other words, since the number of memory
access to the instruction RAM 151 is reduced, reduced power
consumption can be facilitated.
[0198] Recovery processing from an interrupt occurring during the
instruction execution depicted in FIGS. 20 to 36, will be
described. When an interrupt occurs, the processor 102 completes
commit state transition processing (writeback, . . . ) and then
performs interrupt processing. In this case, concerning the commit
pre-stage processing, the processor 102 temporarily saves the value
of the lower recovery register 1543 and executes the interrupt
processing. When the interrupt processing ends, the processor 102
uses the saved value of the lower recovery register 1543 and
resumes the commit pre-stage processing. Hereinafter, a case where
an interrupt occurs during the processing depicted in FIG. 31 will
be described with reference to FIGS. 37 to 42.
[0199] FIGS. 37 to 42 are diagrams of an example of recovery
processing for recovery from an interrupt. The processor 102, via
the interrupt controller 1510, detects the occurrence of an
interrupt by a surrounding module or a timer and upon doing so,
issues via the controller 153, an interrupt signal to the fetch
controller 155, the decoder 156, the executing unit 157, and the
memory access unit 158.
[0200] In FIG. 37, the memory access unit 158, upon receiving the
interrupt signal, saves the value of the lower recovery register
1543 or the value of a generic register to the stack area 1520 of
the data RAM 152.
[0201] In FIG. 38, the fetch controller 155, upon receiving the
interrupt signal, clears the prefetch buffer 1551 and the fetch
buffer 1552, and prepares for interrupt processing. Similarly, the
decoder 156, the executing unit 157, the memory access unit 158,
upon receiving the interrupt signal, respectively clear the values
of the upper recovery register 1541, the intermediate recovery
register 1542, and the lower recovery register 1543, and prepare
for interrupt processing. The processor 102 executes the interrupt
processing.
[0202] In FIG. 39, the decoder 156, upon receiving an interrupt
completion signal through the interrupt controller 1510 and the
controller 153, sets the lower instruction buffer 32 value
(instruction code ISC1) saved in the stack area 1520, the lower BFI
register 33 value (operand pattern D1), and the lower instruction
counter 34 value "2" to the value of the upper instruction buffer
12, the value of the upper BFI register 13, and the value of the
upper instruction counter 14, respectively. The fetch controller
155 again clears the prefetch buffer 1551 and the fetch buffer
1552, and reads in the lower program counter 31 value "34" saved in
the stack area 1520.
[0203] In FIG. 40, the fetch controller 155 divides the lower
program counter 31 value "34" read from the stack area 1520 by the
bit width (32 bits) of the fetch buffer. In this case, the quotient
is "1" with a remainder of "2". The fetch controller 155 multiplies
the quotient "1" by the bit width (32 bits) of the fetch buffer and
thereby, identifies the bit position to be prefetched. In this
case, since the quotient "1".times.32 bits=32, the bit string from
the 32nd bit from the head of the compressed instruction sequence,
i.e., the bit string of address 0xF104 of the instruction RAM 151
is prefetched and held in the prefetch buffer 1551. The fetch
controller 155 sets the program counter 1553 to "32".
[0204] In FIG. 41, the fetch controller 155 determines whether the
bit string in the fetch buffer 1552 is a non-compressed
instruction. In the case of this bit string, since the head bit is
"1", the head bit of the fetched bit string is determined to be a
compressed instruction. In this case, the fetch controller 155
transfers the head bit in the fetch buffer 1552 to the decoder
156.
[0205] The fetch controller 155 updates the program counter 1553 by
the number of bits transferred. In this case, since the transferred
bit string is 1 bit, the value of the program counter 1553 becomes
"33". In this case, since this value and the lower program counter
31 value "34" saved in the stack area 1520 do not coincide, the
fetch controller 155 does not transfer the updated program counter
value "33" to the upper program counter 11 of the decoder 156.
[0206] The decoder 156, despite having received the compressed
instruction transferred from the fetch buffer 1552, discards the
compressed instruction since the value of the program counter 1553
is not received. Thus, until the value of the program counter 1553
of the fetch controller 155 and the lower program counter 31 value
read from the stack area 1520 coincide, the decoder 156 discards
the bit strings from the fetch buffer 1552. As a result, at an
errant bit position, the instruction is not restored.
[0207] In FIG. 42, since 1 bit was transferred at the processing
depicted in FIG. 40, the fetch controller 155 fetches the head bit
of the prefetch buffer 1551. Subsequently, the fetch controller 155
determines whether the bit string in the fetch buffer 1552 is a
non-compressed instruction. In the case of this bit string, since
the head bit is "1", the head bit of the fetched bit string is
determined to be a compressed instruction. In this case, the fetch
controller 155 transfers the head bit in the fetch buffer 1552 to
the decoder 156.
[0208] The fetch controller 155 updates the program counter 1553 by
the number of transferred bits. In this case, since the transferred
bit string is 1 bit, the value of the program counter 1553 becomes
"34". In this case, the fetch controller 155 transfers the updated
program counter 1553 value "34" to the upper program counter 11 of
the decoder 156.
[0209] The decoder 156, having received the compressed instruction
from the fetch buffer 1552 and the value of the program counter
1553, restores the instruction from the values of the upper
recovery register 1541. Thus, the instruction code ISC2 that was
processed up to the memory access unit 158 at the time of the
interrupt is restored. The processing hereinafter is executed
similarly to that depicted in FIGS. 28 to 36. Thus, at the proper
recovery position, the instruction can be restored.
[0210] The fourth embodiment will be described. In the fourth
embodiment, an example where instruction execution is performed
concerning the sequence of compressed instruction groups sys
depicted in FIG. 11C will be described. In the case of a sequence
of compressed instruction groups sys, 1 instruction group (a
non-compressed instruction group or a restored instruction group)
includes N instructions (in FIG. 11A, N=4). Accordingly, the upper
instruction buffer 12, the intermediate BFI register 22, and the
lower instruction buffer 32 hold therein a value for each
instruction. Further, in the fourth embodiment, the bit width of
the prefetch buffer 1551 and the fetch buffer 1552 is assumed to
be, for example, 128 bits.
[0211] FIGS. 43 to 55 are diagrams of an example of pipeline
processing according to the fourth embodiment. In FIG. 43, the
fetch controller 155 prefetches and holds in the prefetch buffer
1551, the bit string at address 0xFF00 in the instruction RAM
151.
[0212] In FIG. 44, the fetch controller 155 fetches and holds in
the fetch buffer, the bit string that is of address 0xFF00 of the
instruction RAM 151 and that is in prefetch buffer 1551. The fetch
controller 155 further prefetches and holds in the prefetch buffer
1551 that has become empty consequent to the fetching, the bit
string at address 0xFF10 in the instruction RAM 151.
[0213] In FIG. 45, the fetch controller 155 determines whether the
fetched bit string of address 0xFF00 and held in the fetch buffer
1552 is a non-compressed instruction. For example, when the first 4
bits (compression bit string) of the fetch buffer 1552 are
respectively "0", the fetch controller 155 determines
no-compression and when the first 4 bits are respectively "1",
fetch controller 155 determines compression. In the case of the bit
string at address 0xFF00, since the first 4 bits are each "0", the
bit string of address 0xFF00 is determined to be a bit string of 4
non-compressed instructions. In this case, the fetch controller 155
transfers the entire bit string in the fetch buffer 1552 to the
decoder 156.
[0214] The fetch controller 155 updates the program counter 1553 by
the number of transferred bits. In this case, since the transferred
bit string is 128 bits, the value of the program counter 1553
becomes "128". The fetch controller 155 transfers the updated
program counter value "128" to the upper program counter 11 of the
decoder 156.
[0215] The decoder 156, upon receiving the non-compressed
instruction group transferred from the fetch controller 155,
divides the non-compressed instruction group into 4 instructions.
The decoder 156 refers to the storage bit (the head bit) of each
resulting non-compressed instruction. In this case, since the value
of the storage bit of each of the non-compressed instructions is
"1" (storage), the decoder 156 holds in the upper instruction
buffer 12, each of the instruction codes A1 to D1 in the
non-compressed instructions.
[0216] The decoder 156 further holds in the upper BFI register 13,
the operand patterns A1-BFI to D1-BFI of the instruction codes A1
to D1. The decoder 156, having received the non-compressed
instructions A1 to D1, sets the instruction counter 14 for each to
the initial value of "1". The decoder 156 sets the program counter
value transferred from the fetch controller 155 as the upper
program counter 11 value.
[0217] In FIG. 46, the fetch controller 155 fetches from the
prefetch buffer 1551 and holds in the fetch buffer 1552, which has
become empty, the bit string of address 0xFF10. The fetch
controller 155 fetches and holds in the prefetch buffer 1551 that
has become empty consequent to the fetching, the bit string at
address 0xFF20 in the instruction RAM 151.
[0218] The decoder 156 transfers the instruction codes A1 to D1 and
the value of the upper recovery register 1541 to the executing unit
157. The executing unit 157 updates the intermediate recovery
register 1542 to the value of the upper recovery register 1541. By
referring to the data register 159 and the data RAM 152, the
executing unit 157 executes the instruction codes A1 to D1
transferred from the decoder 156.
[0219] In FIG. 47, the fetch controller 155 determines whether the
bit string of address 0xFF10 and held in the fetch buffer 1552 is a
non-compressed instruction. In the case of the bit string of
address 0xFF10, since the first 4 bits are each "1", the first 4
bits of the bit string of address 0xFF10 are determined to be a
compressed instruction sequence. In this case, the fetch controller
155 transfers the first 4 bits (=1111) in the fetch buffer 1552 to
the decoder 156.
[0220] The fetch controller 155 updates the program counter by the
number of bits transferred. In this case, since the transferred bit
string is the first 4 bits, the value of the program counter
becomes "132". The fetch controller 155 transfers the updated
program counter value "132" to the upper program counter 11 of the
decoder 156.
[0221] In FIG. 48, since 4 bits have become empty consequent to the
transfer of the 4 compressed instruction sequences as depicted in
FIG. 47, the fetch controller 155 shifts the bit string (124 bits)
remaining in the fetch buffer by 4 bits, and fetches and holds in
the empty area (4 bits), the first 4 bits of the prefetch buffer
1551.
[0222] The decoder 156, upon receiving the compressed instruction
sequences from the fetch controller 155, reads out for each
instruction, the instruction codes A1 to D1 held in the upper
instruction buffer 12, the operand patterns A1-BFI to D1-BFI held
in the BFI register, and the instruction counter value "1". The
decoder 156, via the operand updater 1600, updates the operands of
the instruction codes A1 to D1 for each instruction code, whereby
the decoder 156 restores the original instruction codes A2 to
D2.
[0223] The executing unit 157 transfers the instruction codes A1 to
D1 and the values of the intermediate recovery register 1542 to the
memory access unit 158. The memory access unit 158 updates the
lower recovery register 1543 to the values of the intermediate
recovery register 1542. The memory access unit 158 further accesses
the data RAM 152, according to the operation code of the
transferred instruction codes A1 to D1.
[0224] In FIG. 49, the decoder 156 transfers the restored
instruction codes A2 to D2 and the value of the upper recovery
register 1541 to the executing unit 157. The decoder 156, after the
transfer, increments the upper instruction counters 14 by 1. The
executing unit 157 updates the intermediate recovery register 1542
to the values of the upper recovery register 1541. Accordingly, the
values of the upper recovery register 1541 and the values of the
intermediate recovery register 1542 differ for only the upper
instruction counter 14 value "2" and the intermediate instruction
counter 24 value "1". By referring to the data register 159 and the
data RAM 152, the executing unit 157 executes the instruction codes
A2 to D2 transferred from the decoder 156.
[0225] In FIG. 50, the fetch controller 155 determines whether the
bit string in the fetch buffer 1552 is a non-compressed instruction
group. In the case of this bit string, since the first 4 bits are
"1010", the first bit and the third bit of the bit string held in
the fetch buffer 1552 are determined to be compressed instructions.
The second instruction is a non-compressed instruction concatenated
to a bit string "1 F" that is subsequent to the first 4 bits. The
fourth instruction is a non-compressed instruction concatenated to
a bit string "0 NOP" that is subsequent to the first 4 bits.
[0226] The fetch controller 155 updates the program counter 1553 by
the number of transferred bits. In this case, since the transferred
bit string is 66 bits, the value of the program counter 1553
becomes "198". The fetch controller 155 transfers the updated
program counter 1553 value "198" to the upper program counter 11 of
the decoder 156. At the memory access unit 158, when the
instruction codes A1 to D1 are processed, processing (writeback)
other than the commit state processing is performed.
[0227] In FIG. 51, the fetch controller 155 performs a shift of 66
bits (the number of bits transferred to the decoder 156) toward the
head. The decoder 156, with respect to the first and the third
instructions, uses the values of the upper instruction buffer 12,
the upper BFI register 13, and the upper instruction counter 14 to
restore the original instructions A3, sC3. Further, with respect to
the second and the fourth instructions, the decoder 156 refers to
storage bits. The storage bit in the second instruction is "1" and
thus, the decoder 156 updates the values of the upper instruction
buffer 12, the upper BFI register 13, and the upper instruction
counter 14.
[0228] The storage bit in the fourth instruction is "0" and thus,
the decoder 156 does not update the values of the upper instruction
buffer 12, the upper BFI register 13, and the upper instruction
counter 14 with respect to the instruction code NOP.
[0229] The executing unit 157 transfers the instruction codes A2 to
D2 and the value of the intermediate recovery register 1542 to the
memory access unit 158. The memory access unit 158 updates the
lower recovery register 1543 to the value of the intermediate
recovery register 1542. The memory access unit 158 further accesses
the data RAM 152, according to the operation code of the
transferred instruction code.
[0230] In FIG. 52, the decoder 156 transfers the instruction codes
A3, F, C3, NOP and the value of the upper recovery register 1541 to
the executing unit 157. The decoder 156, after the transfer, in the
upper instruction counter 14, increments by 1, the first and third
instruction counter values used in the operand updating. The
executing unit 157 updates the intermediate recovery register 1542
to the values of the upper recovery register 1541. By referring to
the data register 159 and the data RAM 152, the executing unit 157
executes the instruction codes A3, F, C3, NOP transferred from the
decoder 156.
[0231] In FIG. 53, the fetch controller 155 determines whether the
bit string in the fetch buffer 1552 is a non-compressed instruction
group. In the case of this bit string, since the first 4 bits are
"1001", the first and the fourth bits of the bit string held in the
fetch buffer 1552 are determined to be compressed instructions. The
second instruction is a non-compressed instruction concatenated to
a bit string "1 B3" that is subsequent to the first 4 bits. The
third instruction is a non-compressed instruction concatenated to a
bit string "0 NOP" that is subsequent to the first 4 bits.
[0232] The fetch controller 155 updates the program counter 1553 by
the number of transferred bits. In this case, since the transferred
bit string is 66, the value of the program counter 1553 becomes
"264". The fetch controller 155 transfers the updated program
counter 1553 value "264" to the upper program counter 11 of the
decoder 156. At the memory access unit 158, when the instruction
codes A2 to D2 are processed, processing (writeback) other than the
commit state processing is performed.
[0233] In FIG. 54, the decoder 156, with respect to the first and
the fourth compressed instructions, uses the values of the upper
instruction buffer 12, the upper BFI register 13, and the upper
instruction counter 14 to restore the original instructions A4, D3.
With respect to the second and the third instructions, the decoder
156 refers to storage bits. Since the storage bit in the second
instruction is "1", the decoder 156 updates the values of the upper
instruction buffer 12, the upper BFI register 13, and the upper
instruction counter 14.
[0234] Further, since the storage bit in the third instruction is
"0", the decoder 156 does not update the values of the upper
instruction buffer 12, the upper BFI register 13, and the upper
instruction counter 14, with respect to the third instruction code
NOP.
[0235] The executing unit 157 transfers the instruction codes A3,
F, C3, NOP and the value of the intermediate recovery register 1542
to the memory access unit 158. The memory access unit 158 updates
the lower recovery register 1543 to the value of the intermediate
recovery register 1542. The memory access unit 158 accesses the
data RAM 152, according to the operation code of the transferred
instruction code.
[0236] In FIG. 55, the decoder 156 transfers the instruction codes
A3, F, C3, NOP and the value of the upper recovery register 1541 to
the executing unit 157. The decoder 156, after the transfer, in the
upper instruction counter 14, increments by 1, the first and the
fourth values corresponding to the compressed instructions. The
executing unit 157 updates the intermediate recovery register 1542
to the values of the upper recovery register 1541. By referring to
the data register 159 and the data RAM 152, the executing unit 157
executes the instruction codes A3, F, C3, NOP transferred from the
decoder 156.
[0237] Thus, by pipeline processing a sequence of compressed
instruction groups sys, the sequence of compressed instruction
groups sys can be restored by the decoder 156. Accordingly, the
processor 102 can execute in parallel, a group of instructions that
are the same as the sequence of instruction groups before
compression. Further, since the sequence of compressed instruction
groups sys includes compressed instructions, the number of fetches
from the instruction RAM 151 can be reduced. In other words, the
number of memory accesses to the instruction RAM 151 can be
reduced, thereby enabling reduced power consumption to be
facilitated.
[0238] Recovery processing from an interrupt occurring during the
instruction execution depicted in FIGS. 43 to 55 will be described.
When an interrupt occurs, the processor 102 completes commit state
transition processing (writeback, . . . ) and then performs
interrupt processing. In this case, concerning the commit pre-stage
processing, the processor 102 temporarily saves the value of the
lower recovery register 1543 and executes the interrupt processing.
When the interrupt processing ends, the processor 102 uses the
saved value of the lower recovery register 1543 and resumes the
commit pre-stage processing. Hereinafter, a case where an interrupt
occurs during the processing depicted in FIG. 55 will be described
with reference to FIGS. 56 to 64.
[0239] FIGS. 56 to 64 are diagrams of an example of recovery
processing for recovery from an interrupt. The processor 102, via
the interrupt controller 1510, detects the occurrence of an
interrupt by a surrounding module or timer and upon doing so,
issues via the controller 153, an interrupt signal to the fetch
controller 155, the decoder 156, the executing unit 157, and the
memory access unit 158.
[0240] In FIG. 56, the memory access unit 158, upon receiving the
interrupt signal, saves the values of the lower recovery register
1543 or the value of a generic register (not depicted) to the stack
area 1520 of the data RAM 152.
[0241] In FIG. 57, the fetch controller 155, upon receiving the
interrupt signal, clears the prefetch buffer 1551 and the fetch
buffer 1552, and prepares for interrupt processing. Similarly, the
decoder 156, the executing unit 157, and the memory access unit
158, upon receiving the interrupt signal, respectively clear the
values of the upper recovery register 1541, the intermediate
recovery register 1542, and the lower recovery register 1543, and
prepare for interrupt processing. The processor 102 executes the
interrupt processing.
[0242] In FIG. 58, the decoder 156, upon receiving the interrupt
completion signal through the interrupt controller 1510 and the
controller 153, sets the lower instruction buffer 32 values
(instruction codes A1, F, C1, D1) saved in the stack area 1520, the
lower BFI register 33 values (operand patterns A1-BFI, F-BFI,
C1-BFI, D1-BFI), and the lower instruction counter 34 values "2, 1,
2, 2" to the value of the upper instruction buffer 12, the value of
the upper BFI register 13, and the value of the upper instruction
counter 14. The fetch controller 155 again clears the prefetch
buffer 1551 and the fetch buffer 1152, and reads in the lower
program counter value "198" saved in the stack area 1520.
[0243] In FIG. 59, the fetch controller 155 divides the lower
program counter 31 value "198" read from the stack area 1520, by
the bit width (128 bits) of the fetch buffer. In this case, the
quotient is "1" with a remainder of "70". The fetch controller 155
multiplies the quotient "1" by the bit width (128 bits) of the
fetch buffer and thereby, identifies the bit position to be
fetched. In this case, since the quotient "1".times.128 bits=128,
the bit string from the 128th bit from the head of the sequence of
compressed instruction groups, i.e., the bit string of address
0xFF10 of the instruction RAM 151, is prefetched and held in the
prefetch buffer 1551. The fetch controller 155 sets the program
counter 1553 to "128".
[0244] In FIG. 60, the fetch controller 155 fetches and holds in
the fetch buffer 1552, the bit string in the prefetch buffer 1551.
The fetch controller 155 determines whether the bit string in the
fetch buffer 1552 is a non-compressed instruction group. In the
case of this bit string, since the first 4 bits are "1111", the
first 4 bits are determined to be compressed instruction groups. In
this case, the fetch controller 155 transfers the first 4 bits
(=1111) in the fetch buffer 1552 to the decoder 156.
[0245] The fetch controller 155 updates the program counter 1553 by
the number of bits transferred. In this case, since the transferred
bit string is 4 bits, the value of the program counter 1553 becomes
"132". In this case, since this value and the lower program counter
31 value "198" saved in the stack area 1520 do not coincide, the
fetch controller 155 does not transfer the updated program counter
value "132" to the upper program counter 11 of the decoder 156.
[0246] The decoder 156, despite having received the compressed
instruction groups from the fetch buffer 1552, discards the
compressed instruction groups since the value of the program
counter 1553 is not received. Thus, until the value of the program
counter 1553 of the fetch controller 155 and the lower program
counter 31 value read from the stack area 1520 coincide, the
decoder 156 discards the bit strings from the fetch buffer 1552. As
a result, at an errant bit position, the instruction is not
restored.
[0247] In FIG. 62, since 4 bits were transferred at the processing
depicted in FIG. 61, the fetch controller 155 fetches the first 4
bits of the prefetch buffer 1551. Subsequently, the fetch
controller 155 determines whether the bit string in the fetch
buffer 1552 is a non-compressed instruction. In the case of this
bit string, since the first and the third bits are "1", the first
and the third bits of the fetched bit string are determined to be
compressed instructions.
[0248] In FIG. 63, the fetch controller 155 transfers the first 66
bits in the fetch buffer 1552 to the decoder 156. The fetch
controller 155 updates the program counter 1553 by the number of
bits transferred. In this case, since the transferred bit string is
66 bits, the value of the program counter 1553 becomes "198". In
this case, since this value and the lower program counter 31 value
"198" saved in the stack area 1520 coincide, the fetch controller
155 transfers the updated program counter value "198" to the upper
program counter 11 of the decoder 156.
[0249] In FIG. 64, the decoder 156, having received the bit string
from the fetch buffer 1552 and the program counter 1553 value
"198", restores the instructions from the values of the upper
recovery register 1541. Thus, the instruction codes A3, C3 that
were processed up to the memory access unit 158 at the time of the
interrupt are restored. The processing hereinafter is executed
similarly to that depicted in FIGS. 51 to 55. Thus, at the proper
recovery position, the instruction can be restored.
[0250] In this manner, according to the second embodiment, since an
instruction sequence/a sequence of instruction groups that include
compressed instructions can be restored while being executed, the
number of fetches from the instruction RAM 151 can be reduced. The
number of fetches from the instruction RAM 151 becomes shorter than
the original instruction sequence/sequence of instruction groups,
the higher the instruction compression efficiency, i.e., the
greater the number of compressed instructions is. For example, in
the case of the third embodiment, since a maximum of 32 compressed
instructions can be acquired by 1 fetching and consequently,
32.times.32 non-compressed instructions (1024 bits) are fetched by
1 memory access.
[0251] Further, in the case of the fourth embodiment, since a
maximum of 32 compressed instruction groups can be acquired by 1
fetching, 32.times.32 non-compressed instruction groups (1024 bits)
are fetched by 1 memory access. Therefore, since the number of
accesses to the instruction RAM 151 decreases, reduced power
consumption is enabled.
[0252] Further, when transitioning to the subsequent stage at each
stage of commit pre-stage, the processor 102 also passes, by
pipeline processing, the recovery register values to the subsequent
stage. Consequently, even if an interrupt occurs during execution,
by saving the value of the recovery register at the memory access
of the last stage of commit pre-stage, recovery can be performed
using the saved recovery register value, after the completion of
the interrupt. Thus, even if an instruction sequence/a sequence of
instruction groups that are to be executed are also compressed, by
indicating the instruction that is before transition to the commit
state and re-executing from an instruction fetch, the state before
the interrupt can be recovered.
[0253] Further, according to second embodiment, when a compressed
instruction is restored, since restoration is performed within the
processor 102 and without access to an external memory such as a
dictionary memory, excessive memory accesses become unnecessary and
there is no increase in the number of memory accesses. Therefore,
reduced power consumption can be facilitated. Further, when the
same operation code occurs successively, since coding in which
register numbers and/or memory addresses (which are operands)
consecutively numbered is used, when a programmer creates
instruction code, by varying the operands in a consistent manner
when the same operation code occurs successively, reduced power
consumption at the time of instruction compression and execution
can be facilitated.
[0254] In the second embodiment, although the restoration of
instruction code was described to be performed at a register read
stage by the decoder 156, the restoration at register read may be
performed at a fetch stage. In this case, the upper recovery
register 154 and the operand updater 1600 are included in the fetch
controller 155; and the data holding and reading performed with
respect to the upper recovery register 154 at the register read
stage in the operand updating processing by the operand updater
1600 is executed by the fetch controller 155. Further, in this
case, the decoder 156 performs typical decoder processing and
reading from data registers.
[0255] As described, the processor 102 according to the embodiments
reduces the number of memory accesses by collectively fetching a
sequence of compressed instructions in a memory. Further, the
compression apparatus, the compression method, and the computer
product improve the efficiency at which an instruction code group
is compressed consequent to a reduction in the number of memory
accesses by the processor 102.
[0256] The compression method described in the present embodiment
may be implemented by executing a prepared program on a computer
such as a personal computer and a workstation. The program is
stored on a computer-readable medium such as a hard disk, a
flexible disk, a CD-ROM, an MO, and a DVD, read out from the
recording medium, and executed by the computer. The program may be
distributed through a network such as the Internet. However, the
computer-readable medium does not include a transitory medium such
as a propagation signal.
[0257] All examples and conditional language recited herein are
intended for pedagogical purposes to aid the reader in
understanding the invention and the concepts contributed by the
inventor to furthering the art, and are to be construed as being
without limitation to such specifically recited examples and
conditions, nor does the organization of such examples in the
specification relate to a showing of the superiority and
inferiority of the invention. Although the embodiments of the
present invention have been described in detail, it should be
understood that the various changes, substitutions, and alterations
could be made hereto without departing from the spirit and scope of
the invention.
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