U.S. patent application number 15/234213 was filed with the patent office on 2017-06-15 for cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Markus Brink, Josephine B. Chang, Michael A. Guillorn, Hsinuyu Tsai.
Application Number | 20170170272 15/234213 |
Document ID | / |
Family ID | 57046564 |
Filed Date | 2017-06-15 |
United States Patent
Application |
20170170272 |
Kind Code |
A1 |
Brink; Markus ; et
al. |
June 15, 2017 |
COINTEGRATION OF DIRECTED SELF ASSEMBLY AND SIDEWALL IMAGE TRANSFER
PATTERNING FOR SUBLITHOGRAPHIC PATTERNING WITH IMPROVED DESIGN
FLEXIBILITY
Abstract
After forming transfer layer portions over a portion of a
dielectric cap layer overlying a first portion of a substrate by a
directed self-assembly process, a hard mask layer is formed over
the dielectric cap layer to fill spaces between the transfer layer
portions. Spacers are then formed over a portion of the hard mask
layer overlying a second portion of the substrate by a sidewall
image transfer process. A top semiconductor layer of the substrate
is subsequently patterned using the transfer layer portions and the
spacers as an etch mask to provide densely packed semiconductor
fins in the first region and semi-isolated semiconductor fins in
the second region of the substrate.
Inventors: |
Brink; Markus; (White
Plains, NY) ; Chang; Josephine B.; (Bedford Hills,
NY) ; Guillorn; Michael A.; (Cold Springs, NY)
; Tsai; Hsinuyu; (White Plains, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
57046564 |
Appl. No.: |
15/234213 |
Filed: |
August 11, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14963824 |
Dec 9, 2015 |
9466534 |
|
|
15234213 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/3086 20130101;
H01L 29/7851 20130101; H01L 29/161 20130101; H01L 27/1104 20130101;
H01L 29/1608 20130101; H01L 21/3085 20130101; H01L 29/16 20130101;
H01L 27/1116 20130101; H01L 29/20 20130101; H01L 29/66795 20130101;
H01L 21/823431 20130101; H01L 21/845 20130101; H01L 27/0886
20130101; H01L 29/0692 20130101; H01L 27/1211 20130101; H01L
21/0271 20130101 |
International
Class: |
H01L 29/06 20060101
H01L029/06; H01L 29/78 20060101 H01L029/78; H01L 27/12 20060101
H01L027/12; H01L 29/161 20060101 H01L029/161; H01L 29/20 20060101
H01L029/20; H01L 21/027 20060101 H01L021/027; H01L 27/11 20060101
H01L027/11; H01L 29/16 20060101 H01L029/16 |
Claims
1. A semiconductor structure comprising: a plurality of first
semiconductor fins located in a first region of a substrate and
having a first pitch; and a plurality of second semiconductor fins
located in a second region of the substrate and having a second
pitch that is equal to a non-integer multiple of the first
pitch.
2. The semiconductor structure of claim 1, wherein the second pitch
is 1.5 times the first pitch.
3. The semiconductor structure of claim 1, wherein each of the
plurality of first semiconductor fins has a width less than 50
nm.
4. The semiconductor structure of claim 1, wherein each of the
plurality of second semiconductor fins has a width ranging from 5
nm to 10 nm.
5. The semiconductor structure of claim 1, wherein the first region
is a logic device region and the second region is a static random
access memory (SRAM) device region.
6. The semiconductor structure of claim 1, wherein the first pitch
is equal to a natural pitch of a directed self-assembly (DSA)
material being used.
7. The semiconductor structure of claim 1, wherein a spacing
between adjacent first semiconductor fins in the plurality of first
semiconductor fins is determined by a domain size of the DSA
material being used.
8. The semiconductor structure of claim 7, wherein the spacing
between adjacent first semiconductor fins in the plurality of first
semiconductor fins is less than 50 nm.
9. The semiconductor structure of claim 7, wherein the DSA material
comprises a diblock copolymer, a triblock copolymer, a blend of
homopolymers, a blend of copolymers, and a combination thereof.
10. The semiconductor structure of claim 9, wherein the DSA
material comprises poly(styrene-block-methyl methacrylate)
(PS-b-PMMA), poly(ethylene oxide-block-isoprene) (PEO-b-PI),
poly(ethylene oxide-block-butadiene) (PEO-b-PBD), poly(ethylene
oxide-block-styrene) (PEO-b-PS), poly(ethylene
oxide-block-methylmethacrylate) (PEO-b-PMMA),
poly(ethyleneoxide-block-ethylethylene) (PEO-b-PEE),
poly(styrene-block-vinylpyridine) (PS-b-PVP),
poly(styrene-block-isoprene) (PS-b-PI),
poly(styrene-block-butadiene) (PS-b-PBD),
poly(styrene-block-ferrocenyldimethylsilane) (PS-b-PFS),
poly(butadiene-block-vinylpyridine) (PBD-b-PVP),
poly(isoprene-block-methyl methacrylate) (PI-b-PMMA),
poly(styrene-block-lactic acid) (PS-b-PLA) or
poly(styrene-block-dymethylsiloxane) (PS-b-PDMS).
11. The semiconductor structure of claim 1, wherein a spacing
between adjacent second semiconductor fins in the plurality of
second semiconductor fins is defined by a minimum pitch of an
associated lithographic process.
12. The semiconductor structure of claim 1, wherein each of the
plurality of first semiconductor fins and the plurality of second
semiconductor fins comprises Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs
or InP.
13. The semiconductor structure of claim 1, wherein the substrate
comprises a handle substrate and an insulator layer overlying the
handle substrate, wherein the plurality of first semiconductor fins
and the plurality of second semiconductor fins are in contact with
a top surface of the insulator layer.
14. The semiconductor structure of claim 11, wherein the insulator
layer comprises silicon oxide, silicon nitride, silicon oxynitride,
boron nitride or a combination thereof.
15. The semiconductor structure of claim 1, wherein each of the
plurality of first semiconductor fins and the plurality of second
semiconductor fins has a height ranging from 10 nm to 200 nm.
Description
BACKGROUND
[0001] The present application relates to a pattern formation
method, and more particularly to integration of densely packed
semiconductor fins formed by a directed self-assembly (DSA) process
and semi-isolated semiconductor fins formed by a sidewall image
transfer (SIT) process on a single substrate.
[0002] Directed self-assembly (DSA) is a patterning technique that
generates sub-lithographic line/space patterns through microphase
separation of a block copolymer. The DSA process has shown promise
in creating large areas of patterned lines with a minimum pitch
equal to a natural period (i.e., pitch) of the block copolymer, and
thus is suitable for making dense fin field effect transistors
(FinFETs) in a logic area of an integrated circuit. However, the
DSA process does not allow for forming patterned lines with a
minimum pitch that is 1.5.times. the natural pitch of the block
copolymer; since defects will occur within the DSA pattern. Since
the pitch of patterned features determines the size of static
random access memory (SRAM) cells and the minimum pitch in a SRAM
area of the integrated circuit that is equal to 1.5.times. the
natural pitch of the DSA material is desired to achieve high SRAM
cell density, methods of forming nanoscale features with desirable
pitches for both logic and SRAM devices remain needed.
SUMMARY
[0003] The present application provides methods of integration of
densely packed semiconductor fins formed using a directed
self-assembly (DSA) process and semi-isolated semiconductor fins
formed using a sidewall image transfer (SIT) process on a single
substrate. After forming transfer layer portions over a portion of
a dielectric cap layer overlying a first portion of a substrate by
a directed self-assembly process, a hard mask layer is formed over
the dielectric cap layer to fill spaces between the transfer layer
portions. Spacers are then formed over a portion of the hard mask
layer overlying a second portion of the substrate by a sidewall
image transfer process. A top semiconductor layer of the substrate
is subsequently patterned using the transfer layer portions and the
spacers as an etch mask to provide densely packed semiconductor
fins in the first region and semi-isolated semiconductor fins in
the second region of the substrate.
[0004] In one aspect of the present application, a method of
forming a semiconductor structure is provided. The method includes
forming a self-assembled structure comprising alternating first
domains and second domains over a material stack that is located
over a top semiconductor layer of a substrate, wherein the material
stack includes a transfer layer and a process layer overlying the
transfer layer, and the self-assembled structure overlies a first
region of the top semiconductor layer. The second domains of the
self-assembled structure are then removed, leaving the first
domains protruding from a top surface of the process layer. After
patterning the process layer and the transfer layer using the first
domains as an etch mask to provide transfer layer portions over the
top semiconductor layer, the remaining portions of the process
layer are removed, leaving the transfer layer portions protruding
from a top surface of the top semiconductor layer. Next, a hard
mask layer is formed over the transfer layer portions and the top
semiconductor layer to fill spaces between the transfer layer
portions. Next, spacers are formed on sidewalls of a plurality of
mandrels located over the hard mask layer. The plurality of
mandrels overlies a second region of the top semiconductor layer.
The plurality of mandrels are then removed, leaving the spacers
protruding from a top surface of the hard mask layer. After
patterning the hard mask layer using the spacers as an etch mask to
provide hard mask layer portions, the top semiconductor layer is
patterned using the transfer layer portions and the hard mask layer
portions as an etch mask to provide a plurality of semiconductor
fins.
[0005] In another aspect of the present application, a
semiconductor structure is provided. The semiconductor structure
includes a plurality of first semiconductor fins located in a first
region of a substrate and having a first pitch and a plurality of
second semiconductor fins located in a second region of the
substrate and having a second pitch that is equal to a non-integer
multiple of the first pitch.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0006] FIG. 1 is a cross-sectional view of an exemplary
semiconductor structure after forming template structures over a
material stack including, from bottom to top, a dielectric cap
layer, a transfer layer, an organic planarization layer (OPL) and a
process layer that is located over a substrate according to an
embodiment of the present application.
[0007] FIG. 2 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 1 after forming a self-assembled
structure of alternating first domains and second domains over the
process layer.
[0008] FIG. 3 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 2 after removing the second domains
to provide a DSA pattern comprising the second domains protruding
from a top surface of the process layer.
[0009] FIG. 4 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 3 after transfer the DSA pattern
through the process layer, the OPL and the transfer layer to
provide transfer layer portions.
[0010] FIG. 5 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 4 after forming a hard mask layer
over the dielectric cap layer to fill the spaces between the
transfer layer portions and forming a mandrel material layer over
the hard mask layer.
[0011] FIG. 6 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 5 after patterning the mandrel
material layer to form mandrels.
[0012] FIG. 7 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 6 after forming spacers along
sidewalls of the mandrels.
[0013] FIG. 8 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 7 after removing the mandrels.
[0014] FIG. 9 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 8 after patterning the hard mask
layer using the spacers as an etch mask to provide hard mask layer
portions.
[0015] FIG. 10 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 8 after patterning the dielectric
cap layer using the transfer layer portions and vertical stacks of
the hard mask layer portions and the spacers as an etch mask.
[0016] FIG. 11 is a cross-sectional view of the exemplary
semiconductor structure of FIG. 8 after patterning a top
semiconductor layer in the substrate using the transfer layer
portions and the hard mask layer portions as an etch mask.
DETAILED DESCRIPTION
[0017] The present application will now be described in greater
detail by referring to the following discussion and drawings that
accompany the present application. It is noted that the drawings of
the present application are provided for illustrative purposes only
and, as such, the drawings are not drawn to scale. It is also noted
that like and corresponding elements are referred to by like
reference numerals.
[0018] In the following description, numerous specific details are
set forth, such as particular structures, components, materials,
dimensions, processing steps and techniques, in order to provide an
understanding of the various embodiments of the present
application. However, it will be appreciated by one of ordinary
skill in the art that the various embodiments of the present
application may be practiced without these specific details. In
other instances, well-known structures or processing steps have not
been described in detail in order to avoid obscuring the present
application.
[0019] Referring to FIG. 1, an exemplary semiconductor structure
according to an embodiment of the present application includes
template structures 40 formed over a material stack. The material
stack is formed on a substrate 8 and it includes, from bottom to
top, a dielectric cap layer 32L, a transfer layer 34L, an organic
planarization layer (OPL) 36L, and a process layer 38L. The
template structures 40 are formed in a first region of the
substrate 8 which can be a logic device region.
[0020] The substrate 8 may be formed from a bulk semiconductor
substrate or a semiconductor-on-insulator substrate (SOI) known in
the art. In one embodiment and as shown in FIG. 1, the substrate 8
can be an SOI substrate including a stack, from bottom to top, a
handle substrate 10, a buried insulator layer 12 and a top
semiconductor layer 20L.
[0021] The handle substrate 10 may include a semiconductor material
such as, for example, Si, Ge, SiGe, SiC or SiGeC and an III-V
compound semiconductor such as, for example, InAs, GaAs or InP. The
handle substrate 10 provides mechanical support to the buried
insulator layer 12 and the top semiconductor layer 20L. The
thickness of the handle substrate 10 can be from 30 m to about 2
mm, although less and greater thicknesses can also be employed.
[0022] The buried insulator layer 12 may include a dielectric
material such as silicon oxide, silicon nitride, silicon
oxynitride, boron nitride or a combination thereof. In one
embodiment, the buried insulator layer 12 may be formed by a
deposition process, such as chemical vapor deposition (CVD) or
physically vapor deposition (PVD). In another embodiment, the
buried insulator layer 12 may be formed using a thermal growth
process, such as thermal oxidation, to convert a topmost portion of
the handle substrate 10. The thickness of the buried insulator
layer 12 can be from 50 nm to 200 nm, although lesser or greater
thicknesses can also be employed.
[0023] The top semiconductor layer 20L may include a semiconductor
material such as, for example, Si, Ge, SiGe, SiC or SiGeC, and an
III-V compound semiconductor such as, for example, InAs, GaAs or
InP. The semiconductor materials of the top semiconductor layer 20L
and the handle substrate 10 may be the same or different.
Typically, each of the handle substrate 10 and the top
semiconductor layer 20L comprises a single crystalline
semiconductor material, such as, for example, single crystalline
silicon.
[0024] The top semiconductor layer 20L can be formed by a
deposition process, such as CVD or plasma enhanced chemical vapor
deposition (PECVD). The top semiconductor layer 20L that is formed
may have a thickness from 10 nm to 200 nm, although lesser or
greater thicknesses can also be employed. Alternatively, the top
semiconductor layer 20L may be formed using a Smart Cut.RTM.
process where two semiconductor wafers are bonded together with an
insulator in between.
[0025] The dielectric cap layer 32L may include a dielectric
material such as silicon dioxide, silicon nitride, or silicon
oxynitride. The dielectric cap layer 32L can be formed utilizing a
conventional deposition process such as, for example, CVD or PECVD.
Alternatively, the dielectric cap layer 32L can be formed by a
thermal process such as, for example, oxidation or nitridation of a
topmost portion of the top semiconductor layer 20L. Any combination
of the above mentioned processes can also be used in forming the
dielectric cap layer 32L. The dielectric cap layer 32L that is
formed can have a thickness from 20 nm to 80 nm, although lesser or
greater thicknesses can also be employed.
[0026] The transfer layer 34L may include a high dielectric
constant (high-k) material having a dielectric constant that is
greater than 7.5. In one embodiment, the transfer layer 34L
includes a dielectric metal oxide such as, for example, HfO.sub.2,
ZrO.sub.2, La.sub.2O.sub.3, Al.sub.2O.sub.3, TiO.sub.2,
SrTiO.sub.3, LaAlO.sub.3, Y.sub.2O.sub.3, HfO.sub.xN.sub.y,
ZrO.sub.xN.sub.y, La.sub.2O.sub.xN.sub.y, Al.sub.2O.sub.xN.sub.y,
TiO.sub.xN.sub.y, SrTiO.sub.xN.sub.y, LaAlO.sub.xN.sub.y,
Y.sub.2O.sub.xN.sub.y, SiON, SiN.sub.x, a silicate thereof, and an
alloy thereof. Each value of x is independently from 0.5 to 3 and
each value of y is independently from 0 to 2. The transfer layer
34L can be formed, for example, by CVD, atomic layer deposition
(ALD) or PECVD. The thickness of the transfer layer 34L can be from
10 nm to 300 nm, although lesser and greater thicknesses can also
be formed.
[0027] The OPL 36L may include a self-planarizing organic material
that can provide a smooth and planar top surface when applied. In
one embodiment, the OPL 36L includes a carbon-rich material. The
term "carbon-rich" refers to a material having a composition
comprising greater than 50% by weight carbon, preferably greater
than 70% by weight carbon, and more preferably from 75% to 80% by
weight carbon, based upon the total solids in the carbon-rich
composition taken as 100% by weight. Exemplary carbon-rich
materials include, but are not limited to, spin-on carbon (SOC) and
amorphous carbon. The OPL 36L can be formed by CVD or spin coating.
The thickness of the OPL 20 can be from 10 nm to 300 nm, although
lesser and greater thicknesses can also be employed.
[0028] The process layer 38L represents one or more layers to be
patterned, and may include one or more layers that have desirable
interactions with a DSA material subsequently applied thereon. The
DSA material can thus be induced to orient with phase boundaries
perpendicular to the top surface of the process layer 38L. For
example, the process layer 38L may include a neutral layer that is
substantial neutral toward the different component in the DSA
material. That is, the material in the neural layer does not show a
strong affinity for one of the chemical components over the other
chemical component in the DSA material, thus facilitating the
formation of domains that are oriented perpendicularly to the top
surface of the neutral layer. Alternatively, the process layer 38L
may include a chemical guide layer containing pinning regions that
have a high affinity for one of the components of the DSA material.
The pining regions thus preferably bind to one of the components in
the DSA material so as to induce the DSA material to orient with
phase boundaries that are perpendicular to the top surface of the
process layer 38L. The process layer 38L may also include layers
having antireflective properties to facilitate lithography
patterning process in formation of the template structures 40. In
one embodiment, the process layer 38L may include a layer
containing a silicon-containing antireflective coating (SiARC)
material or a titanium-containing antireflective coating (TiARC)
material as known in the art.
[0029] The template structures 40 may be used in conjunction with
the process layer 38L to guide the phase separation and alignment
of the DSA material. In one embodiment, the template structures 40
can be formed by applying a photoresist layer over the top surface
of the process layer 38L and patterning the photoresist layer to
expose a region of the process layer 38L in which a dense pattern
is formed. The width of the space between template structures 40 is
a function of an integer multiple of the natural period of the DSA
material to avoid introducing defects within the DSA pattern.
Further, the template structures 40 can be treated by known methods
to adjust the wetting properties with respect to the DSA material.
For example, the surfaces of the template structures 40 can be
treated by depositing or grafting a suitable material that affects
surface hydrophilicity of the template structures 40.
[0030] Referring to FIG. 2, a DSA material layer (not shown) is
formed by depositing a DSA material onto the exposed portion of the
process layer 38 and between template structures 40. The DSA
material layer is then annealed, thereby forming a self-assembled
structure including a vertically oriented lamellar pattern of
alternating first domains 50 and second domains 55 protruding from
the top surface of the process layer 38L. As used herein, the term
"lamellar pattern" refers a phase domain pattern having first
chemical component and second chemical component that are arranged
alternately and parallel with respect to one another. Exemplary DSA
materials include, but are not limited to, diblock copolymers,
triblock copolymers, blends of homopolymers, blends of copolymers,
and combinations thereof. The DSA material typically includes
immiscible chemical components that have controlled sizes. Under
suitable conditions, the immiscible chemical components
self-organize into a nanoscale periodic pattern. By "nanoscale
pattern" it is meant that features have a size of less than 50 nm.
In one embodiment, the DSA material layer includes a diblock
copolymer such as, for example, poly(styrene-block-methyl
methacrylate) (PS-b-PMMA), poly(ethylene oxide-block-isoprene)
(PEO-b-PI), poly(ethylene oxide-block-butadiene) (PEO-b-PBD),
poly(ethylene oxide-block-styrene) (PEO-b-PS), poly(ethylene
oxide-block-methylmethacrylate) (PEO-b-PMMA),
poly(ethyleneoxide-block-ethylethylene) (PEO-b-PEE),
poly(styrene-block-vinylpyridine) (PS-b-PVP),
poly(styrene-block-isoprene) (PS-b-PI),
poly(styrene-block-butadiene) (PS-b-PBD),
poly(styrene-block-ferrocenyldimethylsilane) (PS-b-PFS),
poly(butadiene-block-vinylpyridine) (PBD-b-PVP),
poly(isoprene-block-methyl methacrylate) (PI-b-PMMA),
poly(styrene-block-lactic acid) (PS-b-PLA) or
poly(styrene-block-dymethylsiloxane) (PS-b-PDMS). In one
embodiment, PS-b-PMMA is used.
[0031] To form the nanoscale periodic pattern, the DSA material is
first dissolved in a suitable solvent to form a DSA material
solution, which is then applied onto the process layer 38L and
between template structures 40 to provide the DSA material layer.
The solvent system used for dissolving the DSA material and forming
the DSA material solution may comprise any suitable solvent
including, but not limited to, toluene, propylene glycol monomethyl
ether acetate (PGMEA), propylene glycol monomethyl ether (PGME) and
acetone. The DSA material solution can be applied by any suitable
techniques including, but not limited to, spin coating, spraying
and dip coating.
[0032] The microphase separation of the different chemical
components contained in the DSA material can be achieved, for
example, by annealing the DSA material layer at an elevated
temperature. In one embodiment, the DSA material layer can be
annealed by solvent vapor annealing or by thermal annealing at an
elevated temperature to form the first domains 50 composed of a
first chemical component of the DSA material, and the second
domains 55 composed a second chemical component of the DSA
material. The anneal may be performed, for example, at a
temperature from about 180.degree. C. to about 300.degree. C. for a
duration from 30 seconds to about 10 hours.
[0033] Each of the first domains 50 has a first width. Each of the
second domains 55 has a second width. In some embodiments, the
second width is the same as the first width. In other embodiments,
the second width is different from the first width. Each of the
first width and second widths are sub-lithographic, i.e., less than
50 nm.
[0034] Referring to FIG. 3, one type of domain is removed selective
to the other type of domain. In one embodiment and as shown in FIG.
3, the second domains 55 can be removed selective to first domains
50. In this case, the second chemical component of the DSA material
is removed selective to the first chemical component. The removal
of the second domains 55 selective to the first domains 50 can be
performed, for example, by an anisotropic etch. For example, when
the DSA material is a diblock copolymer of PS and PMMA (PS-b-PMMA),
the PMMA component can be selectively removed by a dry etch using
oxygen and/or argon and/or fluorocarbon gas chemistry, for example.
A DSA pattern including the first domains 50 is formed over the
dense pattern region of the process layer 38L. The first domains 50
constitute a set of protruding structures that protrudes above the
top surface of the process layer 38L. After removal of the second
domains 55, the template structures 40 may be removed utilizing
solvent stripper or plasma etching.
[0035] Referring to FIG. 4, the DSA pattern is transferred through
the process layer 38L, the OPL 36L and the transfer layer 34L. An
anisotropic etch can be performed to remove the materials of the
process layer 38L, the OPL 36L and the transfer layer 34L selective
to the material of the dielectric cap layer 32L. The anisotropic
etch can be a dry etch such as reactive ion etching (RIE) or a wet
etch. The remaining portions of the transfer layer 34L constitute
the transfer layer portions 34. The transfer layer portions 34 have
a uniform width, which is the same as the width of the first
domains 50, up to some small process bias due to the etch. The
pitch of the transfer layer portions 34 is characterized by the
natural pitch L.sub.0 of the DSA material which is equal to a total
width of two adjacent first and second domains 50, 55 as shown in
FIG. 3.
[0036] The DSA pattern of the first domains 50 are subsequently
removed, for example, by dissolving in a solvent. The remaining
portions of the process layer 38L and the OPL layer 36L can also be
removed, for example, by a wet etch.
[0037] Referring to FIG. 5, a hard mask layer 60L is formed over
the dielectric cap layer 32L to fill the spaces between the
transfer layer portions 34. The hard mask layer 60L may include any
material that can be etched selective to the materials of the
transfer layer 34L and the dielectric cap layer 32L. In one
embodiment and when the dielectric cap layer 32L is composed of a
dielectric oxide and the transfer layer 34 is composed of a
dielectric metal oxide, the hard mask layer 60L can include a
dielectric nitride such as silicon nitride. The hard mask layer 60L
can be formed by CVD, PVD or spin coating. The hard mask layer 60L
may be self-planarizing, or the top surface of the hard mask layer
60L can be planarized, for example, by chemical mechanical
planarization (CMP). The planarized top surface of the hard mask
layer 60L thus formed is located above the top surfaces of the
transfer layer portions 34.
[0038] A mandrel material layer 70L is subsequently formed over the
hard mask layer 60L. The mandrel material layer 70L includes a
material that can be removed selective to the materials of the hard
mask layer 60L and sidewall spacers to be subsequently formed. In
one embodiment, the mandrel material layer 70L may be composed of
amorphous silicon, polysilicon, amorphous or polycrystalline
germanium, an amorphous or polycrystalline silicon-germanium alloy
material, amorphous carbon, diamond-like carbon or organosilicate
glass. In some embodiments, the mandrel material layer 70L may also
be composed of a metal, such as, for example, Al, W or Cu. The
mandrel material layer 70L can be formed, for example, by CVD or
PECVD. The thickness of the mandrel material layer 70L can be from
30 nm to 300 nm, although lesser and greater thicknesses can also
be employed.
[0039] Referring to FIG. 6, the mandrel material layer 70L is
patterned to form mandrels 70. The patterning of the mandrel
material layer 70L can be performed, for example, by applying a
photoresist layer (not shown) over the mandrel material layer 70L,
lithographically patterning the photoresist layer to define a set
of areas covered by the patterned photoresist layer, and
transferring the pattern in the photoresist layer into the mandrel
material layer 70L by an anisotropic etch. The anisotropic etch can
be a dry etch such as, for example, RIE or a wet etch selective to
the dielectric material of the hard mask layer 60L. The remaining
portions of the mandrel material layer constitute the mandrels 70.
The mandrels 70 are formed in a second region of the substrate 8
which can be a SRAM device region.
[0040] In one embodiment, each of the mandrels 70 that is formed
may have a rectangular shape in cross-section. The mandrels 70 can
be formed with uniform width and spacing or variable width and
spacing depending on the circuit design. In one embodiment and as
shown in FIG. 6, the mandrels 70 have uniform width and spacing.
The width and spacing of the mandrels 70 are set such that the
spacers later formed on sidewalls of the mandrels 70 can have a
pitch that is a non-integer multiple of the natural pitch L.sub.0
of the DSA material. In one embodiment, the mandrels 70 are formed
according to a minimum pitch available to the lithographic
fabrication process being used. In one embodiment and when the
minimum pitch is 80 nm, the mandrels 70 are formed having a width
of 30 nm with a spacing of 50 nm.
[0041] Referring to FIG. 7, spacers 80 are formed along the
sidewalls of the mandrels 70. The spacers 80 may be composed of a
dielectric material that has an etch selectivity that differs with
respect to the materials of the hard mask layer 60L and the
mandrels 70. In one embodiment of the present application, the
spacers 80 may include a dielectric oxide such as silicon
oxide.
[0042] The spacers 80 can be formed by depositing a spacer material
layer (not shown) over exposed surfaces of the mandrels 70 and the
hard mask layer 60L by a conformal deposition process, such as, for
example, CVD, PECVD or ALD. The spacer material layer that is
formed may have a thickness from 5 nm to 15 nm, although lesser and
greater thicknesses can also be employed. Following the conformal
deposition, an anisotropic etch such as, for example, RIE is
performed to completely remove the spacer material deposited on the
horizontal surfaces of the hard mask layer 32L and the mandrels 70,
while the spacer material deposited on vertical sidewalls of the
mandrels 70 is retained. The remaining portions of the spacer
material layer constitute the spacers 80.
[0043] The width of each of the spacers 80, as measured at its
base, can be from 5 nm to 10 nm, although lesser and greater widths
can also be employed. After removal of the horizontal portions of
the spacer material layer, top surfaces of the mandrels 70 are
exposed
[0044] Referring to FIG. 8, a mandrel pull process is performed to
remove the mandrels 70 from the structure, leaving the spacers 80
standing free on the hard mask layer 60L. Any wet or dry etch
process capable of etching the material of the mandrels 70
selective to the materials of the spacers 80 and the hard mask
layer 60L can be used. For example, if the mandrels 70 include a
semiconductor material, the mandrels 70 can be removed utilizing an
oxygen-based plasma etching technique that removes the
semiconductor material while not removing the dielectric material
of the spacers 80. In one embodiment, the spacers 80 are formed
with a uniform pitch which can be a non-integer multiple of the
natural pitch L.sub.0 of the DSA pattern.
[0045] Referring to FIG. 9, the hard mask layer 60L is etched by an
anisotropic etch employing the spacers 80 as an etch mask. The
anisotropic etch removes physically exposed portions of the hard
mask layer 60L to provide hard mask layer portions 60 which are
remaining portions of the hard mask layer 60L after the anisotropic
etch. The removal of the exposed portions of the hard mask layer
60L also reveals the transfer layer portions 34.
[0046] Referring to FIG. 10, the dielectric cap layer 32L is etched
by an anisotropic etch employing the transfer layer portions 34 and
stacks of the hard mask layer portions 60 and the spacers 80 as an
etch mask layer. The anisotropic etch can be a dry etch such as RIE
or a wet etch that removes the dielectric material of the
dielectric cap layer 32L selective to the materials of the transfer
layer portions 34, the hard mask layer portions 60 and the spacers
80. The remaining portions of the dielectric cap layer 32L
constitutes the dielectric cap 32. The spacers 80 are then removed,
for example, with a HF-based wet etch.
[0047] Referring to FIG. 11, the top semiconductor layer 20L is
etched by an anisotropic etch employing the transfer layer portions
34 and the hard mask layer portions 60 as an etch mask. The
anisotropic etch can be a dry etch such as RIE or a wet etch that
removes the semiconductor material of the top semiconductor layer
20L selective to the materials of the transfer layer portions 34,
the hard mask layer portions 60 and the dielectric cap 32. The
remaining portions of the top semiconductor layer 20L constitutes
the semiconductor fins. The semiconductor fins includes a plurality
of first semiconductor fins 20 located in first region of the
substrate (10, 12) and a plurality of second semiconductor fins 20B
located in the second region substrate (10, 12). The first
semiconductor fins 20A are densely packed fins having a pitch
P.sub.1 equals to the natural pitch of the DSA material L.sub.0.
The second semiconductor fins 20B are semi-isolated from each other
and have a pitch P.sub.2 that is a non-integer multiple of the
natural pitch of the DSA material L.sub.0.
[0048] The transfer layer portions 34 and the spacer 80 are then
removed (not shown), for example with a HF-based wet etch and
oxygen-based plasma, respectively, leaving the semiconductor fins
(20A, 20B) standing on the buried insulator layer 12. From this
point, the semiconductor fins (20A, 20B) may be used in any further
fabrication processes. The greater pitch of the second
semiconductor fins 20B ensures merged source/drain regions can only
be formed in the logic device region, but not the SRAM device
region.
[0049] In the present application, by forming a plurality of
densely packed semiconductor fins 20A in a first device region
using a DSA process and a plurality of semi-isolated semiconductor
fins 20B in a second device region using a SIT process, fins with a
constant pitch and fins with variable pitches can be formed over a
same substrate. The full range of constructs required for FinFET
patterning can be addressed. This can greatly enhance the
processing flexibility.
[0050] While the present application has been particularly shown
and described with respect to various embodiments thereof, it will
be understood by those skilled in the art that the foregoing and
other changes in forms and details may be made without departing
from the spirit and scope of the present application. It is
therefore intended that the present application not be limited to
the exact forms and details described and illustrated, but fall
within the scope of the appended claims.
* * * * *