U.S. patent application number 15/387035 was filed with the patent office on 2017-06-15 for electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect.
The applicant listed for this patent is Tessera Advanced Technologies, Inc.. Invention is credited to Adrianus Alphonsus Jozef BUIJSMAN, Patrice GAMAND, Gerardus Tarcisius Maria HUBERT, Antonius Lucien Adrianus Maria KEMMEREN, Freddy ROOZEBOOM.
Application Number | 20170170131 15/387035 |
Document ID | / |
Family ID | 33542572 |
Filed Date | 2017-06-15 |
United States Patent
Application |
20170170131 |
Kind Code |
A1 |
ROOZEBOOM; Freddy ; et
al. |
June 15, 2017 |
Electronic device, assembly and methods of manufacturing an
electronic device including a vertical trench capacitor and a
vertical interconnect
Abstract
A semiconductor substrate comprises both vertical interconnects
and vertical capacitors with a common dielectric layer. The
substrate can be suitably combined with further devices to form an
assembly. The substrate can be made in etching treatments including
a first step on the one side, and then a second step on the other
side of the substrate.
Inventors: |
ROOZEBOOM; Freddy; (Waalre,
NL) ; BUIJSMAN; Adrianus Alphonsus Jozef; (Nijmegen,
NL) ; GAMAND; Patrice; (Douvres-la-Delivrande,
FR) ; KEMMEREN; Antonius Lucien Adrianus Maria;
(Eindhoven, NL) ; HUBERT; Gerardus Tarcisius Maria;
(Eindhoven, NL) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Tessera Advanced Technologies, Inc. |
San Jose |
CA |
US |
|
|
Family ID: |
33542572 |
Appl. No.: |
15/387035 |
Filed: |
December 21, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10560717 |
Dec 15, 2005 |
9530857 |
|
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PCT/IB04/50887 |
Jun 11, 2004 |
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15387035 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/0805 20130101;
H01L 2924/1431 20130101; H01L 2924/00014 20130101; H01L 2924/0002
20130101; H01L 29/66181 20130101; H01L 2224/16225 20130101; H01L
2224/0557 20130101; H01L 2924/00014 20130101; H01L 23/481 20130101;
H01L 2924/1434 20130101; H01L 24/16 20130101; H01L 2224/16265
20130101; H01L 2223/6622 20130101; H01L 2924/0002 20130101; H01L
2224/05009 20130101; H01L 2224/05124 20130101; H01L 2225/06548
20130101; H01L 2924/3011 20130101; H01L 23/66 20130101; H01L
23/49872 20130101; H01L 2224/05147 20130101; H01L 25/0657 20130101;
H01L 21/486 20130101; H01L 25/18 20130101; H01L 21/76898 20130101;
H01L 2225/06572 20130101; H01L 2225/06517 20130101; H01L 28/60
20130101; H01L 2224/05568 20130101; H01L 23/49827 20130101; H01L
2224/05001 20130101; H01L 29/0657 20130101; H01L 23/49838 20130101;
H01L 2924/1205 20130101; H01L 2223/6666 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2224/05599 20130101; H01L
2924/00 20130101 |
International
Class: |
H01L 23/66 20060101
H01L023/66; H01L 21/48 20060101 H01L021/48; H01L 25/18 20060101
H01L025/18; H01L 23/00 20060101 H01L023/00; H01L 25/065 20060101
H01L025/065; H01L 49/02 20060101 H01L049/02; H01L 23/498 20060101
H01L023/498 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 20, 2003 |
EP |
03300035.7 |
Mar 10, 2004 |
EP |
04300132.0 |
Claims
1. A method of manufacturing an electronic device comprising a
semiconductor substrate having a first and a second side and
provided with a capacitor and a vertical interconnect extending
from the first to the second side, on which first side the
capacitor is present, said method comprising the steps of:
providing first trenches in the substrate including the step of
etching from the first side of the substrate; providing second
trenches in the substrate by etching from one side of the substrate
and opening the second trenches by removing material from the
opposite side of the substrate; providing said first trenches with
a conductive surface; applying a layer of dielectric material on
the substrate, covering at least the first side of the substrate
and the inner faces of the first and second trenches; and applying
electrically conductive material in the first trenches and in the
second trenches, which conductive material of the first trenches
together with the layer of dielectric material and the conductive
surface forms the capacitor, and which conductive material of the
second trenches forms the vertical interconnects.
2. A method as claimed in claim 1, wherein the first trenches and
the second trenches are etched in a single step, said first
trenches having a smaller diameter than the second trenches leading
to the through-holes, with the result that the second trenches will
extend further into the substrate than the first trenches, said
trenches having inner faces.
3. A method as claimed in claim 2, characterized in that the step
of applying conductive material in the second trenches comprises
the steps of applying a seed layer and electroplating.
4. A method as claimed in claim 2, characterized in that a
plurality of second trenches are neighbouring and mutually
interconnected so as to form a single vertical interconnect.
5. A method as claimed in claim 4, wherein the electrically
conductive material applied in the first and the second trenches is
polysilicon.
6. A method as claimed in claim 1, wherein the step of removing
material for opening the second trenches comprises the step of
wet-chemical etching to form a cavity, said cavity having a larger
diameter than the second trenches.
7. A method as claimed in claim 1, wherein the second trenches are
formed by wet-chemical etching from the second side of the
substrate before provision of the first trenches, said second
trenches being shaped as cavities and have a larger diameter than
the first trenches.
8. A method as claimed in claim 7, wherein the second trenches are
opened by etching in the same step as the etching of the first
trenches.
9. A method as claimed in claim 7, wherein the second trenches
extend up to the first side of the semiconductor substrate and are
covered by an etch-stop layer provided on the first side of the
substrate.
10. An electronic device comprising: a semiconductor substrate
having a first side and a second side; a plurality of trenches on
the first side of the substrate, each of the trenches extending
into the substrate from the first side to a depth; conductive
material lining each of the trenches; a vertical interconnect that
extends through the substrate from the first side to the second
side, the vertical interconnect having walls; a single deposition
layer of dielectric material on the first and second sides of the
substrate, on the conductive material lining each of the trenches,
and on the walls of the vertical interconnect.
11. The electronic device of claim 10, wherein the vertical
interconnect has a first part and a second part, the first part
extending from the first side of the substrate to the second part,
the second part extending from the second side of the substrate to
the first part and being wider than the first part.
12. The electronic device of claim 10, wherein the vertical
interconnect includes a plurality of parallel trenches.
13. The electronic device of claim 11, wherein the first part of
the vertical interconnect includes a plurality of parallel trenches
each of which extends from the first side of the substrate to the
second part of the vertical interconnect.
14. The electronic device of claim 10, wherein the plurality of
trenches form a vertical trench capacitor.
15. The electronic device of claim 10, wherein the single
deposition layer of dielectric material is on walls of the vertical
interconnect that oppose one another, with the vertical
interconnect extending uninterrupted between the walls.
16. The electronic device of claim 10, further including a second
conductive material in the trenches, the second conductive material
being separated from said conductive material lining each of the
trenches by the single deposition layer of dielectric material on
the conductive material lining each of the trenches, the single
deposition layer of dielectric material being on opposing vertical
sidewalls of the second conductive material, the second conductive
material, single deposition layer of dielectric material and said
conductive material lining each of the trenches forming a vertical
capacitor.
17. An electronic device comprising: a semiconductor substrate
having a first side and a second side and a high-ohmic zone; a
vertical trench capacitor on the first side of the substrate and
including a plurality of trenches having first and second
conductive surfaces; a vertical interconnect that extends through
the substrate from the first side to the second side; a planar
capacitor on the first side of the substrate, the high-ohmic zone
separating the planar capacitor from the vertical trench capacitor;
and a single-deposition layer of dielectric material located
between the first and second conductive surfaces of the vertical
trench capacitor, between conductive plates of the planar
capacitor, and configured and arranged to insulate the vertical
interconnect from the substrate.
Description
[0001] The invention relates to an electronic device comprising a
semiconductor substrate having a first and a second side and
provided with a capacitor and a vertical interconnect through the
substrate extending from the first to the second side, on which
first side the capacitor is present.
[0002] The invention also relates to an assembly therewith.
[0003] The invention further relates to methods of manufacturing
such an electronic device.
[0004] Such an electronic device is known from EP-A 1154481. The
known device is an interposer that is made of a heat-resistant
insulator that is preferably silicon, but alternatively of glass or
resin. Through-holes are made with a laser. Wiring patterns are
then formed on both the first side and the second side of the
device, said wiring pattern extending at the side walls of the
through-holes and thus forming the vertical interconnect. Gold or
solder bumps may be applied on the second side for connection to a
mounting board. A capacitor is present on the first side of the
substrate. The capacitor is a thin-film capacitor with a dielectric
sandwiched between a first and second electrode. The first
electrode forms herein part of the wiring pattern. The dielectric
layer is formed preferably of a ferroelectric substance, such as
strontium titanium oxide or lead zirconium titanate. Thus, a
capacitor having a high capacitance density is obtainable.
[0005] It is a disadvantage of the known device, however, that
application of ferroelectric substances calls for further
conditions and requirements to the processing. Generally, specific
metal layers such as platinum or a conductive oxide are applied as
electrode material for capacitors with such ferroelectric
substances. An alternative seems to be the provision of an
aftertreatment in diminishing atmosphere after the provision and
sintering of the ferroelectric substance. This aftertreatment at a
high temperature is not yet fully developed, however, and has the
problem that all layers in the device must be able to withstand the
temperature and conditions applied. Furthermore, the ferroelectric
substances are sensitive to delamination and cracking, which is
certainly the case if the first bottom electrode forms part of the
wiring pattern and can thus be expected to have a relatively rough
surface.
[0006] It is therefore an, object of the invention to provide an
electronic device of the kind mentioned in the opening paragraph,
which combines, the electrical connection through the substrate
with the presence of capacitors with a high capacitance density and
which is reliable and manufacturable.
[0007] This object is achieved in the invention in that the
capacitor is a vertical trench capacitor provided with a plurality
of trenches in which a layer of dielectric material is present
between a first and a second conductive surface, said layer of
dielectric material also being used as insulation between the
substrate and the vertical interconnect.
[0008] Vertical capacitors are alternatives to ferroelectric
capacitors for providing a high capacitance. The high capacitance
is herein achieved with an increase of the surface area. They are
known per se, such as for instance from U.S. Pat. No. 4,017,885.
However, vertical capacitors cannot directly be substituted for
ferroelectric capacitors. The same process is needed for making the
through-holes and making the trenches of the vertical capacitors,
but with different parameter settings. Hence, the manufacture of
the trench capacitors and the vertical interconnects cannot be
combined, but should be combined subsequently.
[0009] This subsequent processing appears problematic as well,
since the vertical interconnect must be adequately insulated from
the substrate. If first the vertical capacitor is made, and then
the interconnect, the capacitor and other layers made must be
protected very well from the etching liquid or etching gas. The
etching liquid or gas may easily open the interface between the
substrate and the patterned layers and therewith lead to
contamination, delamination and other undesired effects. The
reverse order of making first the vertical interconnect and then
the trench seems not available either. Not only will a large part
of deposited material be removed through the vertical interconnect,
but also an implantation step is required for the provision of a
conductive surface in the vertical capacitor, which would be
detrimental to the constitution of the vertical interconnect.
[0010] It is now the insight of the invention, that both the
vertical capacitors and the vertical interconnects can be combined
with good results by using the dielectric material of the trenches
also as the insulating material for the vertical interconnect. Both
vertical elements are thus processed simultaneously, with steps
carried out not only on the first side of the substrate, but also
on the second side.
[0011] The resulting device has, substantial advantages over the
prior art; first of all, it is ensured that it has adequate
high-frequency properties. Due to the insulating material parasitic
currents through the substrate are prevented, at least to a large
extent. This insulating material can be effectively deposited,
without a mask and including a thermal oxide layer.
[0012] Due to the presence of the vertical interconnects, it is
possible to provide very short connections to ground. Short
connections to ground are important for RF applications, as the
ground is the reference. If the ground is not adequately grounded
due to impedances of interconnects, the complete RF design may
function detrimentally. Furthermore, short connections for signal
lines reduce the impedances. This is particularly true, since the
signal lines are, not only shorter, but can be provided at
locations so as to minimize parasitic behaviour or to establish
microstrip behavior.
[0013] Moreover, the high capacitance capacitors can be used as
decoupling capacitors for any integrated circuit to be applied on
the first side. This will dramatically reduce the number of
external contacts needed. Finally, the capacitor of the invention
has a low resistance compared to planar capacitors, which, is
particularly true for larger capacitance values of 20 nF and more,
and especially for capacitors of more than 40 nF or more.
[0014] Besides, it is advantageous that one or more capacitors in
the device of the invention can be used for more applications.
Ferroelectric capacitors such as strontium titanium oxide show a
dielectric adsorption. As a result of this open loop transceivers
with such capacitors for the PLL function do not give the required
performance. Capacitors with another dielectric, such as silicon
nitride or silicon oxide do not have this problem. Additionally,
the temperature stability of the dielectric constant of thin-film
ferroelectric layers as far as currently available is less than
optimal for applications in or together with transceivers.
[0015] It is another advantage of the device of the present
invention as compared to that in the prior art that it enables the
provision of any desired capacitance value. If a larger capacitance
value is needed the capacitor will comprise a larger number of
vertical trenches. Since the surface area on top of the vertical
capacitors can be used for interconnects, resistors, inductors and
the like, the larger capacitor does not give rise to a new design.
Also, it is quite easy to provide capacitors with slightly
different values while standard design rules can be respected.
[0016] In a preferred embodiment, the trenches of the interconnect
are substantially filled with electrically conductive material.
This filling of the trenches leads to a further reduction of the
impedance of the vertical interconnect. It is noted that such
filling is not foreseen in the prior art EP-A 1154481. The reason
of this must be found in the actual diameter of the through-holes.
Although the trenches of the interconnects are generally wider than
those of the capacitors, the etching technique in which they are
made allows relatively small diameters. With such small diameters
the conductive material will first cover side walls but thereafter
fill the trench. Moreover, the manufacture of the vertical
interconnect generally occurs in a two-step process, wherein first
etching is done from the one side and thereafter the trenches are
opened from the opposite, side. This manufacturing technique allows
the via to be already filled halfway before it is opened.
[0017] In an even further embodiment, the vertical interconnect
comprises a plurality of parallel through-holes through the
substrate, each of which is filled with electrically conductive
material. This construction allows the provision of a very low
impedance. Not only does the resistance decrease due to the
parallel circuitry, but also circular currents within the vertical
interconnect are minimized that would otherwise give rise to
parasitic inductance. Another advantage is that the filling
material may be the same as that of the second conductive surface
of the capacitor. This reduces the number of process steps. A
suitable filling material is polycrystalline silicon, doped with a
conventional dopant.
[0018] In another suitable embodiment, a first vertical
interconnect is used for grounding and a second interconnect is
used for signal transmission. Grounding and signal transmission are
important aspects of the function of an interposing substrate if
the device is used for RF applications. With the vertical
interconnects, these functions can be fulfilled excellently.
[0019] In a further embodiment, the first and second vertical
interconnects are designed so as to form a coaxial structure. The
coaxial structure is one example of a microstrip. Such microstrips
allow signal transmission with very limited impedance. Since the
vertical interconnects are filled, contact pads may be provided on
the second side of the substrate at the end of the vertical
interconnects. Solder balls can be provided on such contact pads
for connection to a printed circuit board. On the first side the
substrate is generally covered with an interconnect structure of a
couple of layers. This allows each of the vertical interconnects to
be contacted without being short-circuited. Also the coaxial
structure may be transformed in the interconnect structure to any
other type of microstrip, such as a transmission line or a coplanar
wave guide. Aims of the interconnect structure are not only the
contacting of the capacitors and any resistor and/or inductor
present, but also the rerouting of the signal path, so as to fit to
the bumps of an integrated circuit.
[0020] In another embodiment an integrated circuit is defined on
the second side of the substrate. This option allows a further
integration of functionality. The contact pads of the device will
then be provided on the first side of the substrate, adjacent to
and/or on top of the vertical capacitors. This, embodiment looks
particularly suitable for the application in smartcards. The
advantage of this concept is that very large decoupling capacitors
can be provided on the same substrate as the integrated circuit,
without the need for additional space. Such a decoupling capacitor
is part of the internal power supply circuit. The capacitor allows
decoupling of the smartcard of any external power supply during a
certain decoupling period. The decoupling period is then used for
carrying out security-relevant operations. The very large
decoupling capacitor thus allows that the decoupling period is
extended, while at the same time no further surface area is needed.
This construction of the decoupling capacitor is furthermore
advantageous from a security point of view. In the current
situation, both the capacitor and any data processing section are
on the outer side of the smart card IC, and hence vulnerable to
attack and misuse by unauthorized persons. By replacing the
capacitor to the other side, only one of the two sides is present
on the outer side. In a further, embodiment, the device further
comprises a scratch-protective, non-transparent layer. Such a
layer, also called `security coating` is specifically aimed at
preventing access to the inside of the integrated circuit. The
coating is for instance a ceramic layer with embedded particles
that is provided via a sol-gel processing. The security coating
could be applied on top of the integrated circuit, on top of the
capacitor, or on both sides. It is understood that for this
embodiment it is not absolutely necessary that the dielectric
material of the vertical capacitor is the same as that of the
insulation in the vertical interconnect.
[0021] Further embodiments are suitable to improve the
characteristics of the electronic device. The substrate may
comprise a high-ohmic zone which is present adjacent to the
vertical capacitors and acts as a protection against parasitic
currents. Such high-ohmic zone could circumfere the vertical
capacitors and preferably extend from the first to the second side
of the substrate. Under `high-ohmic` is usually understood a zone
of more than 500 .OMEGA./cm, preferably more than 1500 .OMEGA./cm.
Such a zone acts as a barrier against, any kind of interaction
through the substrate. This is particularly advantageous for the
reduction of inductive interaction.
[0022] In addition to the vertical capacitors, a planar capacitor
may be present on the first side of the substrate. Whereas the
vertical capacitor generally has a capacitance density in the order
of 30 nF/mm.sup.2 or more, a planar capacitor with the same
dielectric material has a capacitance density in the order of 1-5
nF/mm.sup.2. This allows a further fine-tuning of the desired
capacitance. The presence of such capacitors furthermore allows
that the electronic device can be applied for more than one
application without substantial redesign.
[0023] It will be understood by the skilled person that many other
elements can be present either on the first side and/or on the
second side of the substrate. This includes both active and passive
devices, wherein the actives are generally provided in the
substrate and the passives are provided on top of the substrate.
Also protective layers or specific packages may be provided. In
order to cope with differences in thermal expansion between the
device and any carrier such as a printed circuit board, an
underfill or protective layer such as benzocyclobutene could be
provided on the side to be attached to the carrier.
[0024] It is a farther option that certain semiconductor devices
are assembled in a cavity in the substrate. Their backside could be
exposed to a heatsink by local removal of the substrate. Such local
removal of the substrate can be realized in the same step as the
etching from the second side to provide or to open the vertical
interconnect. A more detailed description of such a process is
given in the non-prepublished patent application EP03101729.6
(PHNL030659), which is herein included by reference. This allows
devices with different substrate materials to be combined with a
single interconnect structure that does not need the provision of
any bond wires or solder balls. This has a functional advantage for
RF applications in addition to the practical advantage of reduced
assembly activities.
[0025] It is desired that the device of the invention is assembled
together with a semiconductor device into an assembly. The
semiconductor device will be attached to either the first side or
the second side of the substrate. In order to contact the device,
use can be made of a flip-chip process or of wirebonding or
optionally of another surface mount technique. A flip-chip process
is herein preferred in view of the lower impedance. The solder or
metal bumps for the flip-chip process can be chosen corresponding
to available processes as well as the desired pitch. The
semiconductor device can thereafter be overmoulded with a
protective layer. Alternatively, a heat-spreader could be provided
on the side facing away from the substrate. Instead of one, more
semiconductor and other electronic devices can be provided on the
chosen, side of the substrate. Examples of suitable semiconductor
devices include devices that need a decoupling capacitor for
adequate functioning, such as a power amplifier, a transceiver IC,
a voltage controlled oscillator. The further electronic devices may
be devices that cooperate with, the semiconductor device to provide
a functional subsystem. Examples hereof are ESD/EMI protection
devices, bandpass filters, such as for instance BAW filters,
impedance matching circuits.
[0026] The assembly is furthermore suitable for digital signal
processing. In such an assembly, the semiconductor device is a
microprocessor with an integrated or separate memory unit.
Furthermore, a power supply signal generator is provided. The
vertical capacitor herein has the function of buffering of the
digital signal processing, that is both for decoupling purposes and
for dampening power overshoot or drop.
[0027] The invention also relates to a method of manufacturing the
device of the invention, and particularly to a method of
manufacturing an electronic device comprising a semiconductor
substrate having a first and a second, side and provided with a
capacitor and a vertical interconnect extending from the first to
the second side, on which first side the capacitor is present and
on which second side contact pads are present for connection to a
carrier.
[0028] It is the object of the invention to provide such a method
that is fully compatible with semiconductor manufacturing, without
the need to provide special materials or extensive processing on
the first and the opposite second side.
[0029] This object is achieved in that the method comprises the
steps of:
[0030] providing first trenches in the substrate including the step
of etching from the first side of the substrate;
[0031] providing second trenches in the substrate by etching from
one side of the substrate and opening the second trenches by
removing material from the opposite side of the substrate;
[0032] providing said first trenches with a conductive surface;
[0033] applying a layer of dielectric material on the substrate,
covering at least the first side of the substrate and the inner
faces of the first and second trenches; and
[0034] applying electrically conductive material in the first
trenches and in the second trenches, which conductive material in
the first trenches together with the layer of dielectric material
and the conductive surface forms the capacitor, and which
conductive material in the second trenches forms the vertical
interconnects.
[0035] The method of the invention leads to vertical capacitors in
combination with vertical interconnects. This is achieved in that
the trenches of the capacitors are made simultaneously with the
trenches of the vertical interconnects. The structure of a
substrate with trenches that is then formed is afterwards processed
in an integral way, so as to provide a dielectric layer and
conductive material. A separation is thus made between the
provision of the trenches and the provision of thin-film layers and
structures on the substrate. This is enabled due to the fact that
the second trenches (for the vertical interconnects) have a
diameter on the first side of the substrate which diameter is
slightly larger but still comparable to that of the first
trenches.
[0036] Basically, there are two embodiments of the method; in the
first embodiment the process starts with the simultaneous formation
of the first trenches and the second trenches from the first side
of the substrate in a single etching process. Thereafter, the
second trenches are opened from the second side of the substrate.
In the second embodiment, the process starts with the formation of
the second trenches from the second side of the substrate;
thereafter, the first trenches are formed; if the second trenches
do not extend to the first side yet, then this etching step may be
used to open the second trenches.
[0037] The application of electrically conductive material in the
first trenches and the second trenches does not mean that this is
the same material, neither that there is a common step in the
application of this conductive material for both first and second
trenches. It appears advantageous that the conductive material
provided in the first trenches forms a seed layer in the second
trenches, that is thereafter thickened in an electroplating
process. Alternatively, the second trenches, and particularly the
narrow part, could be completely filled by the said conductive
material, for instance polycrystalline silicon or TiN, TiW or the
like. In a further alternative, the second trenches are filled by
the provision of a seed only at one of their ends, and subsequent
electroplating. Due to the small diameter, that is of the first
narrower part of the trenches, they will be filled directly in the
plating process. The cavity-like larger part of the second trenches
may be filled by electroplating. In the case where these
cavity-like parts of the second trenches are provided as a first
step, these could immediately be filled with electrically
conductive material. For this purpose use can be made of various
deposition techniques, including sol-gel deposition (for instance
of Ag), electroplating, electroless deposition, etc.
[0038] It must be understood that the simplification of processes
is achieved with the invention in that the process steps carried
out on the second side of the substrate take place at a lower
resolution that those on the first side. As a consequence, any
aligning problems are substantially prevented. Also, the number of
steps on the second side seems very limited: basically there are
two lithographic steps: one for the provision of an etch mask and
one for the definition of a wiring pattern. Particularly
wet-chemical etching, wet-chemical deposition and electroplating
are advantageous processes in this respect, as a number of
substrates can be placed in a bath. It is then not necessary to lay
the substrates down on their first side. The etch mask can be
provided on the second side of the substrate before any other
operation is carried out. Therewith, contamination and damage are
prevented. The mask for the definition of the wiring pattern can be
provided after the vertical interconnect is substantially filled,
and after that the processing on the first side is substantially
completed. The first side is then preferably covered by a
protective layer.
[0039] These and other aspects of the electronic device, the
assembly and the method of the invention will be farther elucidated
with reference to the figures, in which:
[0040] FIG. 1 shows diagrammatically a cross-sectional view of a
first embodiment of the electronic device;
[0041] FIG. 2 a-d show cross-sectional views of four stages in a
first embodiment of the method;
[0042] FIG. 3 a-e show cross-sectional views of five stages in a
second embodiment of the method;
[0043] FIG. 4 a-e show cross-sectional views of five stages in a
third embodiment of the method;
[0044] FIG. 5-7 show different embodiments of the assembly
including the device of the invention.
[0045] The Figures are not drawn to scale and purely
diagrammatical. Identical reference numbers in different Figures
refer to identical parts.
[0046] FIG. 1 shows in a cross-sectional view a first embodiment of
the electronic device 100 of the invention. The device 100
comprises a substrate 10 with a first side 1 and an opposed second
side 2. A vertical trench capacitor 20 is present and exposed on
the first side 1 in addition to a vertical interconnect 30. Both
the vertical interconnect 30 and the capacitor 20 in this
embodiment comprise a plurality of trenches, 21, 311, 312, 313.
However, although very much preferred, this is in principle not
necessary. The vertical interconnect 30 comprises a first part 31
and a second part 32 of wider dimensions. As will become clear from
the farther discussion, the first part 31 is made by anisotropic
etching from the first side 1, and the second part 32 is made by
etching from the second side 2, and particularly wet-chemical
etching. The device 100 comprises a couple of layers on its
surfaces on the first and second sides 1,2 as well as in the
trenches 21, 31, 32. Not shown here are first conductive surfaces
22 that constitute the bottom electrode of the vertical trench
capacitor 20. A layer 11 of dielectric material is shown, that is
present on nearly the whole surface. On top of the layer 11 of
dielectric material, a layer 12 of electrically conductive material
is present. This layer is for instance polysilicon, but may
alternatively be another material such as copper, sol-gel deposited
silver, aluminum. On the first side 1 the capacitor 20 and the
interconnect 30 are provided with a further metallisation of AlCu
in this case. The layers 12 and 13 can be used as interconnect
layers and may be mutually separated at certain positions by an
insulating layer. The second part 32 of the interconnect has its
surface covered with a layer 14, in this case of electroplated
copper. The copper extends on the second side 2 of the substrate
and forms the wiring pattern. The layer 14 may fill, the second
part of the interconnect 30.
[0047] FIG. 2 shows in cross-sectional view four stages in a first
embodiment of the method. This first embodiment leads to a device
100 of the first embodiment, with minor variations.
[0048] FIG. 2a shows the first stage of the method, after etching
from the first side has taken place. Use is made herein of dry
etching. A mask was used with circular opening, of 1.5 .mu.m
diameter and 3.5 .mu.m spacing in the area of the capacitors, and
openings of 10 .mu.m diameter and 14 .mu.m spacing in the area of
the vertical interconnect. The mask contained a stack of 1 .mu.m
thermal oxide and 1.3 .mu.m photoresist. The dry etching was
executed at wafer level, using substrates of 150 mm diameter. The
resistivity of the wafers was in the order of 1 to 5 m.OMEGA.cm,
with the exception of high-ohmic zones 18,19 in the substrate, that
had a resistivity of 1000-1500 .OMEGA.cm. The wafers were etched at
room temperature in an ASE.TM. Inductively Coupled Plasma (ICP)
reactor of STS. Typical etching conditions were 12 to 16 mTorr
pressure and 20.degree. C. chuck temperature, yielding etch rates
of around 0.6 .mu.m/min. With this process the macropore structures
are characterized by a smooth pore wall with a rounded bottom and a
pore depth uniformity of more than 97%. The trenches 21 with a mask
opening of 1.5 .mu.m diameter led to a depth of 40 .mu.m and a
diameter of 2 .mu.m. The trenches 311,312,313 with a mask opening
of 10 .mu.m diameter led to a depth of 200 .mu.m and a diameter of
12 .mu.m. The pore depth is slightly larger than the mask opening
due to underetch. Hence, the difference in openings in the mask led
to differences in the pore depth, which phenomenon was exploited
effectively in the invention.
[0049] FIG. 2b shows a second stage in this first embodiment of the
method. After the etching, the etch mask was removed, and another
mask was deposited. Through this mask, for instance a nitride, an
implantation step was carried out. This implantation step provided
a first conductive surface 22 in the trenches 21. The mask layout
was such that also a conductive surface 42 was provided, to be used
as bottom electrode of a planar capacitor. The high-ohmic zone 18
is present between the conductive surface 22 and 42, so as to
prevent as much as possible any parasitic currents. Furthermore, a
pad 23 was defined in connection with the conductive surface 22, so
as to enable electrical connection of the first conductive surface
22. Use was made of a P indiffusion from a pre-deposited
phosphorous silicate glass layer. The silicate glass layer was then
removed by wet etching in 1% (v/v) HF.
[0050] FIG. 2c shows a third stage in this first embodiment of the
method. In a first step hereof, the vertical interconnects 30 were
opened from the second side 2 of the substrate 10 by wet-chemical
etching. This led to the second parts 32 of the interconnects 30.
Use was made herein of a KOH etch. Alternative methods for the
interconnect opening include power blasting or lasering. A
photolithographical mask was thereto provided on, the second side
of the substrate. It is observed that in the same step saw lanes
can be defined on the second side 2 of the substrate 10. This will
simplify the separation of the substrate into individual devices,
such that other methods than sawing can be used.
[0051] After the provision of the second parts 32 a dielectric
layer 11 was deposited. The dielectric layer 11 was in this example
a nominally 30 nm `ONO` dielectric layer stack consisting of a
thermal oxide (5 nm), LPCVD nitride (20 nm) and an oxide layer (5
nm) deposited by LPCVD TEOS. The layer was deposited without a
mask, such that the complete surface of the device was covered with
the dielectric layer 11.
[0052] In an alternative embodiment, the vertical interconnect 30
is not opened by wet-chemical etching from the second side, but by
removal of part of the substrate. This, can be done, by grinding
and/or chemical-mechanical polishing. The grinding and/or polishing
operation is particularly preferred in combination with the filling
of the trenches 311-313 with a sacrificial layer, particularly a
spin-on-glass material as known per se. This allows to finalize the
thin-film structure on the first side 1 of the substrate 10 before
opening the vertical interconnect 30, while at the same time the
first side 1 constitutes a relatively planar surface. After opening
of the vertical interconnect 30 from the second side, the
spin-on-glass material can be removed in a gentle etching
treatment, and both the first part 31 and the second part 32 of the
interconnect 30 as far as present can be filled with electrically
conductive material.
[0053] FIG. 2d shows the device 100 after that in the following
steps the dielectric layer 11 is partially etched away, and a layer
of electrically conductive material is provided to define a top
electrode 44 of the planar capacitor 40, the second conductive
surface 24 of the vertical capacitor 20, the contact 25 to the
first conductive surface 22, and the filling of the first part 31
of the vertical interconnect 30. Part of the dielectric layer 11
forms a dielectric 43 of the planar capacitor 40. In this example,
use is made of a 0.5 .mu.m thick conductive layer of n-type in situ
doped polysilicon. It was deposited by LPCVD from SiH.sub.4 and
diluted PH.sub.3. After a furnace anneal step of 30 minutes at
1000.degree. C. the conductivity of the polysilicon is in the order
of 1 m.OMEGA./cm. Due to the use of parallel trenches 311, 312, 313
for the first part 31 of the vertical interconnect 30, this
conductivity does not lead to an impedance that is too high. The
trenches 311, 312, 313 are filled. In this filling process the
polysilicon is first deposited on the side-walls and then grows in
the kinetic regime. Although not explicitly shown, the polysilicon
layer 11 is also used as seed layer for the wiring pattern on the
second side 2 of the substrate. This wiring pattern is grown by
electroplating thereafter. Alternatively, use can be made of the
polysilicon as seed layer also in the first part 31 of the
interconnect 30. The trenches 311, 312, 313 in the first part will
be completely filled, even if the seed material is present only at
their ends.
[0054] Instead of the stack of oxide, nitride and oxide, other
materials or combinations thereof may be applied as the dielectric
material. Such a material can be any single layer of oxide, nitride
or the like; any material with a higher dielectric constant, such
as tantalum oxide or hafnium oxide, or the like. These layers can
be suitably applied with (low pressure) chemical vapor deposition.
With this technique, the complete surface as far as uncovered by a
mask is provided of the desired material. An alternative is the
use
of wet-chemical deposition techniques, including sol-gel
processing. It is preferred to apply an oxide layer, such as a
thermal oxide, onto the substrate, in order to improve the
adhesion. Another alternative is the use of a single nitride layer
of about 15 nm--instead of the stack with 30 nm thickness. This
increases the capacitance density from 30 to 90 nF/mm.sup.2, but
reduces the breakdown voltage from 25 to 7 V.
[0055] FIG. 3 shows in cross-sectional view five stages in a second
embodiment of the method of the invention. Contrary to the first
embodiment, the first step of the method is herein the provision of
the second parts 32 of the interconnects 30 from the second side of
the substrate 10. This has the major advantage that after this
first step no photolithographical step is needed anymore on the
second side 2 of the substrate, until the provision of the wiring
pattern 14 in the last step of the method. For reasons of clarity,
the trenches 21 of the vertical capacitor are not indicated in this
Figure.
[0056] FIG. 3a shows the obtained structure after providing the
second parts 32 of the interconnect 30 from the second side 2 of
the substrate 10. In this case, this was carried out by first
providing a mask 51 of oxide and nitride on all sides of the
substrates 10, then patterning the mask 51 according to the desired
pattern on the second side 2 of the substrate 10 and finally
wet-chemical etching of the silicon substrate 10 with KOH.
[0057] FIG. 3b shows the result at a second stage of the method. In
this method, the the mask 51, or at least the nitride layer
thereof, is patterned from the first side 1 of the substrate 10,
and used for definition of high ohmic substrate zones (not-shown).
Thereafter, a hard mask 52 is deposited and patterned on the first
side 1 of the substrate 10 to define the first part 31 of the
interconnect 30.
[0058] FIG. 3c shows the result at a third stage of the method.
First the substrate 10 is etched from the first side 1 through the
deposited mask. This etching can be done both with dry-etching and
with wet-chemical etching. The etching is preferably carried out in
the same step as the etching of trenches 21 to define a vertical
capacitor. However, this is not essential. Thereafter, a conductive
surface is provided in the manner described earlier with respect to
the first embodiment of the method. Only hereafter the mask 51 is
removed and the dielectric layer 11 is provided without a mask.
Thereafter, a layer 12 of electrically conductive material, in this
example polysilicon, is deposited and etched in accordance with any
desired pattern.
[0059] FIG. 3d shows the result at a fourth stage of the method.
Contact windows have been etched in the dielectrical layer 11 on
the first side 1 of the substrate 10. A thick dielectric layer 15,
in this case TEOS, was deposited in part of the windows.
Afterwards, a patterned layer 13 of metal has been deposited, while
leaving the area of the TEOS layer free.
[0060] FIG. 3e shows the result at a fifth stage, after further
steps. After provision of a patterned layer 16 of electrically
insulating material, a patterned layer 17 of electrically
conductive material was provided. This second patterned layer 17,
for instance of AlSiCu, has a sufficient thickness, for instance in
the order of 1-4 microns, for definition of high-quality inductors.
The pattern of electrically insulating material of the layers 15,16
functions as a mechanical support, such that the overlying area in
the second metal layer 13 can be used as bond pad 28. The complete
structure is then covered with a passivation layer 29, for instance
of silicon nitride, that will be locally removed in the area of the
bond pad 28. The substrate 10 is thereafter thinned by grinding
from the second side 2 thereof. This is of course by no means a
necessary step.
[0061] FIG. 4 shows cross-sectional views of five stages in a third
embodiment of the method of the invention, According to this
method, the first side 1 of the substrate 10 is provided with
vertical capacitors 20, whereas a semiconductor device 50 is
defined at the second side 2 of the substrate.
[0062] FIG. 4a shows the first stage of the method. It starts with
the semiconductor device 50, for instance an integrated circuit,
having been fully processed. The substrate 10 is thereto an n-type
substrate provided on its second side 2 with a p-type epitaxial
layer, in which p-wells have been defined that act as channels for
the individual transistors. An n.sup.+-connection is made from the
second side 2 to the n-type substrate layer. This substrate layer
has preferably a thickness of more than 40 .mu.m and more
preferably a thickness of at least more than 70 .mu.m. Then-type
layer provided with an n.sup.+-layer on its second side, so as to
enable the effective etching of the vertical capacitors. The second
side 2 of the substrate 10 is hereafter protected by a temporary
carrier. This could be a glass layer that is attached with a LTV
releasable adhesive. However, alternatively, it can be a
two-layered stack of for instance a 1 micron thick oxide layer and
a 1-10 micron thick photoresist layer. This stack can be present on
all sides of the substrate 10, as is shown in FIG. 2a. This
temporary carrier has the function to withstand pressure
differences needed for dry etching, or to define the conditions for
wet-chemical etching. The etching mask is furthermore applied to
provide the desired implantation step, so as to create the first
conductive surfaces of the vertical trench capacitors.
[0063] FIG. 4b shows the result after the provision of the first
and second trenches 21, 31. Due to the differences in pitch, the
depth of the pores is controlled.
[0064] FIG. 4c shows the result after removal of the etch mask and
after provision of the dielectric layer 11. The removal of the etch
mask effectively provides the opening of the second trenches 21
into vertical interconnects 30. The dielectric layer 11 is provided
both in the first trenches 21 and in the second trenches 31, and is
used as dielectric of the vertical capacitor 20 and as insulation
of the vertical interconnect 20. In view of the fully processed
integrated circuit, no thermal oxide is used as part of the
dielectric layer. Instead, an LPCVD oxide layer is applied. This
LPCVD oxide is hereafter locally removed so as to open the bond
pads of the integrated circuit 50.
[0065] FIG. 4d shows the result after the provision of the second
electrically conductive surface 12, which is in this case a layer
of TiN. This layer 12 is herein used as a seed layer. Alternative
deposition techniques for seed layers, such as sol-gel deposition
of conductive oxides or sol-gel deposition of Ag.
[0066] FIG. 4e shows the result after electroplating. Use is made
of a mask, so as to define the desired wiring pattern. A further
electrically conductive layer 13 is provided in the trenches 21,31.
Thereafter, the parts of the seed layer under the mask are removed.
The resulting device is very suitable for integration in a
smartcard.
[0067] FIGS. 5, 6 and 7 show in diagrammatical cross-sectional
views three examples of the assembly according to the invention.
FIG. 5 shows an assembly 300 including the device 100, a leadframe
310 and a semiconductor device 200. The assembly makes use of a
double flip chip construction, in which the semiconductor device
200 is electrically connected to the leadframe 310 via the
electronic device 100. The bumps 201 between devices 100 and 200
are herein for instance gold bumps, and the bumps 301 between leads
311 of the leadframe 310 and the device 100 are for instance solder
bumps of SAC (tin-silver-copper alloy). Thermally, the
semiconductor device 200 is, coupled to the heatsink 312 of the
leadframe 310 directly.
[0068] This system is assembled in the following manner. Metal has
been applied at the bond pad areas of both the device 100 and the
active device 200. The device 100 is thereto provided with an
underfill metal, such as a Ni or TiW layer on top of the bond pads.
The metal is joined in a thermal compression treatment. Thereafter
an underfill material is provided so as to fill the area between
the device 100 and the active device 200. This underfill acts as a
protective layer against moisture and other chemical contamination.
The leadframe 310 comprises a first and a second electrically
conductive layer of Cu. The lead frame 310 is formed by skillfully
etching it with a semi-etching technique, first from the first side
and then from the second side or the other way around. This results
in a heat sink 312 and in leads 311, while the heat sink 312 is
also a contact surface. The heat sink 312 is customarily connected
to the rest of the lead frame 310 by means of four wires. There is
an open space under the leads 311, which is filled with a molding
material. This provides a mechanical anchoring of the leadframe in
the molding material. On the heatsink 312 a conductive adhesive is
applied i.e. a silver containing, glass epoxy adhesive. Solder dots
are provided on the leads 311, for example, by printing, with a
stencil. The solder is here a low-melting SAC solder which contains
over 96% Sn, 3% Ag and about 0.5% Cu.
[0069] In an example, the active device 200 together with the bumps
201 then has a thickness of 150.+-.15 .mu.m. The layers of the lead
frame 310 have a thickness of 70.+-.20 .mu.m while in the location
of the heat sink 312 relative to the device 100 there is a play of
about 20 .mu.m. The maximum spreading is thus about 55 .mu.m. This
spreading can be eliminated by remelting the solder balls and the
solder dots, and slightly in the adhesive layer which, however, is
chosen to be thin, for example of a thickness of about 20 .mu.m.
After the curing of the conductive adhesive, as a result of a heat
treatment of 100-150.degree. C., the heat sink 312 of the lead
frame 310 is then pulled up when the adhesive layer shrinks. The
result is a downward pressure. The resulting stress is relaxated by
taking the bumps 201, 301 to beyond their reflow temperature. In
this manner the bumps 201,301 are able to distort, and are
particularly flattened.
[0070] Contrary to the other embodiments, the second side 2 of the
device 100 is here not provided with contact pads, for coupling to
an external carrier. The vertical interconnects 30 provide in this
construction a thermal path to the second side 2 of the electronic
device 100. This improves the heat-spreading function of the device
100. Although not indicated, it is preferable to provide a
connection from the second side 2 of the device 100 to the
leadframe 310. Alternatively or additionally, the vertical
interconnects 30 are used for grounding. Although two vertical
interconnects 30 provide an additional resistance to the ground,
this construction of the grounding has the advantage that the
ground can be assumed to have the same potential everywhere in the
device. Such well defined ground is particularly preferred if the
assembly 300 comprises more than a single element. The vertical
capacitors (not-shown) are herein provided on the side 1 of the
device 100 facing the semiconductor device 200.
[0071] FIG. 6 shows an alternative embodiment of the assembly 300.
This embodiment has practical advantages for multichip modules, in
which more than one device 200 is assembled to the electronic
device 100. This electronic device 100 acts here as the carrier of
the assembly 300. The advantages are that devices 200 of different
height can be included, and that there is no need for a
simultaneous attachment of the devices 200 to an individual
heatsinks 312 or one common heatsink 312. In addition, the assembly
300 of this embodiment is a chip-scale package without a leadframe,
which can be provided at wafer level instead of at die level.
Herewith a substantial cost reduction is achieved. A disadvantage
of the embodiment is, however, the reduced possibilities for
thermal dissipation. Although not shown, it is thereto preferred
that the heatsink 180 on the second side of the device 100 is
provided with solder balls or other means for thermal coupling to
an external carrier.
[0072] FIG. 7 shows a further embodiment of the assembly 300, This
embodiment is, a more advanced version of the embodiment of FIG. 6.
It has the further feature that devices 200 are attached to both
the first side 1 and the second side 2 of the device 100. If
desired, a leadframe with heatsink could be used as shown in FIG.
5.
* * * * *