U.S. patent application number 14/967861 was filed with the patent office on 2017-06-15 for selective solder plating.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to QIANWEN CHEN, Bing Dang, Yu Luo, Joana Sofia Branquinho Teresa Maria.
Application Number | 20170167042 14/967861 |
Document ID | / |
Family ID | 59019573 |
Filed Date | 2017-06-15 |
United States Patent
Application |
20170167042 |
Kind Code |
A1 |
CHEN; QIANWEN ; et
al. |
June 15, 2017 |
SELECTIVE SOLDER PLATING
Abstract
A method provides a structure that includes a substrate having a
metal layer disposed on a surface and a metal feature disposed on
the metal layer. The method further includes immersing the
structure in a plating bath contained in an electroplating cell,
the plating bath containing a selected solder material; applying a
voltage potential to the structure, where the structure functions
as a working electrode in combination with a reference electrode
and a counter electrode that are also immersed in the plating bath;
and maintaining the voltage potential at a predetermined value to
deposit the selected solder material selectively only on the metal
feature and not on the metal layer. An apparatus configured to
practice the method is also disclosed.
Inventors: |
CHEN; QIANWEN; (Ossining,
NY) ; Dang; Bing; (Chappaqua, NY) ; Luo;
Yu; (Hopewell Junction, NY) ; Maria; Joana Sofia
Branquinho Teresa; (New York, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
59019573 |
Appl. No.: |
14/967861 |
Filed: |
December 14, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
B23K 35/262 20130101;
C25D 3/30 20130101; C25D 3/54 20130101; C25D 17/001 20130101; C25D
5/02 20130101; C25D 17/12 20130101; B23K 35/26 20130101; C25D 3/60
20130101; C25D 7/04 20130101; C25D 7/123 20130101; H01L 21/2885
20130101; H01L 23/147 20130101 |
International
Class: |
C25D 7/04 20060101
C25D007/04; C25D 3/30 20060101 C25D003/30; H01L 21/288 20060101
H01L021/288; C25D 5/02 20060101 C25D005/02; C25D 17/12 20060101
C25D017/12; B23K 35/26 20060101 B23K035/26; C25D 3/54 20060101
C25D003/54; C25D 3/60 20060101 C25D003/60 |
Claims
1. A method, comprising: providing a structure comprised of a
substrate having a metal layer disposed on a surface and a metal
feature disposed on the metal layer; immersing the structure in a
plating bath contained in an electroplating cell, the plating bath
comprising a selected solder material; applying a voltage potential
to the structure, where the structure functions as a working
electrode in combination with a reference electrode and a counter
electrode that are also immersed in the plating bath; and
maintaining the voltage potential at a predetermined value to
deposit the selected solder material selectively only on the metal
feature and not on the metal layer.
2. The method as in claim 1, where the metal layer is comprised of
Titanium and where the metal feature is comprised of Copper.
3. The method as in claim 1, where the selected solder material is
comprised of Indium.
4. The method as in claim 3, where the plating bath is comprised of
one of Indium Sulfate, Indium Chloride, Indium Methanesulfonate,
Indium Acetate or Indium oxide and is further comprised of a
conductivity salt or acid comprised of one of Sulfuric acid,
Hydrochloric acid, Methane Sulfonic acid or Sulfamic acid.
5. The method as in claim 4, where the plating bath is further
comprised of a wetting agent.
6. The method as in claim 1, where the selected solder material is
comprised of one of Tin, Tin-Silver, Tin-Silver-Copper, Indium-Tin,
Tin-Lead, Tin-Bismuth and Tin-Gold.
7. The method as in claim 1, where the metal layer is comprised of
Titanium, where the metal feature is comprised of Copper, where the
selected solder material is comprised of Indium, and where the
predetermined value of the voltage potential is in a range of about
1V to about 2V.
8. The method as in claim 1, where the metal layer is comprised of
Titanium, where the metal feature is comprised of Copper, where the
selected solder material is comprised of Indium, and where the
predetermined value of the voltage potential is in a range of about
1.875V to about 2V.
9. The method as in claim 1, where the reference electrode is
comprised of Ag/AgCl in 3M KCl, and where the counter electrode is
comprised of a Pt mesh.
10. The method as in claim 1, where the substrate comprises a
recess made in a surface thereof, where the metal feature has a
substantially circular ring shape, and where the recess is disposed
within a circumference of the metal feature.
11. An apparatus, comprising: a tank containing a plating bath of
an electroplating cell, the plating bath comprising a selected
solder material; a working electrode immersed in the plating bath,
the working electrode comprised of a structure that comprises a
semiconductor substrate having a metal layer disposed on a surface
and a metal feature disposed on the metal layer; a reference
electrode and a counter electrode immersed in the plating bath; and
a power supply connected with a potentiostat configured to maintain
a voltage potential of the working electrode at a predetermined
constant value with respect to the reference electrode to deposit
the selected solder material selectively only on the metal feature
and not on the metal layer.
12. The apparatus as in claim 11, where the metal layer is
comprised of Titanium and where the metal feature is comprised of
Copper.
13. The apparatus as in claim 11, where the selected solder
material is comprised of Indium.
14. The apparatus as in claim 13, where the plating bath is
comprised of one of Indium Sulfate, Indium Chloride, Indium
Methanesulfonate, Indium Acetate or Indium oxide and is further
comprised of a conductivity salt or acid comprised of one of
Sulfuric acid, Hydrochloric acid, Methane Sulfonic acid or Sulfamic
acid.
15. The apparatus as in claim 14, where the plating bath is further
comprised of a wetting agent.
16. The apparatus as in claim 11, where the selected solder
material is comprised of one of Tin, Tin-Silver, Tin-Silver-Copper,
Indium-Tin, Tin-Lead, Tin-Bismuth and Tin-Gold.
17. The apparatus as in claim 11, where the metal layer is
comprised of Titanium, where the metal feature is comprised of
Copper, where the selected solder material is comprised of Indium,
and where the predetermined constant value of the voltage potential
is in a range of about 1V to about 2V.
18. The apparatus as in claim 11, where the metal layer is
comprised of Titanium, where the metal feature is comprised of
Copper, where the selected solder material is comprised of Indium,
and where the predetermined constant value of the voltage potential
is in a range of about 1.875V to about 2V.
19. The apparatus as in claim 11, where the reference electrode is
comprised of Ag/AgCl in 3M KCl, and where the counter electrode is
comprised of a Pt mesh.
20. The apparatus as in claim 11, where the semiconductor substrate
is comprised of Silicon having a recess made in a surface thereof,
where the metal feature has a substantially circular ring shape,
where the recess is disposed within a circumference of the metal
feature, and where an edge of the recess is spaced apart from an
inner edge of the metal feature by a distance of about 10 .mu.m or
less.
Description
TECHNICAL FIELD
[0001] The embodiments of this invention relate generally to
soldering operations such as those used to create a seal and, more
specifically, relate to soldering operations performed over a
surface of a substrate containing apertures or voids (recessed
structures) in the surface, or raised structures on the
surface.
BACKGROUND
[0002] A seal made with low melting temperature solder can be
beneficial for certain devices such as devices formed on or in a
surface of a semiconductor wafer. However, solder alloys are
typically not compatible with some typically used semiconductor
wafer processing techniques such as plasma enhanced chemical vapor
deposition (PECVD) and deep reactive ion etch (RIE) processes. In
general it can be difficult to deposit and pattern photoresist on a
substrate surface, so as to selectively apply a desired solder,
after complex structures are fabricated on or in the substrate
surface such as deep vias (recessed structures) and/or raised
structures having a large topography.
SUMMARY
[0003] In a first aspect thereof the embodiments of this invention
provide a method that comprises providing a structure comprised of
a substrate having a metal layer disposed on a surface and a metal
feature disposed on the metal layer; immersing the structure in a
plating bath contained in an electroplating cell, the plating bath
comprising a selected solder material; applying a voltage potential
to the structure, where the structure functions as a working
electrode in combination with a reference electrode and a counter
electrode that are also immersed in the plating bath; and
maintaining the voltage potential at a predetermined value to
deposit the selected solder material selectively only on the metal
feature and not on the metal layer.
[0004] In another aspect thereof the embodiments of this invention
provide an apparatus that comprises a tank containing a plating
bath of an electroplating cell, the plating bath comprising a
selected solder material; a working electrode immersed in the
plating bath, the working electrode comprised of a structure that
comprises a semiconductor substrate having a metal layer disposed
on a surface and a metal feature disposed on the metal layer; a
reference electrode and a counter electrode immersed in the plating
bath; and a power supply connected with a potentiostat configured
to maintain a voltage potential of the working electrode at a
predetermined constant value with respect to the reference
electrode to deposit the selected solder material selectively only
on the metal feature and not on the metal layer.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0005] FIGS. 1A, 1B and 1C, collectively referred to as FIG. 1,
illustrate enlarged views of a structure wherein the various layer
thicknesses and other dimensions are not necessarily drawn to
scale. More specifically, FIG. 1A is a top view of the structure,
FIG. 1B is a cross-sectional view taken along the section line
labeled 1B-1B in FIG. 1A, and FIG. 1C is a further enlarged view of
a portion of the structure shown in FIG. 1B.
[0006] FIG. 2 shows one example of a conventional electroplating
cell.
[0007] FIG. 3 depicts a non-limiting example of a three electrode
electroplating cell that can be used to selectively plate solder on
a patterned substrate in accordance with embodiments of this
invention.
[0008] FIG. 4 is a graph depicting amperometry plots of Indium
plating on Cu/Ti using the electroplating cell of FIG. 3.
DETAILED DESCRIPTION
[0009] The word "exemplary" is used herein to mean "serving as an
example, instance, or illustration." Any embodiment described
herein as "exemplary" is not necessarily to be construed as
preferred or advantageous over other embodiments. All of the
embodiments described in this Detailed Description are exemplary
embodiments provided to enable persons skilled in the art to make
or use the invention and not to limit the scope of the invention
which is defined by the claims.
[0010] The embodiments of this invention will be described below
primarily in the context of a substrate that contains at least one
recessed feature such as a void or an opening or a trench in a
surface of the substrate. However, the embodiments of this
invention apply as well to a substrate having a raised feature
disposed on the surface. Furthermore, in some use-cases of interest
a given substrate could include at least one recessed feature and
at least one raised feature on the surface.
[0011] The embodiments of this invention provide a method to
selectively deposit solder plating onto a predefined plating area
without requiring the use of a layer of photoresist during the
solder plating operation. The use of the embodiments of this
invention can be especially beneficial when there are pre-existing
structures and/or pre-existing apertures or voids (e.g., deep
trenches) on and in the surface of a semiconductor wafer, where the
presence of such structures and/or voids would interfere with an
ability to deposit and pattern photoresist to define regions where
a selected solder material would be deposited.
[0012] Reference can be made to FIGS. 1A, 1B and 1C, collectively
referred to as FIG. 1, for showing enlarged views of an exemplary
structure of interest to the embodiments of this invention. FIG. 1A
is a top view of the structure, FIG. 1B is a cross-sectional view
taken along the section line labeled 1B-1B in FIG. 1A, and FIG. 1C
is a further enlarged view of a portion of the structure shown in
FIG. 1B. The structure is comprised of a substrate 10, e.g., a
Silicon (Si) substrate, having a metal layer 12, e.g., a Titanium
(Ti) layer, a Tantalum (Ta) layer, or a Titanium Tungsten alloy
(TiW) layer, disposed on a top surface thereof. A metal structure
also referred to herein as a metal feature, such as a ring 16,
e.g., a Copper (Cu) ring, is disposed on the Ti layer 12. Enclosed
within an area defined by the ring 16 is an aperture or recess 14
formed through the Ti layer 12 and partially into the Si substrate
10. As non-limiting dimensional examples the recess 14 could have a
diameter in a range of about 200 .mu.m to about 500 .mu.m and a
depth of about 100 .mu.m (or deeper), the Ti layer 12 could have a
thickness in a range of about 30 nm to about 60 nm, and the Cu ring
16 could have a height and a width that is less than about 10 .mu.,
for example in a range of about 1 .mu.m to about 2 .mu.m. The
spacing (Sp) between an inner edge of the Cu ring 16 and the outer
edge of the recess 14 could be, for example, about 10 .mu.m or
less.
[0013] The Cu feature 16 could have a shape other than circular,
such as an ovoid or a square or a rectangular shape, or a hexagonal
shape, or any desired regular or irregular shape. The circular
shape is shown simply for convenience. Likewise the recess 14 could
have other than the circular top opening shape as shown, and in
some embodiments the recess 14 could have other than the vertical
sidewalls that are illustrated.
[0014] FIG. 1C shows a portion of the structure, i.e., a portion of
the Si substrate 10, Ti layer 12 and metal (Cu) ring 16 on the left
side of the view of FIG. 1B, after performing a plating operation
to selectively form a solder plating layer 18 on the surface of the
Cu ring 16 and not on the surface of the surrounding Ti layer 12.
The solder plating layer 18 can then be used to solder bond a cover
(e.g., a solder, gold, or other type of solder wettable
metal-containing cover) over the recess 14 so as to seal (e.g.,
hermetically seal) the recess 14 from the ambient. In an exemplary
end-use of the structure the recess 14 could contain any desired
type of device or devices, such as one or more sensors, actuators,
energy storage devices and/or micro-electro-mechanical systems
(MEMS). The selected device or devices disposed within the recess
14 can be electrically contacted via the Si substrate 10.
[0015] In conventional practice the solder plating operation may
have involved depositing a dielectric layer (e.g. a layer of
photoresist) over the structure followed by a photolithographic
patterning operation to define and etch a circular trench in the
dielectric layer so as to expose the top surface of the Cu ring 16.
Next the desired solder plating material could be blanket deposited
over the patterned photoresist layer so as to also cover the top
surface of the Cu ring 16, followed by resist liftoff and cleaning.
As can be appreciated this approach would involve a time-consuming
multi-step deposition and liftoff process that would be complicated
by the presence of the recess 14 in close proximity to the Cu ring
16. As was noted above the spacing (Sp) between the ring 16 and the
edge of the recess 14 may be only about 10 .mu.m, making it
difficult to pattern the photoresist layer so close to the recess
14.
[0016] In accordance with aspects of this invention the solder
plating operation is performed without requiring the deposition and
patterning of a photoresist layer. Instead the solder plating
operation is performed using a multi-electrode electroplating cell
with a selected solder or solder alloy and plating bath.
[0017] As a point of reference FIG. 2 shows one example of a
conventional electroplating cell 20. In this example, the cell 20
includes a tank 22 that contains a tin plating bath 24. Immersed in
the bath 24 is a cathode 26, i.e., a substrate to be plated, and an
anode 28, e.g., tin metal. The cathode 26 and the anode 28 are
connected to a power supply 30. In an example the anode 28 is the
metal to be plated on the cathode 26 (e.g., Tin) or an insoluble
anode (e.g., platinized Titanium or Iridium oxide coated Titanium).
On the cathode 26 reduction takes place:
M.sup.n++ne.sup.-.fwdarw.M
2H.sup.++2e.sup.-.fwdarw.H.sub.2.
[0018] On the anode 28 oxidation takes place:
M.fwdarw.M.sup.n++ne.sup.-
2H.sub.2O.fwdarw.4H.sup.++O.sub.2+4e.sup.-.
[0019] FIG. 3 shows a more preferred example of an electroplating
cell that can be used in accordance with embodiments of this
invention to selectively deposit the solder plating layer 18 (e.g.,
a layer of Indium) only on the Cu ring 16 as in FIG. 1, and not on
the Ti layer 12. More specifically, FIG. 3 depicts a non-limiting
example of a three electrode electroplating cell 40 that can be
used to plate Indium solder on the patterned silicon wafer 10. In
the illustrated embodiment a tank 42 contains an Indium plating
bath 44. Immersed in the bath 44 is a working electrode 46, a
counter electrode 48 and a reference electrode 50. The three
electrodes are connected to the power supply via a potentiostat 52.
The potentiostat 52 functions by maintaining the potential of the
working electrode 46 at a desired constant level with respect to
the reference electrode 50 and passing the current at the counter
electrode 48. In the illustrated exemplary embodiment the working
electrode 46 is the Si wafer 10 having the Cu ring 16 that is to be
plated (as in FIGS. 1A and 1B), the reference electrode 50 can be
comprised of Ag/AgCl in 3M KCl, and the counter electrode 48 can be
comprised of a Pt mesh.
[0020] On the working electrode 46 reduction takes place as
follows:
In.sup.3-+3e.sup.-.fwdarw.In
2H.sup.++2e.sup.-.fwdarw.H.sub.2.
[0021] On the counter electrode 48 oxidation takes place as
follows:
2H.sub.2O.fwdarw.4H.sup.++O.sub.2+4e.sup.-.
[0022] In the presently preferred embodiments of this invention the
solder plating takes place under constant potential control. The
reference electrode 50, via the potentiostat 52, maintains a
constant electrical potential between the working electrode 46 and
the reference electrode 50, and current flows between the counter
electrode 48 and the working electrode 46.
[0023] Non-limiting examples of solder and solder alloys that can
be used in accordance with embodiments of this invention include,
in addition to Indium: Tin, Tin-Silver, Tin-Silver-Copper,
Indium-Tin, Tin-Lead, Tin-Bismuth and Tin-Gold. When using one of
the exemplary solders and solder alloys other than Indium the
composition of the plating bath 44 is adjusted accordingly.
[0024] When Indium is used as the solder plating material,
non-limiting examples of the composition of the Indium plating bath
44 that can be used in accordance with embodiments of this
invention include: a source of Indium metal such as but not limited
to Indium Sulfate, Indium Chloride, Indium Methanesulfonate, Indium
Acetate or Indium oxide. The Indium plating bath 44 also includes a
conductivity salt or acid such as, but not limited to, Sulfuric
acid, Hydrochloric acid, Methane Sulfonic acid or Sulfamic acid.
The Indium plating bath 44 also preferably includes a wetting agent
or grain refiner such as, but not limited to, about 0.01% to about
2% of organic molecules such as a surfactant.
[0025] Using the electroplating cell 40 of FIG. 3 the following was
observed for an electroplating condition of 1V vs. the Ag/AgCl
reference electrode 50, 2V vs. the Ag/AgCl reference electrode 50
and 3V vs. the Ag/AgCl reference electrode 50. Reference can also
be made to the amperometry plots in FIG. 4 (obtained from detection
of ions in solution based on electric current or changes in
electric current) of Indium plating on Cu/Ti.
[0026] For the 1V vs. the Ag/AgCl reference electrode 50 condition
the result was that selective Indium plating was achieved on the Cu
ring 16 and not on the surrounding surface of the metal layer 12.
The Indium deposit 18 was smooth, but the deposition rate was low,
i.e., less than 0.1 .mu.m/min.
[0027] For the 2V vs. the Ag/AgCl reference electrode 50 condition
the result was that selective Indium plating was achieved on the Cu
ring 16 and not on the surrounding surface of the metal layer 12.
The Indium deposit 18 was smooth, and the deposition rate was 0.8
.mu.m/min, i.e., a 4 .mu.m thickness Indium deposit was achieved in
5 min.
[0028] For the 3V vs. the Ag/AgCl reference electrode 50 condition
the result was that no selective Indium plating was achieved.
Instead it was observed that the Indium plated on both the surface
of the Cu ring 16 and on the surface of the Ti layer 12. The Indium
deposit 18 was found to be rough and not smooth, and the deposition
rate was very low, less than 0.1 .mu.m/min.
[0029] That is, the selective Indium plating on the Cu ring 16 over
the Ti layer 12 was found to occur in a range from about 1.0V to
about 2.0V, and the deposited Indium layer (solder plating layer
18) was observed to be visually smooth. A more optimum voltage
potential range to achieve the smooth selective Indium plating on
the Cu ring 16 was found to be in a range of about 1.875V to about
2.0V. However, at voltage potentials greater than about 2.0 V the
Indium was found to (slowly) plate on both the Cu ring 16 and on
the Ti layer 12, and the deposited Indium layer was observed to be
visually rough and not smooth.
[0030] The embodiments of this invention provide a method and
structure for selectively plating a solder material onto a metal
structure disposed over a metal layer on a surface of a substrate
using a voltage controlled three electrode plating cell. Although
there is one metal feature shown in the drawings, i.e., one Cu ring
16, in practice there could be many such features present and all
can be simultaneously plated with the desired solder material
during immersion in the bath 44. Furthermore, for those embodiments
where the recess or some other substrate structure is present it
need not be enclosed within and surrounded by the metal feature 16
as shown in FIG. 1.
[0031] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," when used in this
specification, specify the presence of stated features, integers,
steps, operations, elements, and/or components, but do not preclude
the presence or addition of one or more other features, integers,
steps, operations, elements, components, and/or groups thereof.
[0032] The corresponding structures, materials, acts, and
equivalents of all means or step plus function elements in the
claims below are intended to include any structure, material, or
act for performing the function in combination with other claimed
elements as specifically claimed. The description of the present
invention has been presented for purposes of illustration and
description, but is not intended to be exhaustive or limited to the
invention in the form disclosed. Many modifications and variations
will be apparent to those of ordinary skill in the art without
departing from the scope and spirit of the invention. The
embodiment was chosen and described in order to best explain the
principles of the invention and the practical application, and to
enable others of ordinary skill in the art to understand the
invention for various embodiments with various modifications as are
suited to the particular use contemplated.
[0033] As such, various modifications and adaptations may become
apparent to those skilled in the relevant arts in view of the
foregoing description, when read in conjunction with the
accompanying drawings and the appended claims. As but some
examples, the use of other similar or equivalent plating materials,
metal-containing substrates to be plated, plating solutions,
electrode materials and voltage potentials may be used by those
skilled in the art. However, all such and similar modifications of
the teachings of this invention will still fall within the scope of
this invention.
* * * * *