U.S. patent application number 15/414335 was filed with the patent office on 2017-05-11 for methods and apparatus for power supply.
The applicant listed for this patent is Infineon Technologies Austria AG. Invention is credited to Laura Carpenter, Kenneth Ostrom, Benjamim Tang.
Application Number | 20170133934 15/414335 |
Document ID | / |
Family ID | 41052932 |
Filed Date | 2017-05-11 |
United States Patent
Application |
20170133934 |
Kind Code |
A1 |
Tang; Benjamim ; et
al. |
May 11, 2017 |
Methods and Apparatus for Power Supply
Abstract
Methods and apparatus for a power supply according various
aspects of the present invention operate in conjunction with a
voltage converter for converting an input voltage to an output
voltage. For example, the converter may comprise an output
controller configured to generate a control signal, a power mode
controller, and an integrated power stage. The power stage may
include a multiple switch segments coupled in parallel between the
input voltage and the output, and a driver circuit responsive to
the output controller and the power mode controller and connected
to the switch segments. The driver circuit controls the switch
segments according to the control signal to activate the switch
segments in the switch circuit. The driver circuit also disables
one or more of the switch segments according to the power mode
signal to permit reduced power delivery and demand states.
Inventors: |
Tang; Benjamim; (Rancho
Palos Verdes, CA) ; Carpenter; Laura; (Palos Verdes
Estates, CA) ; Ostrom; Kenneth; (Palos Verdes
Estates, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Infineon Technologies Austria AG |
Villach |
|
AT |
|
|
Family ID: |
41052932 |
Appl. No.: |
15/414335 |
Filed: |
January 24, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12043261 |
Mar 6, 2008 |
9559590 |
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15414335 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H02M 1/088 20130101;
H02M 2001/0048 20130101; H02M 3/158 20130101; H02M 3/1584 20130101;
H02M 3/156 20130101; H02M 1/08 20130101 |
International
Class: |
H02M 3/158 20060101
H02M003/158; H02M 1/08 20060101 H02M001/08 |
Claims
1. A voltage converter for converting an input voltage to an output
voltage at an output, comprising: an output controller configured
to generate a control signal; a power mode controller configured to
generate a power mode signal corresponding to a power mode; a
plurality of switches coupled in parallel between the input voltage
and the output; and a driver circuit responsive to the output
controller and the power mode controller and connected to the
switches, wherein the driver circuit: controls the switches
according to the control signal; and disables at least one of the
switches according to the power mode signal.
2. The voltage converter of claim 1, wherein the switches and the
driver circuit are integrated on an integrated circuit chip.
3. The voltage converter of claim 2, wherein at least one of the
switches and the driver circuit comprises a hot-running element
that operates at a greater temperature than another component, and
wherein the hot-running component is positioned near an edge of the
electronic chip.
4. The voltage converter of claim 1, further comprising a capacitor
connected to the drive circuit and to a drive voltage, wherein the
capacitor has a capacitance sufficient to support the provision of
the first signal and the second signal sequentially, but not
sufficient to support the provision of the first signal and the
second signal simultaneously.
5. The voltage converter of claim 1, further comprising a second
plurality of switches coupled in parallel between the output and
ground, wherein each of the second plurality of switches has a
terminal coupled to a terminal of a corresponding switch in the
first plurality of switches.
6. The voltage converter of claim 4, wherein the driver circuit is
connected to the second plurality of switches, wherein: the driver
circuit controls the second plurality switches according to the
control signal; and the driver circuit deactivates a switch in the
second plurality of switches before activating the corresponding
switch in the first plurality of switches.
7. The voltage converter of claim 1, wherein the switches comprise
high-power MOSFETs.
8. A voltage converter for converting an input voltage from an
input voltage source to an output voltage at an output, comprising:
a pulse width modulation controller responsive to a reference
voltage and the output voltage, wherein the controller generates a
control signal according to a difference between the reference
voltage and the output voltage; a power mode controller configured
to generate a power mode signal corresponding to a first power mode
and a second power mode; a filter connected to the output; and an
integrated power stage, comprising: a plurality of control MOSFETs
coup led in parallel between the input voltage source and the
filter, wherein the control MOSFETs connect the input voltage
source to the filter when the MOSFETs are activated; a plurality of
synchronous MOSFETs coupled in parallel between the filter and
ground, wherein the synchronous MOSFETs connect the filter to
ground when the MOSFETs are activated; and a driver system,
comprising: a plurality of driver outputs, wherein a gate of each
of the control MOSFETs and synchronous MOSFETs is coupled to at
least one of the driver outputs; and a plurality of driver circuits
responsive to the control signal and coupled to the driver outputs,
wherein at least one of the driver circuits: generates either an
activation signal or a deactivation signal at a first driver output
in response to the control signal when the power mode signal
corresponds to the first power mode; and generates the deactivation
signal at the first driver output when the power mode signal
corresponds to the second power mode.
9. The voltage converter of claim 8, wherein at least one of the
MOSFETs, driver outputs, and delay circuit comprises a hot-running
element that operates at a greater temperature than another
component, and wherein the hot-running component is positioned near
an edge of an integrated circuit chip.
10. The voltage converter of claim 8, further comprising a
capacitor connected to the driver circuit and to a drive voltage,
wherein the capacitor has a capacitance sufficient to support the
generation of the first signal and the second signal sequentially,
but not sufficient to support the generation of the first signal
and the second signal simultaneously.
11. A method for converting an input voltage to an output voltage,
comprising: generating a control signal corresponding to a
difference between a reference voltage and the output voltage;
generating a power mode signal corresponding to either a first
power mode or a second power mode; connecting the input voltage to
an output via a plurality of switches in response to the control
signal when the power mode signal corresponds to the first power
state, wherein the switches are connected in parallel between the
input voltage and the output; and disabling at least one of the
switches when the power mode signal corresponds to the second power
state.
12. A method for converting an input voltage according to claim 11,
further comprising connecting the output to ground via a second
plurality of switches at or immediately after the first time,
wherein the second switches are connected in parallel between the
output and ground.
13. A method for converting an input voltage according to claim 11,
further comprising filtering the output voltage.
Description
BACKGROUND OF INVENTION
[0001] Many high power applications use switching power supplies,
in part due to the small area and volume they occupy. Converters
used for a typical switching power supply include active components
and passive components. For high power applications, the active
components are discrete, not integrated, because of the difficulty
associated with integrating high power components and controlling
heat dissipation.
[0002] Switching power supplies have a number of problems
associated with them. For example, the switching supplies require
power MOSFETs to handle the high currents required by the high
powered applications. These MOSFETs are significantly larger than
typical MOSFETs, and have high parasitic capacitances associated
with them, which reduce the overall performance of the system.
Further, the highly specialized drivers to the drive the large
gate-to-source capacitance of power MOSFETs must be very well
controlled. If the drivers are not well controlled, unnecessary
capacitive switching losses are introduced into the system.
[0003] Switching the power MOSFETs on and off also requires large
currents, which create a significant amount of system noise through
coupling and ground return path parasitics. The large currents
provided to the MOSFETs also create a drop in the power supply,
preventing the MOSFETs from turning on completely until the power
supply has recovered. The drop is due, in part, to the parasitic
inductance of the decoupling capacitor, which provides the
instantaneous power required to activate the MOSFETs.
[0004] In addition, the MOSFETs are timed to ensure that one is
fully off before the other turns on, creating a large non-overlap
time and causing losses to power efficiency. The timing between
turning on one transistor and turning off another are set up to
minimize shoot-thru current which occurs when both transistors are
on. This is done by ensuring that one FET is fully off before
turning on the other FET, which is controlled by non-overlap logic.
In discrete power stages, the non-overlap time can be significant,
causing loss in power efficiency because the output current must be
provided by a diode during the non-overlap time.
SUMMARY OF THE INVENTION
[0005] Methods and apparatus for a power supply according various
aspects of the present invention operate in conjunction with a
voltage converter for converting an input voltage to an output
voltage. For example, the converter may comprise an output
controller configured to generate a control signal, a power mode
controller, and an integrated power stage. The power stage may
include a multiple switch segments coupled in parallel between the
input voltage and the output, and a driver circuit responsive to
the output controller and the power mode controller and connected
to the switch segments. The driver circuit controls the switch
segments according to the control signal to activate the switch
segments in the switch circuit. The driver circuit also disables
one or more of the switch segments according to the power mode
signal to permit reduced power delivery and demand states.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] A more complete understanding of the present invention may
be derived by referring to the detailed description and claims when
considered in connection with the following illustrative figures.
In the following figures like reference numbers refer to similar
elements and steps throughout the figures.
[0007] FIG. 1 is a block diagram of a power supply connected to a
load.
[0008] FIG. 2 is a schematic of a switching power supply according
to various aspects of the present invention.
[0009] FIG. 3 is a flow diagram representing operation of a power
supply.
[0010] Elements and steps in the figures are illustrated for
simplicity and clarity and have not necessarily been rendered
according to any particular sequence. For example, steps that may
be performed concurrently or in different order are illustrated in
the figures to help to improve understanding of embodiments of the
present invention.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS
[0011] The present invention may be described in terms of
functional block components and various processing steps. Such
functional blocks may be realized by any number of hardware or
software components configured to perform the specified functions
and achieve the various results. For example, the present invention
may employ various switches that may be implemented in any
appropriate manner, such as using field effect transistors, diodes,
latches, bipolar transistors, and the like, which may carry out a
variety of functions. In addition, various aspects of the present
invention may be practiced in conjunction with a variety of
converter and/or control applications, and the system described is
merely one exemplary application for the invention. Further, the
present invention may employ any number of conventional techniques
for regulating a power supply, driving a switch, controlling a
driver, filtering a signal, implemented a logic gate, and the
like.
[0012] Various representative implementations of the present
invention may be implemented in conjunction with a power supply.
The power supply may comprise, for example, a converter using
step-down, step-up, buck, boost, buck-boost, forward, flyback,
half-bridge, full-bridge, and/or SEPIC topologies. Referring now to
FIG. 1, a switching power supply 100 according to various aspects
of the present invention comprises a buck converter including an
output controller 101, a power mode controller 140, a filter 105,
and a power stage 160. Generally, the output controller 101
provides a control signal to the power stage 160 to control the
output of the power stage 160. The power stage 160 responds to the
control signal to maintain, increase, or decrease the output
voltage and/or current provided to a load 98. The filter 105
smoothes the output signal to supply a relatively level output
voltage. The power mode controller 140 controls whether the
switching power supply 100 operates in a regular power mode or a
reduced power mode.
[0013] The switching power supply 100 may be adapted for high power
applications, such as providing high current at low voltages, such
as for supplying high-performance integrated circuits tike
microprocessors, graphics processors, and network processors. The
switching power supply 100 may be adapted to be placed as close as
possible to the load to minimize board trace losses, for example in
a distributed power supply system referred to as "Point-of-Load".
The switching power supply 300 may also be optimized for high
efficiency and small area and volume requirements.
[0014] For example, the components can be integrated, partially
integrated (e.g., just the drivers and switches), or discrete. In
the present embodiment, the switching power supply 100 comprises an
integrated power stage 160 configured for high current
applications, such as about 10 to 50 amperes. The integrated power
stage 160 may either fully integrate all components, or partially
integrate a few components. For example, integrating a driver
circuit 115 and a switch circuit 116 of the power stage 160 may
significantly reduce or eliminate parasitic capacitances and
inductances associated with the critical swing, input voltage,
ground, and switch gates compared to a discrete implementation.
[0015] The output controller 101 controls the power stage 160 to
regulate the output, such as the voltage, current, and/or
frequency. The output controller 101 may comprise any appropriate
system and operate in any suitable manner to control the power
stage 160, such as a feedback amplifier or pulse width modulation
(PWM) controller. For example, the output controller 101 may sense
an output voltage, such as via a feedback loop 106, and compare the
output voltage to a reference voltage. The output controller 101
may then adjust the power stage 160 to maintain or change an output
voltage of the power stage 160.
[0016] In the present embodiment, the output controller 101
comprises a PWM controller. The PWM controller controls the power
stage 160 by comparing the output voltage of the power stage 160 to
a reference voltage and varying the duty cycle of the control
signal provided to the power stage 160. The output voltage may be
scaled relative to the reference voltage through the use of a
resistive divider or similar circuit.
[0017] The power mode controller 140 controls whether the power
supply 100 operates in a regular power mode or a reduced power
mode. The power mode controller 140 controls the power stage 160,
for example by providing a power mode signal to the power stage
160. In the present embodiment, the power mode controller 140
determines whether the power supply 100 should operate in a regular
power mode or a reduced power mode, and supplies a corresponding
signal to the power stage 160.
[0018] The power mode controller 140 may comprise any suitable
system for controlling the power mode of the power supply 100, such
as a processor, a sensor, a control system, a feedback element, a
timer, or other system that generates the power mode signal. In the
present embodiment, the power mode controller 140 comprises a logic
element that detects when a reduced power mode may be appropriate,
such as in response to a sleep signal, a hibernation mode,
inactivity over a selected period, activation of a screen saver, a
heat sensor, or the like.
[0019] The filter 105 smoothes the output of the power stage 160.
The filter 105 may comprise any appropriate system for smoothing
the power stage 160 output, such as an analog or digital filter,
and may comprise any device or combination of devices for
regulating a voltage, such as capacitors, resistors, inductors,
integrated circuits, and the like. In an exemplary embodiment,
referring to FIGS. 2 and 3, the filter 105 comprises an output
inductor 112 and an output capacitor 113. The output inductor 112
may comprise a conventional inductor comprising, for example, wire
wound around a core or a conducting loop embedded in a core. In the
present embodiment, the output inductor 112 is configured to handle
the load current without saturating and have low series resistance,
such as less than about 1 mohm, to minimize thermal loss. Typical
values for the output inductor 112 may be, for example, 50 nH to 1
uH, and for the output capacitor 113 about 100 uF to 1000 uF. In
various embodiments, the filter 105 may be omitted, for example if
the power supply 100 docs not require a level output voltage or
includes a dedicated input filter.
[0020] The power stage 160 supplies power according to the control
signal from the output controller 101 and the power mode signal
from the power mode controller 140. The power stage 160 is directly
or indirectly connected to the output controller 101, power mode
controller 140, and the filter 105 such that the power stage 160
responds to the control signal from the output controller 101 and
the power mode signal from the power mode controller 140 to control
the output provided to the filter 105. In the present embodiment,
the power stage 160 includes an input connected to the controller
to receive the control signal, an input connected to the power mode
controller 140 to receive the power mode signal, and an output
connected to the filter 105.
[0021] The power stage 160 may comprise any circuit or other system
for providing power according to the control signal and the power
mode signal, such as an amplifier or converter. In the present
embodiment, the power stage 160 comprises a step-down converter or
other system for converting an input voltage into an output
voltage. The present step-down converter increases average output
voltage in response to a longer duty cycle of the control signal,
and conversely decreases average output voltage in response to a
shorter duty cycle. For example, referring again to FIGS. 2 and 3,
the power stage 160 may comprise a segmented switch circuit 116
comprising one or more switches 103, 104 and a segmented driver
circuit 115 comprising one or more drivers 102, 108, 109. Each
segment may include one control switch, one synchronous switch and
one driver or may include multiple switches and drivers. The
switches 103, 104 alternately supply higher and lower signals to
the filter 105. The drivers 102, 108, 109 control the switches 103,
104 according to the control signal. The segmented aspect of the
integrated power stage 160 facilitates dynamic transition control
for activating and deactivating the switches 103, 104, and permits
the power stage 160 to operate in multiple power modes.
[0022] The power stage 160 may comprise any appropriate number of
switches 103, 104 and drivers 102, 108, 109. Although FIGS. 2 and 3
illustrate eight drivers and eight switches, the power stage 160
may include any suitable number of drivers and switches, such as
twelve control switches 103, twelve synchronous switches 104, two
leading drivers 102, ten control drivers 109, and ten synchronous
drivers 108.
[0023] The various components may be placed on an Integrated
circuit chip in any manner. For example, the hotter-running
components may be placed near the edge of the chip. Integrating the
drivers and the switches on the chip allows for all signals to be
internal to the chip and the drivers and output devices may be
segmented so as to avoid increasing the total area requirement and
have individual control over each segment. Also, the integration
may significantly reduce or eliminate parasitic capacitance and
inductances. The power stage 160 may, however, be implemented in
any suitable manner to allow it to receive the signal from the
output controller 101 and output a voltage based on that
signal.
[0024] The driver circuit 115 controls the switch circuit 116
according to the control signal and the power mode signal. For
example, if the control signal indicates that the output voltage
should be increased, the driver circuit 115 adjusts the switch
circuit 116 to increase the output voltage of the power stage 160.
Conversely, if the control signal indicates that the output voltage
should be decreased, the driver circuit 115 adjusts the switch
circuit 116 to decrease the output voltage of the power stage 160.
The driver circuit 115 receives the control signal, directly or
indirectly, from the output controller 101, and the driver circuit
115 is directly or indirectly connected to the switch circuit 116
to control the switches 103, 104.
[0025] The power (node controller 140 controls the power mode of
the power stage by sending one or more signals to the driver
circuit 115. If the power mode controller 140 requires a regular or
higher power availability, the power mode controller 140 may
provide a corresponding signal to the driver circuit 115. The
driver circuit 115 may then control the switch circuit 116 to
ensure the availability of the higher power. On the other hand, if
the power mode controller 140 requires a lower power availability,
the corresponding signal delivered to the driver circuit 115 causes
the driver circuit 115 to reduce the power delivery capability of
the switching circuit 116.
[0026] In the present embodiment, the driver circuit 115 includes a
leading driver circuit 102 connected to the output controller 101
to receive the control signal and a set of selective drivers 108,
109 to propagate the control signal to different elements of the
switch circuit 116. The driver circuit 115 may comprise any system
for selectively propagating the control signal to elements of the
switch circuit 116, such as a processor-based system generating
control signals or a digital logic circuit. In the present
embodiment, the selective drivers 108, 109 comprise driver circuits
to provide sufficient current to activate the high-power MOSFETs in
the switch circuit 116, such as amplifiers, buffers, or logic
gates, connected in series so that the first driver receives the
control signal, and each subsequent driver receives the output from
a preceding driver. The output of each driver is also connected to
the switch circuit 116. The switch circuit 116 thus receives a
signal from each driver in response to the control signal, with
each subsequent driver generating the signal in response to
receiving the signal the preceding driver.
[0027] The present driver circuit is also configured to selectively
activate portions of the switch circuit 116 in response to the
power mode signal. For example, each driver may receive the power
mode signal or a portion of the power mode signal. The various
drivers may respond to the power mode signal by disabling a portion
of the switch circuit 116 regardless of the control signal.
Consequently, in a lower power mode, portions of the switch circuit
116 may be disabled, regardless of the control signal, while other
portions remain enabled and available to deliver power. The enabled
portions may thus satisfy the reduced power requirements of the
load, while the disabling other portions reduces noise and
switching losses and improves low-load efficiency.
[0028] Referring to FIGS. 2 and 3, the present driver circuit 115
comprises two leading drivers 102, a series of synchronous drivers
108, and a series of control drivers 109, The leading drivers 102
receive the control signal from the output controller 101. The
control signal is transmitted by the leading drivers 102 to the
synchronous and control drivers 108, 109. Depending on the output
of the output controller 101, the drivers 102, 108, 109 either
apply or restrict voltage to the switches 103, 104. Each control
driver 109 and synchronous driver 108 receives the control signal
from the leading drivers 102 and any preceding drivers. The
segmented nature of the driver circuit 115 and the switch circuit
116 makes it possible to operate the switches 103, 104 using
smaller voltages and/or currents, which tends to reduce switching
noise, prevent large sudden power demands for driving the switch
circuit 116, reduce the non-overlap time required to avoid
shoot-through current, and increase the reliability of the
system.
[0029] Each of the control drivers 109 and synchronous drivers 108
also receives the power mode signal. When the power mode signal
indicates a regular power mode, each of the drivers 108, 109 is
enabled and operates the corresponding switch segment according to
the control signal. When the power mode signal indicates a reduced
power mode, one or more of the drivers 108, 109 is disabled and
deactivates the corresponding switches, regardless of the control
signal.
[0030] The drivers 102, 108, 109 may comprise any system for
providing a signal to an electrical switch and relaying the signal
to other components, such as a logic gate, a CMOS gate, an
amplifier, a transistor, electromagnetic relays and the like. In
the present embodiment, the drivers 102, 108, 109 comprise
programmable integrated logic gates. The drivers 102, 108, 109 may
be set to any type of control logic, such as OR, NOR, AND, and XOR,
and may include delay logic which delays transmitting the control
signal from the output controller 101 to the subsequent driver.
Also, the drivers 102, 108, 109 may be implemented with any
combination of logic or components, for example, the drivers 102,
108, 109 may be implemented with only a few drivers responding to
the power mode signal, ail of the drivers responding to the power
mode signal, or different drivers responding to different power
mode signals, which facilitates operation in more than two power
modes.
[0031] The drivers 102, 108, 109 may be configured to provide
appropriate voltage and/or current to control the switches 103,
104. For example, if the switches 103, 104 have large gate
capacitances for activating the switches, the drivers 102, 108, 109
may generate high peak currents, such as about five amperes. In
addition, the drive level of the drivers 102, 108, 109 may be
controlled to provide sufficient voltage to fully turn on the
switches 103, 104, but no higher than necessary so that capacitive
switching losses are minimized.
[0032] The leading drivers 102 receive the control signal from the
output controller 101 and transmit responsive signals to the switch
circuit 116 and to the control drivers 109 and synchronous drivers
108. The leading drivers 102 are directly or indirectly connected
to the output controller 101 to receive the control signal, and to
the switch circuit 116 and the control drivers 109 and synchronous
drivers 108 to propagate the control signal. The leading drivers
102 may comprise any system for receiving and propagating the
control signal at appropriate power levels and times, such as
amplifiers or buffers. In addition, the leading drivers 102 may be
connected to the power mode controller 140 to receive the power
mode signal. In the present embodiment, the leading drivers are not
responsive to the power mode signal, and are thus always
enabled.
[0033] In the present embodiment, the leading drivers 102 comprise
an inverting driver 111 and a non-inverting driver 110, each of
which has an input connected to the output controller 101 to
receive the control signal. The non-inverting driver 110 output is
connected to the gate of the first control switch 124 and the input
of the first control driver 121. Likewise, the inverting driver 111
output is connected to the gate of the first synchronous switch 128
and the input of the first synchronous driver 118. Thus, the
synchronous and control drivers 108, 109 do not receive the control
signal from the output controller 101 until the leading drivers 102
have received the control signal.
[0034] The control drivers 109 propagate the control signal to the
remaining control switches 103. The control drivers 109 may
comprise a series of drivers 121, 122, 123, and may comprise any
suitable number of drivers, such as one, four, twelve or more. The
first control driver 121 is electrically connected to the
non-inverting driver 110, and each remaining control driver 122,
123 is connected to the output of the preceding control driver 121,
122. Thus, the control drivers 109 do not receive the propagating
control signal from the output controller 101 until the
non-inverting driver 110 and all preceding control drivers 109 have
received the signal, in response to receiving the propagating
control signal, each control driver 109 provides the control
signal, after a selected delay, to the following control driver and
a corresponding control switch 103.
[0035] Each control driver 123, 122, 123 also receives the power
mode signal and is either enabled or disabled accordingly. For
example, each control driver 121, 122, 123 may be implemented as an
AND gate receiving the propagating control signal at a first input
and the power mode signal at a second input. As a result, the
control driver 121, 122, 123 does not activate its corresponding
switch segment unless the power mode signal is high. If the power
mode signal is low, the control driver 121, 122, 123 is effectively
disabled.
[0036] Activating the control switches 103 may require a
significant amount voltage and/or current. The drivers 108, 109 may
provide this gate charge by drawing high currents from a voltage
source V.sub.dr. The driver voltage source V.sub.dr may be any
system or component capable of providing power, such as a
capacitor, a battery, an inductor or the like. Additionally, the
driver voltage source V.sub.dr may include a device for regulating
the voltage, such as a diode, a transistor, a capacitor, or an
inductor. The power stage 160 may operate without a separate driver
voltage and the voltage may be provided by the input voltage, the
output controller 101, or any other appropriate component.
[0037] If the voltage source V.sub.dr cannot provide for a large
instantaneous change in the current, for example due to its output
inductance, the power stage 160 may include a decoupling capacitor
132 connected to the voltage source V.sub.dr and the power inputs
of the non-inverting driver 110 and the control drivers 109.
Because the segmented power stage 160 permits staggering the
turn-on times of each segment of the switch circuit 116, for
example by associating a delay with each control driver 108 and
synchronous driver 109, less instantaneous current is required,
causing less droop than simultaneous turn-on. Consequently, a
smaller decoupling capacitance with higher parasitic inductance may
be used than in systems utilizing a single activation current.
[0038] The synchronous drivers 108 propagate the inverse of the
control signal to the remaining synchronous switches 104. The
synchronous drivers 108 may comprise a series of drivers 118, 119,
120, and may comprise any suitable number of drivers, such as one,
four, twelve or more. The first synchronous driver 118 is
electrically connected to the inverting driver 111, and each
remaining synchronous driver 119, 120 is connected to the output of
the preceding synchronous driver 118, 119. Thus, the synchronous
drivers 108 do not receive the propagating inverse control signal
from the output controller 101 until the inverting driver 111 and
all preceding synchronous drivers 109 have received the signal. In
response to receiving the propagating inverse control signal, each
synchronous driver 108 provides the inverted control signal, after
a selected delay, to the following synchronous driver and a
corresponding synchronous switch 103.
[0039] Each synchronous driver 118, 119, 120 also receives the
power mode signal and is either enabled or disabled accordingly.
For example, like the control drivers 121, 122, 123, each
synchronous driver 118, 119, 120 may be implemented as an AND gale
receiving the propagating control signal at a first input and the
power mode signal at a second input. As a result, the synchronous
driver 118, 119, 120 does not activate its corresponding switch
segment unless the power mode signal is high. If the power mode
signal is low, the synchronous driver 118, 119, 120 is effectively
disabled.
[0040] Thus, the leading, synchronous, and control drivers 102,
108, 109 control the control and synchronous switches 103, 104
based on the output from the PWM output controller 101 and the
power mode controller 140. The drivers 102, 108, 109 control the
switches 103, 104 by applying and restricting voltage. When the
control signal Is high, the noninverting driver 110 and the control
drivers 109 sequentially activate the control switches 103, and the
inverting driver 111 and the synchronous drivers sequentially
deactivate the synchronous switches. Likewise, when the control
signal is low, the noninverting driver 110 and the control drivers
109 sequentially deactivate the control switches 103, and the
inverting driver 111 and the synchronous drivers sequentially
activate the synchronous switches. When the power mode signal is
low, the drivers 108, 109 that respond to the power mode signal are
disabled, opening the corresponding switches 103, 104 in the switch
circuit 116.
[0041] The switch circuit 116 performs the step-down function for
the power supply by alternately connecting two voltages, for
example the main supply voltage 99 and ground, to the output of the
power stage 160. The switch circuit 116 is connected to the main
supply 99 and ground, and periodically alternately connects the
output of the switch circuit 116 to the main supply 99 and to
ground according to the signals from the driver circuit 115. The
switch circuit 116 may comprise any suitable system for controlling
the voltage and/or current supplied to the output, such as a
physical switch, latch, relay, transistor, diode, amplifier, or the
like. In the present embodiment, the switch system 116 is fully
switched so that the switch circuit 116 is substantially either
fully on or fully off.
[0042] In the present embodiment, the switch circuit 116 comprises
the control switches 103 and the synchronous switches 104. The
control switches 103 are activated to selectively connect the
output to the main supply 99 according to signals from the control
driver circuit 115, and the synchronous switches 104 are activated
to selectively connect the output to ground according to signals
from the synchronous driver circuit 116. If the control switches
103 are turned on and the synchronous switches 104 are turned off,
the output voltage of the power stage 160 charges the filter 105.
If the synchronous switches 104 are turned on and the control
switches 103 are turned off, then the power stage 160 output is
connected to ground and the filter 105 discharges to the load. If
the control switches 103 are turned off and the synchronous
switches 104 are turned off, such as in a reduced power mode, the
corresponding switch segment is inactive.
[0043] In the present exemplary embodiment, the switches 103, 104
comprise field effect transistors, such as high-current MOSFETs,
for example rated for currents in a range of about 10 A to 50 A.
The MOSFETs may be selected according to any appropriate criteria,
such as power delivery efficiency performance, desired load current
delivery requirements, the relative size of the drivers, the
relative sizes of the control power MOSFETs and synchronous power
MOSFETs, and the ratio of NMOS to PMOS area in the driver
circuitry.
[0044] The switches 103, 104 activate or turn on, closing an open
connection, when sufficient voltage and/or current, is applied to
the gate, and deactivate or turn, off when the voltage and/or
current is removed, opening the connection. In some applications,
the control and synchronous MOSFETs may need to handle high
currents, such as about 10 A to about 50 A, and are significantly
larger than typical MOSFETs. The parasitic capacitance of such
devices may be relatively high (typically around 10 nF), and the
gate to source capacitance (Cgs), gate to drain capacitance (Cgd),
and drain to source capacitance (Cds) may be significant
contributors to the overall performance of the switching power
supply 100.
[0045] The control switches 103 selectively connect the main supply
voltage 99 to the filter 105 and load 98 according to signals from
the leading drivers 102 and control drivers 109. The control
switches 103 may comprise any suitable number of switches, shown in
FIGS. 2 and 3 as four MOSFETs 124, 125, 126, 127. Each control
MOSFET 124, 125, 126, 127 has a terminal connected to the main
supply 99 and a terminal connected to the load 98 via the filter
105. Thus, when each control MOSFET 124, 125, 126, 127 is
activated, it connects the main supply 99 to the filter 105 and
load 98. The gate of the first control MOSFET 124 is connected to
the output of the non-inverting driver 110, and the gates of the
remaining control MOSFETs 125, 126, 127 are connected to the
outputs of the control drivers 121, 122, 123, respectively.
[0046] In the present embodiment, the control MOSFETs' 124, 125,
126, 127 gate voltage levels may be set relative to their sources.
The node is referred to as the swing node, as the node swings from
ground to the input voltage, and the gate voltage tracks these
transitions. The control drivers are boot-strapped drivers having
their negative terminals lied to the swing node and positive
terminals is fixed relative to the swing node.
[0047] The synchronous switches 104 selectively connect the input
of the filter 105 to ground according to signals from the leading
drivers 102 and synchronous drivers 108. The synchronous switches
104 may comprise any suitable number of switches, shown in FIGS. 2
and 3 as four MOSFETs 128, 129, 130, 131. Each synchronous MOSFET
128, 129, 130, 131 has a terminal connected to ground and a
terminal connected to the load via the filter 105. Thus, when each
synchronous MOSFET 128, 129, 130, 131 is activated, it connects the
input of the filter 105 to ground. The gate of the first
synchronous MOSFET 128 is connected to the output of the inverting
driver 110, and the gates of the remaining synchronous MOSFETs 129,
130, 131 are connected to the outputs of the synchronous drivers
118, 119, 120, respectively, hi operation, referring to FIG. 3, the
output controller 101 receives a reference voltage signal and a
feedback signal via the feedback loop 106, and varies the duty
cycle of the control signal according to the difference (310). If
the output controller 101 asserts a high control signal (312), the
non-inverting driver 110 activates the first control switch 124 and
the inverting driver 111 deactivates the first synchronous switch
128 (314). If the output controller 101 outputs a low control
signal, the non-inverting driver 110 deactivates the first control
switch 124 and the inverting driver 111 activates the first
synchronous switch 128 (316).
[0048] The control signal is provided to the control drivers 109
and the synchronous drivers 108 (318). If the power mode signal for
each control driver 109 indicates a regular power mode (320), the
drivers 108, 109 are enabled and operate the control switches 125,
126, 127 and the synchronous switches 129, 130, 131 according to
the control signal (322). If the power mode signal indicates a
reduced power mode, one or more of the drivers 108, 109 are
disabled and the control switches 125, 126, 127 and the synchronous
switches 129, 130, 331 are deactivated (324).
[0049] In another exemplary embodiment, the control switches 103
and/or the synchronous switches 104 may be activated and/or
deactivated simultaneously without propagating the control signal
through a chain of drivers. For example, when the output controller
101 asserts a high control signal, the non-inverting driver 110 may
receive the signal, activate the first control switch 124, and the
linked control drivers 209 may receive the signal sequentially and
sequentially activate the remaining control switches 125, 126, 127.
The inverting driver 111 and the linked synchronous drivers 108
receive the signal simultaneously, for example using a three-input
AND gate instead of a two-input gate with the third input connected
to the inverse of the control signal, which deactivates the
synchronous switches 104 at the same time. Conversely, when the
output controller 101 asserts a low control signal, the
non-inverting driver 110 and the linked control drivers 109 receive
the signal simultaneously, for example using another set of
three-input AND gates instead of a two-input gate with the third
input connected to the control signal, deactivating the control
switches 103 at the same time. The inverting driver 111 receives
the signal and activates the first synchronous switch 128. The
linked synchronous drivers 108 receive the signal sequentially and
sequentially activate the remaining synchronous switches 129, 130,
131.
[0050] The segmented circuit 116 facilitates noise reduction by
reducing the amplitude of the current being switched. Lower
currents are required to activate the several integrated MOSFETs
than are required for conventional, discrete MOSFETs. The system
noise associated with switching large currents through coupling and
ground return path parasitics may be significantly reduced by
staggering the activation and deactivation of each segment. Thus,
switching noise may be reduced by staggering the activation and
deactivation of each segment of the power stage 160.
[0051] In addition, the present integrated segmented power stage
and the staggered timing allow the non-overlap time to be
minimized. For example, the integrated nature of the power stage
160 permits the lighter control of the timing because all signals
are internal to the chip. In addition, slight overlap is not as
critical because not all segments are on, and any shoot-thru
current that might occur is significantly lower.
[0052] Further, the segmented power stage 160 facilitates
optimizing the reliability of the power stage 160. For example, the
layout of the components may affect the performance of the chip.
Components positioned closer to the edge of the chip or closer to
the output pads may operate at different temperatures. Controlling
which power segments are activated and deactivated according to
placement on the chip may facilitate better power dissipation in
"hot" spots.
[0053] The segmented power stage also facilitates multiple power
delivery modes. Switching segments may be disabled in response to
low power demand, such as when the output current is significantly
below the maximum current, minimizing the switching losses. By
scaling the power stage for anticipated low current conditions, the
switching loss may be minimized and low load efficiency improved,
such as in devices that mostly operate in a low power or standby
state, and only occasionally operate under maximum load
conditions.
[0054] Multiple power modes may also be adopted for multiple
anticipated low power operating modes. For example, a system may
expected to operate in a full active mode requiring full power
availability, an intermediate mode requiring 50% of full power
(such as to keep a monitor and a hard drive operating, but when a
processor is largely idle), and a sleep mode requiring 5% of full
power (such as when a computer is in standby mode). The power
supply 100 may be adapted to accommodate all three modes, for
example using a three-level or two-bit power mode signal and driver
logic to accommodate the three levels to that all of the switch
segments 103, 104 are enabled for the first power mode, half of the
switch segments 103, 104 are enabled for the second power mode, and
only one or a few of the switch segments 103, 104 are enabled for
the third.
[0055] In the foregoing specification, the invention has been
described with reference to specific exemplary embodiments. Various
modifications and changes may be made, however, without departing
from the scope of the present invention as set forth in the claims.
The specification and figures are illustrative, rather than
restrictive, and modifications are intended to be included within
the scope of the present invention. Accordingly, the scope of the
invention should be determined by the claims and their legal
equivalents rather than by merely the examples described.
[0056] For example, the steps recited in any method or process
claims may be executed in any order and are not limited to the
specific order presented in the claims. Additionally, the
components and/or elements recited in any apparatus claims may be
assembled or otherwise operationally configured in a variety of
permutations and are accordingly not limited to the specific
configuration recited in the claims.
[0057] Benefits, other advantages and solutions to problems have
been described above with regard to particular embodiments;
however, any benefit, advantage, solution to problem or any element
that may cause any particular benefit, advantage or solution to
occur or to become more pronounced are not to be construed as
critical, required or essential features or components of any or
all the claims.
[0058] As used herein, the terms "comprise", "comprises",
"comprising", "having", "including", "includes" or any variation
thereof, are intended to reference a non-exclusive inclusion, such
that a process, method, article, composition or apparatus that
comprises a list, of elements does not include only those elements
recited, but may also include other elements not expressly listed
or inherent to such process, method, article, composition or
apparatus. Other combinations and/or modifications of the
above-described structures, arrangements, applications,
proportions, elements, materials or components used in the practice
of the present invention, in addition to those not specifically
recited, may be varied or otherwise particularly adapted to
specific environments, manufacturing specifications, design
parameters or other operating requirements without departing from
the general principles of the same.
* * * * *