U.S. patent application number 14/873494 was filed with the patent office on 2017-04-06 for methods of forming metal silicides.
The applicant listed for this patent is ASM IP Holding B.V.. Invention is credited to Jacob Huffman Woodruff.
Application Number | 20170098545 14/873494 |
Document ID | / |
Family ID | 58360113 |
Filed Date | 2017-04-06 |
United States Patent
Application |
20170098545 |
Kind Code |
A1 |
Woodruff; Jacob Huffman |
April 6, 2017 |
METHODS OF FORMING METAL SILICIDES
Abstract
A method of forming a metal silicide can include depositing an
interface layer on exposed silicon regions of a substrate, where
the interface layer includes a silicide forming metal and a
non-silicide forming element. The method can include depositing a
metal oxide layer over the interface layer, where the metal oxide
layer includes a second silicide forming metal. The substrate can
be subsequently heated to form the metal silicide beneath the
interface layer, using silicon from the exposed silicon regions,
the first silicide forming metal of the interface layer and the
second silicide forming metal of the metal oxide layer.
Inventors: |
Woodruff; Jacob Huffman;
(Scottsdale, AZ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ASM IP Holding B.V. |
Almere |
|
NL |
|
|
Family ID: |
58360113 |
Appl. No.: |
14/873494 |
Filed: |
October 2, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/78 20130101;
H01L 21/76889 20130101; H01L 21/28562 20130101; H01L 21/76895
20130101; H01L 21/76843 20130101; H01L 21/32053 20130101; H01L
29/66515 20130101; H01L 21/76855 20130101; H01L 21/28556 20130101;
H01L 29/665 20130101; H01L 21/28568 20130101; H01L 21/28518
20130101 |
International
Class: |
H01L 21/285 20060101
H01L021/285; H01L 21/768 20060101 H01L021/768 |
Claims
1. A method of forming a metal silicide, comprising: depositing an
interface layer on exposed silicon regions of a substrate, the
interface layer comprising a first silicide forming metal and a
non-silicide forming element; depositing a metal oxide layer over
the interface layer, wherein the metal oxide layer comprises a
second silicide forming metal; and heating the substrate to form
the metal silicide beneath the interface layer, the metal silicide
comprising silicon from the formerly exposed silicon regions, first
silicide forming metal from the interface layer, and second
silicide forming metal from the metal oxide layer, wherein
depositing the interface layer comprises a plurality of cycles of a
vapor deposition process, each cycle of the plurality of cycles
comprising alternately and sequentially contacting the surface of
the substrate with a first vapor phase precursor comprising the
first silicide forming metal and a second vapor phase precursor
comprising the non-silicide forming element, wherein the first
vapor phase precursor reacts with the second vapor phase
precursor.
2. The method of claim 1, wherein the second silicide forming metal
is different from the first silicide forming metal.
3. The method of claim 1, wherein the first silicide forming metal
comprises cobalt (Co), titanium (Ti) or platinum (Pt).
4. The method of claim 1, wherein the non-silicide forming element
comprises antimony (Sb), germanium (Ge) or tin (Sn).
5. The method of claim 1, further comprising reducing the metal
oxide layer to form elemental second silicide forming metal.
6. The method of claim 1, wherein the second silicide forming metal
of the metal oxide layer is nickel and the metal oxide layer is a
nickel oxide thin film.
7. The method of claim 1, wherein the second silicide forming metal
of the oxide layer is cobalt, and the metal oxide layer is a cobalt
oxide thin film.
8. (canceled)
9. The method of claim 8, wherein the first vapor phase precursor
is a metal halide.
10. The method of claim 9, wherein the second vapor phase precursor
is an antimony containing precursor having the formula
Sb(SiMe.sub.3).sub.3.
11. A method of forming a metal silicide, comprising: depositing an
interface layer on exposed silicon regions of a substrate, the
interface layer comprising a first silicide forming metal and a
non-silicide forming element; depositing a metal oxide layer over
the interface layer, wherein the metal oxide layer comprises a
second silicide forming metal; and heating the substrate to form
the metal silicide beneath the interface layer, the metal silicide
comprising silicon from the formerly exposed silicon regions, first
silicide forming metal from the interface layer, and second
silicide forming metal from the metal oxide layer, wherein
depositing the interface layer comprises a plurality of
super-cycles, each super-cycle comprising: a first sub-cycle
comprising exposing the substrate to a first vapor phase precursor
comprising the first silicide forming metal and a first reducing
agent; and a second sub-cycle comprising exposing the substrate to
a second vapor phase precursor comprising the non-silicide forming
element and a second reducing agent.
12. The method of claim 11, wherein the first vapor phase precursor
comprises cobalt, and wherein the first reducing agent comprises at
least one of hydrogen gas and hydrazine.
13. The method of claim 12, wherein the first vapor phase precursor
is tBu-AllylCo(CO).sub.3.
14. The method of claim 11, wherein the second vapor phase
precursor comprises SbCl.sub.3, and wherein the second reducing
agent comprises Sb(SiR.sup.1R.sup.2R.sup.3).sub.3, wherein R.sup.1,
R.sup.2, and R.sup.3 are alkyl groups.
15. A method of forming metal silicide, comprising: depositing an
interface layer over at least one exposed silicon region of a
substrate, wherein depositing the interface layer comprises a
plurality of atomic layer deposition cycles, each of the plurality
of atomic layer deposition cycles comprising: contacting a surface
of the exposed silicon regions with a first vapor phase precursor
comprising a first silicide forming metal to form a layer of first
species on the surface of the substrate; and contacting the first
species on the surface of the substrate with a second vapor phase
precursor comprising a non-silicide forming element; depositing a
metal oxide layer over the interface layer, wherein the metal oxide
layer comprises a second silicide forming metal; and forming the
metal silicide beneath the interface layer, the metal silicide
comprising silicon of the at least one formerly exposed silicon
regions, first silicide forming metal of the interface layer and
second silicide forming metal of the metal oxide layer.
16. The method of claim 15, wherein the second silicide forming
metal is nickel.
17. The method of claim 15, wherein the second silicide forming
metal is cobalt.
18. The method of claim 15, wherein the first silicide forming
metal comprises cobalt (Co), titanium (Ti) or platinum (Pt).
19. The method of claim 15, wherein the first vapor phase precursor
comprises a metal halide.
20. The method of claim 19, wherein the first vapor phase precursor
comprises a metal chloride.
21. The method of claim 20, wherein the first vapor phase precursor
comprises TiCl.sub.4 or CoCl.sub.2.
22. The method of claim 15, wherein the second vapor phase
precursor comprises antimony (Sb), germanium (Ge) or tin (Sn).
23. The method of claim 22, wherein the second vapor phase
precursor has a formula of Sb(SiR.sup.1R.sup.2R.sup.3).sub.3,
wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups.
Description
BACKGROUND
[0001] Field
[0002] The present disclosure relates generally to the field of
semiconductor device manufacturing and, more particularly, to
methods for forming metal silicides.
[0003] Description of the Related Art
[0004] Integrated circuit fabrication often includes providing
electrical contact to various features of the circuit, such as
providing electrical contacts to source, drain and/or gate features
of a transistor. Providing reliable and low resistivity electrical
contacts to such features can enhance device performance and/or
increase production yield.
[0005] In forming advanced semiconductor devices, silicon can be
converted to metal silicides, for example to provide
low-resistivity contacts. Part of the silicon that is present in
gate, source and/or drain structures of a semiconductor device can
be converted into low-resistivity metal silicide. This is done to
realize a conductive path with a low bulk resistivity on the one
hand, and to ensure a good contact resistance on the other hand.
Metal silicides can be formed on planar and/or three-dimensional
structures, for example to provide the low-resistivity
contacts.
SUMMARY
[0006] In some aspects, a method of forming a metal silicide can
include depositing an interface layer on exposed silicon regions of
a substrate, the interface layer can include a first silicide
forming metal and a non-silicide forming element; depositing a
metal oxide layer over the interface layer, where the metal oxide
layer comprises a second silicide forming metal; and heating the
substrate to form the metal silicide beneath the interface layer.
The formed metal silicide may include silicon from the exposed
silicon regions and first silicide forming metal from the interface
layer and the second silicide forming metal from the metal oxide
layer. In some embodiments, the first silicide forming metal is
different from the second silicide forming metal.
[0007] In some embodiments, the first silicide forming metal can
include cobalt (Co), titanium (Ti) or platinum (Pt). In some
embodiments, the non-silicide forming element can include antimony
(Sb), germanium (Ge) or tin (Sn).
[0008] In some embodiments, the second silicide forming metal of
the metal oxide layer is nickel and the metal oxide layer is a
nickel oxide thin film. In some embodiments, the metal oxide layer
can be reduced to form elemental second silicide forming metal.
[0009] In some embodiments, the second silicide forming metal of
the oxide layer is cobalt, and the metal oxide layer is a cobalt
oxide thin film.
[0010] In some embodiments, depositing the interface layer can
include a plurality of cycles of a vapor deposition process, each
cycle of the plurality of cycles including alternately and
sequentially contacting the surface of the substrate with a first
vapor phase precursor having the first silicide forming metal and a
second vapor phase precursor having the non-silicide forming
element, where the first vapor phase precursor can react with the
second vapor phase precursor to form the interface layer. In some
embodiments, the first vapor phase precursor is a metal halide. In
some embodiments, the second vapor phase precursor is an antimony
containing precursor having the formula Sb(SiMe.sub.3).sub.3.
[0011] In some embodiments, depositing the interface layer can
include a plurality of super-cycles, each super-cycle comprising a
first sub-cycle comprising exposing the substrate to a first vapor
phase precursor including the first silicide forming metal and a
first reducing agent; and a second sub-cycle comprising exposing
the substrate to a second vapor phase precursor including the
non-silicide forming element and a second reducing agent. In some
embodiments, the first vapor phase precursor can include cobalt,
and the first reducing agent can include at least one of hydrogen
gas and hydrazine. In some embodiments, the first vapor phase
precursor is tBu-AllylCo(CO).sub.3. In some embodiments, the second
vapor phase precursor can include SbCl.sub.3, and the second
reducing agent can include Sb(SiR.sup.1R.sup.2R.sup.3).sub.3,
wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups.
[0012] In some aspects, a method of forming metal silicide can
include depositing an interface layer over at least one exposed
silicon region of a substrate, wherein depositing the interface
layer can include a plurality of atomic layer deposition cycles,
each of the plurality of atomic layer deposition cycles including:
contacting a surface of the exposed silicon regions with a first
vapor phase precursor having a first silicide forming metal to form
a layer of first species on the surface of the substrate; and
contacting the first species on the surface of the substrate with a
second vapor phase precursor having a non-silicide forming element;
depositing a metal oxide layer over the interface layer, wherein
the metal oxide layer includes a second silicide forming metal; and
forming the metal silicide beneath the interface layer. The formed
metal silicide may include silicon of the at least one exposed
silicon regions, first silicide forming metal of the interface
layer and second silicide forming metal of the metal oxide
layer.
[0013] In some embodiments, the second silicide forming metal is
nickel. In some embodiments, the second silicide forming metal is
cobalt.
[0014] In some embodiments, the first silicide forming metal
includes cobalt (Co), titanium (Ti) or platinum (Pt). In some
embodiments, the first vapor phase precursor includes a metal
halide. In some embodiments, the first vapor phase precursor
includes a metal chloride. In some embodiments, the first vapor
phase precursor includes TiCl.sub.4 or CoCl.sub.2.
[0015] In some embodiments, the second vapor phase precursor
includes antimony (Sb), germanium (Ge) or tin (Sn). In some
embodiments, the second vapor phase precursor has a formula of
Sb(SiR.sup.1R.sup.2R.sup.3).sub.3, wherein R.sup.1, R.sup.2, and
R.sup.3 are alkyl groups.
[0016] For purposes of summarizing the invention and the advantages
achieved over the prior art, certain objects and advantages are
described herein. Of course, it is to be understood that not
necessarily all such objects or advantages need to be achieved in
accordance with any particular embodiment. Thus, for example, those
skilled in the art will recognize that the invention may be
embodied or carried out in a manner that can achieve or optimize
one advantage or a group of advantages without necessarily
achieving other objects or advantages.
[0017] All of these embodiments are intended to be within the scope
of the invention herein disclosed. These and other embodiments will
become readily apparent to those skilled in the art from the
following detailed description having reference to the attached
figures, the invention not being limited to any particular
disclosed embodiment(s).
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Various features, aspects, and advantages of the present
disclosure are described with reference to the drawings of certain
embodiments, which are intended to illustrate certain embodiments
and not to limit the invention.
[0019] FIG. 1 is a process flow diagram of an example process for
forming metal silicide, according to some embodiments.
[0020] FIG. 2 is a process flow diagram of another example process
for forming metal silicide, according to some embodiments.
[0021] FIGS. 3A through 3C are a series of schematic cross-sections
of a planar transistor, illustrating silicidation of source/drain
and gate regions in accordance with some embodiments.
[0022] FIGS. 4A through 4C are a series of schematic cross-sections
of a transistor with contacts to be formed after insulation by a
thick interlayer dielectric, illustrating silicidation of
source/drain regions in accordance with some embodiments.
[0023] FIGS. 5A through 5C are a series of schematic cross-sections
of a three-dimensional transistor, illustrating silicidation of
source/drain regions and vertical gate sidewalls in accordance with
some embodiments.
[0024] FIGS. 6A and 6B are schematic diagrams of example film
stacks corresponding to various steps in processes for forming
metal silicides, according to some embodiments.
[0025] FIG. 7 is a process flow diagram of an example process for
forming an interface layer, according to some embodiments.
[0026] FIG. 8 is a process flow diagram of an example deposition
cycle for forming a CoSb interface layer, according to some
embodiments.
[0027] FIG. 9 is a process flow diagram of an example deposition
cycle for forming a TiSb interface layer, according to some
embodiments.
[0028] FIG. 10 shows an example deposition performance of TiSb
deposited on a blanket wafer.
DETAILED DESCRIPTION
[0029] Processes for forming metal silicide, such as a co-metal
silicide, can include forming a sacrificial interface layer over a
substrate. The interface layer may be formed over exposed silicon
regions of the substrate. In some embodiments, the interface layer
can comprise one or more silicide forming metals and one or more
non-silicide forming elements. As used herein, a "silicide forming
metal" is a metal which reacts with exposed silicon of the
substrate to form metal silicide under one or more silicidation
process conditions described herein, and a "non-silicide forming
element" is an element which does not or substantially does not
form metal silicide with exposed silicon of the substrate under
conditions of the silicidation processes described herein. In some
embodiments, as described in further detail below, during
subsequent processing of the substrate, the silicide forming metal
of the interface layer can migrate to and react with silicon of
exposed silicon regions to form metal silicide beneath the
interface layer. Examples of silicide forming metals of the
interface layer may include one or more of cobalt (Co), titanium
(Ti) and platinum (Pt). Examples of the non-silicide forming
element of the interface layer may include one or more of antimony
(Sb), germanium (Ge) and tin (Sn).
[0030] In some embodiments, a metal oxide layer may be subsequently
deposited over the interface layer. The metal oxide layer may
comprise a silicide forming metal, including at least one silicide
forming metal different from a silicide forming metal of the
interface layer. Examples of the silicide forming metal of the
metal oxide layer include one or more of nickel (Ni) and cobalt
(Co). The substrate may then be heated to facilitate silicidation
reaction between the silicon of the exposed silicon regions and the
silicide forming metals of the metal oxide layer and the interface
layer to form a metal silicide comprising two or more different
metals, including a co-metal silicide. For example, the substrate
may be heated as part of a thermal annealing process. In some
embodiments, the deposited metal oxide may be reduced to provide an
elemental form of the silicide forming metal or metals. For
example, the elemental form of the silicide forming metal or metals
may react with the silicon of the substrate in the subsequent
silicidation reaction. In some embodiments, reducing the metal
oxide layer and the silicidation reaction may be achieved in a
single process, such as part of a single annealing process. In some
embodiments, reducing the metal oxide can be performed in a step
prior to and distinct from the silicidation reaction step.
[0031] As used herein, the formula for metal silicide formed
according to one or more processes described herein can be referred
to as ABSi for simplicity and convenience. However, the skilled
artisan will understand that the actual formula of the metal
silicide, representing the A:B:Si ratio in the film and excluding
impurities, can be represented as A.sub.1-xB.sub.xSi.sub.y, where A
can be a silicide forming metal from a metal oxide layer, and where
B can be a silicide forming metal from a silicide forming metal
from an interface layer. In some embodiments, x can be between
about 0.05 and about 0.95, and y can be between about 0.5 and about
2. In some embodiments, a ratio of the metal atoms in the silicide
to Si atoms can be about 1:1 to about 1:2. For example, a ratio of
metal atoms A and B together to Si atoms in the metal silicide can
be about 1:1 to about 1:2. In some embodiments, A and/or B can be
cobalt (Co), platinum (Pt), titanium (Ti), aluminium (Al) or
hafnium (Hf), erbium (Er), ytterbium (Yb), dysprosium (Dy),
tungsten (W), molybdenum (Mo), tantalum (Ta), palladium (Pd),
zirconium (Zr), yttrium (Y), or Vanadium (V).
[0032] In some embodiments, at least a portion of the metal oxide
layer and/or elemental metal or metals of the metal oxide remain
over the substrate after the silicidation reaction, including over
exposed silicon portions of the substrate. For example, unreacted
elemental metal or metals from the metal oxide may remain over the
substrate, including over exposed silicon portions of the
substrate. The non-silicide forming element of the interface layer
can remain over the substrate after the silicidation reaction step,
including over exposed silicon portions of the substrate. In some
embodiments, at least a portion of the one or more silicide forming
metals of the interface layer remains after the silicidation
reaction, including unreacted silicide forming metals over exposed
silicon regions of the substrate. For example, the metal silicide
may be formed beneath the interface layer.
[0033] In some embodiments, the substrate may be cleaned subsequent
to the silicide formation step to remove any remaining interface
layer and/or metal oxide layer, including any unreacted metal from
the metal oxide layer, while leaving the metal silicide intact. For
example, unreacted silicide forming metal of the interface layer
and unreacted metal formed by reducing the metal oxide layer, and
non-silicide forming element of the interface layer, may be removed
by a post clean process. In some embodiments, the post clean
process may comprise a metal etch process. For example, the
substrate may be dipped in a wet etchant (e.g., a dilute aqueous
HCl and/or HNO.sub.3 or piranha solution) to selectively remove
from the substrate surface any unreacted metal from the metal oxide
layer, and the remaining interface layer, including unreacted
silicide forming metal of the interface layer and the non-silicide
forming element of the interface layer.
[0034] As described herein, one or more silicide forming metals may
be co-deposited with one or more non-silicide forming elements in a
process for forming an interface layer. In some embodiments, use of
an interface layer comprising one or more silicide forming metals
can advantageously allow use of additional metals in forming metal
silicide without using instead additional metal or metal oxide
deposition processes. For example, incorporating one or more
silicide forming metals into the interface layer, rather than
depositing a separate metal or metal oxide thin film comprising the
one or more silicide forming metals, can reduce the thermal budget
of the process to form the metal silicide. Avoiding additional
thermal budget in a device fabrication process can reduce undesired
impact upon features of the device due to subsequent deposition
processes. In some embodiments, incorporation of a silicide forming
metal into the interface layer may allow formation of metal
silicide using the metal where an oxide of the metal would
otherwise be difficult to reduce. In some embodiments,
incorporation of a silicide forming metal into the interface layer
may allow formation of metal silicide having desired thermal
stability, thereby providing devices with improved reliability. For
example, use of interface layers comprising one or more silicide
forming metals may facilitate formation of metal silicides
comprising more than one type of metal. In some embodiments, such
metal silicides comprising more than one type of metal can
demonstrate improved thermal stability, such as compared to
silicides comprising only one or fewer of the metals. In some
embodiments, an electrical contact comprising metal silicides
having more than one type of metal can demonstrate improved thermal
stability, such as relative to electrical contacts comprising metal
silicides comprising fewer types of metal.
[0035] In some embodiments, metal silicide can be formed on
three-dimensional structures. For example, for certain
semiconductor structures, such as a nonplanar multiple gate
transistor, such as FinFETs, it may be desirable to form silicide
on vertical walls, in addition to the tops of the gate, source, and
drain regions. In other semiconductor devices, it may be beneficial
to form silicide in narrow openings or trenches. In some
embodiments, one or more conformal interface layers described
herein may be deposited over one or more three-dimensional
structures on a substrate surface such that metal silicide can be
formed on the three-dimensional structures using metal from the
interface layer. For example, a conformal interface layer may be
deposited over the three-dimensional structures, and a conformal
metal oxide layer may be deposited over the interface layer. The
substrate may be subsequently subjected to an anneal process such
that metal silicide can be formed using metal from the interface
and metal oxide layers, and silicon from exposed silicon regions on
the three-dimensional structures. For example, metal silicide may
be formed on one or more vertical surfaces of the three-dimensional
structures.
[0036] In some embodiments, a process for forming one or both of
the interface layer and the metal oxide layer can comprise an
atomic layer deposition (ALD) process. In some embodiments, a
process for forming one or both of the interface layer and the
metal oxide layer can comprise a chemical vapor deposition (CVD)
process. Atomic layer deposition (ALD) and/or chemical vapour
deposition (CVD) processes can be used to form conformal layers
over three-dimensional structures. Conformal and/or uniform
formation of layers over three-dimensional structures can provide
metal silicide of desired resistivity across structures on the
surface of the substrate, for example reducing variation in
resistivity across the structures on the surface of a substrate,
thereby providing uniform electrical performance of electrical
devices formed using the metal silicide.
[0037] The metal silicide forming process can be a self-aligned
process. Self-aligned silicidation is also known in the art as
"salicidation" and the self-aligned resultant metal compound has
been referred to as "salicide." In a self-aligned process, metal
silicide forms only where both silicon and silicide forming metal
are present. For example, a portion of the interface layer can be
formed on and in direct contact with the exposed silicon of the
substrate. In a self-aligned silicidation process, metal silicide
can be formed only or substantially only in the exposed silicon
region in direct contact with the interface layer.
[0038] In some embodiments, an ALD process can be used to form an
interface layer comprising antimony and cobalt over a substrate. In
some embodiments the interface layer is formed over exposed silicon
regions of the substrate. For example, the interface layer is
formed on and in direct contact with the exposed silicon regions of
the substrate. A metal oxide layer can be deposited over the
interface layer. For example, the metal oxide layer may be a nickel
oxide (e.g., NiO) layer, and the nickel oxide layer may be
deposited on and in direct contact with the interface layer
comprising the antimony and cobalt. In some embodiments, an ALD
process can be used to deposit the metal oxide layer. The substrate
may then be subjected to a silicidation process to form a metal
silicide using silicon from the exposed silicon regions, nickel
from the nickel oxide layer, and cobalt from the interface layer.
In some embodiments, the metal oxide layer may be reduced to form
elemental metal. For example, the nickel oxide layer may be reduced
to form elemental nickel, and the elemental metal reacts with
silicon of the substrate to form the metal silicide. In some
embodiments, reducing the metal oxide layer and the silicidation
process can be a single process, such as a single annealing
process.
[0039] Antimony of the interface layer can remain over the
substrate after the silicidation reaction, including over exposed
silicon regions of the substrate. In some embodiments, unreacted
cobalt of the interface layer can remain over the substrate after
the silicidation reaction. For example, a portion of the interface
layer cobalt may remain over exposed silicon regions of the
substrate. In some embodiments, unreacted elemental nickel from the
nickel oxide and/or unreduced nickel oxide can remain over the
substrate after the silicidation reaction, including over exposed
silicon regions of the substrate. For example, NiCoSi may be formed
beneath the remaining interface layer.
[0040] In some embodiments, the interface layer comprises antimony
and titanium and the metal oxide layer is a nickel oxide layer such
that NiTiSi is formed. For example, the antimony and titanium
interface layer may be deposited over a substrate, followed by
deposition of the nickel oxide layer over the antimony and titanium
interface layer. The substrate may be subjected to a silicidation
process such that NiTiSi can be formed using silicon from the
exposed silicon regions, nickel from the nickel oxide layer and
titanium from the interface layer. In some embodiments, the nickel
oxide may be reduced to form elemental nickel such that the
elemental nickel reacts with the silicon during the silicidation
reaction. Unreacted elemental nickel and/or unreduced nickel oxide
can remain on the substrate after the silicidation reaction. In
some embodiments, antimony and unreacted titanium from the
interface layer can remain on the substrate after the silicidation
reaction. For example, the NiTiSi may be formed beneath the
remaining interface layer.
[0041] In some embodiments, the metal oxide layer is cobalt oxide
(e.g., CoO) layer and the interface layer comprises platinum. For
example, the interface layer may comprise antimony and platinum
such that CoPtSi is formed. In some embodiments, the interface
layer comprises antimony and nickel such that CoNiSi is formed. In
some embodiments, the interface layer comprises antimony and
tungsten such that CoWSi is formed. In some embodiments, forming a
cobalt-containing silicide comprising one or more of platinum,
nickel and tungsten can allow formation of cobalt-containing
silicides having desired thermal stability.
[0042] FIG. 1 shows an example process 100 for forming metal
silicide, according to some embodiments. In some embodiments, the
process 100 comprises a self-aligned silicidation process. In block
102, a substrate comprising one or more exposed silicon regions is
provided. In some embodiments, the substrate can have
three-dimensional structures formed thereon. In some embodiments,
the three-dimensional structures comprise one or more exposed
silicon regions. For example, the one or more of the exposed
silicon region may be on a vertical surface of the substrate.
[0043] In block 104, an interface layer comprising one or more
non-silicide forming elements and one or more silicide forming
metals can be deposited over the substrate, including over the one
or more exposed silicon regions. In some embodiments, the interface
layer can be deposited on and in direct contact with one or more
exposed silicon regions. In some embodiments, the interface layer
can be a thin film configured to prevent or substantially prevent
oxidation of the underlying exposed silicon regions during
subsequent processing of the substrate. Desirably, the deposition
of the interface layer also does not induce oxidation of the
underlying silicon. Oxidation of the underlying silicon can inhibit
metal diffusion, and therefore silicide formation. In some
embodiments, the interface layer protects the silicon from
oxidation during subsequent deposition of metal oxide, while also
permitting ready migration of metal and/or silicon across the
interface between the interface layer and the underlying silicon,
without undue energy injection. Undue energy can be such as
destroys integrated circuit structures, such as transistor
junctions.
[0044] In some embodiments, the one or more non-silicide forming
elements and the one or more silicide forming metals can be
co-deposited. For example, the non-silicide forming elements and
silicide forming metals may be deposited in the same deposition
process. As described in further detail herein, in some
embodiments, a process for depositing the interface layer can
include an ALD process and/or a CVD process. For example, the one
or more silicide forming metals and the one or more non-silicide
forming elements of the interface layer can be deposited as part of
the same ALD process, forming an interface layer comprising two or
more metals. For example, a conformal interface layer can be
deposited over three-dimensional features on the substrate using an
ALD process and/or a CVD process. In some embodiments, the
interface layer can have a thickness of about 1 nanometers (nm) to
about 15 nm. In some embodiments, the interface layer can have a
thickness of about 1 nm to about 15 nm, about 1 nm to about 10 nm,
about 5 nm to about 15 nm, or about 1 nm to about 5 nm. In some
embodiments, the interface layer can have a thickness of about 4 nm
to about 15 nm. In some embodiments, the thickness of the interface
layer can be selected based on the desired thickness of silicide to
be formed. In some embodiments, the thickness of the interface
layer can be selected to provide desired protection of the
underlying silicon, while allowing desired diffusion of silicon
and/or silicide forming metals therewithin, demonstrating desired
thickness uniformity and/or providing a desired quantity of
silicide forming metal for the silicide.
[0045] In some embodiments, the interface layer comprises a
semimetal as a non-silicide forming element. In some embodiments,
the interface layer comprise antimony (Sb) as a non-silicide
forming element. In some embodiments, the interface layer comprises
tin (Sn) and/or germanium (Ge) as a non-silicide forming element.
In some embodiments, the one or more silicide forming metals of the
interface layer comprise cobalt (Co). In some embodiments, the one
or more silicide forming metals comprises platinum (Pt), titanium
(Ti), aluminium (Al) and/or hafnium (Hf). In some embodiments, the
one or more silicide-forming metals can comprise one or more of
erbium (Er), ytterbium (Yb) and dysprosium (Dy). In some
embodiments, the one or more silicide forming metals comprise
tungsten (W), molybdenum (Mo), tantalum (Ta) and/or palladium (Pd).
In some embodiments, the one or more silicide forming metals
comprise zirconium (Zr), yttrium (Y), and/or Vanadium (V). In some
embodiments, the one or more non-silicide forming elements comprise
bismuth (Bi), indium (In), zinc (Zn), and/or lead (Pb).
[0046] In block 106, a metal oxide layer is deposited over the
interface layer. In some embodiments, a process for depositing the
metal oxide layer can comprise an ALD and/or a CVD process. For
example, a conformal metal oxide layer may be deposited over
three-dimensional features on a substrate using an ALD process
and/or a CVD process. As described herein, the metal oxide layer
can comprise one or more silicide forming metals. In some
embodiments, the metal oxide layer is a nickel oxide thin film
(e.g., NiO thin film) and the silicide forming metal of the metal
oxide layer is nickel. For example, a nickel oxide thin film can be
deposited on and in direct contact with the interface layer. In
some embodiments, the metal oxide layer is a cobalt oxide thin film
(e.g., CoO thin film) and the silicide forming metal of the metal
oxide layer is cobalt. For example, a cobalt oxide thin film can be
deposited on and in direct contact with the interface layer. The
metal oxide layer can have a thickness of about 1 nm to about 20
nm, including about 2 nm to about 5 nm, or about 5 nm to about 15
nm. In some embodiments, the metal oxide layer can have a thickness
of about 1 nm to about 10 nm. In some embodiments, the thickness of
the metal oxide layer can be selected based on the desired
thickness of the silicide formed. In some embodiments, the
thickness of the metal oxide layer can be selected based on the
thickness of the interface layer, the amount of metal provided by
the metal oxide layer, such as the amount of metal available for
silicide formation after reducing the metal oxide layer, and/or the
desired amount of metal used for forming the metal silicide.
[0047] In block 108, the substrate can be subjected to an annealing
process. In some embodiments, the annealing process allows
formation of the metal silicide. For example, conditions of the
annealing process may be selected such that metal silicide is
formed from silicon of the exposed silicon regions, the one or more
silicide forming metals of the metal oxide layer and the one or
more silicide forming metal of the interface layer. For example, a
metal silicide comprising a metal from the metal oxide layer and a
metal from the interface layer may be formed. In some embodiments,
the annealing process is configured to both reduce the metal oxide
of the metal oxide layer to form elemental metal and provide
desired metal silicide formation from the exposed silicon regions
of the substrate. For example, conditions of the annealing process
in block 108 can be selected such that desired reduction of the
metal oxide layer can be achieved, while also providing desired
migration of the elemental metal formed from the metal oxide layer,
of the one or more silicide forming metals from the interface
layer, and/or migration of silicon from the exposed silicon
regions. Conditions of the annealing process can be selected such
that desired metal silicide comprising silicon from the exposed
silicon regions, the one or more elemental metals formed from the
metal oxide layer and the one or more silicide forming metals of
the interface layer, can be formed.
[0048] In some embodiments, the annealing process can be performed
at temperatures equal to or greater than about 250.degree. C.,
equal to or greater than about 300.degree. C., equal to or greater
than about 350.degree. C., equal to or greater than about
400.degree. C., or even equal to or greater than about 500.degree.
C. In some embodiments, the annealing process can be performed in a
moderately reducing atmosphere, such as hydrogen gas (H.sub.2) or
hydrogen and nitrogen gas (forming gas or H.sub.2/N.sub.2). In some
embodiments, reduction and silicidation can be induced by annealing
at about 550.degree. C. in forming gas (5% H.sub.2 and 95%
N.sub.2), such as for a duration of about 2 minutes.
[0049] In some embodiments, the metal oxide layer comprises nickel
oxide and the interface layer comprises cobalt (e.g., the interface
layer can be a CoSb thin film) such that NiCoSi is formed by the
annealing process. For example, the CoSb interface layer may be
deposited over a substrate, including over exposed silicon regions
of the substrate, and the nickel oxide layer may be deposited over
the CoSb layer, such that the NiCoSi may be formed from silicon of
the exposed silicon regions, cobalt of the CoSb layer and nickel of
the nickel oxide layer when the substrate is exposed to an
annealing process. In some embodiments, the metal oxide layer
comprises nickel oxide and the interface layer comprises titanium
(e.g., the interface layer can be a TiSb thin film) such that the
annealing process forms NiTiSi. In some embodiments, the metal
oxide layer comprises nickel oxide and the interface layer
comprises platinum (e.g., the interface layer can be a PtSb thin
film) such that the annealing process forms NiPtSi. As described in
further details herein, other metal silicides can also be formed
from other combinations of metal oxide and interface layer
compositions.
[0050] In block 110, the substrate can be subjected to a post clean
process. In some embodiments, the post clean process can be
configured to remove any remaining interface layer and/or metal
oxide layer on the substrate surface. For example, the one or more
non-silicide forming elements of the interface layer may remain
over the substrate. In some embodiments, unreacted silicide forming
metal of the interface layer can remain over the substrate,
including over exposed silicon regions of the substrate. In some
embodiments, metal oxide and/or elemental metal from the metal
oxide layer may remain over the substrate, including unreacted
elemental metal over exposed silicon regions. Unreacted elemental
metal remaining after the silicidation reaction may include
elemental metal formed over regions of the substrate where exposed
silicon regions of the substrate are not accessible, and may be
removed in the post clean process. In some embodiments, the post
clean process can be configured to remove any remaining metal oxide
layer, unreacted elemental metal, such as unreacted elemental metal
from the metal oxide layer, and/or any remaining interface layer.
In some embodiments, the post clean process can comprise a wet
metal etch. For example, the wet metal etch can selectively remove
unreacted metal from the substrate surface. In some embodiments,
the wet metal etch process can include dipping the substrate in
dilute aqueous HCl and/or HNO.sub.3 or piranha solution, to
selectively etch the metal. For example, metal, such as nickel, on
the substrate can be etched without or substantially without
appreciable attack of silicon, silicon oxide and/or other non-metal
materials used in integrated circuit manufacture.
[0051] In block 112, the substrate can be optionally subjected to a
further annealing process. The further annealing process can reduce
resistivity of the metal silicide formed in block 108. For example,
a high resistivity phase of metal silicide formed by the
silicidation reaction in block 108 can be subjected to a further
annealing process to form a lower resistivity phase of the metal
silicide.
[0052] Referring to FIG. 2, another example of a process 200 for
forming metal silicide is shown. The process 200 of FIG. 2 includes
steps similar to those of process 100 in FIG. 1, except that
process 200 includes a reducing step distinct from a step in which
desired silicidation is achieved. Referring to block 202, a
substrate comprising one or more exposed silicon regions can be
provided. In block 204, an interface layer comprising one or more
non-silicide forming elements and one or more silicide forming
metals can be deposited over the substrate, including over the one
or more exposed silicon regions. In block 206, a metal oxide layer
can be deposited over the interface layer. In some embodiments, the
substrate of block 202, the deposition of the interface layer in
block 204, and the deposition of the metal oxide layer in block 206
can have one or more characteristics of the substrate, the metal
oxide deposition and the interface layer deposition described with
reference to blocks 102, 104 and 106 in FIG. 1, respectively. For
example, a conformal metal oxide layer and/or a conformal interface
layer may be deposited. In some embodiments, the conformal metal
oxide layer and/or the conformal interface layer may be deposited
using an ALD process and/or a CVD process.
[0053] In block 208, the metal oxide layer can be subjected to a
reducing process. As described herein, the reducing process of
block 208 is distinct from a silicide formation process in which
desired metal silicide is formed from the exposed silicon regions
of the substrate. In some embodiments, conditions of the reducing
process can be selected such that the metal oxide can be reduced to
provide the desired elemental metal without or substantially
without effecting any metal silicide formation. In some
embodiments, the reducing process achieves no or substantially no
silicidation of the exposed silicon regions of the substrate. In
some embodiments, the reducing process can achieve some
silicidation of the exposed silicon regions of the substrate but
does not complete desired silicide formation of the exposed silicon
regions.
[0054] In some embodiments, a process for reducing the metal oxide
layer, which is distinct and separate from the process for
achieving the silicidation reaction, can be accomplished at
relatively lower temperatures than a reducing process also
configured to achieve desired silicidation. For example, a reducing
process which is distinct from a silicidation reaction, such as the
reducing process of block 208, can be performed between room
temperature (e.g., about 20.degree. C. to about 25.degree. C.) and
about 300.degree. C. In some embodiments, a reducing process which
is distinct from a silicidation reaction can be performed with
relatively stronger reducing agents, such as reducing agents
comprising hydrogen containing plasma, hydrogen radicals or
hydrogen atoms and reactive organic compounds, which contain at
least one functional group selected from the group of alcohol
(--OH), aldehyde (--CHO), and carboxylic acid (--COOH).
[0055] In block 210, the substrate can be subjected to a
silicidation process. Desired silicide formation from the exposed
silicon regions and the silicide forming metals of the metal oxide
layer and interface layer can be achieved in block 210. In some
embodiments, the silicidation process of block 210 comprises a
rapid thermal anneal process tailored for silicidation reaction
between the already-formed metal layer, silicide forming metal of
the interface layer, and the exposed silicon. In some embodiments,
the silicide formation in block 210 can be achieved at temperatures
higher than that applied in the reducing process of block 208. For
example, the silicidation process can be performed at temperatures
greater than about 400.degree. C.
[0056] In block 212, the substrate can be subjected to a post clean
process, and in block 214, the substrate can be subjected to a
further annealing process. The post clean process of block 212 and
the further annealing process of block 214 can have one or more
characteristics of the post clean process and further annealing
process of blocks 210 and 212 in FIG. 1, respectively.
[0057] With reference to FIG. 3A, a planar transistor 300 is shown
after formation of an interface layer 305. The interface layer 305
can be formed as described above with respect to block 104 of FIG.
1 or 204 of FIG. 2. The interface layer may be formed by ALD of a
suitable film for the functions described herein, such as an
antimony (Sb) containing film. The transistor 300 is formed within
and on a substrate 380 and includes a gate electrode 310 over a
gate dielectric 320. The gate dielectric 320 overlies a transistor
channel, which is sandwiched between heavily doped source region
330 and drain region 340. The gate electrode 10 is protected by
dielectric sidewall spacers 350, which can facilitate self-aligned
source/drain doping as well as partially self-aligned contact
formation. Field isolation 355 (e.g., shallow trench isolation) is
also shown for electrical isolation of the transistor 300 from
adjacent devices.
[0058] Referring to FIG. 3B, the transistor 300 is shown after
deposition of a metal oxide layer 365. As discussed above, ALD of
metal oxide, such as nickel oxide (NiO), advantageously forms a
conformal layer such that the same thickness of the metal oxide
layer 365 forms at both high points (e.g., over the gate electrode
310) and low points (e.g., over the source/drain regions
330/340).
[0059] Referring to FIG. 3C, the transistor 300 is shown after
reduction and silicidation reactions. As discussed with respect to
FIGS. 1 and 2, these reactions can occur in one process or in
distinct processes. Metal and silicon readily migrate across the
interface formed by the interface layer 305 (FIG. 3B) to form a
metal silicide 370 at regions where silicon was exposed to the
interface layer deposition, e.g., at the upper surfaces of the
source 330, drain 340 and gate electrode 310. Moreover, the metal
oxide is reduced to a metal layer 360 in regions where silicon is
not accessible (e.g., over the field isolation 355 and dielectric
sidewall spacers 350). The unreacted metal can be readily
selectively etched without harm to the remaining metal silicide,
silicon and dielectric structures.
[0060] FIGS. 4A-4C illustrate a similar sequence on a similar
planar transistor 400. Similar parts to those of FIGS. 3A-3C are
referenced by similar reference numerals in the 400 range. The
difference between FIGS. 3A-3C and FIGS. 4A-4C is that in FIGS.
4A-4C the interface layer 405 and the metal oxide layer 465 are
provided over a thick insulating layer 490 through which contact
vias 492 have been formed to open contacts to the source region 430
and drain region 440. In the illustrated arrangement the gate
electrode 410 is protected on an upper surface by a dielectric cap
415. The skilled artisan will appreciate that at other locations of
the integrated circuit, a contact opening to the gate electrode may
be opened simultaneously with the contact vias 492 shown in the
cross-section of FIG. 4A.
[0061] As integrated circuit dimensions are scaled, the aspect
ratio (height:width) of such contact openings 492 continue to
climb, making deposition therein challenging. ALD, as described
herein, of both the interface layer 405 and the metal oxide layer
465 that provides metal for the silicidation facilitates conform
coating such that sufficient metal can be provided at the bottoms
of the vias 492 without the need for excess deposition at higher
regions. Better control of the supply of metal is thereby afforded,
and excess silicon consumption during the silicidation can be
avoided.
[0062] FIG. 4C shows the result of metal oxide reduction and
silicidation, leaving metal silicide layers 470 at the surface of
the source/drain regions 430/440. A metal layer 460 is left over
regions without access to silicon, such as over surfaces of the
insulating layer 490, which can then be removed by selective metal
etching, and the contact vias 492 can be filled with a contact
plug, as is known in the art.
[0063] Referring to FIGS. 5A-5C, silicidation according to the
methods described herein is illustrated in the context of a
three-dimensional transistor. In particular, FIG. 5A shows a
vertical transistor 500 with a source region 530 at the base of a
vertically extending pillar 535 of semiconductor material. The
source region 530 extends laterally to a contact opening in an
insulating layer 590, where it is exposed for silicidation of its
surface. A drain region 540 is formed at an upper end of the
semiconductor pillar 535. A gate dielectric 520 is formed on the
sidewall surfaces of the pillar 535, separating the pillar 535 from
a gate electrode 510. The gate electrode 510 can be formed, e.g.,
as a sidewall spacer surrounding the semiconductor pillar 535. In
the illustrated embodiment, the gate electrode 510 comprises
silicon (e.g., amorphous or polysilicon) and exposed for
silicidation prior to deposition of the interface layer 505 of,
e.g., solid antimony.
[0064] Referring to FIG. 5B, after deposition of the interface
layer 505, a metal oxide layer 565 is deposited. ALD for both the
interface layer 505 and metal oxide layer 565 facilitate conformal
formation over the 3D structure, and an even thickness can be
formed not only on the exposed horizontal surface of the source
region 530 and the drain region 540, but also on the vertical
sidewalls of the gate electrode 510.
[0065] Referring to FIG. 5C, the result of reduction of the metal
oxide and silicidation is shown. A metal silicide 570 is formed
where the interface layer and metal oxide layer had access to
silicon, particularly the exposed surfaces of the source region
530, drain region 540, and gate electrode 510. Additionally, a
metal layer 560 from the metal oxide is left on surfaces with no
access to free silicon, such as over the insulating layer 590 and
gate dielectric 520. As noted above, this excess or unreacted metal
560 can be readily removed by selective metal etch prior to further
processing.
[0066] FIGS. 5A-5C illustrate self-aligned silicidation on a
particularly simple example of a 3D transistor design. In certain
embodiments, the three-dimensional transistor may include
double-gate field effect transistors (DG FET), and other types of
multiple gate FETs, including FinFETs for example as found in IBM
J. Res. & Dev. Vol. 46 No. 2/3 (2002) by H.-S. P. Wong and
Tri-gate FET's for example as found in VLSI Technology Digest of
Technical Papers, June 2006, pp. 62-63 by J. Kavalieros and which
are each incorporated herein by reference.
[0067] Another 3D structure for which the silicidation techniques
taught herein are particularly useful is a 3D elevated source/drain
structure, as taught in U.S. Patent Publication No. 2009/0315120 to
Shifren et al., entitled "RAISED FACET- AND NON-FACET 3D
SOURCE/DRAIN CONTACTS IN MOSFETS, filed Jun. 24, 2008, the
disclosure of which is incorporated herein by reference in its
entirety. Shifren et al. teach elevated source/drain structures
that include vertical sidewalls, which would be difficult to
silicidize in a self-aligned manner without the methods taught
herein.
[0068] FIGS. 6A and 6B show schematic diagrams of example film
stacks corresponding to various steps in processes for forming
metal silicides, according to some embodiments. Although the
schematic diagrams of FIGS. 6A and 6B and corresponding description
refer to formation of a nickel oxide layer over a CoSb interface
layer and TiSb interface layer, respectively, it will be understood
that the processes described with reference to FIGS. 6A and 6B may
also be applicable to other metal oxide layers and/or other
interface layers as described herein. Referring to FIGS. 6A and 6B,
a silicon substrate 600 can be provided. In FIG. 6A, a CoSb
interface layer 610 can be provided over the silicon substrate 600.
The CoSb interface layer can be formed on and in direct contact
with the silicon substrate 600. A NiO layer 630 can be provided
over the interface layer 610. In some embodiments, the NiO 630
layer can be provided on and in direct contact with the CoSb
interface layer 610. The film stack may then be exposed to an
annealing process for reducing the NiO to form elemental nickel and
inducing silicidation reaction between the silicon of the substrate
600 and the elemental nickel formed from the NiO layer 630 and
cobalt from the CoSb interface layer 610. For example, the
annealing process may induce diffusion of the elemental nickel,
cobalt and silicon across the interface between interface layer 610
and the substrate 600 and silicide reaction between the silicon and
the elemental nickel and cobalt. In some embodiments, as described
herein, a process for reducing the NiO layer 630 to form elemental
nickel can be distinct and separate from a subsequent silicidation
process for inducing the silicide reaction between the elemental
nickel, cobalt and silicon.
[0069] In some embodiments, as shown in FIG. 6A, portions of the
NiO layer 630 and CoSb interface layer 610 can remain subsequent to
formation of the NiCoSi layer 640. For example, the NiCoSi layer
640 may be formed beneath the remaining CoSb interface layer 610.
In some embodiments, any remaining NiO layer 630 and CoSb interface
layer 610 can be removed in a post clean process. In some
embodiments, elemental nickel formed from the NiO layer 630 can
remain over the NiCoSi layer 640 after completion of the
silicidation reaction and may be subsequently removed while leaving
the NiCoSi layer 640 intact.
[0070] Referring to FIG. 6B, in some embodiments, a TiSb interface
layer 620 can be formed over the silicon substrate 600 rather than
a CoSb interface layer 610. As a result, a NiTiSi layer 650 can be
formed from the silicon of the substrate 600, the nickel from the
NiO layer 630 and the Ti from the TiSb interface layer 620. For
example, the TiSb interface layer 620 can be formed on and in
direct contact with the silicon substrate 600. The NiO 630 layer
can be provided over, for example on and in direct contact with,
the TiSb interface layer 620. The film stack may then be exposed to
an annealing process for reducing the NiO to form elemental nickel
and inducing silicidation reaction between the silicon of the
substrate 600, the elemental nickel formed from the NiO layer 630
and titanium from the TiSb interface layer 620. The annealing
process may induce diffusion of the elemental nickel, titanium and
silicon across the interface between the TiSb interface layer 620
and the substrate 600, as well as silicide reaction between the
silicon, the elemental nickel and titanium to form the NiTiSi layer
750. In some embodiments, as described herein, a process for
reducing the NiO layer 630 to form elemental nickel can be distinct
and separate from a silicidation process for inducing the silicide
reaction between the elemental nickel, titanium and silicon.
[0071] In some embodiments, portions of NiO layer 630 and TiSb
interface layer 620 can remain subsequent to formation of the
NiTiSi layer 650. For example, the NiTiSi layer 650 may be formed
beneath the remaining TiSb interface layer 620. In some
embodiments, any remaining NiO layer 630 and TiSb interface layer
620 can be removed in a post clean process. In some embodiments,
elemental nickel formed from the NiO layer 630 can remain over the
NiTiSi layer 650 and may be subsequently removed.
[0072] As described herein, in some embodiments, a metal oxide
layer and/or an interface layer may be deposited using an atomic
layer deposition (ALD) process. A layer deposited using ALD may
advantageously allow for deposition at low temperatures while
providing desired conformality. A process that provides good
conformality and uses low temperatures advantageously allows
precise control over the degree of silicidation and can preserve
designed transistor junction depths, increasing yield.
[0073] ALD type processes are based on controlled, self-limiting
surface reactions of precursor chemicals. Gas phase reactions are
avoided by feeding the precursors alternately and sequentially into
the reaction chamber. Vapor phase reactants are separated from each
other in the reaction chamber, for example, by removing excess
reactants and/or reactant by-products from the reaction chamber
between reactant pulses.
[0074] In some embodiments, a first vapor phase precursor is
contacted with a surface of the substrate. As described herein, the
substrate may comprise one or more three dimensional structures.
The first precursor may be contacted with one or more surfaces of a
three dimensional structure such to provide conformal deposition on
the three dimensional structure. Conditions for contacting the
first precursor with the substrate are preferably selected such
that no more than about one monolayer of the first precursor is
adsorbed on the substrate surface in a self-limiting manner. In
some embodiments, excess first precursor, if any, are purged from
the reaction chamber, often with a pulse of inert gas such as
nitrogen or argon.
[0075] In some embodiments, the substrate is contacted with a
second vapor phase precursor, which reacts with the first precursor
adsorbed to the surface of the substrate. As mentioned above, each
phase of each cycle is preferably self-limiting. An excess of
reactant precursors is supplied in each phase to saturate the
susceptible structure surfaces. Surface saturation ensures reactant
occupation of all available reactive sites (subject, for example,
to physical size or "steric hindrance" restraints) and thus ensures
excellent step coverage. In some arrangements, the degree of
self-limiting behavior can be adjusted by, e.g., allowing some
overlap of reactant pulses to trade off deposition speed (by
allowing some CVD-type reactions) against conformality. Ideal ALD
conditions with reactants well separated in time and space provide
near perfect self-limiting behavior and thus maximum conformality,
but steric hindrance results in less than one molecular layer per
cycle. Limited CVD reactions mixed with the self-limiting ALD
reactions can raise the deposition speed.
[0076] Excess second precursor and gaseous by-products of the
surface reaction are purged out of the reaction chamber, preferably
with the aid of an inert gas. The steps of pulsing and purging are
repeated until a thin film of the desired thickness has been formed
on the substrate, with each cycle leaving no more than a molecular
monolayer.
[0077] Some ALD processes can have more complex sequences with
three or more precursor pulses alternated, where each precursor
contributes elements to the growing film. Reactants can also be
supplied in their own pulses or with precursor pulses to strip or
getter adhered ligands and/or free by-product, rather than
contribute elements to the film. Additionally, not all cycles need
to be identical. For example, a binary film can be doped with a
third element by infrequent addition of a third reactant pulse,
e.g., every fifth cycle, in order to control stoichiometry of the
film, and the frequency can change during the deposition in order
to grade film composition.
[0078] Examples of suitable reactors that may be used include
commercially available ALD equipment such as the F120.TM. reactor,
Pulsar.TM. reactor and Advance.TM. 400 Series reactor, available
from ASM America, Inc. of Phoenix, Ariz. and ASM Europe B.V.,
Almere, Netherlands. In addition to these ALD reactors, many other
kinds of reactors capable of ALD growth of thin films, including
CVD reactors equipped with appropriate equipment and means for
pulsing the precursors can be employed. In some embodiments a flow
type ALD reactor is used. Preferably, reactants are kept separate
until reaching the reaction chamber, such that shared lines for the
precursors are minimized. However, other arrangements are possible,
such as the use of a pre-reaction chamber as described in U.S. Pat.
No. 8,152,922, entitled "GAS MIXER AND MANIFOLD ASSEMBLY FOR ALD
REACTOR," filed Aug. 30, 2004 and U.S. Pat. No. 7,105,054, entitled
"METHOD AND APPARATUS OF GROWING A THIN FILM ONTO A SUBSTRATE,"
filed Apr. 16, 2001, the disclosures of each of which are
incorporated herein by reference.
[0079] In some embodiments, the interface layer and the metal oxide
layer can optionally be carried out in a reactor or reaction space
connected to a cluster tool. In a cluster tool, because each
reaction space is dedicated to one type of process, the temperature
of the reaction space in each module can be kept constant, which
improves the throughput compared to a reactor in which is the
substrate is heated up to the process temperature before each
run.
[0080] A stand-alone reactor can be equipped with a load-lock. In
that case, it is not necessary to cool down the reaction space
between each run.
[0081] A substrate can be loaded into a reaction chamber and is
heated to a suitable deposition temperature, generally at lowered
pressure. Deposition temperatures are maintained below the
precursor thermal decomposition temperature but at a high enough
level to avoid condensation of reactants and to provide the
activation energy for the desired surface reactions. Of course, the
appropriate temperature window for any given ALD reaction will
depend upon the surface termination and reactant species
involved.
Interface Layer
[0082] As described herein, the interface layer can be configured
to prevent or substantially prevent oxidation of the underlying
silicon. The interface layer may have a thickness such that
undesired oxidation of the underlying silicon can be avoided during
subsequent processing of the substrate, while allowing diffusion
therewithin of silicide forming metal. In some embodiments, the
interface layer can have a thickness of about 1 nanometers (nm) to
about 15 nm. For example, the interface layer can have a thickness
of about 1 nm to about 5 nm. In some embodiments, the thickness of
the interface layer can be selected based on the composition of the
metal oxide layer and/or the composition of the interface
layer.
[0083] As described herein, the interface layer may comprise one or
more silicide forming metals and one or more non-silicide forming
elements. For example, in some embodiments, a non-silicide forming
element of the interface layer comprises one or more of antimony
(Sb), germanium (Ge) and tin (Sn). In some embodiments, a silicide
forming metal of the interface layer comprises one or more of
cobalt (Co), platinum (Pt), titanium (Ti), aluminum (Al) and
hafnium (Hf). In some embodiments, the silicide forming metal can
comprise one or more of erbium (Er), ytterbium (Yb) and dysprosium
(Dy). For example, the interface layer may be a CoSb layer. In some
embodiments, the interface layer may be a TiSb, an AlSb and/or a
HfSb layer.
[0084] In some embodiments, a process for depositing the interface
layer can comprise an atomic layer deposition (ALD) process. In
some embodiments, an ALD process for forming the interface layer
comprises a plurality of deposition cycles, where one or more of
the plurality of cycles comprises alternating and sequential
exposure of the substrate to vapor phase precursors for forming the
interface layer. For example, a deposition cycle of the ALD process
may comprise alternating and sequential contact of the substrate
with a first vapor phase precursor and a second vapor phase
precursor. In some embodiments, the first vapor phase precursor
comprises a silicide forming metal and the second vapor phase
precursor comprises a non-silicide forming element.
[0085] In some embodiments, a process for depositing the interface
layer can comprise a chemical vapor deposition (CVD) process.
Precursors and/or process conditions for CVD processes can be
selected by a skilled artisan to provide an interface layer
comprising desired characteristics. In some embodiments, a CVD
process for depositing a Ge containing interface layer can be
conducted using germane and/or digermane, and hydrogen gas
(H.sub.2), at a process temperature of greater than about
300.degree. C., or greater than about 400.degree. C.
[0086] FIG. 7 is a process flow diagram of a process 700 for
forming an interface layer on a substrate in a reaction chamber,
according to some embodiments. In block 702, exposed silicon
regions of a substrate can be contacted with a first vapor phase
precursor comprising a silicide forming metal. For example, the
first vapor phase precursor comprising the silicide forming metal
can be contacted with the surface of the substrate such that first
species adsorb onto the surface. In some embodiments, the first
species may be same as the first vapor phase precursor, or may be
modified in the adsorbing step, such as by losing one or more
ligands. In some embodiments, contacting the substrate with the
first vapor phase precursor comprises supplying a first reactant
pulse comprising the first vapor phase precursor into the reaction
chamber. In block 704, the first species on the substrate can be
contacted with a second vapor phase precursor comprising a
non-silicide forming element. For example, the first species
adsorbed onto the substrate surface can be contacted with the
second vapor phase precursor such that the second vapor phase
precursor can react with the first species to form at most a
monolayer of the interface layer. In some embodiments, less than a
monolayer of the interface layer is formed, due for example to
physical size and/or steric hindrance restraints. In some
embodiments, contacting the first species on the substrate with the
second vapor phase precursor comprises supplying a second reactant
pulse comprising the second vapor phase precursor into the reaction
chamber. As discussed herein, in some embodiments, the interface
layer can be a CoSb thin film. In some embodiments, the first vapor
phase precursor may comprise a cobalt containing precursor and the
second vapor phase precursor may comprise an antimony containing
precursor. In some embodiments, the first vapor phase precursor may
comprise a titanium containing precursor and the second vapor phase
precursor may comprise an antimony containing precursor such that
TiSb thin film can be formed.
[0087] The first reactant pulse and/or the second react pulse may
comprise a carrier gas, such as an inert gas. In some embodiments,
the inert gas may comprise nitrogen gas and/or a noble gas, such as
argon gas.
[0088] In some embodiments, one or more reactant pulses can be
followed by an interval in which the substrate is not exposed to
the vapor phase precursors, such as an interval during which the
first precursor and the precursor are not actively supplied into
the reaction chamber. The interval may comprise a purge step and/or
transport of the substrate into a space free or substantially free
of reactants. For example, the substrate may first be transported
to a space free or substantially free of the reactants and the
reaction chamber may then be purged of any excess reactants and/or
reaction byproducts. In some embodiments, each reactant pulse of a
plurality of reactant pulses may be followed by a purge step and/or
transport of the substrate to a space free or substantially free of
the reactants. The purge step may be configured to remove one or
more excess reactants and/or reaction byproducts from the reaction
chamber. For example, a purge step may comprise flowing one or more
purge gases through the reaction chamber, and/or evacuating the
reaction chamber to remove or substantially remove excess reactants
and/or reaction byproducts (e.g., by drawing a vacuum upon the
reaction chamber). In some embodiments, the purge gas comprises an
inert gas. In some embodiments, the purge gas comprises nitrogen
gas. In some embodiments, the purge gas comprises a noble gas. In
some embodiments, the purge gas comprises argon gas.
[0089] In some embodiments, a reactant pulse can be followed by
discontinuing flow of the one or more vapor phase precursors into
the reaction chamber while continuing flow of the carrier gas. For
example, a purge step may comprise continued flow of the carrier
gas (e.g., at a same or different flow rate, such as a higher flow
rate, as compared to that during the reactant pulse) in order to
remove excess reactants and/or reaction byproducts from the
reaction chamber. In some embodiments, a purge step may comprise
continuing flow of at least one component of a carrier gas
comprising a mixture of two or more gases for removing excess
reactant from the reaction chamber. In some embodiments, a process
for depositing an interface layer may include continuously flowing
the carrier gas, or more or more components of a multi-component
carrier gas, while pulsing the first vapor phase precursor and the
second vapor phase precursor at alternating and sequential
intervals.
[0090] A duration of the first or second reactant pulse can be
selected to provide a desired quantity of the first precursor or
second precursor into the reaction chamber. In some embodiments, a
reactant pulse can have a duration of about 0.1 seconds (s) to
about 10 s, including about 0.1 s to about 5 s. For example, a
reactant pulse can have a duration of about 2 s.
[0091] In some embodiments, an interval between reactant pulses can
be about 0.05 second (s) to about 20 s, including about 1 second to
about 15 seconds, about 1 second to about 10 seconds, or about 1 to
about 2 seconds. In some embodiments, the interval can be about 5
s. In some embodiments, the interval comprises a purge step for
removing excess reactants and/or reaction byproducts from the
reactor chamber. In some embodiments, the interval comprises
transport of the substrate to a space free or substantially free of
reactants. For example, the interval may comprise transport of the
substrate to a space free or substantially free of reactants, and a
purge step having a duration of about 0.5 s to about 15 s,
including about 1 s to about 10 s. For example, the purge step can
have a duration of about 5 s. In some embodiments, the purge step
can have a duration of about 1 s.
[0092] In some embodiments, a duration of the reactant pulse and/or
the interval between reactant pulses (e.g., including for example,
duration of a purge step) can be selected based a surface area of
the substrate on which the interface layer is deposited, an aspect
ratio of a three dimensional (3-D) structure on which the interface
layer is deposited, and/or a configuration of the reaction chamber.
For example, the reactant pulse and/or the interval between
reactant pulses may have an increased duration for depositing an
interface layer on a larger surface area, over 3-D structures
having increased aspect ratios, a surface with complex surface
morphology, and/or for deposition in a batch reactor. In some
embodiments, an increased reactant pulse duration and/or interval
between reactant pulses is selected for deposition on ultra-high
aspect ratio features, including for example, features having
aspect ratios of about 40:1 and greater, including about 80:1 and
greater.
[0093] In some embodiments, the substrate temperature during
depositing the interface layer can be up to about 500.degree. C. In
some embodiments, the substrate temperature can be about
100.degree. C. to about 500.degree. C., about 200.degree. C. to
about 500.degree. C., or about 200.degree. C. to about 400.degree.
C. In some embodiments, the substrate temperature during depositing
the interface layer is less than about 250.degree. C., less than
about 200.degree. C., or below about 150.degree. C.
[0094] Pressure of the reaction chamber can vary much depending
from the reactor used for the depositions. Typically reactor
pressures are below normal ambient pressure. In some embodiments,
the pressure in the reaction space is preferably from about 0.5
millibar (mbar) to about 20 mbar, more preferably from about 1 mbar
to about 10 mbar.
[0095] FIG. 8 is a process flow diagram of a deposition cycle 800
for forming a CoSb interface layer on a substrate in a reaction
chamber in accordance with some embodiments. The process for
forming the CoSb interface layer may comprise alternating and
sequential contact of the substrate surface with an antimony
containing vapor phase precursor and a cobalt containing vapor
phase precursor.
[0096] In block 802, exposed silicon regions of a substrate can be
contacted with a cobalt containing vapor phase precursor. For
example, a first reactant pulse comprising the cobalt containing
vapor phase precursor can be provided into the reaction chamber
such that the cobalt containing vapor phase precursor can adsorb
onto the substrate surface and form no more than about a single
molecular layer. In block 804, excess cobalt containing vapor phase
precursor can be removed from the reaction chamber. In block 806,
the cobalt containing species on the substrate can be contacted
with an antimony containing vapor phase precursor. A second
reactant pulse comprising the antimony containing vapor phase
precursor can be provided into the reaction chamber such that
antimony containing precursor can react with the cobalt containing
species adsorbed on the substrate to form CoSb. In block 808,
excess antimony containing precursor and/or reaction byproducts can
be removed from the reaction chamber.
[0097] The deposition cycle 800 can be repeated until a CoSb
interface thin film of a desired thickness is formed. In some
embodiments a CoSb thin film of from about 10 angstroms (.ANG.) to
about 2000 .ANG., preferably from about 20 .ANG. to about 60 .ANG.,
is formed for use as an interface layer prior to metal oxide
deposition.
[0098] FIG. 9 is a process flow diagram of a deposition cycle 900
for forming a TiSb interface layer on a substrate in a reaction
chamber in accordance with some embodiments. The process for
forming the TiSb interface layer may comprise alternating and
sequential contact of the substrate surface with an antimony
containing vapor phase precursor and a titanium containing vapor
phase precursor. In block 902, exposed silicon regions of a
substrate can be contacted with a titanium containing vapor phase
precursor. For example, a titanium containing vapor phase
precursor, such as a first reactant pulse comprising the titanium
containing vapor phase precursor, can be provided into the reaction
chamber. Titanium containing vapor phase species can adsorb onto
the substrate surface and form no more than about a single
molecular layer. In block 904, excess titanium containing vapor
phase precursor can be removed from the reaction chamber. In block
906, the titanium containing species on the substrate can be
contacted with an antimony containing vapor phase precursor. For
example, a second reactant pulse comprising the antimony containing
vapor phase precursor can be provided into the reaction chamber
such that antimony containing precursor reacts with the titanium
containing species adsorbed on the substrate to form TiSb. In block
908, excess antimony containing precursor and/or reaction
byproducts can be removed from the reaction chamber.
[0099] The deposition cycle 900 can be repeated until a TiSb
interface thin film of a desired thickness is formed. In some
embodiments, a TiSb thin film of about 10 angstroms (.ANG.) to
about 2000 .ANG., preferably about 20 .ANG. to about 60 .ANG., is
formed for use as an interface layer prior to metal oxide
deposition.
[0100] Although the illustrated deposition cycle 800 of FIG. 8
begins with provision of the cobalt containing precursor and the
deposition 900 of FIG. 9 begins with provision of the titanium
containing precursor, in other embodiments the deposition cycle can
begin with the provision of the antimony containing precursor.
[0101] In some embodiments, the vapor phase precursor comprising
the silicide forming metal comprises a metal halide, such as a
chloride. For example, the metal halide may be a cobalt halide,
molybdenum halide, a tantalum halide, or a tungsten halide. In some
embodiments, a molybdenum containing vapor phase precursor for
forming an interface layer comprises MoCl.sub.5. In some
embodiments, a tantalum containing vapor phase precursor comprises
TaCl.sub.5. In some embodiments, a tungsten containing vapor phase
precursor comprises WF.sub.6. In some embodiments, cobalt
containing vapor phase precursor has a formula of CoX.sub.2,
wherein X is a halogen element. For example, the Co source is
CoCl.sub.2, CoBr.sub.2, CoF.sub.2 or CoI.sub.2. More preferably the
Co source is CoCl.sub.2. In some embodiments, the titanium
containing vapor phase precursor can have a formula of TiX.sub.4,
wherein X is a halogen element. For example, the Ti source is
TiCl.sub.4, TiBr.sub.4, TiF.sub.4 or TiI.sub.4. More preferably the
Ti source is TiCl.sub.4.
[0102] In some embodiments, an antimony containing vapor phase
precursor can have a formula of Sb(SiR.sup.1R.sup.2R.sup.3).sub.3,
wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups comprising
one or more carbon atoms. The R.sup.1, R.sup.2, and R.sup.3 alkyl
groups can be selected based on the desired physical properties of
the precursor such as volatility, vapor pressure, toxicity, etc. In
some embodiments, the antimony containing vapor phase precursor is
Sb(SiEt.sub.3).sub.3 or Sb(SiMe.sub.3).sub.3. In some embodiments,
the antimony containing vapor phase precursor can be a halide. For
example, the precursor may be SbCl.sub.3. In some embodiments, a
germanium containing vapor phase precursor can comprise germane,
germanium alkoxide, tetrakis(dimethylamino)germanium (TDMAGe),
and/or germanium halide. In some embodiments, the germanium halide
may be GeCl.sub.4. In some embodiments, a tin containing vapor
phase precursor can comprise stannane, tin alkoxide, tin halide,
and/or tetrakis(dimethylamino)tin (TDMAGe).
[0103] In some embodiments, the cobalt containing vapor phase
precursor in an ALD process for forming a CoSb interface layer is
CoCl.sub.2 and the antimony containing vapor phase precursor is
tris(trimethylsilyl)antimony, Sb(SiMe.sub.3).sub.3. In some
embodiments, the titanium containing vapor phase precursor in an
ALD process for forming a TiSb interface layer is TiCl.sub.4 and
the antimony containing vapor phase precursor is
tris(trimethylsilyl)antimony, Sb(SiMe.sub.3).sub.3.
[0104] In some embodiments, an interface layer can be deposited
using ALD processes comprising alternately and sequentially
contacting the substrate with multiple reactants. In some
embodiments, a silicide forming metal can be incorporated into the
layer by a deposition cycle using two reactants, and a non-silicide
forming element can be incorporated into the layer by a deposition
cycle using two reactants. For example, a silicide forming metal
can be introduced into the growing layer by alternately and
sequentially exposing a substrate to a precursor comprising the
silicide forming metal and a first reducing agent. In some
embodiments, a non-silicide forming element can be introduced by
alternately and sequentially exposing a substrate to a precursor
comprising the non-silicide forming element and a second reducing
agent. For example, an ALD process for depositing an interface
layer can include a super cycle comprising one or more deposition
sub-cycles for introducing the silicide forming metal, followed by
one or more deposition sub-cycles for introducing the non-silicide
forming element, or vice versa. In some embodiments, a sub-cycle
for introducing the silicide forming metal comprises exposing the
substrate to a precursor comprising the silicide forming metal and
a first reducing agent. In some embodiments, a sub-cycle for
introducing the non-silicide forming element comprises exposing the
substrate to a precursor comprising the non-silicide forming
element and a second reducing agent. In some embodiments, the
sub-cycle for introducing the silicide forming metal can be
repeated a number of times prior to performing the one or more
sub-cycles for introducing the non-silicide forming element, or
vice versa. In some embodiments, the number of each of the
sub-cycles in the super-cycle process can be adjusted to provide an
interface layer comprising desired characteristics. In some
embodiments, the super-cycle can be repeated a number of times to
deposit an interface layer comprising the desired thickness.
[0105] In some embodiments, a sub-cycle for introducing cobalt into
an interface layer can comprise exposing the substrate to
tertbutylallylcobalttricarbonyl (tBu-AllylCo(CO).sub.3) and a
reducing agent comprising hydrogen and/or hydrazine. In some
embodiments, a sub-cycle for introducing titanium, tantalum, or
tungsten can comprise exposing the substrate to a metal halide and
a reducing agent comprising hydrogen and/or hydrazine. For example,
the metal halide may be MoCl.sub.5, TaCl.sub.5 or WF.sub.6. In some
embodiments, a sub-cycle for introducing tungsten can comprise
exposing the substrate to WF.sub.6 and disilane. In some
embodiments, a sub-cycle for introducing antimony into an interface
layer can comprise exposing the substrate to an alkylsilyl antimony
and SbCl.sub.3. In some embodiments, the alkylsilyl antimony can
have a formula of Sb(SiR.sup.1R.sup.2R.sup.3).sub.3, wherein
R.sup.1, R.sup.2, and R.sup.3 are alkyl groups comprising one or
more carbon atoms. The R.sup.1, R.sup.2, and R.sup.3 alkyl groups
can be selected based on the desired physical properties of the
precursor such as volatility, vapor pressure, toxicity, etc. In
some embodiments, the alkylsilyl antimony is Sb(SiEt.sub.3).sub.3
or Sb(SiMe.sub.3).sub.3.
[0106] FIG. 10 shows an example of deposition performance of TiSb
deposited on blanket wafer at substrate temperatures of about
100.degree. C. The wafer map shows thickness in angstroms (.ANG.)
across the wafer. The TiSb film was deposited using ALD processes
comprising TiCl.sub.4 and Sb(SiMe.sub.3).sub.3. The measurements
shown in FIG. 10 were taken after 200 deposition cycles. The
deposition process demonstrated an average deposition rate of about
2 .ANG./cycle, and the deposited TiSb films demonstrated a
refractive index of about 1.9. As shown in FIG. 10, the average
thickness of the TiSb film after 200 deposition cycles was about
391.78 .ANG., and while demonstrating a 1-sigma (1-.sigma.)
uniformity about 4.77%.
ALD of Metal Oxide
[0107] In some embodiments, a metal oxide thin film can be
deposited over the interface layer. As described herein, the metal
oxide layer may comprise a silicide forming metal. According to
some embodiments, a metal oxide thin film is formed on the
interface layer by a vapor deposition process, such as by an ALD
type process comprising multiple pulsing cycles, each cycle
comprising: [0108] pulsing a vaporized metal precursor into the
reaction chamber to form at most a molecular monolayer of the metal
precursor on the substrate, [0109] purging the reaction chamber to
remove excess metal precursor and reaction by products, if any,
[0110] providing a pulse of a second reactant comprising an oxygen
source onto the substrate, [0111] purging the reaction chamber to
remove excess second reactant and any gaseous by-products formed in
the reaction between the metal precursor layer on the first surface
of the substrate and the second reactant, and [0112] repeating the
pulsing and purging steps until a metal oxide thin film of the
desired thickness has been formed.
[0113] The thin metal oxide film typically comprises multiple
monolayers of a single metal oxide. However, in other embodiments,
the final metal structure may comprise two or more different metal
oxides. For example, the growth can be started with the deposition
of a first metal oxide and ended with the deposition of a second
metal oxide. In other embodiments, alternating layers of metal
oxides can be deposited.
[0114] The metal oxide is preferably selected from the group
consisting of Ni, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Co, Cu, Fe, Ru,
Ir, Rh, Pd and Pt oxides and may be in some cases electrically
conductive, such as in a case of IrO.sub.2 or RuO.sub.2. In some
embodiments, the metal oxide thin film is a nickel oxide thin film,
such as NiO. In some embodiments, the metal oxide thin film is a
cobalt oxide thin film, such as CoO.
[0115] Suitable metal precursors may be selected by the skilled
artisan. In general, metal compounds where the metal is bound or
coordinated to oxygen, nitrogen, carbon or a combination thereof
are preferred. In some embodiments the metal precursors are organic
compounds. More preferably betadiketonate, betadiketiminato
compounds, amidinate compounds, aminoalkoxide, ketoiminate or
cyclopentadienyl compounds or derivatives thereof are used. In some
embodiments, X(acac).sub.y or X(thd).sub.y compounds are used,
where X is a metal, y is generally, but not necessarily between 2
and 3 and thd is 2,2,6,6-tetramethyl-3,5-heptanedionato.
[0116] In some embodiments, metal precursors for depositing cobalt
oxide can include one or more of
bis(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt(II)
(Co(thd).sub.2), bis(cyclopentadienyl)cobalt(II) (Co(Cp).sub.2),
and tertbutylallylcobalttricarbonyl (tBu-AllylCo(CO).sub.3). In
some embodiments, cobalt oxide can be deposited from alternating
and sequential pulses of a Co precursor and an oxygen source, like
water, ozone, oxygen plasma, oxygen radicals or oxygen atoms.
[0117] Some examples of suitable betadiketiminato (e.g.,
Ni(pda).sub.2) compounds for depositing nickel oxide are mentioned
in U.S. Patent Publication No. 2009-0197411, filed Feb. 2, 2009,
entitled "NEW METAL PRECURSORS CONTAINING BETA-DIKETIMINATO
LIGANDS," the disclosure of which is incorporated herein in its
entirety. Some examples of suitable amidinate compounds (e.g.,
Ni(.sup.iPr-AMD).sub.2) are mentioned in U.S. Patent Publication
No. 2006-0141155, filed Nov. 14, 2003, entitled "ATOMIC LAYER
DEPOSITION USING METAL AMIDINATES," the disclosure of which is
incorporated herein in its entirety. Some examples of suitable
aminoalkoxide compounds are mentioned in U.S. Patent Publication
No. 2008-0171890, filed Apr. 7, 2005, entitled "VOLATILE NICKEL
AMINOALKOXIDE COMPLEX AND DEPOSITION OF NICKEL THIN FILM USING
SAME," the disclosure of which is incorporated herein in its
entirety.
[0118] When depositing nickel oxide thin films, preferred metal
precursors can be selected from the group consisting of nickel
betadiketonate compounds, nickel betadiketiminato compounds, nickel
amidinate compounds, nickel cyclopentadienyl compounds, nickel
carbonyl compounds and combinations thereof. The nickel precursor
may also comprise one or more halide ligands. In preferred
embodiments, the precursor is nickel betadiketiminato compound,
such bis(4-N-ethylamino-3-penten-2-N-ethyliminato)nickel (II)
[Ni(EtN-EtN-pent).sub.2], nickel ketoiminate, such
bis(3Z)-4-nbutylamino-pent-3-en-2-one-nickel(II), nickel amidinate
compound, such as
methylcyclopentadienyl-isopropylacetamidinate-nickel (II), nickel
betadiketonato compound, such as Ni(acac).sub.2, Ni(thd).sub.2 or
nickel cyclopentadienyl compounds, such as Ni(cp).sub.2,
Ni(Mecp).sub.2, Ni(Etcp).sub.2 or derivatives thereof, such as
methylcyclopentadienyl-isopropylacetamidinate-nickel (II). In more
preferred embodiment, the precursor is
bis(4-N-ethylamino-3-penten-2-N-ethyliminato)nickel (II).
[0119] In some embodiments nickel oxide, preferably NiO, is
deposited from alternating and sequential pulses of a Ni precursor
and an oxygen source, like water, ozone, oxygen plasma, oxygen
radicals or oxygen atoms. The Ni precursor preferably comprises a
betadiketonate or betadiketiminato compounds and more preferably is
Ni(acac).sub.2. In some embodiments the Ni precursors have at least
one Ni--N bond. The reaction temperature is preferably less than
about 300.degree. C., more preferably less than about 200.degree.
C. In some embodiments, the reaction temperature can be in the
range of about 60.degree. C. to about 150.degree. C. for example,
in the case of Ni(cp).sub.2.
[0120] The metal precursor employed in the ALD type processes may
be solid, liquid or gaseous material under standard conditions
(room temperature and atmospheric pressure), provided that the
metal precursor is in vapor phase before it is conducted into the
reaction chamber and contacted with the substrate surface.
"Pulsing" a vaporized precursor onto the substrate means that the
precursor vapor is conducted into the chamber for a limited period
of time. Typically, the pulsing time is from about 0.05 to about 10
seconds. However, depending on the substrate type and its surface
area, the pulsing time may be even higher than 10 seconds.
[0121] Preferably, for a 300 mm wafer in a single wafer ALD
reactor, the metal precursor is pulsed for from about 0.05 to about
10 seconds, more preferably for from about 0.1 to about 5 seconds
and most preferably for from about 0.3 to about 3.0 seconds. The
oxygen-containing precursor is preferably pulsed for from about
0.05 to about 10 seconds, more preferably for from about 0.1 to
about 5 seconds, most preferably for from about 0.2 to about 3.0
seconds. However, pulsing times can be on the order of minutes in
some cases. The optimum pulsing time can be readily determined by
the skilled artisan based on the particular circumstances.
[0122] The mass flow rate of the metal precursor can be determined
by the skilled artisan. In one embodiment, for deposition on 300 mm
wafers the flow rate of the metal precursor is preferably between
about 1 standard cubic centimeters per minute (sccm) and about 1000
sccm without limitation. The mass flow rate of the metal precursor
is usually lower than the mass flow rate of the oxygen source,
which is usually between about 10 sccm and about 10000 sccm without
limitation, more preferably between about 100 sccm-about 2000 sccm
and most preferably between about 100 sccm-about 1000 sccm.
[0123] The pressure in the reaction chamber is typically from about
0.01 millibar (mbar) to about 20 mbar, more preferably from about 1
to about 10 mbar. However, in some cases the pressure will be
higher or lower than this range, as can be readily determined by
the skilled artisan.
[0124] The oxygen source may be an oxygen-containing gas pulse and
can be a mixture of oxygen and inactive gas, such as nitrogen or
argon. In some embodiments the oxygen source may be a molecular
oxygen-containing gas pulse. The preferred oxygen content of the
oxygen-source gas is from about 10% to about 25%. Thus, one source
of oxygen may be air. In some embodiments, the oxygen source is
molecular oxygen. In some embodiments, the oxygen source comprises
an activated or excited oxygen species. In some embodiments, the
oxygen source comprises ozone. The oxygen source may be pure ozone
or a mixture of ozone, molecular oxygen, and another gas, for
example an inactive gas such as nitrogen or argon. Ozone can be
produced by an ozone generator and it is most preferably introduced
into the reaction space with the aid of an inert gas of some kind,
such as nitrogen, or with the aid of oxygen. In some embodiments,
ozone is provided at a concentration from about 5 vol-% to about 40
vol-%, and preferably from about 15 vol-% to about 25 vol-%. In
other embodiments, the oxygen source is oxygen plasma.
[0125] As mentioned above, the metal oxide ALD process typically
comprises alternating pulses of metal precursor and a reactant
comprising an oxygen source. The oxygen source pulse may be
provided, for example, by pulsing ozone or a mixture of ozone and
another gas into the reaction chamber. In other embodiments, ozone
is formed inside the reactor, for example by conducting oxygen
containing gas through an arc. In other embodiments, an oxygen
containing plasma is formed in the reactor. In some embodiments,
the plasma may be formed in situ on top of the substrate or in
close proximity to the substrate. In other embodiments, the plasma
is formed upstream of the reaction chamber in a remote plasma
generator and plasma products are directed to the reaction chamber
to contact the substrate. As will be appreciated by the skilled
artisan, in the case of a remote plasma the pathway to the
substrate can be optimized to maximize electrically neutral species
and minimize ion survival before reaching the substrate.
[0126] Before starting the deposition of the film, the substrate is
typically heated to a suitable growth temperature. Preferably, the
growth temperature of the metal thin film is less than about
400.degree. C., more preferably less than about 350.degree. C. and
even more preferably less than about 200.degree. C. The preferred
deposition temperature may vary depending on a number of factors
such as, and without limitation, the reactant precursors, the
pressure, flow rate, the arrangement of the reactor, and the
composition of the substrate including the nature of the material
to be deposited on. The specific growth temperature may be selected
by the skilled artisan using routine experimentation.
[0127] The processing time depends on the thickness of the layer to
be produced and the growth rate of the film. In ALD, the growth
rate of a thin film is determined as thickness increase per one
cycle. One cycle consists of the pulsing and purging steps of the
precursors and the duration of one cycle is typically between about
0.2 and about 30 seconds, more preferably between about 1 and about
10 seconds, but it can be on order of minutes or more in some
cases, for example, where large surface areas and volumes are
present.
[0128] A metal oxide, such as nickel oxide, is deposited by ALD
over the interface layer to form a conformal thin film of between
about 1 nm and about 200 nm, preferably between about 3 nm and
about 100 nm in thickness. As described above, in some embodiments,
the metal oxide is deposited conformally over vertical and
horizontal surfaces. Although described in terms of NiO deposition,
the method may be readily adjusted to deposit other metal oxides.
As discussed previously, deposition of metal oxide takes place in a
reaction space maintained at less than about 300.degree. C., more
preferably less than about 250.degree. C. and even more preferably
less than about 200.degree. C. and between about 0.01 and about 20
mbar, more preferably between about 1 and about 10 mbar. In certain
embodiments, deposition by ALD comprises contacting the substrate
with a vapor phase metal source chemical and a vapor phase oxygen
source chemical. This may be done sequentially with either the
metal source chemical or the oxygen source chemical being pulsed
into the reaction space before the other. In certain embodiments, a
purge gas may be introduced into the reaction space between
sequential pulses of the metal and oxygen source chemicals to aid
in removing excess reactant and reaction byproducts, if any, from
the reaction space. In certain embodiments, purging may take place
with the aid of a vacuum pump. In other embodiments, if an inert
carrier gas is used to help flow in the metal or oxygen source
chemicals, the inert gas may also function as the purge gas.
[0129] The metal source chemical may comprise Ni, Ti, Zr, Hf, V,
Nb, Ta, Cr, Mo, W, Co, Cu, Fe, Ru, Ir, Rh, Pd and Pt. The oxygen
source chemical may be chosen from O.sub.2, H.sub.2O, O.sub.3,
oxygen plasma, oxygen radicals or oxygen atoms or a reactive oxygen
gas. By depositing metal oxide by ALD, the metal oxide is placed in
direct contact with the interface layer in at least one location,
but preferably a plurality of regions, and the interface layer thus
prevents direct exposure of the underlying silicon to the oxidizing
environment of the metal oxide deposition.
[0130] Methods for ALD of metal oxide are also disclosed in
Utriainen et al., "Studies of metallic thin film growth in an
atomic layer epitaxy reactor using M(acac).sub.2 (M=Ni, Cu, Pt)
precursors," APPLIED SURFACE SCIENCE 157 (2000), pp. 151-158, and
Utriainen et al., "Studies of NiO thin film formation by atomic
layer epitaxy", MATERIALS SCIENCE AND ENGINEERING B54 (1998), pp.
98-103, the disclosures of which are expressly incorporated herein
by reference.
CVD of Metal Oxide
[0131] The skilled artisan will appreciate that the metal oxide
need not be deposited by ALD and that other conformal techniques
(e.g., CVD) can also be used. CVD of nickel oxide, for example, can
be conducted by known techniques, such as the provision of metal
organic nickel source with an oxidizing source. In some
embodiments, CVD of cobalt oxide can be conducted by known
techniques, such as the provision of metal organic cobalt source
with an oxidizing source. In some embodiments, a metal organic
cobalt source can comprise a dicobalt carbonyl. In some
embodiments, a metal organic cobalt source can comprise one or more
of bis(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt(II)
(Co(thd).sub.2), bis(cyclopentadienyl)cobalt(II) (Co(Cp).sub.2),
and/or tertbutylallylcobalttricarbonyl (tBu-AllylCo(CO).sub.3). In
some embodiments, cobalt oxide can be deposited from pulses of a Co
precursor and an oxygen source, like water, ozone, oxygen plasma,
oxygen radicals or oxygen atoms.
[0132] CVD processes typically involve gas phase reactions between
two or more reactants. The reactants can be provided simultaneously
to the reaction space or substrate. The substrate or reaction space
can be heated to promote the reaction between the gaseous
reactants. CVD deposition occurs when the reactants are provided to
the reaction space. In some embodiments the reactants are provided
until a thin film having a desired thickness is deposited. In some
embodiments cyclical CVD can be used with multiple cycles used to
deposit a thin film having a desired thickness. In some embodiments
one or more plasma reactants can be used in the CVD process.
[0133] In some embodiments the ALD-processes can be modified to be
partial CVD processes. In some embodiments the ALD processes can be
modified to be pulsed CVD processes. In some embodiments the ALD
processes are modified to use overlapping or partially overlapping
pulses of reactants. In some embodiments the ALD processes are
modified to use extremely short purge times, such as below about
0.1 s (depending on the reactor). In some embodiments the ALD
processes are modified to use no purge at all. In some embodiments
the no purge is used after the metal reactant pulse. In some
embodiments no purge is used after the oxygen reactant pulse. In
some embodiments no purge is used after either the metal reactant
pulse or the oxygen reactant pulse.
Reduction and Solid State Reaction
[0134] As described herein, in some embodiments, reduction of the
metal oxide to metal can be conducted simultaneously with
silicidation reaction using a moderately reducing environment
(e.g., H.sub.2 or H.sub.2/N.sub.2) at temperatures (e.g., greater
than about 250.degree. C., more preferably greater than about
300.degree. C. and in some embodiments about 400.degree. C. or
greater or even about 500.degree. C. or greater) sufficient to
effect silicidation through the interface layer. In other
arrangements, reduction can be conducted independently of
silicidation, especially at lower temperatures using stronger
reducing agents. More details and options for the reduction and
silicidation reactions are provided below.
[0135] Regardless of whether simultaneous with the solid phase
reaction or preceding it, the metal oxide layer, such as nickel
oxide, is reduced to metal. In certain embodiments, as discussed in
U.S. Pat. No. 6,921,712, filed Nov. 15, 2002, entitled "PROCESS FOR
PRODUCING INTEGRATED CIRCUITS INCLUDING REDUCTION USING GASEOUS
ORGANIC COMPOUNDS," the entire disclosure of which is incorporated
by reference, the metal oxide layer is contacted with vapor phase
reducing agents, which may include H.sub.2, NH.sub.3, hydrogen
containing plasma, hydrogen radicals or hydrogen atoms and reactive
organic compounds, which contain at least one functional group
selected from the group of alcohol (--OH), aldehyde (--CHO), and
carboxylic acid (--COOH). The vapor phase reducing agents form
stronger bonds with the oxygen in the metal oxide layer than the
metal to the oxygen. Thus, the gaseous reducing agent is capable of
taking away the oxygen that was bound to the metal oxide and thus
leaving an elemental metal layer on the substrate surface. This
reduction step can be performed at temperatures between about
25.degree. C. and about 400.degree. C. and has the benefit of a
high rate of reduction, an operation time of between about 1 s and
about 1000 s, and low levels of carbon or hydrogen impurities. A
skilled artisan will recognize that the metal oxide layer may be
reduced to metal by other methods known in the art, such as for
example by H.sub.2 plasma, formic acid or ethanol.
[0136] In one embodiment, the NiO layer is reduced by exposure to
an organic reducing agent that is capable of removing oxygen from
the metal oxide, leaving elemental nickel on the substrate.
Preferably the NiO layer is reduced by exposure to an organic
reducing agent in vapor form.
[0137] The substrate containing the nickel oxide layer to be
reduced is placed in a reaction space, such as an ALD reaction
chamber, and the reaction space is evacuated to vacuum. The organic
reducing agent is preferably vaporized and fed to the reaction
space, optionally with the aid of an inert carrier gas, such as
nitrogen. In one embodiment a vapor mixture is used, comprising two
or more reducing agents.
[0138] The reducing agent vapor is contacted with the substrate,
preferably at low pressure, whereby the nickel oxide layer is
reduced at least partly to nickel metal and the reducing agent is
oxidized. Typically the reaction space is then purged with an inert
carrier gas to remove the unreacted organic reducing agent and the
reaction products and/or by-products.
[0139] The reactions between nickel oxide and the organic reducing
agent may be carried out in a wide temperature range, even as low
as room temperature. Preferably, reduction with an organic reducing
agent is carried out at low temperatures. Kinetic factors and the
diffusion rate of oxygen from nickel oxide to the nickel surface
set a lower limit to the actual process temperatures that can be
applied successfully. The temperature in the reaction space is
preferably in the range of about 200.degree. C. to about
450.degree. C., more preferably about 300.degree. C. to about
430.degree. C. and even more preferably about 310.degree. C. to
about 400.degree. C. In some cases, such as the case of very thin
metal oxide films, the reduction temperature can be even lower than
about 200.degree. C. For example, in case of hydrogen containing
plasma, hydrogen radical or hydrogen atom reduction can be
performed from about 20.degree. C. to about 450.degree. C. If
reduction and subsequent process steps are not carried out in situ,
the reduction temperature may be less than about 400.degree. C.
Reduction and silicidation may also happen simultaneously.
[0140] The pressure in the reaction space is preferably from about
0.01 to about 20 mbar, more preferably from about 1 to about 10
mbar.
[0141] The processing time will vary according to the thickness of
the layer to be reduced. A layer of nickel oxide having a thickness
of up to about 300 to about 400 nm can be reduced in approximately
3 to 5 minutes. For layers having a thickness of approximately 0.1
to 10 nm, the processing time is in the order of seconds. Reduction
may be somewhat faster in case of plasma reduction.
[0142] According to one embodiment, NiO is reduced to nickel with
one or more organic reducing agents. The organic reducing agents
preferably have at least one functional group selected from the
group consisting of alcohol (--OH), aldehyde (--CHO), and
carboxylic acid (--COOH).
[0143] Such reducing agents have the advantage that the reaction
by-products are volatile and can be easily removed from the
reaction space. In the reduction of nickel oxide, the reducing
agent is oxidized. Thus, alcohols are oxidized into aldehydes and
ketones, aldehydes are oxidized into carboxylic acids and
carboxylic acids are oxidized into carbon dioxide. Depending on the
specific reactants, water may be formed as a gaseous
by-product.
[0144] These bulky source chemical molecules also do not easily
diffuse inside the metal oxide film. Thus, the reduction reaction
takes place only at the surface of the metal oxide layer. Gaseous
by-products are not formed inside the film, but only at the
surface. The structural integrity of the metal film is thereby
preserved and the formation of pinholes in the film is avoided.
[0145] Reducing agents containing at least one alcohol group are
preferably selected from the group consisting of primary alcohols,
secondary alcohols, tertiary alcohols, polyhydroxy alcohols, cyclic
alcohols, aromatic alcohols, halogenated alcohols, and other
derivatives of alcohols.
[0146] Preferred primary alcohols have an --OH group attached to a
carbon atom which is bonded to another carbon atom, in particular
primary alcohols according to the general formula (I):
R.sup.1--OH (I)
[0147] wherein R.sup.1 is a linear or branched C.sub.1-C.sub.20
alkyl or alkenyl groups, preferably methyl, ethyl, propyl, butyl,
pentyl or hexyl. Examples of preferred primary alcohols include
methanol, ethanol, propanol, butanol, 2-methyl propanol and
2-methyl butanol.
[0148] Preferred secondary alcohols have an --OH group attached to
a carbon atom that is bonded to two other carbon atoms. In
particular, preferred secondary alcohols have the general formula
(II):
##STR00001##
[0149] wherein each R.sup.1 is selected independently from the
group of linear or branched C.sub.1-C.sub.20 alkyl and alkenyl
groups, preferably methyl, ethyl, propyl, butyl, pentyl or hexyl.
Examples of preferred secondary alcohols include 2-propanol and
2-butanol.
[0150] Preferred tertiary alcohols have an --OH group attached to a
carbon atom that is bonded to three other carbon atoms. In
particular, preferred tertiary alcohols have the general formula
(III):
##STR00002##
[0151] wherein each R.sup.1 is selected independently from the
group of linear or branched C.sub.1-C.sub.20 alkyl and alkenyl
groups, preferably methyl, ethyl, propyl, butyl, pentyl or hexyl.
An example of a preferred tertiary alcohol is tert-butanol.
[0152] Preferred polyhydroxy alcohols, such as diols and triols,
have primary, secondary and/or tertiary alcohol groups as described
above. Examples of preferred polyhydroxy alcohol are ethylene
glycol and glycerol.
[0153] Preferred cyclic alcohols have an --OH group attached to at
least one carbon atom which is part of a ring of 1 to 10, more
preferably 5-6 carbon atoms.
[0154] Preferred aromatic alcohols have at least one --OH group
attached either to a benzene ring or to a carbon atom in a side
chain. Examples of preferred aromatic alcohols include benzyl
alcohol, o-, p- and m-cresol and resorcinol.
[0155] Preferred halogenated alcohols have the general formula
(IV):
CH.sub.nX.sub.3-n--R.sup.2--OH (IV)
[0156] wherein X is selected from the group consisting of F, Cl, Br
and I, n is an integer from 0 to 2 and R.sup.2 is selected from the
group of linear or branched C.sub.1-C.sub.20 alkyl and alkenyl
groups, preferably methyl, ethyl, propyl, butyl, pentyl or hexyl.
More preferably X is selected from the group consisting of F and Cl
and R.sup.2 is selected from the group consisting of methyl and
ethyl. An example of a preferred halogenated alcohol is
2,2,2-trifluoroethanol.
[0157] Other preferred derivatives of alcohols include amines, such
as methyl ethanolamine.
[0158] Preferred reducing agents containing at least one aldehyde
group (--CHO) are selected from the group consisting of compounds
having the general formula (V), alkanedial compounds having the
general formula (VI), halogenated aldehydes and other derivatives
of aldehydes.
[0159] Thus, in one embodiment preferred reducing agents are
aldehydes having the general formula (V):
R.sup.3--CHO (V)
[0160] wherein R.sup.3 is selected from the group consisting of
hydrogen and linear or branched C.sub.1-C.sub.20 alkyl and alkenyl
groups, preferably methyl, ethyl, propyl, butyl, pentyl or hexyl.
More preferably, R.sup.3 is selected from the group consisting of
methyl or ethyl. Examples of preferred compounds according to
formula (V) are formaldehyde, acetaldehyde and butyraldehyde.
[0161] In another embodiment preferred reducing agents are
aldehydes having the general formula (VI):
OHC--R.sup.4--CHO (VI)
[0162] wherein R.sup.4 is a linear or branched C.sub.1-C.sub.20
saturated or unsaturated hydrocarbon. Alternatively, the aldehyde
groups may be directly bonded to each other (R.sup.4 is null).
[0163] Preferred reducing agents containing at least one --COOH
group are preferably selected from the group consisting of
compounds of the general formula (VII), polycarboxylic acids,
halogenated carboxylic acids and other derivatives of carboxylic
acids.
[0164] Thus, in one embodiment preferred reducing agents are
carboxylic acids having the general formula (VII):
R.sup.5--COOH (VII)
[0165] wherein R.sup.5 is hydrogen or linear or branched
C.sub.1-C.sub.20 alkyl or alkenyl group, preferably methyl, ethyl,
propyl, butyl, pentyl or hexyl, more preferably methyl or ethyl.
Examples of preferred compounds according to formula (VII) are
formic acid and acetic acid, most preferably formic acid
(HCOOH).
[0166] As noted, other methods of reduction are contemplated. In
one embodiment, nickel oxide is reduced by treatment with H.sub.2
plasma. Briefly, the substrate comprising the nickel oxide is
placed in a reaction chamber, such as an ALD reaction chamber. A
gas mixture comprising H.sub.2 is allowed to flow into the chamber
and Radio Frequency (RF) power is applied to create a plasma
discharge in the H.sub.2 gas. The plasma discharge reduces the
nickel oxide, leaving elemental nickel. Care must be taken not to
damage the nickel surface or other exposed substrate surfaces.
[0167] In a further embodiment, nickel oxide is reduced by exposure
to H.sub.2 gas or forming gas at elevated temperature. Briefly, the
substrate comprising the nickel oxide is placed in a reaction
chamber. H.sub.2 gas is allowed to flow into the reaction chamber.
The temperature of the reaction chamber is set to between about
200.degree. C. and about 600.degree. C., more preferably at between
about 300.degree. C. and about 500.degree. C. Reduction with
moderate reducing agents at such elevated temperatures has been
found to simultaneously effect silicidation, obviating a subsequent
silicidation anneal.
[0168] Where the metal oxide to is independently reduced to metal
without silicidation, or with incomplete silicidation, the
substrate is then annealed at a silicidation temperature, i.e., the
temperature at which conversion of the metal layer to a silicide
occurs. For example, the silicidation temperature is the
temperature at which conversion of the Ni layer into nickel
containing silicide takes place. In some embodiments, the
temperature of conversion is between about 200.degree. C. and about
300.degree. C. Preferably, the anneal is a rapid thermal anneal, in
which heating is conducted for less than about 2 minutes, more
preferably less than about 1 minute. The silicide film formed by
annealing advantageously has better adhesion to the underlying
silicon substrate and has a more diffuse boundary than a similar
film formed by, e.g., deposition processes. It will be appreciated
that in certain embodiments, the silicide films preferably contact
underlying source and drains regions.
[0169] It will also be appreciated that the annealing step can be
performed in the same reaction space as the previous metal oxide
layer deposition and/or reduction. The annealing step may also be
performed in an anneal station different from the reaction space
for the deposition and/or reduction. Such an anneal station can be,
e.g., the reactor of a Levitor.RTM. system, commercially available
from ASM International, N.V. of Bilthoven, The Netherlands. A
reactor according to the Levitor.RTM. design is described in U.S.
Pat. No. 6,183,565, the entire disclosure of which is incorporated
herein by reference.
Post-Silicidation Anneal
[0170] In certain embodiments, an additional conversion step may be
performed to convert metal silicide from one phase to the desired
phase. In some embodiments, the conversion step may be carried out
in the same reaction space as the metal oxide deposition step
and/or the annealing step. In other embodiments, the conversion
step may be performed in a separate reaction space. The conversion
step may preferably be carried out at a temperature between about
200.degree. C. and about 700.degree. C., including about
200.degree. C. to about 500.degree. C., a pressure between about
0.01 mbar and about 10 mbar, and from about 5 s to about 1000
s.
[0171] In some embodiments, the additional conversion step can be
performed in an inert atmosphere. For example, the conversion step
can be performed in an atmosphere comprising hydrogen gas (H.sub.2)
and nitrogen gas (N.sub.2). In some embodiments, the conversion
step can be performed in an atmosphere comprising argon (Ar).
* * * * *