U.S. patent application number 15/144521 was filed with the patent office on 2017-03-30 for low-latency high-gain current-mode logic slicer.
The applicant listed for this patent is SAMSUNG DISPLAY CO., LTD.. Invention is credited to Amir Amirkhany, Sanquan Song.
Application Number | 20170093416 15/144521 |
Document ID | / |
Family ID | 58227802 |
Filed Date | 2017-03-30 |
United States Patent
Application |
20170093416 |
Kind Code |
A1 |
Song; Sanquan ; et
al. |
March 30, 2017 |
LOW-LATENCY HIGH-GAIN CURRENT-MODE LOGIC SLICER
Abstract
A low-latency, high-gain (LLHG) slicer includes an input stage
coupled to a differential output port and configured to receive a
differential analog input signal, and to track the differential
analog input signal during a tracking phase, an output stage
coupled to the differential output port and configured to generate
digital output bits corresponding to the differential analog input
signal during a regeneration phase, and a tunable resistor coupled
to the differential output port and configured to provide a first
load impedance during the tracking phase and to provide a second
load impedance during the regeneration phase, the first load
impedance being lower than the second load impedance.
Inventors: |
Song; Sanquan; (Mountain
View, CA) ; Amirkhany; Amir; (Sunnyvale, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG DISPLAY CO., LTD. |
Yongin-City |
|
KR |
|
|
Family ID: |
58227802 |
Appl. No.: |
15/144521 |
Filed: |
May 2, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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62234882 |
Sep 30, 2015 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03K 19/0944 20130101;
H03M 1/12 20130101 |
International
Class: |
H03M 1/12 20060101
H03M001/12; H03K 19/0944 20060101 H03K019/0944 |
Claims
1. A low-latency, high-gain (LLHG) slicer comprising: an input
stage coupled to a differential output port and configured to
receive a differential analog input signal, and to track the
differential analog input signal during a tracking phase; an output
stage coupled to the differential output port and configured to
generate digital output bits corresponding to the differential
analog input signal during a regeneration phase; and a tunable
resistor coupled to the differential output port and configured to
provide a first load impedance during the tracking phase and to
provide a second load impedance during the regeneration phase, the
first load impedance being lower than the second load
impedance.
2. The LLHG slicer of claim 1, wherein the tracking phase
corresponds to a first half of a clock cycle, and the regeneration
phase corresponds to a second half of the clock cycle.
3. The LLHG slicer of claim 1, further comprising a mode selector
coupled to the input and output stages and configured to activate
the input stage and deactivate the output stage during the tracking
phase, and to deactivate the input stage and activate the output
stage during the regeneration phase.
4. The LLHG slicer of claim 3, wherein the mode selector is further
configured to receive a differential clock signal, a first half of
a clock cycle of the differential clock signal corresponding to the
tracking phase, and a second half of the clock cycle of the
differential clock signal corresponding to the regeneration
phase.
5. The LLHG slicer of claim 4, wherein the tunable resistor
comprises a clocked CMOS resistor configured to receive the
differential clock signal, and to provide a third impedance during
the tracking phase and to provide a fourth impedance during the
regeneration phase, the third impedance being lower than the fourth
impedance.
6. The LLHG slicer of claim 5, wherein the tunable resistor further
comprises an active inductor connected in parallel with clocked
CMOS resistor and configured to provide a clock-independent
impedance.
7. The LLHG slicer of claim 6, wherein the first load impedance is
a cumulative resistance of the third impedance and the
clock-independent impedance, and the second load impedance is a
cumulative resistance of the fourth impedance and the
clock-independent impedance.
8. A low-latency, high-gain (LLHG) slicer comprising: a
current-mode logic (CML) differential transistor pair coupled to a
differential output port and configured to receive a differential
analog input signal, and to track the differential analog input
signal when activated; a cross-coupled transistor pair coupled to
the differential output port and configured to generate digital
output bits corresponding to the differential analog input signal
when activated; a clock-enable transistor pair configured to
receive a differential clock signal, to activate the CML
differential transistor pair and deactivate the cross-coupled
transistor pair during a first half of a clock cycle of the
differential clock signal, and to deactivate the CML differential
transistor pair and activate the cross-coupled transistor pair
during a second half of the clock cycle of the differential clock
signal; and a tunable resistor coupled to the differential output
port and configured to receive the differential clock signal, to
provide a first load impedance during the first half of the clock
cycle, and to provide a second load impedance during the second
half of the clock cycle, the first load impedance being lower than
the second load impedance.
9. The LLHG slicer of claim 8, wherein the differential clock
signal comprises a first clock signal and a second clock signal,
the first and second clock signals being out of phase by 180
degrees, and wherein the first half of the clock cycle corresponds
to a period in time in which one of the first and second clock
signals is at a logic high level, and the second half of the clock
cycle corresponds to a subsequent period in time in which the one
of the first and second clock signals is at a logic low level.
10. The LLHG slicer of claim 9, wherein the tunable resistor
comprises a clocked CMOS resistor, the clocked CMOS resistor
comprising first and second output transistors coupled between a
first voltage source and the differential output port, gate
electrodes of the first and second output transistors receiving one
of the first and second clock signals, and wherein the first and
second transistors are configured to provide a third impedance
during the first half of the clock cycle and to provide a fourth
impedance during the second half of the clock cycle, the third
impedance being lower than the fourth impedance.
11. The LLHG slicer of claim 10, wherein the first and second
output transistors comprise PMOS transistors, and the one of the
first and second clock signals is the first clock signal.
12. The LLHG slicer of claim 10, wherein the first and second
output transistors comprise NMOS transistors, and the one of the
first and second clock signals is the second clock signal.
13. The LLHG slicer of claim 10, wherein the clocked CMOS resistor
further comprises first and second output resistors connected in
parallel with respective ones of the first and second output
transistors, the first and second output resistors having a set
resistance.
14. The LLHG slicer of claim 8, wherein the tunable resistor
comprises a first active inductor, the first active inductor
comprising: an active transistor coupled between a first voltage
source and the differential output port; a diode-connected
transistor coupled between a first electrode and a gate electrode
of the active transistor; and a current source coupled to the
active and diode-connected transistors, wherein the diode-connected
transistor and the current source are configured to maintain the
active transistor in an active state such that the first active
inductor provides a clock-independent impedance throughout the
first and second half of the clock cycle.
15. The LLHG slicer of claim 14, wherein the active state
corresponds to a mode of operation at an edge of a linear region
and a saturation region of the active transistor.
16. The LLHG slicer of claim 14, wherein the active and
diode-connected transistors comprise PMOS transistors, and wherein
the CML differential transistor pair and the cross-coupled
transistor pair comprise NMOS transistors.
17. The LLHG slicer of claim 14, wherein the active and
diode-connected transistors comprise NMOS transistors, and wherein
the CML differential transistor pair and the cross-coupled
transistor pair comprise PMOS transistors.
18. The LLHG slicer of claim 14, wherein the first active inductor
further comprises an output resistor connected in series with the
active transistor, the output resistor having a set resistance.
19. The LLHG slicer of claim 14, wherein the tunable resistor
further comprises a second active inductor, the second active
inductor being a same as the first active inductor.
20. A low-latency, high-gain slicer comprising: a current-mode
logic (CML) differential transistor pair coupled to a differential
output port and configured to receive a differential analog input
signal, and to track the differential analog input signal when
activated; a cross-coupled transistor pair coupled to the
differential output port and configured to generate digital output
bits corresponding to the differential analog input signal when
activated; a clock-enable transistor pair configured to receive a
differential clock signal, to activate the CML differential
transistor pair and deactivate the cross-coupled transistor pair
during a first half of a clock cycle of the differential clock
signal, and to deactivate the CML differential transistor pair and
activate the cross-coupled transistor pair during a second half of
the clock cycle of the differential clock signal; and a tunable
resistor coupled to the differential output port and comprising a
clocked CMOS resistor and first and second active inductors, the
tunable resistor being configured to receive the differential clock
signal, to provide a first load impedance during the first half of
the clock cycle, and to provide a second load impedance during the
second half of the clock cycle, the first load impedance being
lower than the second load impedance, wherein the clocked CMOS
resistor comprises first and second output transistors coupled
between a first voltage source and the differential output port,
gate electrodes of the first and second output transistors
receiving the differential clock signal, wherein the first and
second transistors are configured to provide a third impedance
during the first half of the clock cycle and to provide a fourth
impedance during the second half of the clock cycle, wherein each
of the first active inductors comprising: an active transistor
coupled between a first voltage source and the differential output
port; a diode-connected transistor; and a current source, wherein
the diode-connected transistor and the current source are
configured to maintain the active transistor in an active state
such that the first active inductor provides a clock-independent
impedance throughout the first and second half of the clock cycle,
and wherein the first load impedance is a cumulative resistance of
the third impedance and the clock-independent impedance, and the
second load impedance is a cumulative resistance of the fourth
impedance and the clock-independent impedance.
Description
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application claims priority to, and the benefit of,
U.S. Provisional Application No. 62/234,882, entitled "A
Low-latency High-gain CML Slicer," filed on Sep. 30, 2015, the
entire content of which is incorporated herein by reference.
FIELD
[0002] Aspects of the present invention relate to a current-mode
logic slicer.
BACKGROUND
[0003] Current-mode logic (CML) slicers, which quantify analog
input signals into digital output bits, have been widely adopted in
receivers (e.g., serial/deserializer (SerDes) receivers). The CML
slicer has two phases of operation: a tracking phase during which
the CML slicer tracks the input signal (e.g., analog signal
waveform) for a first half of a clock cycle, and a regeneration
phase during which the CML slicer regenerates the analog input as a
digital output during a second half of the clock cycle.
[0004] The operational demands placed on conventional CML slicers
often result in conflicting requirements. For example, low tracking
latency (i.e., high tracking bandwidth) is desired because it
reduces the circuit-induced inter-symbol-interface (ISI), which is
additive to channel induced ISI, and because lower tracking latency
serves to close the timing paths where decision feedback
equalization (DFE) is applied. To achieve low tracking latency, the
load resistor needs to be sufficiently small. On the other hand,
high regeneration gain is also desired so that the output of the
CML slicer may be a wide-swing digital signal, which is more immune
to noise and other non-ideality than an analog signal. To achieve
high regeneration gain, the load resistor needs to be sufficiently
large. Therefore, a trade-off exists between the tracking latency
and the regeneration gain in conventional slicer designs.
[0005] Conventional solutions attempt to reach a compromise between
the two requirements by selecting an output resistance that is
small enough to satisfy a minimum tracking latency requirement, and
is large enough to satisfy a minimum regeneration gain requirement.
This, however, leads to sub-optimal design.
[0006] The above information disclosed in this Background section
is only for enhancement of understanding of the invention, and
therefore it may contain information that does not form the prior
art that is already known to a person of ordinary skill in the
art.
SUMMARY
[0007] Aspects of embodiments of the present invention are directed
toward a low-latency, high-gain common-mode logic slicer
(hereinafter, an LLHG slicer) utilizing a dynamically tuned load
impedance to decouple the tracking latency and the regeneration
gain of the LLHG slicer. According to some embodiments, in the
tracking phase, a clocked complementary metal-oxide semiconductor
(CMOS) device reduces the load impedance of the LLHG slicer, while
in the regeneration phase, an active inductor device sets (e.g.,
increases) the load impedance. In some embodiments, the LLHG slicer
utilizes low power diode-connected devices to bias the active
inductor devices, which automatically compensates for process
variation (e.g., transistor threshold variation) and results in
power savings.
[0008] According to some exemplary embodiments of the invention,
there is provided a low-latency, high-gain (LLHG) slicer including:
an input stage coupled to a differential output port and configured
to receive a differential analog input signal, and to track the
differential analog input signal during a tracking phase; an output
stage coupled to the differential output port and configured to
generate digital output bits corresponding to the differential
analog input signal during a regeneration phase; and a tunable
resistor coupled to the differential output port and configured to
provide a first load impedance during the tracking phase and to
provide a second load impedance during the regeneration phase, the
first load impedance being lower than the second load
impedance.
[0009] In an embodiment, the tracking phase corresponds to a first
half of a clock cycle, and the regeneration phase corresponds to a
second half of the clock cycle.
[0010] In an embodiment, the LLHG slicer further includes a mode
selector coupled to the input and output stages and configured to
activate the input stage and deactivate the output stage during the
tracking phase, and to deactivate the input stage and activate the
output stage during the regeneration phase.
[0011] In an embodiment, the mode selector is further configured to
receive a differential clock signal, a first half of a clock cycle
of the differential clock signal corresponding to the tracking
phase, and a second half of the clock cycle of the differential
clock signal corresponding to the regeneration phase.
[0012] In an embodiment, the tunable resistor includes a clocked
CMOS resistor configured to receive the differential clock signal,
and to provide a third impedance during the tracking phase and to
provide a fourth impedance during the regeneration phase, the third
impedance being lower than the fourth impedance.
[0013] In an embodiment, the tunable resistor further includes an
active inductor connected in parallel with clocked CMOS resistor
and configured to provide a clock-independent impedance.
[0014] In an embodiment, the first load impedance is a cumulative
resistance of the third impedance and the clock-independent
impedance, and the second load impedance is a cumulative resistance
of the fourth impedance and the clock-independent impedance.
[0015] According to some exemplary embodiments of the invention,
there is provided a low-latency, high-gain (LLHG) slicer including:
a current-mode logic (CML) differential transistor pair coupled to
a differential output port and configured to receive a differential
analog input signal, and to track the differential analog input
signal when activated; a cross-coupled transistor pair coupled to
the differential output port and configured to generate digital
output bits corresponding to the differential analog input signal
when activated; a clock-enable transistor pair configured to
receive a differential clock signal, to activate the CML
differential transistor pair and deactivate the cross-coupled
transistor pair during a first half of a clock cycle of the
differential clock signal, and to deactivate the CML differential
transistor pair and activate the cross-coupled transistor pair
during a second half of the clock cycle of the differential clock
signal; and a tunable resistor coupled to the differential output
port and configured to receive the differential clock signal, to
provide a first load impedance during the first half of the clock
cycle, and to provide a second load impedance during the second
half of the clock cycle, the first load impedance being lower than
the second load impedance.
[0016] In an embodiment, the differential clock signal includes a
first clock signal and a second clock signal, the first and second
clock signals being out of phase by 180 degrees, and the first half
of the clock cycle corresponds to a period in time in which one of
the first and second clock signals is at a logic high level, and
the second half of the clock cycle corresponds to a subsequent
period in time in which the one of the first and second clock
signals is at a logic low level.
[0017] In an embodiment, the tunable resistor includes a clocked
CMOS resistor, the clocked CMOS resistor including first and second
output transistors coupled between a first voltage source and the
differential output port, gate electrodes of the first and second
output transistors receiving one of the first and second clock
signals, and the first and second transistors are configured to
provide a third impedance during the first half of the clock cycle
and to provide a fourth impedance during the second half of the
clock cycle, the third impedance being lower than the fourth
impedance.
[0018] In an embodiment, the first and second output transistors
include PMOS transistors, and the one of the first and second clock
signals is the first clock signal.
[0019] In an embodiment, the first and second output transistors
include NMOS transistors, and the one of the first and second clock
signals is the second clock signal.
[0020] In an embodiment, the clocked CMOS resistor further includes
first and second output resistors connected in parallel with
respective ones of the first and second output transistors, the
first and second output resistors having a set resistance.
[0021] In an embodiment, the tunable resistor includes a first
active inductor, the first active inductor including: an active
transistor coupled between a first voltage source and the
differential output port; a diode-connected transistor coupled
between a first electrode and a gate electrode of the active
transistor; and a current source coupled to the active and
diode-connected transistors, wherein the diode-connected transistor
and the current source are configured to maintain the active
transistor in an active state such that the first active inductor
provides a clock-independent impedance throughout the first and
second half of the clock cycle.
[0022] In an embodiment, the active state corresponds to a mode of
operation at an edge of a linear region and a saturation region of
the active transistor.
[0023] In an embodiment, the active and diode-connected transistors
include PMOS transistors, and the CML differential transistor pair
and the cross-coupled transistor pair include NMOS transistors.
[0024] In an embodiment, the active and diode-connected transistors
include NMOS transistors, and the CML differential transistor pair
and the cross-coupled transistor pair include PMOS transistors.
[0025] In an embodiment, the first active inductor further includes
an output resistor connected in series with the active transistor,
the output resistor having a set resistance.
[0026] In an embodiment, the tunable resistor further includes a
second active inductor, the second active inductor being a same as
the first active inductor.
[0027] According to some exemplary embodiments of the invention,
there is provided a low-latency, high-gain slicer including: a
current-mode logic (CML) differential transistor pair coupled to a
differential output port and configured to receive a differential
analog input signal, and to track the differential analog input
signal when activated; a cross-coupled transistor pair coupled to
the differential output port and configured to generate digital
output bits corresponding to the differential analog input signal
when activated; a clock-enable transistor pair configured to
receive a differential clock signal, to activate the CML
differential transistor pair and deactivate the cross-coupled
transistor pair during a first half of a clock cycle of the
differential clock signal, and to deactivate the CML differential
transistor pair and activate the cross-coupled transistor pair
during a second half of the clock cycle of the differential clock
signal; and a tunable resistor coupled to the differential output
port and including a clocked CMOS resistor and first and second
active inductors, the tunable resistor being configured to receive
the differential clock signal, to provide a first load impedance
during the first half of the clock cycle, and to provide a second
load impedance during the second half of the clock cycle, the first
load impedance being lower than the second load impedance, wherein
the clocked CMOS resistor includes first and second output
transistors coupled between a first voltage source and the
differential output port, gate electrodes of the first and second
output transistors receiving the differential clock signal, wherein
the first and second transistors are configured to provide a third
impedance during the first half of the clock cycle and to provide a
fourth impedance during the second half of the clock cycle, wherein
each of the first active inductors including: an active transistor
coupled between a first voltage source and the differential output
port; a diode-connected transistor; and a current source, wherein
the diode-connected transistor and the current source are
configured to maintain the active transistor in an active state
such that the first active inductor provides a clock-independent
impedance throughout the first and second half of the clock cycle,
and wherein the first load impedance is a cumulative resistance of
the third impedance and the clock-independent impedance, and the
second load impedance is a cumulative resistance of the fourth
impedance and the clock-independent impedance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The above and other features and aspects of the invention
will be made more apparent by the following detailed description of
exemplary embodiments thereof with reference to the attached
drawings, in which:
[0029] FIG. 1A is a schematic diagram of the low-latency, high-gain
(LLHG) slicer according to some exemplary embodiments of the
present invention;
[0030] FIG. 1B illustrates a relation between the tracking and
regeneration phases of the LLHG slicer and the waveforms of the
differential clock signals input to the LLHG slicer, according to
some exemplary embodiments of the present invention.
[0031] FIG. 2A illustrates the operation of the LLHG slicer in a
tracking mode, according to some exemplary embodiments of the
present invention;
[0032] FIG. 2B illustrates the operation of the LLHG slicer in a
regenerative mode, according to some exemplary embodiments of the
present invention;
[0033] FIG. 3A illustrates the tunable resistor utilizing
parallel-connected fixed resistors, according to some exemplary
embodiments of the present invention; and
[0034] FIG. 3B illustrates the tunable resistor utilizing
series-connected fixed resistors, according to some other exemplary
embodiments of the present invention.
DETAILED DESCRIPTION
[0035] The attached drawings for illustrating exemplary embodiments
of the invention are referred to in order to provide a sufficient
understanding of the invention, the merits thereof, and the
objectives accomplished by the implementation of the invention. The
invention may, however, be embodied in many different forms and
should not be construed as being limited to the exemplary
embodiments set forth herein; rather, these exemplary embodiments
are provided so that this disclosure will be thorough and complete,
and will fully convey the concept of the invention to those skilled
in the art.
[0036] Hereinafter, the invention will be described in detail by
explaining exemplary embodiments of the invention with reference to
the attached drawings. In the drawings, like reference numerals are
used throughout the figures to reference like features and
components.
[0037] Aspects of embodiments of the present invention are directed
to a low-latency, high-gain slicer that decouples its tracking
latency from its regeneration gain by dynamically tuning the load
impedance (e.g., the load resistance). According to some
embodiments, the load impedance is tuned to a relatively low output
impedance during the tracking phase and tuned to a relatively high
output impedance during the regeneration phase. Clocked CMOS
devices are utilized as dominant load resistors during the tracking
phase, accelerating the tracking and minimizing the latency. Active
inductor devices (including active devices, such as transistors),
which exhibit relatively low impedance at low frequencies and
relatively high impedance at high frequencies, are adopted as the
dominant load impedance during the regeneration phase, sharpening
the edge and boosting the regeneration gain. Furthermore, diode
connected CMOS devices are adopted to bias the active inductor
devices, which require small (e.g., minimum) DC current and
compensate for the device's variations automatically.
[0038] FIG. 1A is a schematic diagram of the low-latency, high-gain
(LLHG) slicer 100 according to some exemplary embodiments of the
present invention. FIG. 1B illustrates the relation between the
tracking and regeneration phases of the LLHG slicer 100 and the
waveforms of the differential clock signals (or the clock signals)
CK.sub.P and CK.sub.N input to the LLHG slicer 100, according to
some exemplary embodiments of the present invention.
[0039] Referring to FIGS. 1A-1B, the LLHG slicer 100 receives
differential input signals IN.sub.N and IN.sub.P (also collectively
referred to as a differential analog input signal), which represent
an analog input waveform, and differential clock signals CK.sub.P
and CK.sub.N, which are used to control the operation modes of the
LLHG slicer 100, and outputs differential output signals O.sub.N
and O.sub.P, which are in the form of digital bits (e.g., a bit
stream) and correspond to the differential analog input signals
IN.sub.N and IN.sub.P. In some examples, the differential clock
signals CK.sub.P and CK.sub.N may be logical inverses of one
another (e.g., be out of phase by 180 degrees). For example, when
the first clock signal CK.sub.P is at a logic high level, the
second clock signal CK.sub.N is at a logic low level. The voltage
levels of the logic high and logic low levels may be determined by
the process technology used to fabricate the transistors of the
LLHG slicer 100.
[0040] The differential input signals IN.sub.N and IN.sub.P are
applied to the respective gate electrodes of the first and second
input transistors M.sub.IN and M.sub.IP, which constitute a
current-mode logic (CML) differential transistor pair (also
referred to as an input stage). In some embodiments, the first and
second input transistors M.sub.IN and M.sub.IP are negative-channel
metal-oxide (NMOS) transistors that are coupled together, and
coupled to the first clock-enable transistor M.sub.CKP, at their
respective source electrodes.
[0041] The first and second input transistors M.sub.IN and M.sub.IP
(e.g., their respective drain electrodes) may be coupled to a
tunable resistor 102, which includes a clocked complementary
metal-oxide semiconductor (CMOS) resistor 104, at output nodes
N.sub.1 and N.sub.2 (that may be collectively referred to as
differential output port). When activated, the first and second
input transistors M.sub.IN and M.sub.IP (together with the tunable
resistor 102) track the differential analog input signals IN.sub.N
and IN.sub.P. The clocked CMOS resistor 104 includes first and
second output transistors M.sub.ON and M.sub.OP. In some
embodiments, the first and second output transistors M.sub.ON and
M.sub.OP are positive-channel metal-oxide (PMOS) transistors that
are coupled to a first voltage source V.sub.D at their respective
drain electrodes, and are driven at their respective gate
electrodes by the second clock signal CK.sub.N. When
activated/fully ON (e.g., when the second clock signal CK.sub.N is
at a logic low level), each of the first and second output
transistors M.sub.ON and M.sub.OP may operate in a linear region
and may exhibit (e.g., provide) low resistance. On the other hand,
when deactivated/fully OFF (e.g., when the second clock signal
CK.sub.N is at a logic high level), each of the first and second
output transistors M.sub.ON and M.sub.OP may operate in a
sub-threshold region (e.g., a deep sub-threshold region) and may
exhibit (e.g., provide) relatively high resistance. The first
voltage source V.sub.D may supply a voltage that is at or greater
than the voltage corresponding to the logic high level. The value
and range of the first voltage source V.sub.D may depend on the
process technology used. For example, the first voltage source
V.sub.D may be about 1.8 V for a 180 nm process, and may be about
1.2 V for a 65 nm process.
[0042] The first and second cross-coupled transistors M.sub.XN and
M.sub.XP, which constitute a cross-coupled transistor pair (also
referred to as an output stage), provide positive feedback and
(together with the tunable resistor 102) generate digital output
bits corresponding to the differential analog input signals
IN.sub.N and IN.sub.P when activated. The first and second
cross-coupled transistors M.sub.XN and M.sub.XP may be coupled to
the tunable resistor 102 (e.g., the clocked CMOS resistor 104) at
the output nodes N.sub.1 and N.sub.2. In some embodiments, the
first and second cross-coupled transistors M.sub.XN and M.sub.XP
are NMOS transistors that are coupled together, and coupled to the
second clock-enable transistor M.sub.CKN, at their respective
source electrodes.
[0043] Referring to FIGS. 1A-1B, the differential clock signals
CK.sub.P and CK.sub.N are applied to respective gate electrodes of
the first and second clock-enable transistors M.sub.CKP and
M.sub.CKN (collectively referred to as a clock-enable transistor
pair or a mode selector), which activate/turn ON (by biasing)
either the first and second input transistors M.sub.IN and M.sub.IP
and the clocked CMOS resistor 104 (e.g., the first and second
output transistors M.sub.ON and M.sub.OP) or the first and second
cross-coupled transistors M.sub.XN and M.sub.XP based on the logic
levels of the differential clock signals CK.sub.P and CK.sub.N. For
example, in the first half clock cycle (i.e., the tracking phase
TM) when the first clock signal CK.sub.P is at a logic high level
and the second clock signal CK.sub.N is at a logic low level, the
first and second input transistors M.sub.IN and M.sub.IP and the
first and second output transistors M.sub.ON and M.sub.OP are
activated/turned ON, while the first and second cross-coupled
transistors M.sub.XN and M.sub.XP are deactivated/turned OFF.
Further, in the second half clock cycle (i.e., the regeneration
phase RM) when the first clock signal CK.sub.P is at a logic low
level and the second clock signal CK.sub.N is at a logic high
level, the first and second input transistors M.sub.IN and M.sub.IP
and the first and second output transistors M.sub.ON and M.sub.OP
are deactivated/turned OFF, while the first and second
cross-coupled transistors M.sub.XN and M.sub.XP are
activated/turned ON.
[0044] As a result, in the tracking phase TM, the output impedance
(e.g., the output resistance) exhibited (e.g., provided) by the
tunable resistor 102 is relatively low, and thus, the slicer
tracking latency, which is determined by the output resistance and
the output capacitors, is low relative to a conventional slicer
using a constant load resistance. Additionally, in the regeneration
phase RM, the output impedance (e.g., the output resistance)
exhibited (e.g., provided) by the tunable resistor 102 is
relatively high, and thus, the regeneration gain (and the output
swing), which is substantially proportional to the output
impedance, is high relative to the conventional slicer.
[0045] According to some embodiments of the present invention, the
tunable resistor 102 further includes first and second active
inductors 106 and 108 coupled to output nodes N.sub.1 and N.sub.2
and connected in parallel with clocked CMOS resistor 104, which
allow the LLHG slicer 100 to achieve a faster swing slope during
the regeneration phase RM due to their active inductance
nature.
[0046] In some embodiments, the first active inductor 106 includes
a first active transistor M.sub.A1 coupled between the first
voltage source V.sub.D and the first output node N.sub.1, which
provides a high impedance (e.g., high resistance or low
transconductance) when activated (e.g., in an ON state). The
impedance of the first active transistor M.sub.A1 may be higher
than (e.g., substantially higher than) the on-resistance of the
output transistors M.sub.ON and M.sub.OP, and may be lower than
(e.g., substantially lower than) the resistance of the output
transistors M.sub.ON and M.sub.OP in the deactivated/OFF state. The
first active transistor M.sub.A1 may be biased via a first current
source I.sub.D1 and a first diode-connected transistor M.sub.D1
coupled between the source and gate electrodes of the first active
transistor M.sub.A1. As a result, the impedance (e.g., the
transconductance g.sub.m) of the first active transistor M.sub.A1,
which is determined by the difference between the gate-to-source
voltage V.sub.GS and the threshold voltage V.sub.TH of the first
active transistor M.sub.A1, remains substantially constant during
both the tracking and regeneration phases, and is not controlled by
(e.g., affected by) the first and second clock signals CK.sub.P and
CK.sub.N. In some embodiments, the first and second active
transistors M.sub.A1 and M.sub.A2 may be biased at the edge of the
linear and saturation regions (e.g., such that V.sub.GS is
substantially equal to V.sub.TH). In some embodiments, the second
active inductor 106 includes a second active transistor M.sub.A2, a
second diode-connected transistor M.sub.D2, and a second current
source I.sub.D2, and is the same or substantially the same, in
structure and operation, as the first active inductor 106.
[0047] In addition to maintaining the first and second active
transistors M.sub.A1 and M.sub.A2 in an activated/ON state (e.g.,
near the edge of the linear region and the saturation region), the
first and second diode-connected transistors M.sub.D1 and M.sub.D2
also automatically track, and compensate for, process variations
(e.g., device threshold variations) in the first and second active
transistors M.sub.A1 and M.sub.A2. In addition, the first and
second diode-connected transistors M.sub.D1 and M.sub.D2 use a
small amount of (e.g., minimal) biasing current from the first and
second current sources I.sub.D1 and I.sub.D2, which reduces the
overall power usage of the tunable resistor 102 (and hence, the
LLHG slicer 100). The use of the diode-connected biasing scheme
also reduces (e.g., substantially eliminates) the effects of bias
current variation of the first and second current sources I.sub.D1
and I.sub.D2 on the impedance of the active inductors 106 and
108.
[0048] The first and second diode-connected transistors M.sub.D1
and M.sub.D2 and the first and second active transistors M.sub.A1
and M.sub.A2 may be PMOS transistors.
[0049] In some examples, the first and second active inductors 106
and 108 may be replaced with fixed (or set and clock-independent)
resistors having the same or substantially the same resistance as
the impedance (e.g., 1/g.sub.m) of the first and second active
transistors M.sub.A1 and M.sub.A2. However, as the impedance of the
resistors would be substantially constant across operating
frequencies, the swing slope during the regeneration phase RM may
be adversely affected, as compared to embodiments that include the
active inductors 106 and 108. Further, doing so may increase the
power usage and die area of the tunable resistor 102 and make it
more susceptible to process variations, as compared to embodiments
in which the tunable resistor 102 includes the active inductors 106
and 108.
[0050] In some embodiments, the LLHG slicer 100 utilizes a biasing
current source I.sub.tail coupled to the clock-enable transistors
M.sub.CKN and M.sub.CKP (e.g., their respective source electrodes)
for biasing the circuit. The biasing current source I.sub.tail may
include a CMOS circuit and/or include any other suitable circuit
known to a person of ordinary skill in the art.
[0051] In some examples, the two constituent transistors of the
following pairs of transistors are identical or substantially
identical: the first and second input transistors M.sub.IN and
M.sub.IP, the first and second output transistors M.sub.ON and
M.sub.OP, the first and second cross-coupled transistors M.sub.XN
and M.sub.XP, the first and second clock-enable transistors
M.sub.CKN and M.sub.CKP, the first and second diode-connected
transistors M.sub.D1 and M.sub.D2, and the first and second active
transistors M.sub.A1 and M.sub.A2; however, embodiments of the
present invention are not limited thereto.
[0052] As will be understood by a person of ordinary skill in the
art, the exemplary embodiments illustrated by FIG. 1A may be
modified by substituting NMOS transistors for the PMOS transistors,
and vice versa. In such a case, the polarity of the
voltages/signals applied to the gate electrodes of the
aforementioned transistors may be reversed.
[0053] FIG. 2A illustrates the operation of the LLHG slicer 100-TM
in a tracking mode, according to some exemplary embodiments of the
present invention. FIG. 2B illustrates the operation of the LLHG
slicer 100-RM in a regenerative mode, according to some exemplary
embodiments of the present invention.
[0054] Referring to FIG. 2A, during the tracking phase TM (i.e.,
the first half clock cycle) when the first clock signal CK.sub.P is
at a logic high level and the second clock signal CK.sub.N is at a
logic low level, the input transistors M.sub.IN and M.sub.XP and
the output transistors M.sub.ON and M.sub.OP are activated/turned
ON, and the cross-coupled transistors M.sub.XN and M.sub.XP are
deactivated/turned OFF. During this phase, the output transistors
M.sub.ON and M.sub.OP operate in the linear region and exhibit
(e.g., provide) a deterministic impedance (e.g., resistance) of
about 1/g.sub.ds (where g.sub.ds is the transconductance of the
output transistors M.sub.ON and M.sub.OP), which is lower than
(e.g., substantially lower than) the impedance of the parallel
active transistors M.sub.A1 and M.sub.A2. Thus, the effective load
resistance (hereinafter also referred to as the first impedance) of
the LLHG slicer 100 is low (e.g., about 1/g.sub.ds). The value of
1/g.sub.ds may depend on the desired latency of the LLHG slicer
100, and in some examples may be from about 100 ohms to several
hundred ohms at low operating frequencies, and several kilo-ohms at
high frequencies.
[0055] As the tracking latency of the LLHG slicer 100 is determined
by the effective load resistance and capacitance (i.e., the
effective load impedance), the low load resistance (of, e.g., about
1/g.sub.ds) translates to the LLHG slicer having low tracking
latency and high output bandwidth, both of which are desirable
characteristics during the tracking phase TM. In some examples,
1/g.sub.ds may be about a quarter of the load resistance of
comparable designs, as such, latency may be reduced by a factor of
four relative to such comparable designs.
[0056] Referring to FIG. 2B, during the regeneration phase RM
(i.e., the second half clock cycle) when the first clock signal
CK.sub.P is at a logic low level and the second clock signal
CK.sub.N is at a logic high level, the input transistors M.sub.IN
and M.sub.IP and the output transistors M.sub.ON and M.sub.OP are
deactivated/turned OFF, and the cross-coupled transistors M.sub.XN
and M.sub.XP are activated/turned ON. During this phase, the output
transistors M.sub.ON and M.sub.OP operate in the sub-threshold
region (e.g., the deep sub-threshold region) and exhibit (e.g.,
provide) high impedance, which is greater than (e.g., substantially
greater than) the impedance of the parallel active transistors
M.sub.A1 and M.sub.A2. Thus, the resistance of the output
transistors M.sub.ON and M.sub.OP is no longer dominant, and the
effective load impedance of the LLHG slicer 100 (hereinafter also
referred to as the second impedance) is substantially determined by
the impedance (e.g., the transconductance g.sub.m) of the active
transistors M.sub.A1 and M.sub.A2.
[0057] As the effective DC gain (e.g., the effective DC
regeneration gain) of the LLHG slicer 100 in the regeneration mode
is substantially determined by the transconductance of the active
transistors M.sub.A1 and M.sub.A2, which is set to be low, the LLHG
slicer 100 may exhibit high effective DC gain, which is a desirable
characteristic during the regeneration phase TM.
[0058] Further, the inductance exhibited (e.g., provided) by the
active inductors 106 and 108 allows the LLHG slicer 100 to
partially or substantially cancel, or compensate for, the effect of
the equivalent capacitance on the output nodes N.sub.1 and N.sub.2,
and thus sharpens the slope of (i.e., allows faster swings of) the
differential output signals O.sub.N and O.sub.P relative to a
conventional slicer utilizing fixed load resistors. In some
examples, the impedance at high operating frequencies may be about
four times that at low operating frequencies, which may result in a
peaking of about 12 dB and sharpen the swing slope accordingly.
[0059] Accordingly, the dynamic load impedance of the tunable
resistor 102 effectively decouples the delay of the tracking phase
from the gain of the regeneration phase.
[0060] As described above, the tunable resistor 102 represents a
bimodal load impedance that has a dynamically changing (e.g., a
clocked) portion (e.g., the clocked CMOS resistor 104) and a fixed
(e.g., a clock-independent) portion (e.g., the active inductors 106
and 108). As shown in FIGS. 1A-1B and 2A-2B, the load impedance of
the LLHG slicer 100 is controlled by the same clock phases that
control the tracking and regeneration modes.
[0061] FIG. 3A illustrates the tunable resistor 102-1 utilizing
parallel-connected fixed resistors, according to some exemplary
embodiments of the present invention. FIG. 3B illustrates the
tunable resistor 102-2 utilizing series-connected fixed resistors,
according to some other exemplary embodiments of the present
invention.
[0062] Referring to FIG. 3A, the tunable resistor 102-1, according
to some embodiments, further includes first and second output
resistors R.sub.1 and R.sub.2 respectively connected in parallel
with the output transistors M.sub.ON and M.sub.OP and the active
transistors M.sub.A1 and M.sub.A2. The first and second output
resistors R.sub.1 and R.sub.2 have a fixed (e.g., set or clock
independent) resistance.
[0063] Referring to FIG. 3B, the tunable resistor 102-2, according
to some other embodiments, further includes the first and second
output resistors R.sub.1 and R.sub.2 respectively connected in
series with the active transistors M.sub.A1 and M.sub.A2. That is,
the first and second output resistors R.sub.1 and R.sub.2 are
coupled between the first voltage source V.sub.D and respective
ones of the output nodes N.sub.1 and N.sub.2.
[0064] In some examples, series-connected resistors may be
connected in series with the output transistors M.sub.ON and
M.sub.OP in lieu of, or in addition to, the first and second output
resistors R.sub.1 and R.sub.2 of the embodiments illustrated in
FIGS. 3A-3B.
[0065] The parallel-connected (or series-connected) output
resistors R.sub.1 and R.sub.2 (and any other additional fixed
resistors) serve to modify (e.g., shift) the tunable resistance
range of the tunable resistors 102-1 and 102-2.
[0066] Accordingly, the LLHG slicer, described through the above
exemplary embodiments, decouples the tracking latency from the
regeneration gain by adopting a dynamically tuned output
resistance. Therefore, the LLHG slicer is capable of achieving both
low latency and high gain.
[0067] Because the LLHG slicer, according to exemplary embodiments
of the present invention, replaces the loading resistors of
conventional designs with clocked CMOS devices, and because active
inductors are made by CMOS devices without any resistor, the LLHG
slicer may occupy a small (e.g., minimum) amount of die area,
relative to conventional solutions. Further, the diode-connected
devices of the LLHG slicer may automatically compensate for the
process variations (e.g., transistor threshold variations and/or
bias current variations) within the active inductor devices.
Furthermore, as compared to conventional solutions, the
diode-connected devices are low powered and use only a small amount
(e.g., a minimum amount) of DC current to provide a voltage drop to
bias the active inductor devices.
[0068] The LLHG slicer may be utilized in, for example, any serial
link (e.g., high-speed serial link), such as a high-definition
multimedia interface (HDMI) link, a universal serial bus (USB)
link, a peripheral component interconnect (PCI) link, an Ethernet
link, and/or the like. However, embodiments of the present
invention are not limited thereto.
[0069] While this invention has been described in detail with
particular references to illustrative embodiments thereof, the
embodiments described herein are not intended to be exhaustive or
to limit the scope of the invention to the exact forms disclosed.
Persons skilled in the art and technology to which this invention
pertains will appreciate that alterations and changes in the
described structures and methods of assembly and operation can be
practiced without meaningfully departing from the principles,
spirit, and scope of this invention, as set forth in the following
claims and equivalents thereof.
[0070] It will be understood that, although the terms "first,"
"second," "third," etc., may be used herein to describe various
elements, components, and/or sections, these elements, components,
and/or sections should not be limited by these terms. These terms
are used to distinguish one element, component, or section from
another element, component, or section. Thus, a first element,
component, or section discussed above could be termed a second
element, component, or section, without departing from the spirit
and scope of the invention.
[0071] It will also be understood that when an element is referred
to as being "between" two elements, it can be the only element
between the two elements, or one or more intervening elements may
also be present.
[0072] The terminology used herein is for the purpose of describing
particular embodiments and is not intended to be limiting of the
invention. As used herein, the singular forms "a" and "an" are
intended to include the plural forms as well, unless the context
clearly indicates otherwise. It will be further understood that the
terms "include," "including," "comprises," and/or "comprising,"
when used in this specification, specify the presence of stated
features, integers, steps, operations, elements, and/or components,
but do not preclude the presence or addition of one or more other
features, integers, steps, operations, elements, components, and/or
groups thereof. As used herein, the term "and/or" includes any and
all combinations of one or more of the associated listed items.
Further, the use of "may" when describing embodiments of the
invention refers to "one or more embodiments of the invention."
Also, the term "exemplary" is intended to refer to an example or
illustration.
[0073] It will be understood that when an element or component is
referred to as being "connected to" or "coupled to" another element
or component, it can be directly connected to or coupled to the
other element or component, or one or more intervening elements or
components may be present. When an element or layer is referred to
as being "directly connected to" or "directly coupled to" another
element or component, there are no intervening elements or
components present.
[0074] As used herein, the terms "substantially," "about," and
similar terms are used as terms of approximation and not as terms
of degree, and are intended to account for the inherent variations
in measured or calculated values that would be recognized by those
of ordinary skill in the art.
[0075] As used herein, the terms "use," "using," and "used" may be
considered synonymous with the terms "utilize," "utilizing," and
"utilized," respectively.
* * * * *