U.S. patent application number 14/867463 was filed with the patent office on 2017-03-30 for multi-level signaling for on-package chip-to-chip interconnect through silicon bridge.
This patent application is currently assigned to ALTERA CORPORATION. The applicant listed for this patent is ALTERA CORPORATION. Invention is credited to Dinesh PATIL.
Application Number | 20170092586 14/867463 |
Document ID | / |
Family ID | 57226741 |
Filed Date | 2017-03-30 |
United States Patent
Application |
20170092586 |
Kind Code |
A1 |
PATIL; Dinesh |
March 30, 2017 |
MULTI-LEVEL SIGNALING FOR ON-PACKAGE CHIP-TO-CHIP INTERCONNECT
THROUGH SILICON BRIDGE
Abstract
One embodiment relates to an apparatus for data communication
between at least two in-package semiconductor dies. On the first
semiconductor die in a package, a digital-to-analog converter (DAC)
converts a plurality of binary signals to an analog signal. The
analog signal is transmitted through a silicon bridge to a second
semiconductor die. Another embodiment relates to a method of data
communication between at least two in-package semiconductor dies. A
plurality of binary signals is converted to an analog signal by a
digital-to-analog converter on a first semiconductor die. The
analog signal is transmitted through a silicon bridge to a second
semiconductor die. Other embodiments, aspects and features are also
disclosed.
Inventors: |
PATIL; Dinesh; (Sunnyvale,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ALTERA CORPORATION |
San Jose |
CA |
US |
|
|
Assignee: |
ALTERA CORPORATION
San Jose
CA
|
Family ID: |
57226741 |
Appl. No.: |
14/867463 |
Filed: |
September 28, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/5381 20130101;
H01L 25/0655 20130101; H01L 23/538 20130101; H01L 23/5385 20130101;
H01L 2224/16227 20130101; H01L 2924/15311 20130101 |
International
Class: |
H01L 23/538 20060101
H01L023/538; H03M 1/12 20060101 H03M001/12; H03M 1/66 20060101
H03M001/66 |
Claims
1. An apparatus for data communication between at least two
in-package semiconductor dies, the apparatus comprising: an
digital-to-analog converter on a first semiconductor die in a
package that converts a plurality of binary signals to an analog
signal and drives the first analog signal; and a silicon bridge for
receiving the analog signal from the first semiconductor die and
transmitting the analog signal to a second semiconductor die in the
package; and an analog-to-digital converter on the second
semiconductor die that receives the analog signal from the silicon
bridge and converts the analog signal to a plurality of recovered
binary signals.
2. The apparatus of claim 1, wherein the plurality of binary
signals comprises n binary signals, where n is an integer that is
two or more, and wherein the digital-to-analog converter comprises
an N-level digital-to-analog converter, where N=2.sup.n.
3. The apparatus of claim 1, further comprising: a first register
on the first semiconductor die that receives a multiple-bit data
signal from logic circuitry on the first semiconductor die and
outputs the plurality of binary signals to the digital-to-analog
converter.
4. (canceled)
5. The apparatus of claim 1, further comprising: a first register
on the first semiconductor die that receives a multiple-bit data
signal from logic circuitry on the first semiconductor die and
outputs the plurality of binary signals to the digital-to-analog
converter; and a second register on the second semiconductor die
that receives the plurality of recovered binary signals from the
analog-to-digital converter and outputs an multiple-bit recovered
data signal to logic circuitry on the second semiconductor die.
6. The apparatus of claim 5, further comprising: a clock
transmitter on the first semiconductor die that transmits a clock
signal through the silicon bridge to the second semiconductor die;
and a clock receiver on the second semiconductor die that receives
the clock signal.
7. The apparatus of claim 6, wherein the clock signal is provided
to the first register and provides timing for switching the binary
signals.
8. The apparatus of claim 7, further comprising: an inverter on the
second semiconductor die that receives the clock signal and outputs
an inverted clock signal, wherein the inverted clock signal is
provided to the analog-to-digital converter and provides timing for
sampling the analog signal.
9. A method of data communication between at least two in-package
semiconductor dies, the method comprising: receiving by a first
register a multiple-bit data signal from logic circuitry on a first
semiconductor die; outputting the plurality of binary signals to a
digital-to-analog converter; converting a plurality of binary
signals to an analog signal by the digital-to-analog converter on
the first semiconductor die in a package; transmitting the analog
signal through a silicon bridge to a second semiconductor die in
the package; converting the analog signal to a plurality of
recovered binary signals by an analog-to-digital converter on the
second semiconductor die; receiving by a second register the
plurality of recovered binary signals from the analog-to-digital
converter; and outputting an multiple-bit recovered data signal to
logic circuitry on the second semiconductor die.
10. The method of claim 9, wherein the plurality of binary signals
comprises n binary signals, where n is an integer that is two or
more, and wherein the digital-to-analog converter comprises an
N-level digital-to-analog converter, where N=2.sup.n.
11. (canceled)
12. (canceled)
13. (canceled)
14. The method of claim 9, further comprising: transmitting a clock
signal through the silicon bridge to the second semiconductor die
by a clock transmitter on the first semiconductor die; and
receiving the clock signal by a clock receiver on the second
semiconductor die.
15. The method of claim 14, wherein the clock signal is provided to
the first register and provides timing for switching the binary
signals.
16. The method of claim 15, further comprising: receiving the clock
signal and outputting an inverted clock signal by an inverter on
the second semiconductor die; and using the inverted clock signal
by the second register to provide timing for sampling of the analog
signal.
17. (canceled)
18. An apparatus for data communication between at least two
in-package semiconductor dies, the apparatus comprising: a first
digital-to-analog converter on a first semiconductor die in a
package that converts a first plurality of binary signals to a
first analog signal and drives the first analog signal to a silicon
bridge; a first analog-to-digital converter on the first
semiconductor die that receives a second analog signal from the
silicon bridge and converts the second analog signal to a first
plurality of recovered binary signals; a second digital-to-analog
converter on a second semiconductor die in the package that
converts a second plurality of binary signals to the second analog
signal and drives the second analog signal to the silicon bridge;
and a second analog-to-digital converter on the second
semiconductor die that receives the first analog signal from the
silicon bridge and converts the first analog signal to a second
plurality of recovered binary signals.
Description
BACKGROUND
[0001] Technical Field
[0002] The present invention relates generally to data
communications. More particularly, the present invention relates to
circuitry for data communications between integrated circuit
devices.
[0003] Description of the Background Art
[0004] High-speed data links are used to communicate data between
integrated circuit devices in a system. Serial interface protocols
have been developed at increasingly fast data-rates for such
high-speed links.
SUMMARY
[0005] One embodiment relates to an apparatus for data
communication between at least two in-package semiconductor dies.
On the first semiconductor die in a package, a digital-to-analog
converter (DAC) converts a set of binary signals to an analog
signal level (out of 2.sup.n possibilities, for example). A silicon
bridge transmits the analog signal to a second semiconductor die in
the package.
[0006] Another embodiment relates to a method of data communication
between at least two in-package semiconductor dies. A plurality of
binary signals is converted to an analog signal by a
digital-to-analog converter on a first semiconductor die. The
analog signal is transmitted through a silicon bridge to a second
semiconductor die.
[0007] Another embodiment relates to a system for transmitting a
multiple-level data signal across an interposer from a first
integrated circuit to a second integrated circuit. A first register
on the first semiconductor die receives a multiple-bit data signal
from logic circuitry on the first integrated circuit and outputs a
plurality of binary signals. A digital-to-analog converter on the
first integrated circuit each receives the plurality of binary
signals, converts the plurality of binary signals to an analog
signal, and drives the analog signal to an output node on the first
integrated circuit. A connection is provided through the interposer
between the output node of the first integrated circuit and an
input node of the second integrated circuit.
[0008] Another embodiment relates to an apparatus for data
communication between at least two in-package semiconductor dies. A
first digital-to-analog converter on a first semiconductor die in a
package converts a first plurality of binary signals to a first
analog signal and drives the first analog signal to a silicon
bridge. A first analog-to-digital converter on the first
semiconductor die that receives a second analog signal from the
silicon bridge and converts the second analog signal to a first
plurality of recovered binary signals.
[0009] Another embodiment relates to a method for data
communication between at least two in-package semiconductor dies. A
plurality of binary signals are received from first logic circuitry
in a first semiconductor die in a package. The plurality of binary
signals are converted to a first analog signal using an
digital-to-analog converter on the first semiconductor die. The
first analog signal is driven from the first semiconductor die to a
silicon bridge.
[0010] Other embodiments, aspects, and features are also
disclosed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a schematic diagram illustrating two semiconductor
dies interconnected through a silicon bridge in accordance with an
embodiment of the invention.
[0012] FIG. 2A is a block diagram depicting multiple PAM-N
transmitter circuits of a first semiconductor die connecting via a
silicon bridge to multiple PAM-N receiver circuits of a second
semiconductor die in accordance with an embodiment of the
invention.
[0013] FIG. 2B is a block diagram depicting multiple PAM-N
transmitter circuits of a first semiconductor die connecting via a
silicon bridge to multiple PAM-N receiver circuits of a second
semiconductor die and multiple PAM-N transmitter circuits of the
second semiconductor die connecting via the silicon bridge to
multiple PAM-N receiver circuits of the first semiconductor die in
accordance with an embodiment of the invention.
[0014] FIG. 3 is a block diagram of a PAM-N transmitter circuit in
accordance with an embodiment of the invention.
[0015] FIG. 4 is a block diagram of a PAM-N receiver circuit in
accordance with an embodiment of the invention.
[0016] FIG. 5 is a flow chart of a method of transmitting a
multi-level amplitude signal to a silicon bridge in accordance with
an embodiment of the invention.
[0017] FIG. 6 is a flow chart of a method of receiving a
multi-level amplitude signal from a silicon bridge in accordance
with an embodiment of the invention.
[0018] FIG. 7 is a simplified partial block diagram of a field
programmable gate array that may be arranged or configured to
include one or more of the circuits disclosed herein in accordance
with an embodiment of the invention.
[0019] FIG. 8 is a block diagram of an exemplary digital system
that may employ a multi-level signaling data link in accordance
with an embodiment of the invention.
DETAILED DESCRIPTION
[0020] The conventional wisdom is to use PAM-N signaling to lower
the signaling baud rate for serial links when signal loss at higher
baud rate is too high. In the case of interconnections through a
silicon bridge (or other similar interposer), channel loss is
generally very low. Hence, the conventional wisdom would be against
using PAM-N signaling across a silicon bridge.
[0021] The presently-disclosed solution goes counter to this
conventional wisdom and implements PAM-N signaling across a silicon
bridge. This solution is based on the determination by the
applicant that, despite no need to improve channel loss across a
silicon bridge (or similar interposer), using PAM-N signaling
simplifies and improves other different issues, specifically for a
parallel interface. These issues include clock generation and
distribution, cross talk, simultaneous switching noise, and
pin-to-pin skew.
[0022] One embodiment of the invention relates to a packaged device
containing multiple semiconductor die (integrated circuit chips)
connected by an embedded silicon bridge (an interposer). For such a
package device, increasing the interconnect bandwidth between the
die (assuming binary signaling) either costs more micro-bumps of
interconnect, or entails increasing the design complexity in the
clocking network to support a higher data-rate (for example, to
greater than one gigabits per second).
[0023] However, issues such as on-die variations, pin-to-pin skew,
duty cycle variations, high-speed clock generation and distribution
and so on, cost additional area and power to accommodate. These
costs offset the noise benefits of simple binary signaling.
[0024] The present solution uses a data signal with multiple (three
or more) logical levels on one lane to transfer more than one bit
of data per symbol on the lane. A lane may correspond to a
micro-bump for a single-ended signal or a pair of micro-bumps for a
differential signal. Hence, in this solution, for a given aggregate
data-rate, sending more than one bit per symbol for each lane
enables using fewer micro-bumps for the same baud-rate.
Alternatively, for a given aggregate data-rate, sending more than
one bit per symbol for each lane enables running at a lower
baud-rate for the same number of micro-bumps.
[0025] One specific implementation uses a 4-level transmit
digital-to-analog converter (DAC) to send, and a 4-level receive
analog-to-digital converter (ADC) to receive, two bits per symbol
for each lane. Another specific implementation uses an 8-level
transmit DAC to send, and an 8-level receive ADC to receive, three
bits per symbol for each lane. Another specific implementation uses
a 16-level transmit DAC to send, and an 16-level receive ADC to
receive, four bits per symbol for each lane.
[0026] Advantageously, using a lower baud-rate simplifies clocking
and mitigates concerns over on-chip pin-to-pin skew, power supply
noise, and duty cycle variations. In addition, the lower baud-rate
allows using simpler circuits to decode the data. Hence, this
solution not only reduces symbol interference, but it may also lead
to reduction of the overall area and/or number of micro-bumps
(interconnections) needed for a given data-rate.
[0027] FIG. 1 is a schematic diagram illustrating two semiconductor
dies (106-1 and 106-2) interconnected through a silicon bridge 108
in accordance with an embodiment of the invention. As shown, the
two semiconductor dies (integrated circuit chips) may be
interconnected with micro-bump interconnections 107 to circuitry on
a laminate substrate 102.
[0028] As further shown, the laminate substrate 102 may include an
embedded silicon bridge 108 that acts as an interposer between the
two semiconductor dies (106-1 and 106-2). The micro-bumps 107 may
be used to interconnect circuitry on each of the semiconductor dies
with circuitry on the silicon bridge 108. As described further
below, the two semiconductor dies (106-1 and 106-2) may communicate
by way of a multiple-lane data channel that goes through the
silicon bridge 108.
[0029] FIG. 2A is a block diagram depicting multiple PAM-N
transmitter circuits 202 of a first semiconductor die 106-1
connecting via a silicon bridge 108 to multiple PAM-N receiver
circuits 204 of a second semiconductor die 106-2 in accordance with
an embodiment of the invention. As discussed above, N is three or
greater such that more than one bit is transmitted per symbol. In
preferred embodiments, N is 4, 8, 16, etc. In other words, in a
preferred embodiment N=2.sup.n, where n is an integer that is two
or more. An implementation of a PAM-N transmitter circuit 202 is
described below in relation to FIG. 3, and an implementation of a
PAM-N receiver circuit 204 is described below in relation to FIG.
4.
[0030] As further shown in FIG. 2A, a clock generation circuit 206
on the first semiconductor die 106-1 may generate the clock signal
Clk, which may be distributed to each of the PAM-N transmitter
circuits 202 and to a clock transmitter circuit 208. The clock
signal Clk may be a CMOS clock signal, for example. The PAM-N
transmitter circuits 202 may use the clock signal Clk to determine
the baud-rate and timing for data transmission via the multiple
lanes. The clock transmitter (Clk TX) circuit 208 on the first
semiconductor die 106-1 may be used to transmit the clock signal
Clk via the silicon bridge 108 to the second semiconductor die
106-2.
[0031] The clock signal Clk may be received by the clock receiver
(Clk RX) circuit on the second semiconductor die 106-2. An inverter
circuit 211 may be used to generate the inverted clock signal Clk,
and clock distribution circuitry 212 may distribute the inverted
clock signal Clk to the PAM-N receiver circuits 204 on the second
semiconductor die 106-2. The PAM-N receiver circuits 204 may use
the inverted clock signal Clk to determine the timing for data
reception on the multiple lanes.
[0032] The clock edges that are 180 degrees apart may be used to
time symbol transitions by a transmitter circuit 202 and to sample
the data signal by a corresponding receiver circuit 204. For
example, if the rising edge of the clock signal Clk may be used to
time the transitions between symbols by the PAM-N transmitter
circuit 202, then the rising edge of the inverted clock signal Clk
may be used for sampling data by a PAM-N receiver circuit 204.
[0033] FIG. 2B is a block diagram depicting multiple PAM-N
transmitter circuits 202 of a first semiconductor die 106-1
connecting via a silicon bridge 108 to multiple PAM-N receiver
circuits 104 of a second semiconductor die 106-2 and multiple PAM-N
transmitter circuits 202 of the second semiconductor die 106-2
connecting via the silicon bridge 108 to multiple PAM-N receiver
circuits 104 of the first semiconductor die 106-1 in accordance
with an embodiment of the invention. The circuits in FIG. 2B
operate as described above in relation to FIG. 2A. However, while
FIG. 2A provides one-way communication from the first semiconductor
die 106-1 to the second semiconductor die 106-2, FIG. 2B provides
bi-directional communication between the first and second
semiconductor dies.
[0034] FIG. 3 is a block diagram of a PAM-N transmitter circuit 202
on the first semiconductor die 106-1 in accordance with an
embodiment of the invention. As shown, the PAM-N transmitter
circuit 202 may include an n-bit register circuit 302 and a N-level
digital-to-analog converter (DAC) circuit 304. In a preferred
embodiment, N=2.sup.n, where n is an integer that is two or
more.
[0035] The n-bit register circuit 302 may receive and latch n bits
of data. The data may be received in parallel from logic circuitry
on the first semiconductor die 106-1. The timing for the n-bit
register circuit 302 may be provided by a clock edge (for example,
the rising edge) of the clock signal Clk, described above in
relation to FIG. 2A.
[0036] The n binary signals output from the n-bit register circuit
302 may be provided to the N-level DAC circuit 304. The N-level DAC
circuit 304 may convert the n binary signals to an analog
signal.
[0037] The amplitude of the analog signal that is output by each of
the N-level DAC circuit 304 depends on the values of the n bits.
For example, with n=4 and N=2.sup.4=16, the output range of the
analog signal may be 0 volts to 1.5 volts in steps of 100
millivolts. For example: if the 4 binary signals are 0000, then the
analog signal may be 0 volts; if the 4 binary signals are logical
0001, then the analog signal may be 0.1 volts; if the 4 binary
signals are logical 0010, then the analog signal may be 0.2 volts;
if the 4 binary signals are logical 0011, then the analog signal
may be 0.3 volts; . . . ; if the 4 binary signals are logical 1111,
then the analog signal may be 1.5 volts.
[0038] The analog signal goes from the output node 306 through the
silicon bridge 108 to a corresponding PAM-N receiver circuit 204 on
the second semiconductor die 106-2.
[0039] In one embodiment, PAM-16 may be implemented such that one
lane carries four bits. Specific multiple-lane implementations to
achieve an aggregate data rate of 32 Gbps may be as follows: 16
lanes of PAM-16 with a 500 MHz clock; or 8 lanes of PAM-16 with a 1
GHz clock; or 4 lanes of PAM-16 with a 2 GHz clock.
[0040] Advantageously, with simplified clocking, power may be
scaled with the data rate. In particular, the driver circuits may
be made slower with lower power for lower data rates.
[0041] FIG. 4 is a block diagram of a PAM-N receiver circuit 204 on
the second semiconductor die 106-2 in accordance with an embodiment
of the invention. As shown, the PAM-N receiver circuit 204 may
include an N-level analog-to-digital converter (ADC) circuit 402,
and an n-bit register circuit 404. In a preferred embodiment,
N=2.sup.n, where n is an integer that is two or more.
[0042] The analog data signal may be received by the N-level ADC
circuit 402. The N-level ADC circuit 402 may be implemented with
N-1 comparators, and the structure of the N-level ADC circuit 402
may be flashed or pipelined.
[0043] The N-level ADC circuit 402 converts the analog signal to n
recovered binary signals. The n recovered binary signals may be
provided in parallel to, and sampled by, the n-bit register circuit
404 to recover an n-bit data signal. The timing for the sampling
may be provided by a clock edge (for example, the rising edge) from
the inverted clock signal Clk, described above in relation to FIG.
2A.
[0044] Finally, the n-bit register circuit 404 may output the
recovered n-bit data signal in parallel to logic circuitry on the
second semiconductor die 106-2 for further processing and use.
[0045] FIG. 5 is a flow chart of a method 500 of transmitting a
multi-level amplitude signal to a silicon bridge in accordance with
an embodiment of the invention. The method may be performed by
using a PAM-N transmitter 202 of the first semiconductor die
106-1.
[0046] Per step 502, n bits of a data signal received from logic
circuitry of the first semiconductor die 106-1 and latched by the
n-bit register circuit 302. Subsequently, per step 504, the n-bit
register circuit 302 may output n binary signals corresponding to
the n bits.
[0047] Per step 506, the n binary signals may be converted to an
analog signal. As described above in relation to FIG. 3, the
conversion may be performed by aDAC circuit. Per step 508, the
output of the DAC circuit may be combined and switched
simultaneously to drive the analog signal from the first die 106-1
through the silicon bridge to the second die 106-2.
[0048] FIG. 6 is a flow chart of a method 600 of receiving a
multi-level amplitude signal from a silicon bridge in accordance
with an embodiment of the invention. The method 600 may be
performed by using a PAM-N receiver 204 of the second semiconductor
die 106-2. Before the method 600, each comparator may be calibrated
for offset correction.
[0049] Per step 602, the analog data signal may be received by an
N-level ADC circuit 402. The N-level ADC circuit 402 may be
implemented with N-1 comparators, and the structure of the N-level
ADC circuit 402 may be flashed or pipelined.
[0050] Per step 604, the analog signal may be converted to n
recovered binary signals. Per step 606, the n recovered binary
signals may be provided in parallel to, and sampled by, the n-bit
register circuit 404 to recover an n-bit data signal. The timing
for the sampling may be provided by a clock edge (for example, the
rising edge) from the inverted clock signal Clk, described above in
relation to FIG. 2.
[0051] Finally, per step 608, the recovered n-bit data signal may
be output from the n-bit register circuit 404 in parallel to logic
circuitry on the second semiconductor die 106-2 for further
processing and use.
[0052] FIG. 7 is a simplified partial block diagram of a field
programmable gate array (FPGA) 10 that may be arranged or
configured to include one or more of the circuits disclosed herein
in accordance with an embodiment of the invention. It should be
understood that embodiments of the present invention may be used in
numerous types of integrated circuits, including FPGAs,
programmable logic devices (PLDs), complex programmable logic
devices (CPLDs), programmable logic arrays (PLAs), digital signal
processors (DSPs) and application specific integrated circuits
(ASICs).
[0053] FPGA 10 includes within its "core" a two-dimensional array
of programmable logic array blocks (or LABs) 12 that are
interconnected by a network of column and row interconnect
conductors of varying length and speed. LABs 12 include multiple
(e.g., ten) logic elements (or LEs). An LE is a programmable logic
block that provides for efficient implementation of user defined
logic functions. An FPGA has numerous logic elements that can be
configured to implement various combinatorial and sequential
functions. The logic elements have access to a programmable
interconnect structure. The programmable interconnect structure can
be programmed to interconnect the logic elements in almost any
desired configuration.
[0054] FPGA 10 may also include a distributed memory structure
including random access memory (RAM) blocks of varying sizes
provided throughout the array. The RAM blocks include, for example,
blocks 14, blocks 16, and block 18. These memory blocks can also
include shift registers and FIFO buffers. FPGA 10 may further
include digital signal processing (DSP) blocks 20 that can
implement, for example, multipliers with add or subtract
features.
[0055] Input/output elements (IOEs) 22 located, in this example,
around the periphery of the chip support numerous single-ended and
differential input/output standards. Each 10E 22 is coupled to an
external terminal (i.e., a pin) of FPGA 10. A transceiver (TX/RX)
channel array may be arranged as shown, for example, with each
TX/RX channel circuit 30 being coupled to several LABs. A TX/RX
channel circuit 30 may include, among other circuitry, the
transmitter and receiver circuitry described herein.
[0056] It is to be understood that FPGA 10 is described herein for
illustrative purposes only and that the present invention can be
implemented in many different types of PLDs, FPGAs, and ASICs.
[0057] FIG. 8 is a block diagram of an exemplary digital system 50
that may employ multi-level amplitude signaling in accordance with
an embodiment of the invention. As shown, system 50 may include an
FPGA as one of several components.
[0058] System 50 may be, for example, a programmed digital computer
system, digital signal processing system, specialized digital
switching network, or other processing system. System 50 may be
designed for a wide variety of applications such as
telecommunications systems, automotive systems, control systems,
consumer electronics, personal computers, Internet communications
and networking, and others. Further, system 50 may be provided on a
single board, on multiple boards, or within multiple
enclosures.
[0059] As shown, system 50 includes a processing unit 52, a memory
unit 54, and an input/output (I/O) unit 56 interconnected together
by one or more buses. According to this exemplary embodiment, FPGA
58 is embedded in processing unit 52. FPGA 58 may serve many
different purposes within the system 50. FPGA 58 may, for example,
be a logical building block of processing unit 52, supporting its
internal and external operations. FPGA 58 is programmed to
implement the logical functions necessary to carry on its
particular role in system operation. FPGA 58 can be specially
coupled to memory 54 through connection 60 and to I/O unit 56
through connection 62.
[0060] Processing unit 52 may direct data to an appropriate system
component for processing or storage, execute a program stored in
memory 54, receive and transmit data via I/O unit 56, or other
similar function. Processing unit 52 may be a central processing
unit (CPU), microprocessor, floating point coprocessor, graphics
coprocessor, hardware controller, microcontroller, field
programmable gate array programmed for use as a controller, network
controller, or any type of processor or controller. Furthermore, in
many embodiments, there is often no need for a CPU.
[0061] For example, instead of a CPU, one or more FPGAs 58 may
control the logical operations of the system. As another example,
FPGA 58 acts as a reconfigurable processor that may be reprogrammed
as needed to handle a particular computing task. Alternately, FPGA
58 may itself include an embedded microprocessor. Memory unit 54
may be a random access memory (RAM), read only memory (ROM), fixed
or flexible disk media, flash memory, tape, or any other storage
means, or any combination of these storage means.
[0062] In the above description, numerous specific details are
given to provide a thorough understanding of embodiments of the
invention. However, the above description of illustrated
embodiments of the invention is not intended to be exhaustive or to
limit the invention to the precise forms disclosed. One skilled in
the relevant art will recognize that the invention can be practiced
without one or more of the specific details, or with other methods,
components, etc.
[0063] In other instances, well-known structures or operations are
not shown or described in detail to avoid obscuring aspects of the
invention. While specific embodiments of, and examples for, the
invention are described herein for illustrative purposes, various
equivalent modifications are possible within the scope of the
invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the
above detailed description.
* * * * *