U.S. patent application number 15/366726 was filed with the patent office on 2017-03-23 for pixel array substrate and liquid crystal display panel.
The applicant listed for this patent is AU Optronics Corporation. Invention is credited to Jen-Yang CHUNG, Shin-Mei GONG, Chien-Huang LIAO, Kun-Cheng TIEN, Wei-Chun WEI, Ming-Huei WU.
Application Number | 20170082901 15/366726 |
Document ID | / |
Family ID | 49192831 |
Filed Date | 2017-03-23 |
United States Patent
Application |
20170082901 |
Kind Code |
A1 |
WU; Ming-Huei ; et
al. |
March 23, 2017 |
PIXEL ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL
Abstract
A pixel array substrate with new pixel design and a liquid
crystal display panel with the pixel array substrate are provided.
The pixel array substrate includes a plurality of data lines, a
plurality of scan lines and a plurality of pixels. Each of the
pixels comprises a first electrode, a first connecting line, a
second electrode and a second connecting line. The first electrode
is electrically connected with corresponding data line and scan
line through the first connecting line, and having a slit. The
second pixel is electrically connected with corresponding data line
and scan line through the second connecting line. At least a part
of the second connecting line is exposed by the slit of the first
electrode.
Inventors: |
WU; Ming-Huei; (HSIN-CHU,
TW) ; TIEN; Kun-Cheng; (HSIN-CHU, TW) ; GONG;
Shin-Mei; (HSIN-CHU, TW) ; CHUNG; Jen-Yang;
(HSIN-CHU, TW) ; WEI; Wei-Chun; (HSIN-CHU, TW)
; LIAO; Chien-Huang; (HSIN-CHU, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
AU Optronics Corporation |
HSIN-CHU |
|
TW |
|
|
Family ID: |
49192831 |
Appl. No.: |
15/366726 |
Filed: |
December 1, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14041071 |
Sep 30, 2013 |
9541796 |
|
|
15366726 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G02F 1/134309 20130101;
G02F 2001/134345 20130101; G02F 1/136213 20130101; G02F 1/133707
20130101; G02F 1/136286 20130101; G02F 1/13624 20130101; G02F
2201/123 20130101 |
International
Class: |
G02F 1/1343 20060101
G02F001/1343; G02F 1/1362 20060101 G02F001/1362; G02F 1/1337
20060101 G02F001/1337 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 22, 2013 |
TW |
102102336 |
Claims
1. A pixel array substrate, comprising: a plurality of pixels
comprising: a first pixel electrode having a first slit; a first
connecting line electrically connected to the first pixel
electrode; a second pixel electrode; and a second connecting line,
electrically connected to the second pixel electrode, wherein at
least a part of the second connecting line is exposed by the first
slit of the first pixel electrode, the first pixel electrode
comprises a first sub-pixel electrode and a second sub-pixel
electrode, the first slit is substantially positioned between the
first sub-pixel electrode and the second sub-pixel electrode, and
the first sub-pixel electrode comprises: a first main electrode; a
second main electrode, the first main electrode and the second main
electrode being electrically connected and are substantially
orthogonally arranged to define a first area, a second area, a
third area and a fourth area; a plurality of first branch
electrodes disposed in the first area; a plurality of second branch
electrodes disposed in the second area; a plurality of third branch
electrodes disposed in the third area; and a plurality of fourth
branch electrodes disposed in the fourth area, wherein the
plurality of first branch electrodes, the plurality of second
branch electrodes, the plurality of third branch electrodes and the
plurality of fourth branch electrodes are electrically connected
with at least one of the first main electrode and the second main
electrode, the first branch electrodes are arranged parallel to
each other, the second branch electrodes are arranged parallel to
each other, the third branch electrodes are arranged parallel to
each other and the fourth branch electrodes are arranged parallel
to each other, and the plurality of first branch electrodes, the
plurality of second branch electrodes, the plurality of third
branch electrodes and the plurality of fourth branch electrodes
respectively extend to different directions from the first main
electrode or the second main electrode.
2. The pixel array substrate of claim 1, wherein the first slit is
an open slit.
3. The pixel array substrate of claim 1, wherein the first slit is
a closed slit.
4. The pixel array substrate of claim 1, further comprising: a
plurality of data lines; a plurality of scan lines crossed to the
plurality of data lines to define a plurality of pixel areas,
wherein the pixels are respectively disposed in the plurality of
pixel areas, and the first connecting line and the second
connecting line are electrically connected to a data line of the
plurality of data lines.
5. The pixel array substrate of claim 4, wherein the first main
electrode is substantially parallel to the first slit, and the
distance between the first main electrode and the first slit is
greater than that between the first main electrode and the data
line of the plurality of data lines.
6. The pixel array substrate of claim 1, further comprising: a
plurality of data lines; a plurality of scan lines crossed to the
plurality of data lines to define a plurality of pixel areas,
wherein the pixels are respectively disposed in the plurality of
pixel areas, and the first connecting line and the second
connecting line are electrically connected to different data lines
of the plurality of data lines.
7. The pixel array substrate of claim 1, wherein the first
sub-pixel electrode and the second sub-pixel electrode are mirror
symmetry structures with respect to the first slit.
8. The pixel array substrate of claim 1, wherein each of the pixels
further comprises: a third pixel electrode having a second slit;
and a third connecting line electrically connected to the third
pixel electrode; wherein at least a part of the second connecting
line is exposed by the first slit of the first pixel electrode and
the second slit of the third pixel electrode.
9. The pixel array substrate of claim 8, further comprising: a
plurality of data lines; a plurality of scan lines crossed to the
plurality of data lines to define a plurality of pixel areas,
wherein the pixels are respectively disposed in the plurality of
pixel areas, and the first connecting line and the third connecting
line are electrically connected to a data line of the plurality of
data lines.
10. The pixel array substrate of claim 8, wherein the third
connecting line is disposed on an edge of the first sub-pixel
electrode, the third pixel electrode comprises a third sub-pixel
electrode and a fourth sub-pixel electrode, the second slit is
substantially positioned between the third sub-pixel electrode and
the fourth sub-pixel electrode, and the second slit is
substantially positioned along the extending line of the first
slit, the first sub-pixel electrode and the second sub-pixel
electrode are mirror symmetry structures with respect to the first
slit, the third sub-pixel electrode and the fourth sub-pixel
electrode are mirror symmetry structures with respect to the second
slit.
11. The pixel array substrate of claim 10, wherein the third
sub-pixel electrode and the fourth sub-pixel electrode respectively
comprise: a first main electrode; a second main electrode, the
first main electrode and the second main electrode being
electrically connected and are substantially orthogonally arranged
to define a first area, a second area, a third area and a fourth
area; a plurality of first branch electrodes disposed in the first
area; a plurality of second branch electrodes disposed in the
second area; a plurality of third branch electrodes disposed in the
third area; and a plurality of fourth branch electrodes disposed in
the fourth area, wherein the plurality of first branch electrodes,
the plurality of second branch electrodes, the plurality of third
branch electrodes and the plurality of fourth branch electrodes are
electrically connected with one of the first main electrodes and
the second main electrodes, the first branch electrodes are
arranged parallel to each other, the second branch electrodes are
arranged parallel to each other, the third branch electrodes are
arranged parallel to each other and the fourth branch electrodes
are arranged parallel to each other, and the plurality of first
branch electrodes, the plurality of second branch electrodes, the
plurality of third branch electrodes and the plurality of fourth
branch electrodes respectively extend to different directions from
the first main electrode or the second main electrode, the first
sub-pixel electrode and the second sub-pixel electrode are mirror
symmetry structures with respect to the first slit, the third
sub-pixel electrode and the fourth sub-pixel electrode are mirror
symmetry structures with respect to the second slit, the first main
electrode of the first sub-pixel electrode is substantially
parallel to the first slit, the first main electrode of the third
sub-pixel electrode is substantially parallel to the second
slit.
12. The pixel array substrate of claim 1, further comprising: a
plurality of first switches respectively disposed on a side of each
of the pixel areas, a first end of each first switch being
electrically connected to the respective first pixel electrodes
through the first connecting line; and a plurality of second
switches respectively disposed on the side of each of the pixel
areas, each of the second switches being electrically connected to
the second pixel electrode through the second connecting line.
13. The pixel array substrate of claim 12, wherein each one of the
plurality of pixels further comprises: a charge-sharing capacitor;
and a third switch, wherein a first end of the charge-sharing
capacitor is electrically connected to the first pixel electrode,
and a second end of the charge-sharing capacitor is electrically
connected to the second pixel electrode through the third
switch.
14. A pixel array substrate, comprising: a plurality of data lines;
a plurality of scan lines crossed to the plurality of data lines to
define a plurality of pixel areas; and a plurality of pixels
respectively disposed in the plurality of pixel areas, each of the
pixels comprising: a first pixel electrode electrically connected
to one of the plurality of data lines and one of the plurality of
scan lines, the first pixel electrode having a first slit; a first
connecting line, the first pixel electrode electrically connected
to a data line of the plurality of data lines through the first
connecting line; a second pixel electrode electrically connected to
the data line or another one of the plurality of data lines and the
scan line of the plurality of scan lines, wherein the second pixel
electrode comprises a first main electrode paralleled to the data
line of the plurality of data lines; and a second connecting line,
the second pixel electrode electrically connected to the data line
or the another one of the plurality of data lines through the
second connecting line, wherein at least a part of the second
connecting line is exposed by the first slit of the first pixel
electrode, and the second connecting line is connected to the first
main electrode of the second pixel electrode.
15. The pixel array substrate of claim 14, wherein the first slit
is substantially parallel to the data line of the plurality of data
lines.
16. The pixel array substrate of claim 14, wherein the second pixel
electrode further comprises: a second main electrode, the first
main electrode and the second main electrode being electrically
connected and are substantially orthogonally arranged to define a
first area, a second area, a third area and a fourth area; a
plurality of first branch electrodes disposed in the first area; a
plurality of second branch electrodes disposed in the second area;
a plurality of third branch electrodes disposed in the third area;
and a plurality of fourth branch electrodes disposed in the fourth
area, wherein the plurality of first branch electrodes, the
plurality of second branch electrodes, the plurality of third
branch electrodes and the plurality of fourth branch electrodes are
electrically connected with at least one of the first main
electrode and the second main electrode, the first branch
electrodes are arranged parallel to each other, the second branch
electrodes are arranged parallel to each other, the third branch
electrodes are arranged parallel to each other and the fourth
branch electrodes are arranged parallel to each other, and the
plurality of first branch electrodes, the plurality of second
branch electrodes, the plurality of third branch electrodes and the
plurality of fourth branch electrodes respectively extend to
different directions from the first main electrode or the second
main electrode.
17. The pixel array substrate of claim 14, wherein the first pixel
electrode comprises a first sub-pixel electrode and a second
sub-pixel electrode, the first slit is substantially positioned
between the first sub-pixel electrode and the second sub-pixel
electrode, and the first sub-pixel electrode comprises: a first
main electrode; a second main electrode, the first main electrode
and the second main electrode being electrically connected and are
substantially orthogonally arranged to define a first area, a
second area, a third area and a fourth area; a plurality of first
branch electrodes disposed in the first area; a plurality of second
branch electrodes disposed in the second area; a plurality of third
branch electrodes disposed in the third area; and a plurality of
fourth branch electrodes disposed in the fourth area, wherein the
plurality of first branch electrodes, the plurality of second
branch electrodes, the plurality of third branch electrodes and the
plurality of fourth branch electrodes are electrically connected
with at least one of the first main electrode and the second main
electrode of the first sub-pixel electrode, and the plurality of
first branch electrodes, the plurality of second branch electrodes,
the plurality of third branch electrodes and the plurality of
fourth branch electrodes respectively extend to different
directions from the first main electrode or the second main
electrode.
18. The pixel array substrate of claim 17, wherein the first main
electrode of the first sub-pixel electrode is substantially
parallel to the first slit, and the distance between the first main
electrode of the first sub-pixel electrode and the first slit is
greater than that between the first main electrode of the first
sub-pixel electrode and the data line of the plurality of data
lines.
19. The pixel array substrate of claim 14, wherein each of the
pixels further comprises: a third pixel electrode electrically
connected to the data line of the plurality of data lines and the
scan line of the plurality of scan lines, the third pixel electrode
having a second slit; and a third connecting line, the third pixel
electrode electrically connected to the data line of the plurality
of data lines through the third connecting line; wherein at least a
part of the second connecting line is exposed by the first slit of
the first pixel electrode and the second slit of the third pixel
electrode.
20. The pixel array substrate of claim 19, wherein the third
connecting line is disposed on an edge of the first sub-pixel
electrode, the third pixel electrode comprises a third sub-pixel
electrode and a fourth sub-pixel electrode, the second slit is
substantially positioned between the third sub-pixel electrode and
the fourth sub-pixel electrode, and the second slit is
substantially positioned along the extending line of the first
slit, the first slit and the second slit are substantially parallel
to the plurality of data lines, the first sub-pixel electrode and
the second sub-pixel electrode are mirror symmetry structures with
respect to the first slit, and the third sub-pixel electrode and
the fourth sub-pixel electrode are mirror symmetry structures with
respect to the second slit.
Description
RELATED APPLICATIONS
[0001] The present application is a continuation application of
U.S. application Ser. No. 14/041,071, filed Sep. 30, 2013, which
claims priority to Taiwan Application Serial Number 102102336,
filed Jan. 22, 2013, which are herein incorporated by reference in
their entireties.
BACKGROUND
[0002] Technical Field
[0003] The present disclosure relates to a substrate, and more
particularly, to a pixel array substrate of a display panel
[0004] Description of Related Art
[0005] Liquid crystal display (LCD) panels have become the
mainstream display products because of advantages such as low
radiation, low power consumption and compact size. A variety of
techniques in the LCD panels are developed corresponding to
different needs. Among which, Vertical Alignment (VA) of the wide
viewing angle display technology has wider viewing angle than that
of Twisted Nematic (TN), fast responding, and high contrast ratio,
thus has been widely applied in a LCD panel.
[0006] However, the VA LCD panel is known for its color washout
issue. To solve the issue, the pixel area of the pixel array
substrate of current VA LCD panels is divided into two parts. As
illustrated in FIG. 1 and FIG. 2, FIG. 1 is a top-view of the
conventional pixel, and FIG. 2 is the equivalent circuit diagram of
the pixel illustrated in FIG. 1. Referring to FIG. 1 and FIG. 2,
pixel 100 includes a first pixel electrode 102, a second pixel
electrode 104, a first connecting line 106, and a second connecting
line 108. The first electrode 102 is electrically connected to its
corresponding data line DL1 and scan line SL1 through the first
connecting line 106 and the a switch T1; The second pixel electrode
104 is also electrically connected to its corresponding data line
DL1 and scan line SL1 through the second connecting line 108 and a
switch T2. In addition, pixel 100 also includes a switch T3,
storage capacitors C.sub.ST1, C.sub.ST2, common electrode
V.sub.COM, liquid crystal capacitors C.sub.LC1, C.sub.LC2, and
charge-sharing capacitor Cs (C.sub.CSA and C.sub.CSB). Switches T1,
T2, and T3 are thin-film transistors (TFT), for example. Liquid
crystal capacitors C.sub.LC1, C.sub.LC2 respectively represent the
capacitances which are generated between pixel electrode (the first
pixel electrode 102 and the second pixel electrode 104) and the
electrode(s) applied with V.sub.COM voltage on the opposite
substrate of the LCD panel (not illustrated in FIG. 1 and FIG. 2).
C.sub.ST1 and C.sub.ST2 respectively represent the capacitances
which are generated between common electrode applied with V.sub.COM
voltage and each pixel electrode (the first pixel electrode 102 and
the second pixel electrode 104) of the pixel array substrate of the
LCD panel. Charge-sharing capacitor Cs is an extension from the
switch T3, charge-sharing capacitor Cs forms capacitors with other
conductive layers, for example, C.sub.CSA is the capacitor formed
between the first pixel electrode 102 and Cs, and C.sub.CSB is the
capacitor formed between the common electrode V.sub.COM and Cs.
[0007] As to the main display area which corresponds to the first
pixel electrode 102, the switch T1 is electrically connected
between data line DL1 and the first pixel electrode 102. The switch
T1 is also electrically connected to scan line SL1, and a signal
passing through scan line SL1 controls the switch T1 to turn
on/off. The storage capacitor C.sub.ST1 is electrically connected
between the first pixel electrode 102 and the common electrode
V.sub.COM. When the switch T1 turns on, a data signal of data line
DL1 is transmitted through the switch T1 to the first electrode
102, so that the storage capacitor C.sub.ST1 is charged to have
corresponding voltage.
[0008] As to the secondary display area which is corresponding to
the second pixel electrode 104, the switch T2 is electrically
connected between data line DL1 and the second pixel electrode 104.
The switch T2 is also electrically connected to scan line SL1, a
signal passing through scan line SL1 controls the switch T2 to turn
on/off. The storage capacitor C.sub.ST2 is electrically connected
between the second pixel electrode 104 and the common electrode
V.sub.COM. When the switch T2 turns on, a data signal of data line
DL1 is transmitted through the switch T2 to the second electrode
104, so that the storage capacitor C.sub.ST2 is charged to have
corresponding voltage. To solve the issue of color washout of the
LCD panel, charge sharing is performed. After the first pixel
electrode 102 and the second pixel electrode 104 are charged by the
signal from scan line SL1, in next time sequence, the switch T3
turns on by the signal inputted from scan line T3, so as a part of
the voltage of the second pixel electrode 104 is shared to the
capacitor C.sub.CSB and the other part of the voltage of the second
pixel electrode 104 is shared to the capacitor C.sub.CSA through
the switch T3. It results in charge sharing between the first pixel
electrode 102 and the second pixel electrode 104 by the
charge-sharing capacitor Cs, the voltage of the first pixel
electrode 102 increases and that of the second pixel electrode 104
decreases. Therefore, the voltages of the first pixel electrode 102
and the second pixel electrode 104 are different. It causes the
tilting angle of liquid crystals corresponding to the first pixel
electrode 102 and the second pixel electrode 104 are different
within the same pixel 100, so as the brightness within the same
pixel 100 can be optimized since the transmittance within the same
pixel 100 can be different, thus the issue of color washout can be
solved.
[0009] However, continually referring FIG. 1 and FIG. 2, as
illustrated in dot lines area of FIG. 1, in the path of the second
connecting line 108 connecting to the second pixel electrode 104,
part of the path is underpass the first pixel electrode 102. This
overlapping structure of the second connecting line 108 and the
first pixel electrode 102 in vertical direction will generate an
extra coupling capacitance Cx as illustrated in dot lines area of
FIG. 2. When the coupling capacitance Cx is generated between the
first pixel electrode 102 and the second pixel electrode 104,
charge sharing will be weaken. Thus the effects of the voltage
increase of the first pixel electrode 102 and the voltage decrease
of the second pixel electrode 104 are diminished. Therefore, to
increase the voltage difference between the first pixel electrode
102 and the second pixel electrode 104 becomes difficult. In order
to maintain the voltage difference between the first pixel
electrode 102 and the second pixel electrode 104 to solve the color
washout issue, further increase the capacitance of the
charge-sharing capacitor Cs to release more electric charge from
the second pixel electrode 104 and lower the voltage of the second
pixel electrode 104 is generally performed. However, the efficiency
of the LCD panel is decreased to maintain the voltage difference
between the first pixel electrode 102 and the second pixel
electrode 104 in this way.
SUMMARY
[0010] The present disclosure relates to an array substrate of a
display panel, which has a whole new design of pixel layout. The
coupling capacitance Cx of the pixel array substrate in the present
disclosure is much less than that of prior arts, the difficulty of
increasing the voltage difference between the first pixel electrode
and the second pixel electrode is obviously improved. Therefore, LC
efficiency and the open ratio of the pixel array substrate of the
present disclosure are improved under the premise of solving the
issue of color washout.
[0011] The present disclosure, in one aspect, relates to a pixel
array substrate includes a plurality of data lines, a plurality of
scan lines, and a plurality of pixels. The plurality of scan lines
is crossed to the plurality of data lines to define a plurality of
pixel areas. The plurality of pixels is respectively disposed in
the plurality of pixel areas, each pixel includes a first pixel
electrode, a first connecting line, a second pixel electrode, and a
second connecting line. The first pixel electrode is electrically
connected to corresponding one of the data lines and one of the
scan lines, and the first pixel electrode has a first slit. The
first pixel electrode is electrically connected to corresponding
data line through the first connecting line. The second pixel
electrode is electrically connected to corresponding data line and
scan line. The second pixel electrode is electrically connected to
corresponding data line through the second connecting line, wherein
at least a part of the second connecting line is exposed by the
first slit of the first pixel electrode.
[0012] In one embodiment of the present disclosure, the first slit
is an open slit.
[0013] In another embodiment of the present disclosure, the first
slit is a closed slit.
[0014] In one embodiment of the present disclosure, the first slit
is substantially parallel to the plurality of data lines.
[0015] In one embodiment of the present disclosure, the first
connecting line and the second connecting line are electrically
connected to the same data line.
[0016] In another embodiment of the present disclosure, the first
connecting line and the second connecting line are electrically
connected to different data lines.
[0017] In one embodiment of the present disclosure, the first pixel
electrode includes a first sub-pixel electrode and a second
sub-pixel electrode, and the first slit is substantially positioned
between the first sub-pixel electrode and the second sub-pixel
electrode.
[0018] In one embodiment of the present disclosure, the first
sub-pixel electrode and the second sub-pixel electrode are mirror
symmetry structures with respect to the first slit.
[0019] In one embodiment of the present disclosure, the first
sub-pixel electrode includes a first main electrode, a second main
electrode, a plurality of first branch electrodes, a plurality of
second branch electrodes, a plurality of third branch electrodes,
and a plurality of fourth branch electrodes. The first main
electrode and the second main electrode are electrically connected
and are substantially orthogonally arranged to define a first area,
a second area, a third area and a fourth area. The plurality of
first branch electrodes is disposed in the first area. The
plurality of second branch electrodes is disposed in the second
area. The plurality of third branch electrodes is disposed in the
third area. The plurality of fourth branch electrodes is disposed
in the fourth area. The plurality of first branch electrodes, the
plurality of second branch electrodes, the plurality of third
branch electrodes and the plurality of fourth branch electrodes are
electrically connected with one of the first main electrode and the
second main electrode, the first branch electrodes are arranged
parallel to each other, the second branch electrodes are arranged
parallel to each other, the third branch electrodes are arranged
parallel to each other and the fourth branch electrodes are
arranged parallel to each other, and the plurality of first branch
electrodes, the plurality of second branch electrodes, the
plurality of third branch electrodes and the plurality of fourth
branch electrodes respectively extend to different directions from
the first main electrode or the second main electrode, the first
sub-pixel electrode and the second sub-pixel electrode are mirror
symmetry structures with respect to the first slit.
[0020] In one embodiment of the present disclosure, the first main
electrode is substantially parallel to the first slit, and the
distance between the first main electrode and the first slit is
greater than that of the first main electrode and the data line
which is adjacent to the first main electrode.
[0021] In one embodiment of the present disclosure, each pixel
further includes a third pixel electrode and a third connecting
line. The third pixel electrode is electrically connected to
corresponding data line and scan line, and the third pixel
electrode has a second slit. The third pixel electrode is
electrically connected to corresponding data line through the third
connecting line, wherein at least a part of the second connecting
line is exposed by the first slit of the first pixel electrode and
the second slit of the third pixel electrode.
[0022] In one embodiment of the present disclosure, the third
connecting line is disposed on an edge of the first sub-pixel
electrode or the second sub-pixel electrode.
[0023] In one embodiment of the present disclosure, the third pixel
electrode includes a third sub-pixel electrode and a fourth
sub-pixel electrode, the second slit is substantially positioned
between the third sub-pixel electrode and the fourth sub-pixel
electrode, and the second slit is substantially positioned in the
extending line of the first slit.
[0024] In one embodiment of the present disclosure, the first slit
and the second slit are substantially parallel to the plurality of
data lines, the first sub-pixel electrode and the second sub-pixel
electrode are mirror symmetry structures with respect to the first
slit, the third sub-pixel electrode and the fourth sub-pixel
electrode are mirror symmetry structures with respect to the second
slit.
[0025] In one embodiment of the present disclosure, wherein the
third sub-pixel electrode and the fourth sub-pixel electrode
respectively include a first main electrode, a second main
electrode, a plurality of first branch electrodes, a plurality of
second branch electrodes, a plurality of third branch electrodes,
and a plurality of fourth branch electrodes. The first main
electrode and the second main electrode are electrically connected
and are substantially orthogonally arranged to define a first area,
a second area, a third area and a fourth area. The plurality of
first branch electrodes is disposed in the first area. The
plurality of second branch electrodes is disposed in the second
area. The plurality of third branch electrodes is disposed in the
third area. The plurality of fourth branch electrodes is disposed
in the fourth area, wherein the plurality of first branch
electrodes, the plurality of second branch electrodes, the
plurality of third branch electrodes and the plurality of fourth
branch electrodes are electrically connected with one of the first
main electrode and the second main electrode, the first branch
electrodes are arranged parallel to each other, the second branch
electrodes are arranged parallel to each other, the third branch
electrodes are arranged parallel to each other and the fourth
branch electrodes are arranged parallel to each other, and the
plurality of first branch electrodes, the plurality of second
branch electrodes, the plurality of third branch electrodes and the
plurality of fourth branch electrodes respectively extend to
different directions from the first main electrode or the second
main electrode, the first sub-pixel electrode and the second
sub-pixel electrode are mirror symmetry structures with respect to
the first slit, the third sub-pixel electrode and the fourth
sub-pixel electrode are mirror symmetry structures with respect to
the second slit.
[0026] In one embodiment of the present disclosure, the first main
electrode of the first sub-pixel electrode is substantially
parallel to the first slit, and the distance between the first main
electrode and the first slit is greater than that of the first main
electrode of the first sub-pixel electrode and the data line which
is adjacent to the first main electrode of the first sub-pixel
electrode, the first main electrode of the third sub-pixel
electrode is substantially parallel to the second slit, and the
distance between the first main electrode of the third sub-pixel
electrode and the second slit are greater than that of the first
main electrode of the third sub-pixel electrode and the data line
which is adjacent to the first main electrode of the third
sub-pixel electrode.
[0027] In one embodiment of the present disclosure, the pixel array
substrate further includes a plurality of first switches and a
plurality of second switches. The plurality of first switches
respectively disposed on a side of each pixel area, a first end of
each first switch is electrically connected to respective first
pixel electrode through respective first connecting line, a second
end of each first switch is electrically connected to corresponding
data line and scan line. The plurality of second switches
respectively disposed on the side of each pixel area and
electrically connected to corresponding data line and scan line,
each second switch is electrically connected to corresponding
second pixel electrode through corresponding second connecting
line.
[0028] In one embodiment of the present disclosure, each one of the
plurality of pixels further includes a charge-sharing capacitor and
a third switch. A first end of the charge-sharing capacitor is
electrically connected to the first pixel electrode, a second end
of the charge-sharing capacitor is electrically connected to the
second pixel electrode through the third switch.
[0029] The present disclosure, in another aspect, relates to a
pixel array substrate includes a plurality of data lines, a
plurality of scan lines, and a plurality of pixels. Each pixel
includes a first pixel electrode which is electrically connected to
corresponding data line and scan line, the first pixel electrode
includes a first sub-pixel electrode and a second sub-pixel
electrode. The second sub-pixel electrode electrically connected to
the first sub-pixel electrode, wherein the first sub-pixel
electrode and the second sub-pixel electrode are mirror symmetry
structures with respect to a symmetry axis.
[0030] In one embodiment of the present disclosure, the symmetry
axis is substantially parallel to the plurality of data lines.
[0031] In one embodiment of the present disclosure, the distance
between the symmetry axis and one adjacent data line is the same as
that between the symmetry axis and the other adjacent data
line.
[0032] In one embodiment of the present disclosure, the first
sub-pixel electrode includes a first main electrode, a second main
electrode, a plurality of first branch electrodes, a plurality of
second branch electrodes, a plurality of third branch electrodes
and a plurality of fourth branch electrodes. The first main
electrode and the second main electrode are electrically connected
and are substantially orthogonally arranged to define a first area,
a second area, a third area and a fourth area. The plurality of
first branch electrodes is disposed in the first area. The
plurality of second branch electrodes is disposed in the second
area. The plurality of third branch electrodes is disposed in the
third area. The plurality of fourth branch electrodes is disposed
in the fourth area, wherein the plurality of first branch
electrodes, the plurality of second branch electrodes, the
plurality of third branch electrodes and the plurality of fourth
branch electrodes are electrically connected with one of the first
main electrode and the second main electrode, the first branch
electrodes are arranged parallel to each other, the second branch
electrodes are arranged parallel to each other, the third branch
electrodes are arranged parallel to each other and the fourth
branch electrodes are arranged parallel to each other, and the
plurality of first branch electrodes, the plurality of second
branch electrodes, the plurality of third branch electrodes and the
plurality of fourth branch electrodes are respectively extend to
different directions from the first main electrode or the second
main electrode.
[0033] In one embodiment of the present disclosure, the first main
electrode is substantially parallel to the symmetry axis, and the
distance between the first main electrode and the symmetry axis is
greater than that between the first main electrode and the data
line which is adjacent to the first main electrode.
[0034] In one embodiment of the present disclosure, the pixel array
substrate further includes a second pixel electrode and a second
connecting line. The second pixel electrode is electrically
connected to corresponding data line and scan line. The second
pixel electrode is electrically connected to corresponding data
line through the second connecting line, wherein the second
connecting line is positioned along the direction of the symmetry
axis.
[0035] In one embodiment of the present disclosure, the first pixel
electrode and the second pixel electrode are electrically connected
to the same data line.
[0036] In another embodiment of the present disclosure, the first
pixel electrode and the second pixel electrode are respectively
electrically connected to different data lines.
[0037] In one embodiment of the present disclosure, the first pixel
electrode has a first slit which is along the direction of the
symmetry axis to expose a part of the second connecting line.
[0038] In one embodiment of the present disclosure, the pixel array
substrate further includes a third pixel electrode and a third
sub-pixel electrode. The third pixel electrode is disposed between
the first pixel electrode and the second pixel electrode, and
electrically connected to corresponding data line and scan line,
the third pixel electrode includes a third sub-pixel electrode and
a fourth sub-pixel electrode. The fourth sub-pixel electrode
electrically connected to the third sub-pixel electrode, wherein
the third sub-pixel electrode and the fourth sub-pixel electrode
are mirror symmetry structures with respect to the symmetry
axis.
[0039] In one embodiment of the present disclosure, the third
sub-pixel electrode and the fourth sub-pixel electrode respectively
includes a first main electrode, a second main electrode, a
plurality of first branch electrodes, a plurality of second branch
electrodes, a plurality of third branch electrodes and a plurality
of fourth branch electrodes. The first main electrode and the
second main electrode are electrically connected and are
substantially orthogonally arranged to define a first area, a
second area, a third area and a fourth area. The plurality of first
branch electrodes is disposed in the first area. The plurality of
second branch electrodes is disposed in the second area. The
plurality of third branch electrodes is disposed in the third area.
The plurality of fourth branch electrodes is disposed in the fourth
area, wherein the plurality of first branch electrodes, the
plurality of second branch electrodes, the plurality of third
branch electrodes and the plurality of fourth branch electrodes are
electrically connected with one of the first main electrode and the
second main electrode, the first branch electrodes are arranged
parallel to each other, the second branch electrodes are arranged
parallel to each other, the third branch electrodes are arranged
parallel to each other and the fourth branch electrodes are
arranged parallel to each other, and the plurality of first branch
electrodes, the plurality of second branch electrodes, the
plurality of third branch electrodes and the plurality of fourth
branch electrodes respectively extend to different directions from
the first main electrode or the second main electrode.
[0040] In one embodiment of the present disclosure, the first main
electrode of the first sub-pixel electrode and the first main
electrode of the third sub-pixel electrode are substantially
parallel to the symmetry axis, and the distance between the first
main electrode and the symmetry axis is greater then that between
the first main electrode and adjacent data line.
[0041] In one embodiment of the present disclosure, the first pixel
electrode has a first slit which is along the direction of the
symmetry axis, and the third pixel electrode has a second slit
which is also along the direction of the symmetry axis to expose a
part of the second connecting line.
[0042] The present disclosure, in another aspect, relates to a LCD
panel, includes the pixel array substrate aforementioned, an
opposite substrate, and a liquid crystal layer. The opposite
substrate is disposed above the pixel array substrate. The liquid
crystal layer is disposed between the pixel array substrate and the
opposite substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0043] The disclosure may be more fully understood by reading the
following detailed description of the embodiment, with reference
made to the accompanying drawings as follows:
[0044] FIG. 1 illustrates a top-view of a part of the pixel layout
of the conventional array substrate;
[0045] FIG. 2 illustrates the equivalent circuit diagram of the
pixel layout of the array substrate illustrated in FIG. 1;
[0046] FIG. 3 illustrates a top-view of a part of one embodiment of
the pixel layout of the pixel array substrate of the present
disclosure;
[0047] FIG. 4 illustrates a top-view of a part of another
embodiment of the pixel layout of the pixel array substrate of the
present disclosure;
[0048] FIG. 5 illustrates a top-view of a part of another
embodiment of the pixel layout of the pixel array substrate of the
present disclosure;
[0049] FIG. 6 illustrates a top-view of a part of another
embodiment of the pixel layout of the pixel array substrate of the
present disclosure;
[0050] FIG. 7(A) to FIG. 7(B) illustrate the simulation of the
transmittance of the pixel array substrate of the present
disclosure;
[0051] FIG. 8 illustrates a top-view of a part of another
embodiment of the pixel layout of the pixel array substrate of the
present disclosure;
[0052] FIG. 9 illustrates a top-view of a part of another
embodiment of the pixel layout of the pixel array substrate of the
present disclosure;
[0053] FIG. 10 illustrates a top-view of a part of another
embodiment of the pixel layout of the pixel array substrate of the
present disclosure;
[0054] FIG. 11 illustrates a top-view of a part of another
embodiment of the pixel layout of the pixel array substrate of the
present disclosure;
[0055] FIG. 12 illustrates the equivalent circuit diagram of the
pixel layout of the pixel array substrate of the present disclosure
illustrated in FIG. 11; and
[0056] FIG. 13 illustrates a schematic diagram of the LCD panel
with the pixel array substrate of the present disclosure.
DETAILED DESCRIPTION
[0057] The present disclosure is described by the following
specific embodiments. Those with ordinary skill in the arts can
readily understand the other advantages and functions of the
present invention after reading the disclosure of this
specification. The present disclosure can also be implemented with
different embodiments. Various details described in this
specification can be modified based on different viewpoints and
applications without departing from the scope of the present
disclosure.
[0058] As used herein, the singular forms "a," "an" and "the"
include plural referents unless the context clearly dictates
otherwise. Therefore, reference to, for example, a data sequence
includes aspects having two or more such sequences, unless the
context clearly indicates otherwise.
[0059] Reference will now be made in detail to the embodiments of
the present disclosure, examples of which are illustrated in the
accompanying drawings. Wherever possible, the same reference
numbers are used in the drawings and the description to refer to
the same or like parts.
[0060] Referring FIG. 3, FIG. 3 illustrates a part of one
embodiment of the pixel array substrate of the present disclosure.
The pixel array substrate of this embodiment includes data lines,
scan lines and pixels. The scan lines are crossed to the data lines
to define pixel areas. The pixels are respectively disposed in the
pixel areas. As illustrated in FIG. 3, two adjacent scan lines SL1,
SL2 (the upper group of scan lines SL1, SL2 provides the scan
signals to the pixel illustrated in FIG. 3, and the lower group of
scan lines SL1, SL2 provides the scan signals to the pixel which is
not illustrated in FIG. 3) are crossed to two adjacent data lines
DL1, DL2. A pixel 300 is disposed in a pixel area which is defined
by two adjacent scan lines SL1 and two adjacent data lines DL1,
DL2. The pixel 300 includes a first pixel electrode 302, a first
connecting line 306, a second pixel electrode 304 and a second
connecting line 308. The first pixel electrode 302 is electrically
connected to data line DL1 through the first connecting line 306,
and the second pixel electrode 304 is electrically connected to
data line DL1 through the second connecting line 308. The area of
the first pixel electrode 302 and the second pixel electrode 304
may be different. In the present embodiment and the following
embodiments illustrated in FIG. 4 and FIG. 5, the area of the
second pixel electrode 304 is greater than that of the first pixel
electrode 302, however, the present disclosure is not limited
thereto. For example, the pattern of the first pixel electrode 302
and the second pixel electrode 304 are both fishbone patterns. In
the present embodiment, the first pixel electrode 302 and the
second pixel electrode 304 are simultaneously charged by inputting
a scan signal via scan line SL1 to turn on the first switch 310 and
the second switch 312 in the same time sequence, and the first
pixel electrode 302 and the second pixel electrode 304 are
simultaneously charged in the voltage of data line DL1. In next
time sequence, the first pixel electrode 302 and the second pixel
electrode 304 perform charge sharing, thus the voltage of the first
pixel electrode 302 is different from that of the second pixel
electrode 304. For example, the way of charge sharing may be that
pixel 300 further includes a third switch T3 and charge-sharing
capacitor Cs. One end of the charge-sharing capacitor Cs is
electrically connected to the first pixel electrode 302, and the
other end of the charge-sharing capacitor Cs is electrically
connected to the second pixel electrode 304 through the third
switch T3. The third switch T3 is turned on by a signal passing
through scan line SL2, and the electric charges flow from the
second pixel electrode 304 to the capacitor C.sub.CSA and
C.sub.CSB. Therefore the voltage of the first pixel electrode 302
is increased and the voltage of the second pixel electrode 304 is
decreased. However, the present disclosure is not limited thereto.
It should be noticed that, the first pixel electrode 302 has a
first slit 314, and the second connecting line 308 of the second
pixel electrode 304, which electrically connects the second pixel
electrode 304 and its corresponding data line DL1 and scan line
SL1, is exposed by the first slit 314. Therefore, the overlapping
structure of the second connecting line 308 and the first pixel
electrode 202 in vertical direction is much less than that of the
conventional structure. Accordingly, the coupling capacitance Cx
induced by the overlapping structure is minimized. As illustrated
in FIG. 3 and FIG. 4, the first slit 314 can be an open slit, but
not limited to it. As illustrated in FIG. 5, the first slit 314 can
be a closed slit, but not limited to it either. When charge sharing
is performed to decrease the voltage of the second pixel electrode
304 and increase the voltage of the first pixel electrode 302
through the charge-sharing capacitor, the difficulty of increasing
the voltage difference between the first pixel electrode and the
second pixel electrode is improved. Since the coupling capacitance
Cx in the present embodiment is much less than that of conventional
arts, increasing the voltage difference between the first pixel
electrode and the second pixel electrode is much easier.
Accordingly, it is not necessary to further increase the
capacitance of the charge-sharing capacitor Cs to decrease the
voltage of the second pixel electrode 304. Therefore, the voltage
of the first pixel electrode 302 of the present embodiment is
higher than that of conventional arts, the voltage of the second
pixel electrode 304 of the present embodiment is also higher than
that of conventional arts, and the voltage difference (between the
first pixel electrode 302 and the second pixel electrode 304) of
the present embodiment is substantially equal to that of
conventional arts. Accordingly, the present embodiment of the
present disclosure is not only capable to improve the issue of
color washout, but also enhance the LC efficiency of the LCD
panel.
[0061] Referring to FIG. 6, FIG. 6 is a part of another embodiment
of the pixel array substrate of the present disclosure. The pixel
array substrate of this embodiment includes data lines, scan lines
and pixels. The scan lines are crossed to the data lines to define
pixel areas. The pixels are respectively disposed in the pixel
areas. That is, each pixel is respectively disposed in each pixel
area. As illustrated in FIG. 6, two adjacent scan lines SL1, SL2
(the upper group of scan line SL1, SL2 provides the scan signals to
the pixel illustrated in FIG. 6, and the lower group of scan line
SL1, SL2 provides the scan signals to the pixel which is not
illustrated) are crossed to two adjacent data line DL1, DL2. A
pixel 600 is disposed in a pixel area which is defined by two
adjacent scan lines SL1 and two adjacent data lines DL1, DL2. The
pixel 600 includes a first pixel electrode 602, a first connecting
line 306, a second pixel electrode 304, and a second connecting
line 308. The area of the first pixel electrode 302 and the second
pixel electrode 304 may be different. In the present embodiment,
the area of the second pixel electrode 304 is greater than that of
the first pixel electrode 602, however, the present disclosure is
not limited thereto. The pattern of the second pixel electrode 304,
for example, is the same as the aforementioned second pixel
electrode 304 illustrated in FIGS. 3-5. The first pixel electrode
602 is electrically connected to data line DL1 and scan line SL1
through the first connecting line 306 and the first switch 310
respectively. The second pixel electrode 304 is electrically
connected to data line DL1 and scan line SL1 through the second
connecting line 308 and the second switch 312 respectively. The
first pixel electrode 602 has the first slit 314, and the second
connecting line 308 of the second pixel electrode 304, which
electrically connects the second pixel electrode 304 and its
corresponding data line DL1 and scan line SL1, is exposed by the
first slit 314. It should be noticed that the first pixel electrode
602 includes the first sub-pixel electrode 602a and the second
sub-pixel electrode 602b. The first slit 314 is between the first
sub-pixel electrode 602a and the second sub-pixel electrode 602b.
The first sub-pixel electrode 602a and the second sub-pixel
electrode 602b are mirror symmetry structures with respect to the
first slit 314. As illustrated in FIG. 6, the first sub-pixel
electrode 602a includes a first main electrode 602aT1, a second
main electrode 602aT2, first branch electrodes 602aS1, second
branch electrodes 602aS2, third branch electrodes 602aS3 and fourth
branch electrodes 602aS4. The first main electrode 602aT1 and the
second main electrode 602aT2 are electrically connected and are
substantially orthogonally arranged to define a first area, a
second area, a third area and a fourth area. The first branch
electrodes 602aS1, second branch electrodes 602aS2, third branch
electrodes 602aS3 and fourth branch electrodes 602aS4 are
respectively disposed in the first area, the second area, the third
area and the fourth area. The first branch electrodes 602aS1,
second branch electrodes 602aS2, third branch electrodes 602aS3 and
fourth branch electrodes 602aS4 are electrically connected with one
of the first main electrode 602aT1 and the second main electrode
602aT2. The first branch electrodes 602aS1 are arranged parallel to
each other, the second branch electrodes 602aS2 are arranged
parallel to each other, the third branch electrodes 602aS3 are
arranged parallel to each other and the fourth branch electrodes
602aS4 are arranged parallel to each other. The first branch
electrodes 602aS1, the second branch electrodes 602aS2, the third
branch electrodes 602aS3 and the fourth branch electrodes 602aS4
are respectively extend to different directions from the first main
electrode 602aT1 or the second main electrode 602aT2. To be more
specific, each first branch electrode 602aS1 is electrically
connected to the first main electrode 602aT1 or the second main
electrode 602aT2, and each first branch electrode 602aS1 are
arranged in parallel and extends outward along the direction S1.
And so on the second branch electrodes 602aS2, the third branch
electrodes 602aS3, and the fourth branch electrodes 602aS4 are also
arranged similarly to the first branch electrodes 602aS1. The
difference among them is only their respective extending
directions. In other word, each second branch electrode 602aS2 are
arranged in parallel and extends outward along the direction S2;
each third branch electrode 602aS3 are arranged in parallel and
extends outward along the direction S3; and each fourth branch
electrode 602aS4 are arranged in parallel and extends outward along
the direction S4.
[0062] In comparison with the pattern of the first pixel electrode
602 illustrated in FIG. 6 to that of the first pixel electrode 302
illustrated in FIG. 3, the first pixel electrode 602 illustrated in
FIG. 6 has more main electrodes (such as the first main electrode
602aT1 and the second main electrode 602aT2) than that of the first
pixel electrode 302 illustrated in FIG. 3. Accordingly, stronger
electric field is provided to each branch electrode (such as the
first branch electrodes 602aS1, the second branch electrodes
602aS2, the third branch electrodes 602aS3, and the fourth branch
electrodes 602aS4 of the first sub-pixel electrode 602a), thus
better control of the tilting angle of the LC molecules which are
corresponding to the first pixel electrode 602 is also provided
than that of the first pixel electrode 302 illustrated in FIG.
3.
[0063] Referring to FIG. 7, the main electrodes offer stronger
electric field than the branch electrodes do. However, the electric
field offered by the main electrodes does not possess specific
direction as that offered by the branch electrodes. Therefore, the
LC molecules corresponding to the main electrodes do not tilt in
one specific direction, and the transmittance corresponding to the
main electrodes is substantially zero. Accordingly, the positions,
which are corresponded to the main electrodes of the LCD panel,
usually display black lines.
[0064] FIG. 7(A) illustrates the transmittance simulation of the
first pixel electrode 302 (as aforementioned embodiments in FIGS.
3-5). The slit 314 can be regarded as the edge of the domain of the
pixel electrode 302. The electric field at the edge of the domain
of the pixel electrode 302 will conflict with that in adjacent data
line. Therefore, the controlling of the electric field of the whole
pixel electrode is weak. Accordingly, the black lines in vertical
direction could randomly appear in any region of the whole pixel
electrode. In contrast, FIG. 7(B) illustrates the transmittance
simulation of the first pixel electrode having the main electrodes
(as the first sub-pixel electrode 602a and the second sub-pixel
electrode 602b in FIG. 6). Because the main electrodes in vertical
direction improve the control of the electric field of the whole
pixel electrode, the LC molecules will tilt along the slits which
are between the branches of the sub-pixel electrode. The issue of
LC molecules tilting conflicts does not occur, hence the black
lines in vertical direction can be restricted in the positions
along a vertical direction which are corresponded to the main
electrodes. Therefore, the first sub-pixel electrode 602a and the
second sub-pixel electrode 602b (illustrated in FIG. 6) control the
positions of the black lines better than the pixel electrode 302
(illustrated in FIG. 3) do.
[0065] Referring to FIG. 6 again, the first main electrode 602aT1
is substantially parallel to the first slit 314, and the distance
between the first main electrode 602aT1 and the first slit 314 is
greater than that between the first main electrode 602aT1 and the
data line DL1 which is adjacent to the first main electrode 602aT1.
The first main electrode 602aT1 is substantially between data line
DL1 and the first slit 314. That is, the first main electrode
602aT1 is disposed at the edge of the pixel area. Therefore, the
black lines in vertical direction can be restricted at the edge of
the pixel area by the main electrodes in vertical direction.
Accordingly, the open ratio of the pixel is increased. In summary,
the embodiment illustrated in FIG. 6 of the present disclosure not
only minimizes the issue caused by the coupling capacitor Cx and
improves the LC efficiency of the LCD panel, but also improves the
open ratio of the pixel by restricting the black lines at the edge
of the pixel are.
[0066] Referring to FIG. 8, FIG. 8 illustrates a part of the pixel
array substrate of another embodiment of the present disclosure.
The connections between each element are similar to described
above, therefore the details are omitted here. It should be noticed
that the first connecting line 306 and the second connecting line
308 are respectively electrically connected to different data
lines. The first connecting line 306 is electrically connected to
data line DL1 through the first switch 310, the second connecting
line 308 is electrically connected to data line DL2 through the
second switch 312. Therefore, the first pixel electrode 602 and the
second pixel electrode 304 can be respectively charged with
different voltages by data line DL1 and date line DL2 in the same
time sequence. Specifically, in one time sequence, one scan signal
is transmitted by the same scan line SL1 and the first switch 310
and the second switch 312 are turned on, so that the first pixel
electrode 602 and the second pixel electrode 304 can be charged
with data line DL1 and data line DL2 respectively and possesses
different voltages.
[0067] Referring FIG. 9, FIG. 9 illustrates a part of the pixel
array substrate of another embodiment of the present disclosure.
The pixel array substrate of this embodiment includes data lines,
scan lines and pixels. The scan lines are crossed to the data lines
to define pixel areas. The pixels are respectively disposed in the
pixel areas. Each pixel is respectively disposed in each pixel
area. As illustrated in FIG. 9, two adjacent scan lines SL1, SL2
(the upper group of scan line SL1, SL2 provides the scan signals to
the pixel illustrated in FIG. 9, and the lower group of scan line
SL1, SL2 provides the scan signals to the pixel which is not
illustrated in FIG. 9) are crossed to two adjacent data lines DL1,
DL2. A pixel 900 is disposed in the pixel area which is defined by
two adjacent scan lines SL1 and two adjacent data lines DL1, DL2.
The pixel 900 includes a first pixel electrode 902, a first
connecting line 306, a second pixel electrode 304 and a second
connecting line 308. The first pixel electrode 902 is electrically
connected to data line DL1 and scan line SL1 through the first
connecting line 306 and the first switch 310 respectively, and the
second pixel electrode 304 is electrically connected to data line
DL1 and scan line SL1 through the second connecting line 308 and
the second switch 312 respectively. It should be noticed that, the
first pixel electrode 902 includes a first sub-pixel electrode 902a
and a second sub-pixel electrode 902b. The first sub-pixel
electrode 902a and the second sub-pixel electrode 902b are mirror
symmetry structures with respect to a symmetry axis 914. Two
adjacent data lines DL1, DL2 are also mirror symmetry structures
with respect to the symmetry axis 914. The distance between the
symmetry axis 914 and the data line DL1 may be substantially the
same as the distance between the symmetry axis 914 and the data
line DL2. In addition, the first pixel electrode 902 may include
the first sub-pixel electrode 902a and the second sub-pixel
electrode 902b (the same as that illustrated in FIG. 6), and the
pattern of the first sub-pixel electrode 902a and the second
sub-pixel electrode 902b also can be the same as that illustrated
in FIG. 6. Therefore, the details are omitted here. However, it
should be noticed that, the first pixel electrode 902 illustrated
in FIG. 9 does not have the first slit 314 as the first pixel
electrode 602 illustrated in FIG. 6. More specifically, the first
sub-pixel electrode 902a and the second sub-pixel electrode 902b of
the first pixel electrode 902 are not separated as the first
sub-pixel electrode 602a and the second sub-pixel electrode 602b of
the first pixel electrode 602 are separated by the first slit 314.
In contrast, the first sub-pixel electrode 902a and the second
sub-pixel electrode 902b are connected by some of their branch
electrodes. There are slits between those connected branch
electrodes to expose part of the second connecting line 308. As
shown in FIG. 9, the first main electrode of the present embodiment
can also be disposed at the edge of the pixel area to increase the
open ratio of the pixel. Besides, the overlapping of the second
connecting line 308 and the first pixel electrode 902 in vertical
direction is also less than that of conventional arts (as shown in
FIG. 1). It results in that the coupling capacitance Cx generated
by the overlapping of the second connecting line 308 and the first
pixel electrode 902 is reduced. Accordingly, the pixel array
substrate of the present embodiment does not only improve the open
ratio within each pixel on the pixel array substrate, but also
reduce the issue which is caused by the coupling capacitance Cx in
conventional arts. Therefore, the target of solving color washout
is achieved, and the LC efficiency of the LCD panel is also
improved.
[0068] Referring to FIG. 10, FIG. 10 illustrates a part of the
pixel array substrate of another embodiment of the present
disclosure. The connections of elements are similar to those
described in last paragraph; therefore the details are omitted
here. The only difference in the present embodiment is that the
first connecting line 306 and the second connecting line 308 are
electrically connected to different data lines. Specifically, the
first connecting line 306 is electrically connected to data line
DL1 through the first switch 310, and the second connecting line
308 is electrically connected to data line DL2 through the second
switch 312. Therefore, the first pixel electrode 902 and the second
pixel electrode 304 can be respectively charged with different
voltages by data line DL1 and date line DL2 in the same time
sequence. Specifically, in one time sequence, one scan signal is
transmitted by the same scan line SL1 and the first switch 310 and
the second switch 312 are turned on, so that the first pixel
electrode 902 and the second pixel electrode 304 can be charged
with data line DL1 and data line DL2 respectively and possesses
different voltages.
[0069] Referring to FIG. 11, FIG. 11 illustrates a part of the
pixel array substrate of another embodiment of the present
disclosure. The elements in FIG. 11 which are the same as those in
FIG. 6 are labeled the same. The connections between those elements
are also the same as aforementioned, and the details are omitted
here. It should be noticed that the pixel in FIG. 11 further
includes a third pixel electrode 1102, a fourth switch 1110 and a
third connecting line 1118. The third pixel electrode 1102 is
electrically connected to corresponding data line DL1 through the
third connecting line 1118 and the fourth switch 1110, and the
third pixel electrode 1102 has a second slit 1114. The third pixel
electrode 1102 can be disposed between the first pixel electrode
602 and the second pixel electrode 304. However, the present
disclosure is not limited thereto. The third connecting line 1118
may be disposed at the edge of the first pixel electrode 602 or the
second pixel electrode 304, but the present disclosure is still not
limited thereto. As long as the third connecting line 1118 is not
overlapped with the first pixel electrode 602 and the second pixel
electrode 304 in vertical direction, the coupling capacitance Cx is
not induced. Besides, as illustrated in FIG. 12 (FIG. 12
illustrates the equivalent circuit diagram of FIG. 11), the first
switch 310 is electrically connected between data line DL1 and the
first pixel electrode 602. The first switch 310 is also
electrically connected to scan line SL1, and is controlled by the
input signals from scan line SL1. The storage capacitor C.sub.ST1
is electrically connected between the first pixel electrode 602 and
the common electrode V.sub.COM. When the first switch 310 is turned
on, the data signal of data line DL1 is transmitted to the storage
capacitor C.sub.ST1 and the first pixel electrode 602 through the
first switch 310. The storage capacitor C.sub.ST1 and the first
pixel electrode 602 are charged to corresponding voltages according
to the data signals. The second switch 312 is electrically
connected between data line DL1 and the second pixel electrode 304.
The second switch 312 is also electrically connected to scan line
SL1, and is controlled by the input signals from scan line SL1. The
storage capacitor C.sub.ST2 is electrically connected between the
second pixel electrode 304 and the common electrode V.sub.COM. When
the second switch 312 is turned on, the data signal of data line
DL1 is transmitted to the storage capacitor C.sub.ST2 through the
second switch 310, so that the storage capacitor C.sub.ST2 is
charged to corresponding voltage according to the data signal. The
fourth switch 1110 is electrically connected between data line DL1
and the third pixel electrode 1102. The fourth switch 1110 is also
electrically connected to scan line SL1, and is controlled by the
input signals from scan line SL1. The storage capacitor C.sub.ST3
is electrically connected between the third pixel electrode 1102
and the common electrode V.sub.COM. When the fourth switch 1110 is
turned on, the data signal of data line DL1 is transmitted to the
storage capacitor C.sub.ST3 through the fourth switch 1110, so that
the storage capacitor C.sub.ST3 is charged to corresponding voltage
according to the data signal. Accordingly, the liquid crystal
capacitors C.sub.LC 1-3 and the storage capacitors C.sub.ST1-3 are
charged to their corresponding voltages in the same time. Further,
to solve the issue of color washout of LCD panels, charge sharing
is performed. That is, in next time sequence right after the signal
is transmitted by scan line SL1, the first switch 316 is turned on
by the signal which is transmitted by scan line SL2. One part of
the voltage of the second pixel electrode 304 is shared to the
capacitor C.sub.CSB and the other part of the voltage of the second
pixel electrode 304 is shared to the capacitor C.sub.CSA. In other
words, charge sharing is performed between the first pixel
electrode 602 and the second pixel electrode 304 through the
charge-sharing capacitor Cs so that the voltage of the first pixel
electrode 602 increases and the voltage of the second pixel
electrode 304 decreases. In the other hand, the third pixel
electrode 1102 is not relevant to the charge sharing but keeps its
original voltage. As a result, the first pixel electrode 602, the
second pixel electrode 304 and the third pixel electrode 1102
possesses different voltages, and the LC molecules of different
pixel areas (which are corresponded to the first pixel electrode
602, the second pixel electrode 304, and the third pixel electrode
1102 respectively) have different tilting angles. Accordingly,
different transmittances within one pixel are achieved, so as the
issue of color washout can be improved.
[0070] Referring to FIG. 11, the third pixel electrode 1102
includes a third sub-pixel electrode 1102a and a fourth sub-pixel
electrode 1102b. The second slit 1114 is substantially disposed
between the third sub-pixel electrode 1102a and the fourth
sub-pixel electrode 1102b, and the second slit 1114 is
substantially positioned along the extending line of the first slit
314. The third sub-pixel electrode 1102a and the fourth sub-pixel
electrode 1102b of the third pixel electrode 1102 are similar to
the first sub-pixel electrode 602a and the second sub-pixel
electrode 602b of the first pixel electrode. The third sub-pixel
electrode 1102a and the fourth sub-pixel electrode 1102b are mirror
symmetry structures with respect to the second slit 1114, and the
pattern of the third sub-pixel electrode 1102a may be the same as
that of the first sub-pixel electrode 602a, but not limited to it.
It should be noticed that, in the present embodiment, the second
connecting line 308 is exposed by both the first slit 314 of the
first pixel electrode 602 and the second slit 1114 of the third
pixel electrode 1102. Accordingly, the coupling capacitance Cx in
the present embodiment is much less than that of conventional arts,
the difficulty of increasing the voltage difference between the
first pixel electrode and the second pixel electrode is improved.
Since the coupling capacitance Cx in the present embodiment is much
less than that of conventional arts, increasing the voltage
difference between the first pixel electrode and the second pixel
electrode is much easier. Accordingly, it is not necessary to
further increase the capacitance of the charge-sharing capacitor
Cs. The present embodiment of the present disclosure is not only
capable to improve the issue of color washout, but also enhance the
LC efficiency of the LCD panel to approximately 12.45%. As
aforementioned, the locations of the black lines can be also
controlled and restricted at the edge of the pixel area by special
pattern design of pixel electrodes (602a, 602b, 1102a, and 1102b).
Therefore, the open ratio of the pixel can be further increased. In
another embodiment of the present disclosure, the structures of the
first sub-pixel electrode 602a, the second sub-pixel electrode
602b, the third sub-pixel electrode 1102a and the fourth sub-pixel
electrode 1102b can be designed as the structures of the first
sub-pixel electrode 902a and the second sub-pixel electrode 902b.
That is, the first sub-pixel electrode 602a and the third sub-pixel
electrode 1102a are designed as the first sub-pixel electrode 902a,
and the second sub-pixel electrode 602b and the fourth sub-pixel
electrode 1102b are designed as the second sub-pixel electrode 902b
so that the first sub-pixel electrode 602a and the second sub-pixel
electrode 602b are mirror symmetry structures with respect to the
symmetry axis 914, and the third sub-pixel electrode 1102a and the
fourth sub-pixel electrode 1102b are also mirror symmetry
structures with respect to the symmetry axis 914. Accordingly, the
LC efficiency and the open ratio of the pixel array substrate of
the present embodiment are also improved under the premise of
solving the issue of color washout.
[0071] Referring to FIG. 13, FIG. 13 illustrates the LCD panel 1300
of the present disclosure. The LCD panel 1300 includes a pixel
array substrate 1302, an opposite substrate 1304 and a liquid
crystal layer 1306. The pixel array substrate 1302 can be any one
of aforementioned embodiments of pixel array substrate of the
present disclosure. The opposite substrate 1304 is disposed on the
pixel array substrate 1302, and the liquid crystal layer 1306 is
disposed between the pixel array substrate 1302 and the opposite
substrate 1304. According to the structure of LCD panel 1300,
different opposite substrate 1304 can be correspondingly chosen to
cope with the LCD panel 1300. The material of the liquid crystal
layer 1306 can be chosen the liquid crystals with an adequate
dielectric anisotropy (.DELTA..di-elect cons.), and a birefringence
(.DELTA.n). The birefringence (.DELTA.n) of the liquid crystals can
also be coped with an adequate cell gap of the liquid crystal layer
1306 to achieve the predetermined transmittance. The opposite
substrate 1304 can optionally further includes a color filter. The
opposite substrate 1304 can also be called a color filter
substrate.
[0072] It should be noticed that the pixel array substrate of the
present disclosure has a whole new design of pixel layout.
Therefore, the coupling capacitance Cx of the pixel array substrate
in the present disclosure is much less than that of prior arts, the
difficulty of increasing the voltage difference between the first
pixel electrode and the second pixel electrode is obviously
improved. Accordingly, LC efficiency and the open ratio of the
pixel array substrate of the present disclosure are also improved
under the premise of solving the issue of color washout.
[0073] Although the present disclosure has been described in
considerable detail with reference to certain embodiments thereof,
other embodiments are possible. Therefore, the spirit and scope of
the appended claims should not be limited to the description of the
embodiments contained herein.
[0074] It will be apparent to those ordinarily skilled in the art
that various modifications and variations may be made to the
structure of the present disclosure without departing from the
scope or spirit of the disclosure. In view of the foregoing, it is
intended that the present disclosure cover modifications and
variations thereof provided they fall within the scope of the
following claims.
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