U.S. patent application number 14/983049 was filed with the patent office on 2017-03-16 for electronic package and fabrication method thereof.
The applicant listed for this patent is Siliconware Precision Industries Co., Ltd.. Invention is credited to Fu-Tang Huang, Meng-Tsung Lee.
Application Number | 20170077047 14/983049 |
Document ID | / |
Family ID | 58227345 |
Filed Date | 2017-03-16 |
United States Patent
Application |
20170077047 |
Kind Code |
A1 |
Lee; Meng-Tsung ; et
al. |
March 16, 2017 |
ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
Abstract
An electronic device package and manufacturing method are
provided, including steps of: providing a carrier having at least
an electronic element and at least a package block disposed
thereon, wherein the package block has a plurality of conductive
posts bonded to the carrier; forming an encapsulant on the carrier
for encapsulating the electronic element and the package block; and
removing the carrier so as to expose the electronic element and the
conductive posts from a surface of the encapsulant. As such, the
invention dispenses with formation of through holes in the
encapsulant for forming the conductive posts as in the prior art,
thereby saving the fabrication cost.
Inventors: |
Lee; Meng-Tsung; (Taichung,
TW) ; Huang; Fu-Tang; (Taichung, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Siliconware Precision Industries Co., Ltd. |
Taichung |
|
TW |
|
|
Family ID: |
58227345 |
Appl. No.: |
14/983049 |
Filed: |
December 29, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/73265
20130101; H01L 24/20 20130101; H01L 2924/00012 20130101; H01L
2224/48227 20130101; H01L 2224/48227 20130101; H01L 2224/32225
20130101; H01L 2224/73265 20130101; H01L 23/31 20130101; H01L
2924/00 20130101; H01L 23/3128 20130101; H01L 25/50 20130101; H01L
2224/04105 20130101; H01L 21/561 20130101; H01L 2924/15311
20130101; H01L 2224/12105 20130101; H01L 23/552 20130101; H01L
2924/18162 20130101; H01L 2924/00014 20130101; H01L 2224/32225
20130101; H01L 2224/73265 20130101; H01L 24/19 20130101; H01L
2224/48091 20130101; H01L 21/56 20130101; H01L 2225/1041 20130101;
H01L 25/105 20130101; H01L 2224/24137 20130101; H01L 21/568
20130101; H01L 2924/15311 20130101; H01L 2224/32225 20130101; H01L
2924/19041 20130101; H01L 24/96 20130101; H01L 2224/16227 20130101;
H01L 2924/19042 20130101; H01L 2924/19043 20130101; H01L 2225/1035
20130101; H01L 2224/48227 20130101; H01L 2224/48091 20130101; H01L
2224/73267 20130101; H01L 2225/1058 20130101 |
International
Class: |
H01L 23/60 20060101
H01L023/60; H01L 21/56 20060101 H01L021/56; H01L 23/31 20060101
H01L023/31 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 11, 2015 |
TW |
104130064 |
Claims
1. An electronic package, comprising: an encapsulant having a first
surface and a second surface opposite to the first surface; at
least an electronic element embedded in the encapsulant and exposed
from the first surface of the encapsulant; and at least a package
block embedded in the encapsulant and having at least one
conductive post exposed from the first surface of the
encapsulant.
2. The electronic package of claim 1, wherein the encapsulant and
the package block are made of the same or different materials.
3. The electronic package of claim 1, wherein the electronic
element is further exposed from the second surface of the
encapsulant.
4. The electronic package of claim 1, wherein a shielding layer is
formed on the electronic element.
5. The electronic package of claim 4, wherein the shielding layer
is exposed from the second surface of the encapsulant.
6. The electronic package of claim 1, wherein the conductive post
is further exposed from the second surface of the encapsulant.
7. The electronic package of claim 6, further comprising a circuit
structure formed on the second surface of the encapsulant and
electrically connected to the conductive posts.
8. The electronic package of claim 1, further comprising a circuit
structure formed on the first surface of the encapsulant and
electrically connected to the electronic element and the conductive
post.
9. A method for fabricating an electronic package, comprising the
steps of: providing a carrier having at least an electronic element
and at least a package block disposed thereon, wherein the package
block has at least one conductive post bonded to the carrier;
forming an encapsulant on the carrier for encapsulating the
electronic element and the package block, wherein the encapsulant
has a first surface and a second surface opposite to the first
surface; and removing the carrier so as to expose the electronic
element and the conductive post from the first surface of the
encapsulant.
10. The method of claim 9, wherein fabricating the package block
comprises: providing a metal board having at least one conductive
post thereon; forming an encapsulant on the metal board to
encapsulate the conductive post; and removing the metal board,
thereby forming the package block having the conductive post
exposed from a surface thereof.
11. The method of claim 9, wherein the encapsulant is formed by
molding or lamination.
12. The method of claim 9, wherein the encapsulant and the package
block are made of the same or different materials.
13. The method of claim 9, wherein the electronic element is
further exposed from the second surface of the encapsulant.
14. The method of claim 9, wherein a shielding layer is formed on
the electronic element.
15. The method of claim 14, wherein the shielding layer is exposed
from the second surface of the encapsulant.
16. The method of claim 9, wherein the conductive post is further
exposed from the second surface of the encapsulant.
17. The method of claim 16, further comprising forming on the
second surface of the encapsulant a circuit structure electrically
connected to the conductive post.
18. The method of claim 9, further comprising forming on the first
surface of the encapsulant a circuit structure electrically
connected to the electronic element and the conductive post.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to packaging processes, and
more particularly, to an electronic package having an electronic
element embedded therein and a fabrication method thereof.
[0003] 2. Description of Related Art
[0004] Along with the progress of semiconductor packaging
technologies, various package types have been developed for
semiconductor devices. To improve electrical performance and save
space, a plurality of packages can be stacked to form a package on
package (PoP) structure, for example, a fan out package on package
(FO PoP) structure, thereby greatly increasing I/O count and
integrating integrated circuits having different functions. Such a
packaging method allows merging of heterogeneous technologies in a
system-in-package (SiP) so as to systematically integrate a
plurality of electronic elements having different functions, such
as a memory, a CPU (Central Processing Unit), a GPU (Graphics
Processing Unit), an image application processor and so on, and
therefore is applicable to various thin type electronic
products.
[0005] FIGS. 1A to 1F are schematic cross-sectional views showing a
method for fabricating a semiconductor package 1 of a PoP structure
according to the prior art.
[0006] Referring to FIG. 1A, a semiconductor element 10 such as a
chip is disposed on a release layer 110 of a first carrier 11, and
then an encapsulant 13 is formed on the release layer 110 to
encapsulate the semiconductor element 10.
[0007] Referring to FIG. 1B, a second carrier 12 having a copper
foil 120 is disposed on the encapsulant 13.
[0008] Referring to FIG. 1C, the first carrier 11 and the release
layer 110 are removed to expose the electronic element 10 and the
encapsulant 13.
[0009] Referring to FIG. 1D, a plurality of through holes 130 are
formed by laser drilling in the encapsulant 13 around a periphery
of the electronic element 10.
[0010] Referring to FIG. 1E, a conductive material is filled in the
through holes 130 to form a plurality of conductive posts 14.
Further, a plurality of redistribution layers (RDLs) 15 are formed
on the encapsulant 13 and electrically connected to the conductive
posts 14 and the electronic element 10.
[0011] Referring to FIG. 1F, the second carrier 12 is removed and a
patterning process is performed on the copper foil 120 to form a
circuit structure 16. Then, a singulation process is performed to
obtain an electronic package 1.
[0012] However, the laser drilling process for forming the through
holes 130 can easily destroy the copper foil 120 and consequently
adversely affect the quality of the circuit structure 16. Further,
the laser drilling process is quite slow and time-consuming,
especially when the number of the through holes is large.
Furthermore, residue (generated from such as the encapsulant 13 or
the copper material) easily accumulates on the bottom of the
through holes 130. Accordingly, a cleaning process is required
before filling of the conductive material in the through holes 130,
thus increasing the number of fabrication steps and the fabrication
cost.
[0013] In addition, if the through holes 130 have a high aspect
ratio, it will become difficult to completely remove the residue in
the through holes 130. As such, the electrical transmission
performance of the conductive posts 14 may be adversely affected by
the remaining residue.
[0014] Further, the laser drilling process results in uneven wall
surfaces of the through holes 130. As such, during a subsequent
electroplating process, the conductive material cannot be
effectively attached to the wall surfaces of the through holes 130
and easily delaminates therefrom, thus reducing the product
reliability of the semiconductor package 1.
[0015] Also, a laser beam used in the laser drilling process
produces a heat affected zone. That is, if the position of the
through holes 130 is close to the semiconductor element 10, high
heat from the laser beam will damage the semiconductor element 10.
Therefore, a certain distance must be kept between the conductive
posts 14 and the semiconductor element 10, thus hindering
miniaturization of the semiconductor package 1.
[0016] Therefore, there is a need to provide an electronic package
and a fabrication method thereof so as to overcome the
above-described drawbacks.
SUMMARY OF THE INVENTION
[0017] In view of the above-described drawbacks, the present
invention provides an electronic package, which comprises: an
encapsulant having a first surface and a second surface opposite to
the first surface; at least an electronic element embedded in the
encapsulant and exposed from the first surface of the encapsulant;
and at least a package block embedded in the encapsulant and having
at least one conductive post exposed from the first surface of the
encapsulant.
[0018] The present invention further provides a method for
fabricating an electronic package, which comprises the steps of:
providing a carrier having at least an electronic element and at
least a package block disposed thereon, wherein the package block
has at least one conductive post bonded to the carrier; forming an
encapsulant on the carrier for encapsulating the electronic element
and the package block, wherein the encapsulant has a first surface
and a second surface opposite to the first surface; and removing
the carrier so as to expose the electronic element and the
conductive posts from the first surface of the encapsulant.
[0019] In the above-described method, fabricating the package block
can comprise: providing a metal board having at least one
conductive post thereon; forming an encapsulant on the metal board
to encapsulate the conductive post; and removing the metal board,
thereby forming the package block having the conductive post
exposed from a surface thereof.
[0020] In the above-described method, the encapsulant can be formed
by molding or lamination.
[0021] In the above-described package and method, the encapsulant
and the package block can be made of the same or different
materials.
[0022] In the above-described package and method, the electronic
element can further be exposed from the second surface of the
encapsulant.
[0023] In the above-described package and method, a shielding layer
can be formed on the electronic element. For example, the shielding
layer is exposed from the second surface of the encapsulant.
[0024] In the above-described package and method, the conductive
post can further be exposed from the second surface of the
encapsulant. Furthermore, a circuit structure can be on formed on
the second surface of the encapsulant and electrically connected to
the conductive post.
[0025] In the above-described package and method, a circuit
structure can further be formed on the first surface of the
encapsulant and electrically connected to the electronic element
and the conductive post.
[0026] According to the present invention, the package block having
the conductive post are fabricated first and then the encapsulant
is formed to encapsulate the package block. As such, the present
invention dispenses with the conventional processes for forming the
conductive post in the encapsulant, for example, a laser drilling
process for forming through holes in the encapsulant, a cleaning
process for cleaning the through holes, and an electroplating
process for filling the through holes with a conductive material.
Therefore, the present invention saves the fabrication time,
improves the electrical transmission performance of the conductive
posts and avoids the conventional drawback of delamination of the
conductive posts from uneven wall surfaces of the through holes,
thereby improving the reliability of the electronic package.
[0027] Further, by dispensing with the laser drilling process, the
present invention avoids formation of a heat affected zone and
hence allows the conductive posts or the package block to be
positioned close to the electronic element according to the
practical need. Therefore, the size of the electronic package can
be reduced to meet the miniaturization requirement.
BRIEF DESCRIPTION OF DRAWINGS
[0028] FIGS. 1A and 1F are schematic cross-sectional views showing
a method for fabricating a semiconductor package according to the
prior art;
[0029] FIGS. 2A to 2G are schematic cross-sectional views showing a
method for fabricating an electronic package according to the
present invention, wherein FIG. 2D' is a schematic upper view of
FIG. 2D, FIGS. 2F' and 2F'' show other embodiments of FIG. 2F, and
FIGS. 2G' and 2G'' show other embodiments of FIG. 2G; and
[0030] FIGS. 3 and 3' are schematic cross-sectional views showing
other embodiments of FIG. 2G''.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0031] The following illustrative embodiments are provided to
illustrate the disclosure of the present invention, these and other
advantages and effects can be apparent to those in the art after
reading this specification.
[0032] It should be noted that all the drawings are not intended to
limit the present invention. Various modifications and variations
can be made without departing from the spirit of the present
invention. Further, terms such as "first", "second", "on", "a" etc.
are merely for illustrative purposes and should not be construed to
limit the scope of the present invention.
[0033] FIGS. 2A to 2G are schematic cross-sectional views showing a
method for fabricating an electronic package 2 according to the
present invention.
[0034] Referring to FIG. 2A, a metal board 24' having a plurality
of conductive posts 24 thereon is provided.
[0035] In the present embodiment, the metal board 24' and the
conductive posts 24 are integrally formed. For example, a copper
substrate is patterned by laser, mechanical drilling, etching or
the like so as to form the metal board 24' having the conductive
posts 24.
[0036] In other embodiments, the metal board 24' and the conductive
posts 24 are not integrally formed. For example, the conductive
posts 24 are formed on the metal board 24' by electroplating.
[0037] Referring to FIG. 2B, an encapsulant 22' is formed on the
metal board 24' to encapsulate the conductive posts 24.
[0038] In the present embodiment, the encapsulant 22' is formed by,
for example, resin molding, dry film lamination, coating or
printing.
[0039] Referring to FIG. 2C, the metal board 24' is removed,
thereby forming a package block 22''.
[0040] In the present embodiment, each of the conductive posts 24
has a first end surface 24a flush with and exposed from a surface
of the package block 22'' and a second end surface 24b opposite to
the first end surface 24a.
[0041] According to the practical need, the package block 22'' can
be cut along cutting paths L so as to obtain a plurality of
small-sized package blocks 22.
[0042] Referring to FIG. 2D, an electronic element 21 and a
plurality of package blocks 22 are disposed on a carrier 20 with
the conductive posts 24 bonded to the carrier 20.
[0043] In the present embodiment, the carrier 20 is a board made
of, for example, a semiconductor material, a dielectric material, a
ceramic material, glass or metal. The carrier 20 can correspond in
size to a wafer type substrate or a panel type substrate.
[0044] A bonding layer (not shown) made of such as a release film,
an adhesive material or an insulating material can be formed on the
carrier 20 by coating or adhering for bonding with the electronic
element 21 and the package blocks 22, and the first end surfaces
24a of the conductive posts 24 are in contact with the bonding
layer.
[0045] The electronic element 21 is an active element such as a
semiconductor chip, a passive element such as a resistor, a
capacitor or an inductor, or a combination thereof. In particular,
the electronic element 21 has an active surface 21a with a
plurality of electrode pads 210 and a non-active surface 21b
opposite to the active surface 21a, and the electronic element 21
is bonded to the bonding layer via the active surface 21a
thereof.
[0046] Referring to FIG. 2D', the package blocks 22 are arranged
adjacent to the electronic element 21.
[0047] Referring to FIG. 2E, an encapsulant 23 is formed on the
carrier 20 to encapsulate the electronic element 21 and the package
blocks 22.
[0048] In the present embodiment, the encapsulant 23 has a first
surface 23a and a second surface 23b opposite to the first surface
23a, and the encapsulant 23 is bonded to the bonding layer of the
carrier 20 via the first surface 23a thereof.
[0049] The encapsulant 23 covers the non-active surface 21b of the
electronic element 21 and the upper portions of the package blocks
22.
[0050] The encapsulant 23 is made of an insulating material such as
a liquid compound, and formed by injection, lamination or
molding.
[0051] The encapsulant 23 and the package blocks 22 can be made of
the same or different materials.
[0052] Referring to FIG. 2F, the carrier 20 and the bonding layer
are removed to expose the first surface 23a of the encapsulant 23
and the package blocks 22. As such, the active surface 21a of the
electronic element 21 and the first end surfaces 24a of the
conductive posts 24 are exposed from the first surface 23a of the
encapsulant 23.
[0053] Further, a thinning process can be performed according to
the practical need. Referring to FIG. 2F', a thinning process is
performed on the second surface 23b of the encapsulant 23 so as to
expose a non-active surface 21b' of the electronic element 21 and
second end surfaces 24b' of the conductive posts 24 from a second
surface 23b' of the encapsulant 23. Alternatively, referring to
FIG. 2F'', only the second end surfaces 24b' of the conductive
posts 24 are exposed from the second surface 23b' of the
encapsulant 23.
[0054] Referring to FIG. 2G, continued from FIG. 2F, a first
circuit structure 25 is formed on the first surface 23a of the
encapsulant 23 and electrically connected to the electrode pads 210
of the electronic element 21 and the first end surfaces 24a of the
conductive posts 24. Thereafter, a singulation process can be
performed according to the practical need.
[0055] In the present embodiment, the circuit structure 25 has an
insulating body 250 made of, for example, a dielectric material or
a solder mask material, and at least a redistribution layer 251
embedded in the insulating body 250. The innermost redistribution
layer 251 is electrically connected to the electrode pads 210 of
the electronic element 21 and the conductive posts 24, and a
plurality of conductive elements 26 made of such as metal posts or
a solder material are formed on the outermost redistribution layer
251 for mounting another electronic element 29 such as a passive
element. Alternatively, referring to FIG. 2G', an electronic device
9 such as a circuit board is mounted on the conductive elements
26.
[0056] If the process is continued from FIG. 2F', an electronic
package 2' of FIG. 2G' is obtained.
[0057] In another embodiment, referring to FIG. 2G'', the
encapsulant 23 encapsulates a plurality of electronic elements 21,
and a second circuit structure 27 is formed on the second surface
23b' of the encapsulant 23 and electrically connected to the
conductive posts 24. The circuit structure 27 has an insulating
body 270 made of, for example, a dielectric material or a solder
mask material, and at least a redistribution layer 271 electrically
connected to the conductive posts 24. Further, a plurality of
conductive elements 28 made of such as metal posts or a solder
material are formed on the redistribution layer 271.
[0058] Subsequently, an electronic device is stacked on the second
surface 23b, 23b' of the encapsulant 23 so as to form a stack-type
package structure. In particular, referring to FIG. 2G'', an
electronic device 3 is disposed on the electronic package 2''
through the conductive elements 28 on the second circuit structure
27.
[0059] In the present embodiment, the electronic device 3 is a
package, a chip or a substrate. The electronic device 3 can have a
wire-bonding type chip 31 or a flip-chip type chip.
[0060] In an embodiment, referring to FIG. 3, the non-active
surface 21b' of the electronic element 21 is exposed from the
second surface 23b' of the encapsulant 23, and a shielding layer
272 is formed on the non-active surface 21b' of the electronic
element 21 during formation of the redistribution layer 271 of the
second circuit structure 27. The shielding layer 272 is
electrically grounded through a portion of the redistribution layer
271 for EMI (electromagnetic interference) shielding.
[0061] In another embodiment, referring to FIG. 3', a metal sheet
is disposed on the non-active surface 21b of the electronic element
21 to serve as a shielding layer 40, and the shielding layer 40 is
flush with and exposed from the second surface 23b' of the
encapsulant 23. Then, a second circuit structure 27' is formed on
the second surface 23b' of the encapsulant 23 and electrically
connected to the conductive posts 24. For example, the circuit
structure 27' has an insulating body 270' made of such as a
dielectric material or a solder mask material and a plurality of
redistribution layers 271' electrically connected to the conductive
posts 24, and the shielding layer 40 is electrically grounded
through a portion of the redistribution layers 271'.
[0062] According to the present invention, the package blocks 22
having the conductive posts 24 are fabricated first and then the
encapsulant 23 is formed to encapsulate the package blocks 22. As
such, the present invention dispenses with the conventional
processes for forming the conductive posts in the encapsulant, for
example, a laser drilling process for forming through holes in the
encapsulant, a cleaning process for cleaning the through holes, and
an electroplating process for filling the through holes with a
conductive material. Therefore, the present invention saves the
fabrication time, improves the electrical transmission performance
of the conductive posts 24 and avoids the conventional drawback of
delamination of the conductive posts 24 from uneven wall surfaces
of the through holes, thereby improving the reliability of the
electronic package 2, 2', 2'', 4, 4'.
[0063] Further, by dispensing with the laser drilling process, the
present invention avoids formation of a heat affected zone and
hence allows the conductive posts 24 or the package blocks 22 to be
positioned close to the electronic element 21 according to the
practical need. Therefore, the size of the electronic package 2,
2', 2'', 4, 4' can be reduced to meet the miniaturization
requirement.
[0064] The present invention further provides an electronic package
2, 2', 2'', 4, 4', which has: an encapsulant 23 having a first
surface 23a and a second surface 23b, 23b' opposite to the first
surface 23a; at least an electronic element 21 embedded in the
encapsulant 23 and exposed from the first surface 23a of the
encapsulant 23; and at least a package block 22 embedded in the
encapsulant 23 and having a plurality of conductive posts 24
exposed from the first surface 23a of the encapsulant 23.
[0065] In an embodiment, an active surface 21a of the electronic
element 21 is flush with the first surface 23a of the encapsulant
23.
[0066] In an embodiment, each of the conductive posts 24 has a
first end surface 24a flush with the first surface 23a of the
encapsulant 23 and a second end surface 24b, 24b' opposite to the
first end surface 24a.
[0067] In an embodiment, the encapsulant 23 and the package block
22 are made of the same or different materials.
[0068] In an embodiment, the electronic element 21 is further
exposed from the second surface 23b' of the encapsulant 23. For
example, a non-active surface 21b' of the electronic element 21 is
flush with the second surface 23b' of the encapsulant 23.
[0069] In an embodiment, a shielding layer 272, 40 is formed on the
non-active surface 21b, 21b' of the electronic element 21 and
exposed from the second surface 23b' of the encapsulant 23.
[0070] In an embodiment, the conductive posts 24 are further
exposed from the second surface 23b' of the encapsulant 23. For
example, the second end surfaces 24b' of the conductive posts 24
are flush with the second surface 23b' of the encapsulant 23.
Further, a second circuit structure 27, 27' is formed on the second
surface 23b' of the encapsulant 23 and electrically connected to
the conductive posts 24.
[0071] In an embodiment, a first circuit structure 25 is further
formed on the first surface 23a of the encapsulant 23 and
electrically connected to the electronic element 21 and the
conductive posts 24. For example, the first circuit structure 25
has at least a redistribution layer 251 electrically connected to
the electronic element 21 and the conductive posts 24.
[0072] According to the present invention, the package block having
the conductive posts are fabricated first and then the encapsulant
is formed to encapsulate the package block. Therefore, the present
invention dispenses with the conventional laser drilling process so
as to simplify the fabrication process, reduce the fabrication time
and cost, improve the reliability of the electronic package and
reduce the size of the electronic package.
[0073] The above-described descriptions of the detailed embodiments
are only to illustrate the preferred implementation according to
the present invention, and it is not to limit the scope of the
present invention. Accordingly, all modifications and variations
completed by those with ordinary skill in the art should fall
within the scope of present invention defined by the appended
claims.
* * * * *