U.S. patent application number 15/340098 was filed with the patent office on 2017-02-16 for semiconductor device with self-aligned back side features.
The applicant listed for this patent is QUALCOMM INCORPORATED. Invention is credited to Stephen A. Fanelli.
Application Number | 20170047346 15/340098 |
Document ID | / |
Family ID | 55264346 |
Filed Date | 2017-02-16 |
United States Patent
Application |
20170047346 |
Kind Code |
A1 |
Fanelli; Stephen A. |
February 16, 2017 |
Semiconductor Device With Self-Aligned Back Side Features
Abstract
Various methods and devices that involve self-aligned features
on a semiconductor on insulator process are provided. An exemplary
method comprises forming a gate on a semiconductor on insulator
wafer. The semiconductor on insulator wafer comprises a device
region, a buried insulator, and a substrate. The exemplary method
further comprises applying a treatment to the semiconductor on
insulator wafer using the gate as a mask. The treatment creates a
treated insulator region in the buried insulator. The exemplary
method also comprises removing at least a portion of the substrate.
The exemplary method also comprises, selectively removing the
treated insulator region from the buried insulator to form a
remaining insulator region after removing that portion of the
substrate.
Inventors: |
Fanelli; Stephen A.; (San
Marcos, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
QUALCOMM INCORPORATED |
San Diego |
CA |
US |
|
|
Family ID: |
55264346 |
Appl. No.: |
15/340098 |
Filed: |
November 1, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14453595 |
Aug 6, 2014 |
9515181 |
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15340098 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/31155 20130101;
H01L 27/1203 20130101; H01L 29/7849 20130101; H01L 21/31111
20130101; H01L 21/2652 20130101; H01L 21/84 20130101; H01L 29/78654
20130101; H01L 29/42384 20130101; H01L 21/28176 20130101; H01L
29/7838 20130101; H01L 23/367 20130101; H01L 29/7843 20130101; H01L
21/266 20130101; H01L 21/7624 20130101; H01L 29/78603 20130101;
H01L 29/66772 20130101; H01L 21/31116 20130101; H01L 29/78648
20130101; H01L 21/28008 20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12; H01L 21/762 20060101 H01L021/762; H01L 21/266 20060101
H01L021/266; H01L 23/367 20060101 H01L023/367; H01L 21/3115
20060101 H01L021/3115; H01L 21/84 20060101 H01L021/84; H01L 29/78
20060101 H01L029/78; H01L 21/28 20060101 H01L021/28; H01L 21/311
20060101 H01L021/311 |
Claims
1-21. (canceled)
22. A semiconductor device comprising: a gate formed on a
semiconductor on insulator wafer, wherein the semiconductor on
insulator wafer comprises a device region and a buried insulator,
wherein the gate is formed on a top side of the device region, and
wherein the device region is less than 100 nanometers thick; and a
deposited layer located: (i) in an excavated region of the buried
insulator; (ii) on a back side of the device region; and (iii)
along a vertical edge of a remaining region of the buried
insulator; wherein a vertical edge of the gate is aligned to the
vertical edge of the remaining region of the buried insulator
within a margin of error; and wherein the margin of error is less
than 80 nanometers.
23. The semiconductor device of claim 22, wherein: the deposited
layer comprises a strain layer; and the gate contacts the device
region.
24. The semiconductor device of claim 22, wherein: the deposited
layer comprises a thermally conductive layer; and the gate is
formed in the device region.
25. The semiconductor device of claim 22, wherein: the
semiconductor on insulator wafer comprises a second device region
and a second buried insulator; the deposited layer comprises a
strain layer; the gate contacts the second device region and is
associated with a channel; and the device region comprises a second
gate associated with the channel.
26. The semiconductor device of claim 22, wherein: the
semiconductor device comprises an ultra-thin body region; and the
semiconductor device comprises a fully depleted silicon on
insulator transistor.
27. A semiconductor device comprising: a gate formed on a
semiconductor on insulator wafer, wherein the semiconductor on
insulator wafer comprises a first device region and a first buried
insulator layer, wherein the gate is formed on a top side of the
first device region; a remaining portion of the first buried
insulator layer formed on a back side of the gate and aligned with
the gate; and a deposited layer located: in an excavated region of
the first buried insulator layer, on a back side of the first
device region, and along a vertical edge of the remaining portion
of the first buried insulator layer; wherein a vertical edge of the
gate is aligned to the vertical edge of the remaining portion of
the first buried insulator layer.
28. The semiconductor device of claim 27, further comprising: a
second buried insulator layer and a second device region formed
under the gate.
29. The semiconductor device of claim 28, wherein the gate includes
a gate electrode for a channel formed in the second device region;
and wherein the first device region comprises an additional gate
electrode for a channel formed in the second device region.
30. The semiconductor device of claim 28, wherein the second buried
insulator layer is thinner than the first buried insulator
layer.
31. The semiconductor device of claim 27, wherein the deposited
layer comprises a strain layer.
32. The semiconductor device of claim 27, wherein the deposited
layer comprises a thermal dissipation layer.
33. The semiconductor device of claim 27, wherein the gate is
included in a transistor, the semiconductor device further
comprising: a conductive contact extending through a patterned
portion of the deposited layer coupling with the transistor.
Description
BACKGROUND OF THE INVENTION
[0001] The production of semiconductor devices at decreasing
geometries and at lower costs has long been recognized as one of
the key contributing factors to the widespread benefits of the
digital age. The cost of a semiconductor device is set largely by
the size of the substrate, the cost of materials that are consumed
as the substrate is processed, and by the amount of capital
overhead that is assignable to each part. The first two
contributors to cost can be reduced by decreasing the size of the
device, and by utilizing readily available materials. Capital
overhead costs can be decreased by using readily available
manufacturing equipment, and through the development of processing
techniques that eliminate the need for more exotic equipment and
reduce the time it takes to build each device. These processing
techniques are sometimes associated with distinctive manufacturing
features that provide evidence of how the device was made.
[0002] A self-aligned gate is a manufacturing feature that is
indicative of a particular processing technique that can be
described with reference to FIG. 1. Semiconductor wafer 100
comprises a substrate 101 covered by gate 102. As illustrated, gate
102 includes a photomask 103, a gate electrode 104, and a gate
insulator 105. At this point in the process, photomask 103 has been
used to create the gate stack. In other words, gate electrode 104
and gate insulator 105 previously had additional portions such that
they extended lateral across the surface of substrate 101.
Photomask 103 was then used to shield the gate stack while those
additional portions were removed. Once gate 102 has been formed,
photomask 103 can be put to use in another processing step. As
illustrated in FIG. 1, gate 102 can serve as a mask to shield
channel 107 while wafer 100 is exposed to a diffusion of dopants
108. As a result, photomask 103 can be used to not only form the
gate stack, but also to create the source and drain regions of the
transistor 109. Therefore, a different mask is not required for the
creation of gate stack 102 and source and drain regions 109.
[0003] In addition to reducing the number of processing steps
required, a self-aligned gate process produces an additional
benefit in that the resulting device has superior characteristics
when compared to devices formed according to certain alternative
processing methodologies. The performance of a transistor is
directly impacted by the interdependence of the gate, channel,
source, and drain regions of the transistor. In particular, it is
important to tightly control the location of the source-channel and
drain-channel junctions relative to the gate of the transistor. As
the same mask is used to form both the gate stack and the source
and drain regions in a self-aligned gate process, errors resulting
from the misalignment of two different masks are eliminated. The
self-aligned gate process therefore provides for both a more cost
effective and functionally superior device.
SUMMARY OF INVENTION
[0004] In one embodiment, a method comprises forming a gate on a
semiconductor on insulator wafer. The semiconductor on insulator
wafer comprises a device region, a buried insulator, and a
substrate. The method also comprises applying a treatment to the
semiconductor on insulator wafer using the gate as a mask. The
treatment creates a treated insulator region in the buried
insulator. The method also comprises removing at least a portion of
the substrate. The method also comprises selectively removing the
treated insulator region from the buried insulator to form a
remaining insulator region after removing the portion of the
substrate.
[0005] In another embodiment, a method comprises forming a gate on
a semiconductor on insulator wafer. The semiconductor on insulator
wafer comprises a device region, a buried insulator, and a
substrate. The exemplary method further comprises applying a
treatment to the semiconductor on insulator wafer using the gate as
a mask. The treatment creates a treated insulator region in the
buried insulator. The exemplary method also comprises removing at
least a portion of the substrate. The exemplary method also
comprises, selectively removing the treated insulator region from
the buried insulator to form a remaining insulator region after
removing that portion of the substrate.
[0006] In another embodiment, a semiconductor device comprises a
gate formed on a semiconductor on insulator wafer. The
semiconductor on insulator wafer comprises a device region and a
buried insulator. The gate is formed on a top side of the device
region. The device region is less than 100 nanometers thick. The
semiconductor device also comprises a deposited layer located: (i)
in an excavated region of the buried insulator; (ii) on a back side
of the device region; and (iii) along a vertical edge of a
remaining region of the buried insulator. A vertical edge of the
gate is aligned to the vertical edge of the remaining region of the
buried insulator within a margin of error. The margin of error is
less than 80 nanometers.
[0007] FIG. 2 illustrates a semiconductor on insulator (SOI)
structure 200 that includes semiconductor on insulator wafer 201,
contact layer 202, and metallization layers 203. The SOI wafer 201
in turn comprises substrate 204, insulator layer 205, and active
device layer 206. Substrate 204 can be a semiconductor material
such as silicon. Insulator layer 205 can be a dielectric such as
silicon dioxide formed through the oxidation of substrate 204.
Active device layer 206 can include transistors that conduct the
signal processing or power operations of device 200. As drawn, gate
207 serves as the gate for a transistor having a channel in active
device layer 206 immediately below gate 207. Active device layer
206 is coupled to metallization layers 203 via contact layer 202.
These layers can include a combination of dopants, dielectrics,
polysilicon, metal wiring, passivation, and other layers, materials
or components that are present after circuitry has been formed
therein. The circuitry may include metal wiring, passive devices
such as resistors, capacitors, and inductors; and active devices
such as transistors and diodes.
[0008] As used herein and in the appended claims, the "top" of SOI
structure 200 references a top surface 208 while the "bottom" of
SOI structure 200 references a bottom surface 209. This orientation
scheme persists regardless of the relative orientation of the SOI
structure 200 to other frames of reference, and the removal of
layers from, or the addition of layers to the SOI structure 200.
Therefore, the active layer 206 is always "above" the insulator
layer 205. In addition, a vector originating in the center of
active layer 206 and extending towards the bottom surface 209 will
always point in the direction of the "back side" of the SOI
structure 200 regardless of the relative orientation of the SOI
structure 200 to other frames of references, and the removal of
layers from, or the addition of layers to the 501 structure
200.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 illustrates a self-aligned implant for forming the
source and drain of a transistor.
[0010] FIG. 2 illustrates a semiconductor on insulator
structure.
[0011] FIG. 3 illustrates a flow chart of a process for producing a
semiconductor device with self-aligned back side features.
[0012] FIG. 4a-e illustrate a semiconductor structure at various
stages of the process described with reference to FIG. 3.
[0013] FIG. 5 illustrates the effect of a self-aligned back side
strain layer on the channel of a transistor.
[0014] FIG. 6 illustrates a flow chart of a process for producing a
semiconductor device with a dual gate transistor and self-aligned
back side features.
[0015] FIG. 7a-e illustrate a semiconductor structure at various
stages of the process described with reference to FIG. 6.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0016] Reference now will be made in detail to embodiments of the
disclosed invention, one or more examples of which are illustrated
in the accompanying drawings. Each example is provided by way of
explanation of the present technology, not as a limitation of the
present technology. In fact, it will be apparent to those skilled
in the art that modifications and variations can be made in the
present technology without departing from the spirit and scope
thereof. For instance, features illustrated or described as part of
one embodiment may be used with another embodiment to yield a still
further embodiment. Thus, it is intended that the present subject
matter covers all such modifications and variations within the
scope of the appended claims and their equivalents.
[0017] Active device layer 206 of semiconductor on insulator (SOI)
structure 200 is a critical region in terms of the performance of
the semiconductor device of which structure 200 is a part. In order
to create active devices with a desired characteristic, efforts
need to be taken to protect the device layer from processing steps
that introduce excessive variation into the active layer. For
example, it is generally beneficial to not disrupt the interface
between active device layer 206 and insulator layer 205. In
particular, in the region of active device layer 206 in which a
channel is to be formed, the interruption of this interface may
create dangling bonds that will alter the relationship of the
voltage in the gate electrode of gate 207 to the current in the
channel region, and may deleteriously degrade the mobility of
carries in the channel resulting in a device that cannot operate at
high frequency. However, benefits can arise from patterning the
insulator layer 205 from the back side such that different
materials can be placed in close proximity to the channel of an
active device without overly disrupting the active layer. For
example, thermal dissipation layers can be placed in close
proximity to the channel regions of active devices in active device
layer 206 to channel heat away from the active devices. As another
example, strain layers can be deposited in close proximity to the
channel regions of the active devices to enhance the mobility of
carriers in the channel. As a further example, electrical contacts
can be formed through a patterned insulator that need to be aligned
with contact regions that lie in or above active device layer
206.
[0018] A method for producing a semiconductor structure with
self-aligned back side features can be described with reference to
the flow chart in FIG. 3 and the structure cross sections in FIGS.
4a-e. The process of FIG. 3 begins with step 301 in which a gate is
formed on an SOI wafer. The gate can be the gate of a field effect
transistor (FET) which can be a metal-oxide-semiconductor (MOS) FET
or an insulated gate bipolar junction transistor (IGBT). The gate
could also be the gate of any kind of FET including a FinFET,
lateral diffusion MOS (LDMOS), or a vertical device. The active
layer may provide a channel for fully depleted (FD) FETand may
serve as an ultrathin body region for such a device. The gate will
generally include an insulator and a gate electrode. For example,
the gate insulator could be silicon dioxide and the gate electrode
could be a layer of polysilicon formed on the gate insulator. The
gate electrode could also comprise a metal, such as copper,
tungsten, or molybdenum, or a metal silicide. The gate could also
include additional insulators or layers of passivation to isolate
the gate. For example, the gate could include sidewall spacers
covering the gate stack in a vertical direction, and could include
a gate cap covering the gate stack in a lateral direction opposite
the gate insulator. Finally, the gate could also include a layer of
photoresist or some other form of hard mask used to form the gate
stack from layers of material with greater lateral extents than the
final gate stack. These layers could be permanent features of the
gate or they could be temporary layers that are removed before the
device is finalized.
[0019] SOI structure 400 in FIG. 4a includes SOI wafer 401 having
substrate 405, buried insulator layer 406, and active device layer
407. As mentioned previously, substrate 405 can comprise a
semiconductor such as silicon or an insulator such as sapphire. In
situations where substrate 405 is an insulator, there may not be a
distinction between buried insulator layer 406 and substrate 405.
Buried insulator layer 406 could also be formed through the
implantation of ions into a donor wafer, and substrate 405 could
also be a handle wafer used to steady active device layer 407 as it
is separated from that donor wafer. In situations where substrate
405 is silicon, buried insulator layer 405 could comprise silicon
dioxide formed through the oxidation of substrate 405. In these
situations, active device layer 407 can be formed through epitaxy.
Alternatively, buried insulator layer 406 can be formed in a
uniform substrate through the application of a SIMOX process.
Regardless of the particular process used to prepare SOI wafer 401,
buried insulator layer 406 can be referred to as a buried insulator
because it is covered on a top side by active device layer 407 and
covered on its back side by substrate 405. The term buried
insulator can be used to describe this layer even if the substrate
or active layers are removed to expose the insulator (i.e., the
term "buried" refers to the physical region regardless of whether
or not it remains buried in a finished device).
[0020] SOI structure 400 in FIG. 4a further illustrates gate 408
formed on the top side of the device region. As illustrate, gate
408 comprises three layers of material. Gate insulator 409 covers a
portion of active device region 407 that will serve as the channel
of a device formed in the active device region 407. Gate insulator
409 is covered by gate electrode 410. In this particular example,
gate 408 also includes a layer of photoresist 411 that covers gate
electrode 410. However, as mentioned previously, gate 408 might not
include this additional layer, and the layer may or may not be a
permanent feature of gate 408. In the illustrated example,
photoresist 411 is removed from gate stack 408 before the device is
finalized. However, photoresist 411 could also be replaced in the
figure with a dielectric that will serve as a mask and as a
permanent portion of the gate.
[0021] Process 300 continues with step 302 in which a treatment is
applied to the SOI wafer using the gate as a mask. The treatment
forms a treated insulator region in the buried insulator layer. In
specific approaches, the treatment is applied to the top side of
the SOI wafer. For example, the treatment could comprise the
diffusion of dopant ions into the active layer and buried
insulator. As another example, the treatment could comprise an ion
implant to dope the buried insulator layer. The treatment uses the
gate as a mask such that the treatment is effectively self-aligned.
However, the gate could be used as either a negative or positive
mask such that the treated insulator region could be formed in the
buried insulator layer below the gate, or outside the lateral scope
of the gate. The treatment could be applied in a wafer level
process such that multiple gates on multiple devices would provide
the pattern for the treated insulator layer. In situations in which
the gate acted as a negative mask, the first exposure would prime
the insulator layer that was outside the lateral scope of the gate
to withstand a second processing step meant to ultimately form the
treated insulator region within the lateral scope of the gate. In a
particular example, the treatment will be a self-aligned ion
implant into a buried oxide layer of a silicon on oxide wafer to
form a doped region of the buried oxide that is aligned with, but
outside the lateral scope of, the channels of the wafer.
[0022] SOI structure 400 in FIG. 4a further illustrates ion
bombardment 412 which is directed to the top side of SOI wafer 401
using gate 408 as a mask. The ion bombardment could involve the
implantation of dopant ions into buried insulator layer 406. The
energy of the ion bombardment could be tuned to focus its effect on
the insulator layer 406 while minimizing damage to active device
layer 407. The ion bombardment could also be tuned to only affect a
portion of buried insulator layer 406 such that the treated
insulator region would be distinguishable from the untreated
insulator region in both a lateral and vertical dimension. In
particular, the treated insulator region could be positioned
towards the back side of buried insulator layer 406 such that the
treated insulator region was below portions of untreated insulator
as well as to the left and right of untreated insulator.
[0023] Ion bombardment 412 could comprise various ion implant
species. For example, the bombardment could comprise boron,
phosphorous, or arsenic. In particular, the ion bombardment 412
could comprise dopant ions having a lower atomic weight than carbon
and greater than lithium. In specific approaches, ion bombardment
412 will be conducted through regions of a silicon active device
layer that may ultimately form the source and drain regions of a
FET or the emitter of an IGBT. As such, the dopant ions can be
chosen to minimize damage to these regions. While dopant ions that
have low atomic weights are less likely to damage the active layer
as they pass through, they are also less likely to be effective in
treating the buried insulator to the extent that it can be
selectively processed. Dopant ions with atomic weights that are
less than carbon, but greater than lithium, are less likely to
damage the active region as they pass through, while at the same
time retaining their efficacy as the creators of a treated
insulator region.
[0024] Process 300 continues with step 303 in which a portion of
the substrate is removed. In specific approaches, the substrate is
removed from the back side of the SOI wafer to expose the buried
insulator layer. The substrate can be removed by a grinding process
and may involve the application of a chemical-mechanical polish
(CMP) processing step. The substrate could be removed in a single
step or a multiple step process. In particular, a rapid grind could
be applied to remove a majority of the substrate, while a slower
process with higher selectivity to the buried insulator, such as a
wet etch, could be applied as a second step. During step 303, the
wafer may be held in place by a vacuum chuck or an alternative
handler such that the back side of the SOI wafer could be readily
accessed. Alternatively, the SOI wafer could be held in place by a
handle wafer attached to the top side of the SOI wafer.
[0025] Process 300 can include an addition step 304 in which a
handle wafer is bonded to the 501 wafer after the treatment is
applied to the 501 wafer in step 302. The handle wafer can be
bonded to the top side of the SOI wafer. The bond can be a
permanent bond or a temporary bond. In situations where the bond is
temporary, the SOI wafer may be transferred to another permanent
handle wafer at a later time. The handle wafer can provide a
stabilizing force to the active device layer of the SOI wafer while
the substrate is removed in step 303. In addition, the handle wafer
can serve as a permanent feature of the overall SOI structure such
that the handle wafer continues to provide a stabilizing force to
the active device layer after the substrate is removed. The handle
wafer can comprise a trap rich layer as described in commonly
assigned U.S. Pat. No. 8,466,036 and its related patents. The
handle wafer can also comprise additional active or passive devices
that can be electrically coupled to the active device layer of the
SOI wafer.
[0026] SOI structure 420 in FIG. 4b illustrates SOI wafer 401 after
treated insulator region 421 has been formed in buried insulator
layer 406. SOI structure 420 further illustrates how SOI wafer 401
has been bonded to handle wafer 422 and subsequently inverted for
back side processing. Handle wafer 422 can be bonded to SOI wafer
401 using a permanent or temporary bond. Handle wafer 422 can
comprise a trap rich layer and can additionally be comprised
entirely of a trap rich material. As illustrated, mask 411 has been
removed from the gate 408 at this point in the process. However, as
stated previously, mask 411 may comprise a permanent portion of the
device. Active device layer 407 is illustrated with contacts 423
connecting it to the handle wafer 422. However, contacts 423 are
merely representative of the additional processing that SOI wafer
401 will undergo prior to the bonding of handle wafer 422. Although
active device layer 407 can be connected to circuitry in handle
wafer 422, the contacts may also connect to metallization layers
meant to route signals solely within SOI wafer 401.
[0027] Various additional layers can be added to 501 wafer 401 to
lie in-between active layer 406 and handle wafer 422. These layers
can include metallization for routing signals between active
devices in active device layer 406. The number of steps that lie
between different approaches that are in accordance with cross
sections 400 and 420 can include any kind of processing associated
with variant technologies such as CMOS or BiCMOS. In specific
approaches, standard CMOS fabrication will continue after step 302
and continue up to the deposition of inter-level dielectric, at
which point step 304 can be executed. In other approaches, any
number of additional wafers may be added to the top side of the SOI
wafer before step 304 is executed. These additional wafers can
contain trap rich layers and may also include additional passive
and active circuitry that can be coupled to the circuitry in active
device layer 407 using direct metal contacts, through silicon vias
(TSVs), or similar structures.
[0028] SOI structure 440 in FIG. 4c illustrates the SOI wafer after
substrate 405 has been removed. As illustrated, substrate 405 has
been completely removed from the back side of SOI wafer 401 to
thereby expose treated insulator region 421. However, the substrate
can also be removed in a patterned fashion. For example, the
substrate might only be removed below certain regions of an overall
die such as the regions in which active devices will ultimately be
formed. As a further example, the substrate might only be removed
below certain features such as the regions that lie directly below
the gates such as gate 408. In particular, the substrate can be
partially removed such that a remaining portion of the substrate
continues to provide a stabilizing force to active device layer 407
as the substrate is removed. The remaining portion of the substrate
could also provide a stabilizing force to active device layer 407
in a final device. In these approaches, a handle wafer might not be
needed, or a handle wafer might only be required while the
substrate is partially removed, but the remaining substrate could
provide the required stabilizing force to the active device layer
in a final device.
[0029] Process 300 continues with step 305 in which the treated
insulator region is selectively removed from the buried insulator
layer. The removal of the treated insulator region from the
insulator layer forms a remaining insulator region. As the gate was
used to pattern the treated insulator region, the remaining
insulator region will be aligned to the gate and lie under the
active region of the SOI structure underneath the gate. A benefit
of this approach is that the insulator region is thereby patterned
without the need for an additional mask.
[0030] The insulator can be removed in step 305 using any process
that is selective to the treated insulator region. Thus the removal
process is linked to the treatment applied in step 302. As a
particular example, the treatment could be the implantation of
boron ions into a buried insulator layer comprising silicon dioxide
to form a doped oxide, and the removal process could be a
hydrofluoric etch delivered in vapor form that would remove the
doped oxide and leave the untreated silicon dioxide in place. The
selective removal process could comprise a wet hydrofluoric etch or
a vapor hydrofluoric etch. In The insulator could alternatively be
removed using a plasma etch.
[0031] SOI structure 460 in FIG. 4d illustrates SOI wafer 401 after
treated insulator region 421 has been removed. The resulting
structure includes a self-aligned feature of remaining insulator
461 on the back side of a channel in active region 407. The
original SOI insulator layer has been removed from other portions
of the wafer while it remains underneath the gates that were used
to pattern the treatment applied in step 302. As shown, the
remaining insulator and the gate are both in contact with a channel
formed in the device region. Depending on the selectivity of the
removal process applied in step 305, remaining insulator region 461
may be thinner in both a lateral and vertical dimension than the
original insulator region. However, an informed selection of the
treatment to apply in step 302 and a removal process for step 305
that are both based on the material that comprises the original
buried insulator layer, will lead to a highly selective removal
process that contributes to the reliable alignment of the remaining
insulator region 461 to the channel of devices in active region
407.
[0032] In alternative approaches, the selective removal process in
step 305 will result in a negative pattern to that of the treatment
applied in step 302. In an alternative step, just prior to step
305, the entire insulator region could undergo a second treatment
after being exposed by the removal of the substrate, and then be
acted upon by a selective removal process such that only the
insulator region that was treated in step 302 would remain. In
these approaches, the first treatment serves to counteract the
effect of the second treatment such that only those portions of the
insulator that did not receive the first treatment would remain
after the application of the selective removal process.
[0033] Although SOI structure 460 illustrates treated insulator
region 421 as having been completely removed in certain places, the
treated insulator region could instead by removed to various
degrees at different points along the lateral expanse of the back
side of the SOI structure. As mentioned previously, the treatment
from step 302 could be targeted to a specific depth of the buried
insulator region such that treated insulator region 421 did not
extend through the entire vertical expanse of the original buried
insulator. For example, if the treatment from step 302 was targeted
to just cover the back half of the insulator layer, the selective
removal in step 305 could result in only half of the insulator
region being removed at specific points in the overall pattern such
that remaining insulator region 461 would be a raised plateau
surrounded by an expanse of thinned remaining insulator.
[0034] Process 300 continues with step 306 in which a layer is
deposited. The layer can be deposited on the back side of the SOI
wafer. The layer can be formed on the remaining insulator region.
The layer can be deposited via a blanket deposition or it can be a
targeted deposition. The deposition step can use a mask, or it can
rely only on the pattern formed by the remaining insulator region.
The deposition can include a chemical enhanced vapor deposition
(CVD), plasma enhanced CVD, atomic layer deposition (ALD),
dielectric spin or sprat coating, or a high density plasma
deposition (HDP). Alternatively, the layer could be formed by
bringing the SOI wafer into contact with a conforming layer of
material that would conform to the shape of the remaining insulator
region. The conforming layer could be brought into contact using an
additional wafer.
[0035] Cross section 480 in FIG. 4e illustrates the 501 wafer after
layer 481 has been deposited on the back side of the wafer.
Although only a single layer is illustrated, multiple layers can be
deposited on the SOI wafer to achieve various results. In the
illustrated example, removal of the treated insulator region
exposed the device region 407, and the formation of layer 481
comprised a blanket deposition of material on the remaining
insulator region 461 and the device region 407. In the illustrated
example, the deposition was directed to the back side of the SOI
wafer. Layer 481 could comprise a strain layer, a thermal
dissipation layer, or any other region of material that would
benefit from being patterned to surround the channels of active
device in device region 407.
[0036] In contrast to example illustrated in FIG. 4e, but in
accordance with examples mentioned previously, gate 408 could have
a negative pattern relationship with the remaining insulator region
such that the insulator was removed from beneath the channels but
left in place in other regions of the structure. In these examples,
the deposited layer could be an electrically insulating thermal
dissipation layer. This approach would carry the benefit of placing
the heat dissipation layer as close as possible to the heat
generating channels of the active devices. However, these
approaches would be accompanied by the risk of damage to the
delicate channels of active devices in layer 407 unless specific
tolerances were selected for the processing steps involved with the
selective removal of the insulator, and the deposition of layer
481.
[0037] FIG. 5 displays a cross section 500 of a transistor in an
SOI device that has been processed in accordance with the procedure
described with reference to FIG. 3. Cross section 500 includes gate
408 which was formed on the SOI wafer. The gate includes gate
electrode 501 and gate insulator 502. The cross section also
illustrates channel region 503 that is associated with gate 408,
and that is in contact with both the remaining insulator region 461
and the gate 408. As described previously, the gate 408 is formed
on a top side of device region 407. Since the gate was used to
pattern remaining insulator region 461, layer 481 is located in an
excavated region of the buried insulator 504, on a back side of
active device region 407, and along a vertical edge of the
remaining insulator region 461.
[0038] Certain benefits accrue to approaches in which the edges of
remaining insulator region 461 can be reliably aligned to gate 408.
The processes described with reference to FIG. 3 provides a degree
of alignment of these two features that is not otherwise attainable
through reasonable commercial efforts. Using process 300, the
vertical edge of gate 408 can be reliably aligned to the vertical
edge of remaining insulator 461 within a margin of error that is
constrained by the thickness of active device layer 407, the
species and implant energy of any ions used to treat the insulator
layer, the concentration doping concentration of the treated
insulator region, and post implant thermal conditions that may
alter the extent of the treated insulator region. As active device
layer 407 decreases in thickness, the margin of error increases. As
the implant energy and weight of any ions used to treat the
insulator layer increases, the margin of error increases. As the
doping concentration of the treated insulator region increases, the
margin of error decreases. Based on simulations, approaches
described with reference to FIG. 3 can provide reliable alignment
of the gate 408 and the remaining insulator 461 to within a margin
of error of less than 80 nanometers for a device region that is
less than 100 nanometers thick. Notably, process 300 can achieve
reliable alignment even when the ultimate device comprises fully
depleted SOI devices with particularly thin active layers. The
channel region 503 in these situations would comprise an ultra-thin
body region.
[0039] As mentioned previously, layer 481 can be a strain inducing
layer. The strain inducing layer can be a compressive or tensile
film. The strain inducing layer can also induce strain in active
device layer 407 through a lattice mismatch effect. For example,
the strain inducing layer 481 could comprise silicon germanium
while active device layer 407 comprised silicon in which case the
mismatch of the two materials would induce strain in active device
layer 407. The strain inducing layer can enhance the mobility of
carriers in the device by inducing strain 505 in channel region
503. Strain layer 481 enhances the mobility of carriers in channel
region 503, and thereby enhances the performance of devices formed
in device layer 407. A strain layer benefits from being more
closely aligned with the channel region because it is thereby able
to more directly exert stain on the devices while at the same time
not directly overlapping the channel region and deleteriously
altering the behavior of the device.
[0040] Different combinations of the type of treatment applied to
the insulator layer, and the type of strain layer deposited create
different kinds of strain in channel region 503. As mentioned
previously, depending upon the treatment applied to the insulator
layer, the gate could be used as either a negative or positive mask
such that the treated insulator region could be formed in the
insulator layer below the gate, or outside the lateral scope of the
gate. The strain induced by the strain layer can also be considered
to exhibit a negative or positive strain in that the deposited film
can be compressive or tensile respectively. Notably, this
characteristic of the film can be independent of the pattern on
which the film is applied. Therefore, the combination of
independently positive or negative straining films with positive or
negative patterns creates the potential for four different
configurations that produce two different strain profiles (i.e., a
negative film with a negative pattern creates a positive strain,
both negative and positive combinations create a negative strain,
and a positive film with a negative pattern creates a positive
strain). This ability to achieve a given strain profile using
different combinations provides a degree of freedom to the designer
in that certain kinds of insulator treatment or strain layer
materials can be avoided for cost or concerns regarding technical
feasibility.
[0041] Additional variants of layer 481 also benefit from being
tightly aligned to gate 408. For example, since channels are one of
the largest sources of heat in a semiconductor device, thermal
dissipation layers benefit from being closely aligned to the
channel region in order to minimize the distance through which the
heat must diffuse before being efficiently removed from the device.
At the same time, it is important to keep the buried insulator in
place below the channel as a thermal dissipative layer is generally
a less effective substitute for the original buried insulator.
[0042] After step 306, additional processing steps can be conducted
to connect to the circuitry in active device layer 407 as well as
to package the final device. For example, the deposited layer could
be patterned and etched to form contacts to devices in active
device layer 407 to allow external connect. In addition, back side
metallization can be formed on the back side of the SOI wafer to
provide for interconnection between different circuit components in
device layer 407. For example, the back side metallization may be
used to connect a transistor to another transistor, a transistor to
a diode, or a transistor to a passive component.
[0043] FIG. 6 illustrates method 600 which continues method 300 at
step 303. In method 600, steps 301-304 can be conducted as
described above. However, method 600 is intended to operate on a
wafer with an alternative structure to that which was described
previously. Method 600 produces a self-aligned dual gate device.
SOI structure 700 in FIG. 7a illustrates an SOI wafer 701 that can
be processed in accordance with method 600. The starting wafer
comprises many of the features of SOI wafer 401, and differs mainly
in that substrate 702 is associated with not only buried insulator
layer 406 and active device layer 407, but a second active layer
703 and a second buried insulator layer 704. As show in FIG. 7a,
gate 408 is used as a mask for the implantation of dopant ions into
SOI wafer 701. In contrast to method 300, the ion implant, or other
treatment used in method 600, must be controlled to pass through
second buried insulator layer 704 to instead treat buried insulator
region 406 and form treated insulator region 705. As before, the
formation of treated insulator region 705 leaves untreated
insulator region 706 in its original state.
[0044] Any of the processing steps described with reference to
process 300 can likewise be applied to method 600 as these
processing steps continue. FIG. 7b illustrates SOI structure 720 as
processing continues in a similar fashion to what was described
with reference to FIG. 4b. The SOI wafer has been inverted, and an
optional handle wafer 422 has been bonded to the top of the wafer.
As mentioned previously, handle wafer 422 may comprise a trap rich
layer. FIG. 7c illustrates cross section 740 after substrate 702
has been removed.
[0045] Method 600 continues with step 601 in which the treated
insulator is removed from the buried insulator layer. An example of
this processing step is illustrated by 501 structure 760 in FIG.
7d. SOI structure 760 shows the SOI wafer after treated insulator
region 705 has been removed such that only untreated insulator
layer 706 remains. At this point in the process, active device
layer 407 is exposed while second active layer 703 and second
buried insulator layer 704 remain covered.
[0046] Method 600 continues with either step 602 or 603. In step
602, a portion of the exposed device region is removed. The device
region can be removed using remaining buried insulator 706 as a
mask, or an additional mask may be used instead. The etchant used
to etch device region 407 can perform an isotropic etch and may
also involve a specific chemical etchant that is selective to
second buried insulator 704. In step 603, a layer of material is
deposited on the back side of the wafer. Step 603 can be conducted
in accordance with any of the variations of step 306 discussed
above.
[0047] FIG. 7e illustrates 501 structure 780 which shows SOI wafer
701 after a portion of device region 407 has been removed to form
remaining device region 781, and a layer 481 has been deposited on
the back side of the wafer. In this situation, the remaining device
region 781 serves as an additional gate electrode for a channel
formed in second device region 703 while second buried insulator
704 serves as the gate insulator for the additional gate. The
resulting structure comprises a self-aligned DG-FET. In this
structure, gate 408 contacts second device region 703 and is
associated with a channel formed in second device region 703. The
remaining device region 781 servers as a second gate electrode for
the same channel, and the remaining buried insulator 706 serves to
isolate and shield remaining device region 781.
[0048] Insulator layer 406 in FIGS. 7a-e is thicker than second
insulator layer 704 to illustrate certain benefits that accrue to
such a structure. In particular, in situations where the treatment
to the buried insulator layer is an ion implantation step, the
thickness of insulator layer 406 makes it an easier target for
implantation. At the same time, the thickness of a gate insulator
is inversely proportional to certain figures of merit associated
with the transistor--such as its transconductance. Since insulator
layer 704 will serve as a gate insulator for the additional gate,
it is beneficial to make insulator layer 704 relatively thin.
Therefore, when used with an ion implantation treatment, process
600 is particularly amenable to the creation of a high performance
DG-FET.
[0049] The dual gate structure illustrated in FIG. 7e benefits
greatly from the degree of alignment provided by process 300 and
600 in that misaligned gates in a DG-FET can result in extra
capacitance and a commensurate loss of current drive. However, when
the gates are reliably aligned with a high degree of accuracy, the
speed and power dissipation of a DG-FET is substantially lower than
that of a single gate FET. Therefore, the creation of a dual gate
structure according to a self-aligned process, such as process 600,
can produce a superior transistor to approaches in which a separate
mask is used to create additional gate electrode 781. The process
of FIGS. 3 and 6 can reliably align the dual gates of the DG-FET
with similar constraints to what was discussed above. However, in
this situation, the thickness of the buried insulator is also a
constraint on the reliability of the alignment because the implant
is through both the buried insulator and the top active region.
Based on simulations, approaches described with reference to FIGS.
3 and 6 can provide reliable alignment of the gate 408 and
remaining device region 781 to within a margin of error of less
than 70 nanometers for a device region that is less than 80
nanometers thick with a buried insulator thickness of 10
nanometers. Notably, process 300 can achieve reliable alignment
even when the ultimate device comprises fully depleted SOI devices
with particularly thin active layers. The channel region 503 in
these situations would comprise an ultra-thin body region.
[0050] Deposited layer 481 can take on any of the characteristics
described above with reference to FIGS. 4e and 5. In particular,
deposited layer 481 can be a strain layer that enhances the
mobility of carriers in the channel formed in second device layer
704. As described previously, the film can be compressive or
tensile. Layer 481 can also be a thermal dissipation layer. Also,
as noted above with reference to FIG. 4e, SOI structure 780 can
undergo additional processing steps to connect to circuitry in
active layer 703. In addition, SOI structure 780 can undergo
additional processing steps to connect gate electrode 781 to
circuitry in different wafers, on a package, or to circuitry in
active layer 703. In particular, gate electrode 781 could be
connected to the same circuitry as the gate electrode of gate
408.
[0051] Although some embodiments in the above disclosure were
specifically illustrated by cross sections wherein a gate structure
is used as the mask for an initial treatment of an SOI insulator
layer, other features can be used to mask the initial treatment
instead. Indeed, any feature to which back side alignment is
desired could be used to pattern the applied treatment. Depending
upon the characteristics of the feature, the material used to
define the feature could be used as a mask itself, or the actual
mask used to pattern that feature can be used as the mask for the
initial treatment. As a particular example, the mask used to
pattern TSVs in the SOI wafer could also be used to apply a
treatment to the insulator. Such an approach would be useful in
situations where the TSVs were intended to be connected through the
back side insulator.
[0052] While the specification has been described in detail with
respect to specific embodiments of the invention, it will be
appreciated that those skilled in the art, upon attaining an
understanding of the foregoing, may readily conceive of alterations
to, variations of, and equivalents to these embodiments. These and
other modifications and variations to the present invention may be
practiced by those skilled in the art, without departing from the
spirit and scope of the present invention, which is more
particularly set forth in the appended claims.
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