U.S. patent application number 15/285665 was filed with the patent office on 2017-02-09 for method for producing an sgt-including semiconductor device.
The applicant listed for this patent is UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.. Invention is credited to NOZOMU HARADA, FUJIO MASUOKA.
Application Number | 20170040329 15/285665 |
Document ID | / |
Family ID | 51897939 |
Filed Date | 2017-02-09 |
United States Patent
Application |
20170040329 |
Kind Code |
A1 |
MASUOKA; FUJIO ; et
al. |
February 9, 2017 |
METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE
Abstract
A method for producing an SGT-including semiconductor device
includes forming a gate insulating layer on an outer periphery of a
Si pillar, forming a gate conductor layer on the gate insulating
layer, and forming an oxide layer on the gate conductor layer. Then
a hydrogen fluoride ion diffusion layer containing moisture is
formed so as to make contact with the oxide layer and lie at an
intermediate position of the Si pillar. A part of the oxide film in
contact with the hydrogen fluoride ion diffusion layer is etched
with hydrogen fluoride ions generated from hydrogen fluoride gas
supplied to the hydrogen fluoride ion diffusion layer and an
opening is thereby formed on the outer periphery of the Si
pillar.
Inventors: |
MASUOKA; FUJIO; (TOKYO,
JP) ; HARADA; NOZOMU; (TOKYO, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNISANTIS ELECTRONICS SINGAPORE PTE. LTD. |
SINGAPORE |
|
SG |
|
|
Family ID: |
51897939 |
Appl. No.: |
15/285665 |
Filed: |
October 5, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14732208 |
Jun 5, 2015 |
9514944 |
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15285665 |
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PCT/JP2013/063701 |
May 16, 2013 |
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14732208 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/66666 20130101;
H01L 21/28158 20130101; G11C 11/412 20130101; H01L 29/78642
20130101; H01L 29/42392 20130101; H01L 21/31116 20130101; H01L
29/42356 20130101; H01L 21/28247 20130101; H01L 27/1108 20130101;
H01L 29/7827 20130101 |
International
Class: |
H01L 27/11 20060101
H01L027/11; H01L 29/66 20060101 H01L029/66; H01L 29/786 20060101
H01L029/786; H01L 21/311 20060101 H01L021/311; H01L 29/423 20060101
H01L029/423; H01L 29/78 20060101 H01L029/78; H01L 21/28 20060101
H01L021/28 |
Claims
1. A method of producing an SGT-including semiconductor device, the
method comprising: a semiconductor-pillar-forming step of forming a
semiconductor pillar on a substrate; a
first-impurity-region-forming step of forming a first impurity
region below the semiconductor pillar; a
second-impurity-region-forming step of forming a second impurity
region in the semiconductor pillar so that the second impurity
region is distanced from and above the first impurity region; a
first-gate-insulating-layer-forming step of forming a first gate
insulating layer on an outer periphery of the semiconductor pillar
and at least a portion of the semiconductor pillar located between
the first impurity region and the second impurity region; a
first-gate-conductor-layer-forming step of forming a first gate
conductor layer on an outer periphery of the first gate insulating
layer; a first-insulating-layer-forming step of forming a first
insulating layer so that the first insulating layer covers the
semiconductor pillar and the first gate conductor layer; a
second-insulating-layer-forming step of forming a second insulating
layer on the substrate and on an outer periphery of the first
insulating layer, the second insulating layer being shorter than
the semiconductor pillar; a
hydrogen-fluoride-ion-diffusion-layer-forming step of forming a
hydrogen fluoride ion diffusion layer containing
hydrogen-fluoride-ion and having a particular thickness on the
second insulating layer and the first insulating layer; a
first-insulating-layer-etching step of etching a part of the first
insulating layer on the hydrogen fluoride ion diffusion layer by
using the hydrogen fluoride ions diffused from the hydrogen
fluoride ion diffusion layer; and a
hydrogen-fluoride-ion-diffusion-layer-removing step of removing the
hydrogen fluoride ion diffusion layer after the
first-insulating-layer-etching step, wherein an SGT is constituted
by the first impurity region and the second impurity region that
respectively function as a source and a drain or vice versa, the at
least a portion of the semiconductor pillar located between the
first impurity region and the second impurity region that functions
as a channel between the drain and the source, the first gate
insulating layer, and the first gate conductor layer.
2. The method according to claim 1, which comprises generating the
hydrogen-fluoride-ion in the hydrogen-fluoride-ion diffusion-layer
by supplying hydrogen fluoride gas to the hydrogen-fluoride-ion
diffusion-layer.
3. The method according to claim 1, which further comprises: a
third-impurity-region-forming step of forming a third impurity
region on the second impurity region and in the semiconductor
pillar, the third-impurity-region-form ing step being performed
after the second-impurity-region-forming step and before the
hydrogen-fluoride-ion-diffusion-layer-forming step, wherein, in the
hydrogen-fluoride-ion-diffusion-layer-forming step, the hydrogen
fluoride ion diffusion layer is formed in a range that extends
across where the second impurity region and the third impurity
region are formed with respect to an upright direction of the
semiconductor pillar; and a first-gate-conductor-layer-etching step
of etching the first gate conductor layer by using the first
insulating layer as a mask, the first-gate-conductor-layer-etching
step being performed after the
hydrogen-fluoride-ion-diffusion-layer-removing step.
4. The method according to claim 3, further comprising a
first-gate-insulating-layer-etching step of etching the first gate
insulating layer by using one or both of the first insulating layer
and the first gate conductor layer as a mask, the
first-gate-insulating-layer-etching step being performed after the
first-gate-conductor-layer-etching step.
5. The method according to claim 4, wherein: a top portion of the
second insulating layer is positioned within a range where the
second impurity region is formed in the semiconductor pillar with
respect to the upright direction of the semiconductor pillar, and
the method further comprises a first-conductor-wiring-layer-forming
step of forming a first conductor wiring layer so as to connect
exposed portions of the second impurity region and the third
impurity region in the semiconductor pillar, the
first-conductor-wiring-layer-forming step being performed after the
first-gate-insulating-layer-etching step.
6. The method according to claim 1, wherein: a top portion of the
hydrogen-fluoride-ion-diffusion-layer and a bottom portion of the
hydrogen-fluoride-ion-diffusion-layer are positioned within a range
where the first gate conductor layer is formed with respect to an
upright direction of the semiconductor pillar, and the method
further comprises an insulating-film-partial-etching-step of
etching a part of the first insulating film in contact with the
hydrogen-fluoride-ion-diffusion-layer.
7. The method according to claim 6, further comprising a
second-conductor-wiring-layer-form ing step of forming a second
conductor wiring layer connected to an exposed portion of the first
gate conductor layer, the second-conductor-wiring-layer-forming
step being performed after the
hydrogen-fluoride-ion-diffusion-layer-removing step.
8. The method according to claim 1, further comprising: a
third-impurity-region-forming step of forming a third impurity
region in the semiconductor pillar and on the second impurity
region; a fourth-impurity-region-forming step of forming a fourth
impurity region above the third impurity region, the fourth
impurity region containing a donor impurity or an acceptor impurity
and having the same conductivity type as the third impurity region;
a second-gate-insulating-layer-forming step of forming a second
gate insulating layer on the outer periphery of the semiconductor
pillar and on at least a portion of the semiconductor pillar
located between the third impurity region and the fourth impurity
region, the second gate insulating layer being separated from the
first gate insulating layer; and a
second-gate-conductor-layer-forming step of forming a second gate
conductor layer on an outer periphery of the second gate insulating
layer, the second gate conductor layer being separated from the
first gate conductor layer.
9. The method according to claim 8, wherein, in the
hydrogen-fluoride-ion-diffusion-layer-forming step, the hydrogen
fluoride ion diffusion layer is formed to be in contact with a part
of the first insulating layer in an outer periphery direction so
that a top portion of the hydrogen fluoride ion diffusion layer
comes within a range of the third impurity region with respect to
an upright direction of the semiconductor pillar and a bottom
portion of the hydrogen fluoride ion diffusion layer comes within a
range of the second impurity region with respect to the upright
direction, and the method comprises: a
first-insulating-layer-etching step of etching a part of the first
insulating layer on the hydrogen fluoride ion diffusion layer by
using the hydrogen fluoride ions diffused from the hydrogen
fluoride ion diffusion layer; and a
third-gate-insulating-layer-etching step of etching the first gate
conductor layer by using the first insulating layer as a mask and
then etching the first gate insulating layer by using one or both
of the first insulating layer and the first gate conductor layer as
a mask, the third-gate-insulating-layer-etching step being
performed after the hydrogen-fluoride-ion-diffusion-layer-removing
step.
10. The method according to claim 1, wherein the
first-impurity-region-forming step is performed after the
first-gate-conductor-layer-forming step.
11. The method according to claim 1, wherein: the method comprises
a third-impurity-region-forming step of forming a third impurity
region in the semiconductor pillar and on the second impurity
region, the third impurity region containing a donor impurity or an
acceptor impurity, the third-impurity-region-forming step being
performed after the second-impurity-region-form ing step and before
the hydrogen-fluoride-ion-diffusion-layer-form ing step, wherein in
the hydrogen-fluoride-ion-diffusion-layer-forming step, the
hydrogen fluoride ion diffusion layer is formed so as to contact a
part of the first insulating layer in an outer periphery direction
so that a top portion of the hydrogen fluoride ion diffusion layer
comes within a range of the third impurity region with respect to
an upright direction of the semiconductor pillar and a bottom
portion of the hydrogen fluoride ion diffusion layer comes within a
range of the second impurity region with respect to the upright
direction, and the method comprises: a
second-insulating-layer-etching step of etching a part of the first
insulating layer on the hydrogen fluoride ion diffusion layer by
using the hydrogen fluoride ions diffused from the hydrogen
fluoride ion diffusion layer; and a
third-gate-insulating-layer-etching step of etching the first gate
conductor layer by using the first insulating layer as a mask and
then etching the first gate insulating layer by using one or both
of the first insulating layer and the first gate conductor layer as
a mask, the third-gate-insulating-layer-etching step being
performed after the hydrogen-fluoride-ion-diffusion-layer-removing
step.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation of copending patent application Ser.
No. 14/732,208, filed Jun. 5, 2015, which is a continuation of
international patent application PCT/JP2013/063701, filed May 16,
2013; the contents of the prior applications are incorporated
herein by reference in their entirety.
BACKGROUND OF THE INVENTION
[0002] Field of the Invention
[0003] The present invention relates to a method for producing a
semiconductor device that includes surrounding gate MOS transistors
(SGTs).
[0004] Description of the Related Art
[0005] Applications of surrounding gate MOS transistors
(hereinafter referred to as SGTs) to semiconductor elements that
offer highly integrated semiconductor devices have expanded in
recent years and higher integration of SGT-including semiconductor
devices is pursued under such trends.
[0006] FIG. 5 shows a structure of a representative example of a
CMOS inverter circuit that includes MOS transistors. The CMOS
inverter circuit includes an N-channel MOS transistor 100a and a
P-channel MOS transistor 100b. A gate 101a of the N-channel MOS
transistor 100a and a gate 101b of the P-channel MOS transistor
100b are connected to an input terminal Vi. A drain 102a of the
N-channel MOS transistor 100a and a drain 102b of the P-channel MOS
transistor 100b are connected to an output terminal Vo. A source
103b of the P-channel MOS transistor 100b is connected to a power
source terminal VDD. A source 103a of the N-channel MOS transistor
100a is connected to a ground terminal VSS. In this CMOS inverter
circuit, when an input voltage corresponding to "1" or "0" is
applied to the input terminal Vi, an output voltage corresponding
to the inverted input voltage, "0" or "1," is output from the
output terminal Vo.
[0007] These types of CMOS inverter circuits are used in many
circuit chips such as microprocessors and the like. Increasing the
degree of integration of CMOS inverter circuits directly leads to
size-reduction of circuit chips such as microprocessors. Moreover,
size reduction of circuit chips that use CMOS inverter circuits
leads to cost reduction of circuit chips.
[0008] FIG. 6 is a cross-sectional view of a known planar CMOS
inverter circuit. As illustrated in FIG. 6, an N-well region 105
(hereinafter a semiconductor region where a P-channel MOS
transistor is formed and that contains a donor impurity is referred
to as an N-well region) is formed in a P-type semiconductor
substrate 104 (hereinafter a semiconductor substrate that contains
an acceptor impurity is referred to as a P-type semiconductor
substrate). Element isolation insulating layers 106a and 106b are
each formed between a surface layer portion of the N-well region
105 and a surface layer portion of the P-type semiconductor
substrate 104. A gate oxide film 107a for a P-channel MOS
transistor and a gate oxide film 107b for an N-channel MOS
transistor are respectively formed on a surface of the P-type
semiconductor substrate 104 and a surface of the N-well region 105.
A gate conductor layer 108a for a P-channel MOS transistor and a
gate conductor layer 108b for an N-channel MOS transistor are
respectively formed on the gate oxide film 107a and the gate oxide
film 107b. On the left side of the gate conductor layer 108a for a
P-channel MOS transistor, a P.sup.+ region 109a (a semiconductor
region that has a high acceptor impurity concentration is
hereinafter referred to as a "P.sup.+ region") is formed on a
surface of the N-well region 105. On the right side of the gate
conductor layer 108a, a P.sup.+ region 109b is formed on the
surface of the N-well region 105. Similarly, a N.sup.+ region 110b
(a semiconductor region having a high donor impurity concentration
is hereinafter referred to as an "N.sup.+ region") is formed on the
surface of the P-type semiconductor substrate 104 on the right side
of the gate conductor layer 108b for a N-channel MOS transistor,
and a N.sup.+ region 110a is formed on the surface of the P-type
semiconductor substrate 104 on the left side of the gate conductor
layer 108b. A first interlayer insulating layer 111 is formed.
Contact holes 112a, 112b, 112c, and 112d are formed in the first
interlayer insulating layer 111 so as to be on the P.sup.+ regions
109a and 109b and the N.sup.+ regions 110a and 110b,
respectively.
[0009] A power supply wiring metal layer Vdd formed on the first
interlayer insulating layer 111 is connected to the P.sup.+ region
109a of the P-type MOS transistor through the contact hole 112a. An
output wiring metal layer Vo formed on the first interlayer
insulating layer 111 is connected to the P.sup.+ region 109b of a
P.sup.- channel MOS transistor and the N.sup.+ region 110a of an
N-channel MOS transistor through the contact holes 112b and 112c. A
ground wiring metal layer Vss is connected to the N.sup.+ region
110b of an N-channel MOS transistor through the contact hole 112d.
A second interlayer insulating layer 113 is formed on the first
interlayer insulating layer 111. Contact holes 114a and 114b are
formed so as to penetrate through the first interlayer insulating
layer 111 and the second interlayer insulating layer 113. The
contact hole 114a is on the gate conductor layer 108a for a
P-channel MOS transistor and the contact hole 114b is on the gate
conductor layer 108b for a N-channel MOS transistor. An input
wiring metal layer Vi formed on the second interlayer insulating
layer 113 is connected to the gate conductor layer 108a for a
P-channel MOS transistor and the gate conductor layer 108b for an
N-channel MOS transistor through the contact holes 114a and
114b.
[0010] In order to reduce the area in which a planar CMOS inverter
circuit is formed, it is necessary to reduce the two-dimensional
size of the P-type semiconductor substrate 104, on which the gate
conductor layers 108a and 108b of P- and N-channel MOS transistors,
the N.sup.+ regions 110a and 110b, the P.sup.+ regions 109a and
109b, the contact holes 112a, 112b, 112c, 112d, 114a, and 114b, and
the wiring metal layers 108a and 108b are formed, as viewed in plan
in a direction perpendicular to the substrate surface. In a typical
planar CMOS inverter circuit, many contact holes are formed in
addition to the contact holes 112a, 112b, 112c, 112d, 114a, and
114b. Accordingly, in order to form fine contact holes at high
accuracy, processing technologies such as lithographic technologies
and etching technologies are required to achieve ever higher
accuracy.
[0011] In a typical planar MOS transistor, the channel of a P- or
N-channel MOS transistor lies in a horizontal direction along the
surface of the P-type semiconductor substrate 104 and the N-well
region 105 and between the source and the drain. In contrast, the
channel of an SGT lies in a direction perpendicular to a surface of
a semiconductor substrate (for example, refer to Japanese
Unexamined Patent Application Publication No. 2-188966, and Hiroshi
Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko
Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on
Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)).
[0012] FIG. 7A is a schematic diagram illustrating an N-channel
SGT. N.sup.+ regions 116a and 116b are respectively formed in a
lower portion and an upper portion of a P-type or i-type
(intrinsic) Si pillar 115 (hereinafter a silicon semiconductor
pillar is referred to as a Si pillar). When one of the N.sup.+
regions 116a and 116b functions as a source, the other functions as
a drain. A portion of the Si pillar 115 that lies between the
source and drain N.sup.+ regions 116a and 116b is a channel region
117. A gate insulating layer 118 is surrounds the channel region
117, and a gate conductor layer 119 surrounds the gate insulating
layer 118. In a SGT, source and drain N.sup.+ regions 116a and
116b, the channel region 117, the gate insulating layer 118, and
the gate conductor layer 119 are formed in one Si pillar 115. Thus,
the area of the surface of the SGT appears to be equal to the area
of one source or drain N.sup.+ region of a planar MOS transistor.
Accordingly, a circuit chip that includes SGTs can achieve further
chip-size reduction compared to a circuit chip that includes planar
MOS transistors.
[0013] FIG. 7B is a cross-sectional view of an SGT-including CMOS
inverter circuit (for example, refer to Japanese Unexamined Patent
Application Publication No. 7-99311).
[0014] As illustrated in FIG. 7B, an i-layer 121 ("i-layer" refers
to an intrinsic Si layer) is formed on an insulating layer
substrate 120 and a Si pillar SP1 for a P-channel SGT and a Si
pillar SP2 for an N-channel SGT are formed on the i-layer 121.
[0015] The i-layer 121 is connected to a lower portion of the Si
pillar SP1 of a P-channel SGT. A P.sup.+ region 122 of a P-channel
SGT is formed in the same layer as the i-layer 121 and surrounds
the lower portion of the Si pillar SP1. A N.sup.+ region 123 of an
N-channel SGT is formed in the same layer as the i-layer 121 and
surrounds the lower portion of the Si pillar SP2.
[0016] A P.sup.+ region 124 of a P-channel SGT is formed in an
upper portion of the Si pillar SP1 for a P-channel SGT. A N.sup.+
region 125 of an N-channel SGT is formed in an upper portion of the
Si pillar SP2 for an N-channel SGT.
[0017] As illustrated in FIG. 7B, gate insulating layers 126a and
126b are formed so as to surround the Si pillars SP1 and SP2. A
gate conductor layer 127a of a P-channel SGT and a gate conductor
layer 127b of an N-channel SGT are formed so as to surround the
gate insulating layers 126a and 126b.
[0018] Insulating layers 128a and 128b are formed so as to surround
the gate conductor layers 127a and 127b.
[0019] The P.sup.+ region 122 of a P-channel SGT and the N.sup.+
region 123 of an N-channel SGT are connected to each other through
a silicide layer 129b. A silicide layer 129a is formed on the
P.sup.+ region 124 of a P-channel SGT and a silicide layer 129c is
formed on the N.sup.+ region 125 of an N-channel SGT. An i-layer
130a between the P.sup.+ region 122 under the Si pillar SP1 and the
P.sup.+ region 124 in an upper portion of the Si pillar SP1 serves
as a channel of a P-channel SGT. An i-layer 130b between the
N.sup.+ region 123 under the Si pillar SP2 and the N.sup.+ region
125 in an upper portion of the Si pillar SP2 serves as a channel of
an N-channel SGT.
[0020] As illustrated in FIG. 7B, a SiO.sub.2 layer 131 is formed
by chemical vapor deposition (CVD) so as to cover the i-layer
substrate 120 (insulating layer substrate) and the Si pillars SP1
and SP2. Contact holes 132a, 132b, and 132c are formed in the
SiO.sub.2 layer 131. The contact hole 132a is formed on the Si
pillar SP1, the contact hole 132c is formed on the Si pillar SP2,
and the contact hole 132b is formed on part of the P.sup.+ region
122 and the N.sup.+ region 123.
[0021] A power supply wiring metal layer Vdd on the SiO.sub.2 layer
131 is connected to the P.sup.+ region 124 of a P-channel SGT and
the silicide layer 129a through the contact hole 132a. An output
wiring metal layer Vo on the SiO.sub.2 layer 131 is connected to
the P.sup.+ region 122 of a P-channel SGT, the N.sup.+ region 123
of an N-channel SGT, and the silicide layer 129b through the
contact hole 132b. The ground wiring metal layer Vss on the
SiO.sub.2 layer 131 is connected to the N.sup.+ region 125 of an
N-channel SGT and the silicide layer 129c through the contact hole
132c.
[0022] The gate conductor layer 127a of a P-channel SGT and the
gate conductor layer 127b of an N-channel SGT are connected to each
other and to an input wiring metal layer (not shown in the
drawing). Since a P-channel SGT and an N-channel SGT are
respectively formed in the Si pillar SP1 and the Si pillar SP2 in
the inverter circuit that has these SGTs, the area of the circuit
in a plan view taken in a direction perpendicular to the insulating
layer substrate 120 is reduced. Accordingly, the circuit can
achieve further side reduction compared to an inverter circuit that
has typical planar MOS transistors.
[0023] Currently, efforts are being made to further reduce the size
of a circuit chip that includes SGTs. In this regard, as
illustrated in the diagram of FIG. 8, it has been predicted that
the circuit area can be reduced by respectively forming two SGTs in
an upper portion and a lower portion of one Si pillar SPa (for
example, refer to Hyoungiun Na and Tetsuo Endoh: "A New Compact
SRAM cell by Vertical MOSFET for Low-power and Stable Operation",
Memory Workshop, 201 3rd IEEE International Digest, pp. 1 to 4
(2011)).
[0024] As illustrated in FIG. 8, a CMOS inverter circuit includes
an N-channel SGT 133a formed in a lower portion of the Si pillar
SPa and a P-channel SGT 133b is formed above the N-channel SGT
133a. A N.sup.+ region 134a of the N-channel SGT 133a is formed in
a lower portion of the Si pillar SPa, and is connected to the
ground wiring metal layer Vss. A channel i-layer 136a is formed on
the N.sup.+ region 134a. A gate insulating layer 137a is formed on
the outer periphery of the channel i-layer 136a. A gate conductor
layer 138a for an N-channel SGT is formed on the outer periphery of
the gate insulating layer 137a. A N.sup.+ region 134b is formed on
the channel i-layer 136a. A P.sup.+ region 135a of the P-channel
SGT 133b is formed on the N.sup.+ region 134b. A channel i-layer
136b is formed on the P.sup.+ region 135a. A gate insulating layer
137b is formed on the outer periphery of the channel i-layer 136b,
and a gate conductor layer 138b for the P-channel SGT 133b is
formed on the outer periphery of the gate insulating layer 137b. A
P.sup.+ region 135b is formed in a top portion of the Si pillar SPa
and on the channel i-layer 136b. The P.sup.+ region 135b is
connected to the power supply wiring metal layer VDD. A connecting
part 160a that is in contact with the gate conductor layer 138a of
the N-channel SGT 133a and is formed of a metal wire having an
opening and a connecting part 160b that is in contact with the gate
conductor layer 138b of the P-channel SGT 133b and is formed of a
metal wire having an opening are connected to the input wiring
metal layer Vi. A connecting part 161 formed of a metal wire and
having an opening in contact with the N.sup.+ region 134b of the
N-channel SGT 133a and the P.sup.+ region 135a of the P-channel SGT
133b (this opening corresponds to the contact hole 132b on the
P.sup.+ region 122 and the N.sup.+ region 123 in FIG. 7B) is
connected to an output terminal wire Vo.
[0025] Some production difficulties need to be resolved in order to
form an SGT-including inverter circuit in one Si pillar SPa as
illustrated in FIG. 8. That is, in FIG. 8, the P.sup.+ region 135a
of the P-channel SGT 133b and the N.sup.+ region 134b of the
N-channel SGT 133a that lie in a middle portion of the Si pillar
SPa are in contact with each other. Thus, the connecting part 161
that is in contact with the N.sup.+ region 134b of the N-channel
SGT 133a and the P.sup.+ region 135a of the P-channel SGT 133b must
be formed on the side wall of the Si pillar SPa. This means that
the opening of the connecting part 161 must be formed on the side
wall of the Si pillar SPa. Similarly, the openings of the
connecting parts 160a and 160b in contact with the gate conductor
layers 138a and 138b must also be formed on the side wall of the Si
pillar SPa. This means that fine openings of the connecting parts
160a, 160b, and 161 each formed of a metal wire having an opening
must be formed on the side wall of the Si pillar SPa with high
accuracy. Although it is necessary to highly accurately form fine
openings on the side wall of the Si pillar SPa in order to form
openings of the connecting parts 160a, 160b, and 161, this cannot
be achieved by a known method for forming fine contact holes 112a,
112b, 112c, 112d, 114a, 114b, 132a, 132b, and 132c with high
accuracy in a flat region on the semiconductor substrate 104 and
the insulating layer substrate 120 described by referring to FIGS.
6 and 7B.
[0026] FIG. 9 is a diagram showing a structure that includes two Si
pillars, SPb and SPc, two SGTs, namely, SGT 139a and SGT 139b,
formed in the Si pillar SPb, and two SGTs, namely, SGT 140a and
140b, formed in the Si pillar SPc with the SGTs 139a, 139b, 140a,
and 140b being connected to one another through a conducting wire.
The SGT 139a formed in a lower portion of the Si pillar SPb is
constituted by source and drain N.sup.+ regions 141a and 141b, a
channel i-region 150a, a gate insulating layer 143a, and a gate
conductor layer 144a. The SGT 139b in the upper portion of the Si
pillar SPb is constituted by P.sup.+ regions 142a and 142b, a
channel i-region 150b, a gate insulating layer 143b, and a gate
conductor layer 144b. The SGT 140a in the lower portion of the Si
pillar SPc is constituted by N.sup.+ regions 145a and 145b, a
channel i-region 151a, a gate insulating layer 147a, and a gate
conductor layer 148a. The SGT 140b in the upper portion of the Si
pillar SPc is constituted by N.sup.+ regions 146a and 146b, a
channel i-region 151b, a gate insulating layer 147b, and a gate
conductor layer 148b.
[0027] As illustrated in FIG. 9, a connecting part 163a that is
formed of a metal wire having an opening, the metal wire contacting
the gate conductor layer 144a and surrounding the Si pillar SPb, is
formed. A connecting part 163b that is formed of a metal wire
having an opening, the metal wire contacting the gate conductor
layer 144b and surrounding the Si pillar SPb, is formed. A
connecting part 149a that is formed of a metal wire having an
opening, the metal wire contacting the gate conductor layer 148a
and surrounding the Si pillar SPc, is formed. A connecting part
149b that is formed of a metal wire having an opening, the metal
wire contacting the gate conductor layer 148a and surrounding the
Si pillar SPc, is formed. A connecting part 164a that is formed of
a metal wire having an opening, the metal wire contacting the
N.sup.+ region 141b and the P.sup.+ region 142a and surrounding the
Si pillar SPb, is formed. A connecting part 164b that is formed of
a metal wire having an opening, the metal wire contacting the
N.sup.+ region 145b and the N.sup.+ region 146a, is formed.
[0028] As illustrated in FIG. 9, in the Si pillar SPb, the
connecting part 163a is connected to a metal terminal wiring V1,
the connecting part 163b is connected to a metal terminal wiring
V2, and the connecting part 164a is connected to a metal terminal
wiring V4. In the Si pillar SPc, the connecting part 149a is
connected to a metal wiring 162a, the connecting part 149b is
connected to a metal terminal wiring V3, and the connecting part
164b is connected to a metal wiring 162b. The connecting part 163a
and the connecting part 149a are connected to each other via the
metal wiring 162a and the connecting part 164a and the connecting
part 164b are connected to each other via the metal wiring
162b.
[0029] In forming an SGT-including inverter circuit illustrated in
FIG. 9, it is preferable to form the connecting part 163a and the
connecting part 149a simultaneously at the same position in terms
of the height in a perpendicular direction (height direction) of
the Si pillars SPb and SPc. As a result, the number of steps
required to form the connecting parts 163a and 149a can be reduced.
Similarly, it is preferable to form the connecting part 163b and
the connecting part 149b simultaneously at the same position in
terms of the height in the perpendicular direction of the Si
pillars SPb and SPc. The connecting part 164a and the connecting
part 164b are preferably formed simultaneously at the same position
in terms of height in the perpendicular direction of the Si pillars
SPb and SPc. In order to achieve this, the openings of the
connecting part 163a and the connecting part 149a must be formed
simultaneously at the same height in the perpendicular direction of
the Si pillars SPb and SPc and the same applies to the openings of
the connecting part 163b and the connecting part 149b and the
openings of the connecting part 164a and the connecting part 164b.
Furthermore, the openings of these connecting parts 163a, 163b,
149a, 149b, 164a, and 164b must be fine and made highly accurately.
Although it is necessary to highly accurately form fine openings on
the side walls of the Si pillars SPb and SPc to form these
openings, this cannot be achieved by a known method for forming
fine contact holes 112a, 112b, 112c, 112d, 114a, 114b, 132a, 132b,
and 132c with high accuracy in a flat region on the semiconductor
substrate 104 and the insulating layer substrate 120 described by
referring to FIGS. 6 and 7B.
[0030] As illustrated in FIG. 10, a gate insulating layer 152 that
surrounds the Si pillar SPb is formed as one continuous layer that
bridges the SGT 139a and the SGT 139b in the upper and lower
portions of the Si pillar SPb. A gate conductor layer 153 is also
formed as one continuous layer. A connecting part 154 and a metal
terminal wiring V5 are formed to be in contact with the gate
conductor layer 153. A connecting part 155 that is in contact with
the N.sup.+ region 141b and the P.sup.+ region 142a and is
connected to the connecting part 164b via the metal wiring 162b is
formed so as not to electrical short with the gate conductor layer
153. According to this approach illustrated in FIG. 10, the gates
of the SGT 139a and the SGT 139b in the upper and lower portions of
the Si pillar SPb can be electrically connected to each other via
the gate conductor layer 153, the connecting part 154, and the
metal terminal wiring V5 whereas the structure illustrated in FIG.
9 requires two connecting parts 145a and 145b and two metal
terminal wirings V1 and V2 in order to electrically connect the
gate conductor layers 144a and 144b of the SGT 139a and the SGT
139b in the upper and lower portions of the Si pillar SPb to each
other. In order to form the structure illustrated in FIG. 10, it is
necessary to form the opening of the connecting part 155 so as not
to be in contact with the gate conductor layer 153. Forming this
opening requires highly accurate forming of a fine opening in the
side wall of the Si pillar SPb. However, this cannot be achieved by
a known method for forming fine contact holes 112a, 112b, 112c,
112d, 114a, 114b, 132a, 132b, and 132c with high accuracy in a flat
region on the semiconductor substrate 104 and the insulating layer
substrate 120 described by referring to FIGS. 6 and 7B.
[0031] According to the methods for producing SGT-including
semiconductor devices described by referring to FIGS. 8, 9, and 10,
SGTs are formed on top of the other in each of the Si pillars SPa,
SPb, and SPc in a longitudinal direction and Si pillars SPa, SPb,
and SPc are formed in which the N-channel SGTs 133a, 139a, 140a,
and 140b, and P-channel SGTs 133b and 139b positioned in upper and
lower portions of the Si pillars SPa, SPb, and SPc are used in
different combinations. According to these production methods, it
is difficult to form openings of the connecting parts 161, 164a,
164b, and 155 in contact with the N.sup.+ regions 134b, 141b, 145b,
and 146a and the P.sup.+ regions 135a and 142a that contain donor
or acceptor impurities and openings of the connecting parts 163a,
163b, 149a, 149b, and 154 of the gate conductor layers 138a, 138b,
145a, 145b, 149a, 149b, and 153 at predetermined positions with
high accuracy.
SUMMARY OF THE INVENTION
[0032] It is accordingly an object of the invention to provide a
method for producing an SGT-including semiconductor device which
overcomes the above-mentioned and other disadvantages of the
heretofore-known devices and methods of this general type.
[0033] With the foregoing and other objects in view there is
provided, in accordance with the invention, a method for producing
an SGT-including semiconductor device. The method comprises a
semiconductor pillar forming step of forming a semiconductor pillar
on a semiconductor substrate; a first impurity region forming step
of forming a first impurity region below the semiconductor pillar,
the first impurity region containing a donor impurity or an
acceptor impurity; a second impurity region forming step of forming
a second impurity region in the semiconductor pillar so that the
second impurity region is distanced from and above the first
impurity region, the second impurity region having the same
conductivity type as the first impurity region; a first gate
insulating layer forming step of forming a first gate insulating
layer on an outer periphery of the semiconductor pillar and on at
least a portion of the semiconductor pillar that lies between the
first impurity region and the second impurity region; a first gate
conductor layer forming step of forming a first gate conductor
layer on an outer periphery of the first gate insulating layer; a
first insulating layer forming step of forming a first insulating
layer so that the first insulating layer covers the semiconductor
pillar and the first gate conductor layer; a second insulating
layer forming step of forming a second insulating layer on the
semiconductor substrate and on an outer periphery of the first
insulating layer, the second insulating layer being shorter than
the semiconductor pillar; a hydrogen fluoride ion diffusion layer
forming step of forming a hydrogen fluoride ion diffusion layer
having a particular thickness on the second insulating layer, the
hydrogen fluoride ion diffusion layer being capable of generating
hydrogen fluoride ions and allowing the hydrogen fluoride ions to
diffuse therein; a hydrogen fluoride gas supplying step of
supplying hydrogen fluoride gas to the hydrogen fluoride ion
diffusion layer; a first insulating layer etching step of etching a
part of the first insulating layer in contact with the hydrogen
fluoride ion diffusion layer by using the hydrogen fluoride ions
generated in the hydrogen fluoride ion diffusion layer from the
hydrogen fluoride gas supplied to the hydrogen fluoride ion
diffusion layer; and a hydrogen fluoride ion diffusion layer
removing step of removing the hydrogen fluoride ion diffusion layer
after the first insulating layer etching step. An SGT is
constituted by the first impurity region and the second impurity
region that respectively function as a source and a drain or vice
versa, a part of the semiconductor pillar that lies between the
first impurity region and the second impurity region and serves as
a channel between the drain and the source, the first gate
insulating layer, and the first gate conductor layer.
[0034] The method may further include a third impurity region
forming step of forming a third impurity region containing a donor
impurity or an acceptor impurity on the second impurity region and
in the semiconductor pillar, the third impurity region forming step
being performed after the second impurity region forming step and
before the hydrogen fluoride ion diffusion layer forming step. In
the hydrogen fluoride ion diffusion layer forming step, the
hydrogen fluoride ion diffusion layer may be formed in a range that
extends across where the second impurity region and the third
impurity region are formed with respect to an upright direction of
the semiconductor pillar. The method may further include a first
gate conductor layer etching step of etching the first gate
conductor layer by using the first insulating layer as a mask, the
first gate conductor layer etching step being performed after the
hydrogen fluoride ion diffusion layer removing step.
[0035] The method may further include a first gate insulating layer
etching step of etching the first gate insulating layer by using
one or both of the first insulating layer and the first gate
conductor layer as a mask. The first gate insulating layer etching
step may be performed after the first gate conductor layer etching
step.
[0036] A top portion of the second insulating layer may be
positioned within a range where the second impurity region is
formed in the semiconductor pillar with respect to the upright
direction of the semiconductor pillar. The method may further
include a first conductor wiring layer forming step of forming a
first conductor wiring layer so as to connect exposed portions of
the second impurity region and the third impurity region in the
semiconductor pillar, the first conductor wiring layer forming step
being performed after the first gate insulating layer etching
step.
[0037] A top portion of the second insulating layer and a bottom
portion of the second insulating layer may be positioned within a
range where the first gate conductor layer is formed with respect
to an upright direction of the semiconductor pillar. The method may
further include a second conductor wiring layer forming step of
forming a second conductor wiring layer connected to the exposed
first gate conductor layer, the second conductor wiring layer
forming step being performed after the hydrogen fluoride ion
diffusion layer removing step.
[0038] The method preferably further includes a third impurity
region forming step of forming a third impurity region in the
semiconductor pillar and on the second impurity region, the third
impurity region containing a donor impurity or an acceptor
impurity; a fourth impurity region forming step of forming a fourth
impurity region above the third impurity region, the fourth
impurity region containing a donor impurity or an acceptor impurity
and having the same conductivity type as the third impurity region;
a second gate insulating layer forming step of forming a second
gate insulating layer on the outer periphery of the semiconductor
pillar and on at least a portion of the semiconductor pillar that
lies between the third impurity region and the fourth impurity
region, the second gate insulating layer being separated from the
first gate insulating layer; and a second gate conductor layer
forming step of forming a second gate conductor layer on an outer
periphery of the second gate insulating layer, the second gate
conductor layer being separated from the first gate conductor
layer.
[0039] In the hydrogen fluoride ion diffusion layer forming step,
the hydrogen fluoride ion diffusion layer may be formed so as to be
in contact with a part of the first insulating layer in an outer
periphery direction so that a top portion of the hydrogen fluoride
ion diffusion layer comes within a range of the third impurity
region with respect to an upright direction of the semiconductor
pillar. A bottom portion of the hydrogen fluoride ion diffusion
layer may come within a range of the second impurity region with
respect to the upright direction. The method may include a second
hydrogen fluoride gas supplying step of supplying hydrogen fluoride
gas to the hydrogen fluoride ion diffusion layer; a second
insulating layer etching step of etching a part of the first
insulating layer in contact with the hydrogen fluoride ion
diffusion layer by using the hydrogen fluoride ions generated in
the hydrogen fluoride ion diffusion layer from the hydrogen
fluoride gas supplied to the hydrogen fluoride ion diffusion layer;
and a third gate insulating layer etching step of etching the first
gate conductor layer by using the first insulating layer as a mask
and then etching the first gate insulating layer by using one or
both of the first insulating layer and the first gate conductor
layer as a mask, the third gate insulating layer etching step being
performed after the hydrogen fluoride ion diffusion layer removing
step.
[0040] The first impurity region forming step may be performed
after the first gate conductor layer forming step.
[0041] The method may include a third impurity region forming step
of forming a third impurity region in the semiconductor pillar and
on the second impurity region, the third impurity region containing
a donor impurity or an acceptor impurity, the third impurity region
forming step being performed after the second impurity region
forming step and before the hydrogen fluoride ion diffusion layer
forming step. In the hydrogen fluoride ion diffusion layer forming
step, the hydrogen fluoride ion diffusion layer may be formed so as
to contact a part of the first insulating layer in an outer
periphery direction so that a top portion of the hydrogen fluoride
ion diffusion layer comes within a range of the third impurity
region with respect to an upright direction of the semiconductor
pillar and a bottom portion of the hydrogen fluoride ion diffusion
layer comes within a range of the second impurity region with
respect to the upright direction. The method may include a second
hydrogen fluoride gas supplying step of supplying hydrogen fluoride
gas to the hydrogen fluoride ion diffusion layer; a second
insulating layer etching step of etching a part of the first
insulating layer in contact with the hydrogen fluoride ion
diffusion layer by using the hydrogen fluoride ions generated in
the hydrogen fluoride ion diffusion layer from the hydrogen
fluoride gas supplied to the hydrogen fluoride ion diffusion layer;
and a third gate insulating layer etching step of etching the first
gate conductor layer by using the first insulating layer as a mask
and then etching the first gate insulating layer by using one or
both of the first insulating layer and the first gate conductor
layer as a mask, the third gate insulating layer etching step being
performed after the hydrogen fluoride ion diffusion layer removing
step.
[0042] According to the present invention, in producing a circuit
in which two or more SGTs are formed in one semiconductor pillar in
a vertical direction, an opening of a connecting part in contact
with a side wall of a gate conductor layer or a source or drain
N.sup.+ or P.sup.+ region that lies between plural SGTs can be
formed with high accuracy and separation of a gate conductor layer
can be carried out at a desired position with high accuracy.
BRIEF DESCRIPTION OF THE DRAWINGS
[0043] FIG. 1A is a diagram illustrating an SRAM cell circuit
according to a first embodiment of the present invention.
[0044] FIG. 1B is a schematic diagram illustrating a structure of
the SRAM cell circuit of the first embodiment constituted by four
Si pillars.
[0045] FIG. 1C is a plan view showing an arrangement of Si pillars
in the SRAM cell circuit of the first embodiment.
[0046] FIGS. 2AA to 2AC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating a method for
producing an SGT-including semiconductor device according to a
first embodiment.
[0047] FIGS. 2BA to 2BC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0048] FIGS. 2CA to 2CC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0049] FIGS. 2DA to 2DC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0050] FIGS. 2EA to 2EC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0051] FIGS. 2FA to 2FC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0052] FIGS. 2GA to 2GC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0053] FIGS. 2HA to 2HC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0054] FIGS. 2IA to 2IC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0055] FIGS. 2JA to 2JC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0056] FIGS. 2KA to 2KC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0057] FIGS. 2LA to 2LC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0058] FIGS. 2MA to 2MC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0059] FIGS. 2NA to 2NC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0060] FIGS. 2OA to 2OC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0061] FIGS. 2PA to 2PC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0062] FIGS. 2QA to 2QC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0063] FIGS. 2RA to 2RC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0064] FIGS. 2SA to 2SC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0065] FIGS. 2TA to 2TC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0066] FIGS. 2UA to 2UC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0067] FIGS. 2VA to 2VC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0068] FIGS. 2WA to 2WC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
first embodiment.
[0069] FIGS. 3AA to 3AC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating a method for
producing an SGT-including semiconductor device according to a
second embodiment.
[0070] FIGS. 3BA to 3BC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
second embodiment.
[0071] FIGS. 3CA to 3CC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
second embodiment.
[0072] FIGS. 3DA to 3DC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
second embodiment.
[0073] FIGS. 3EA to 3EC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
second embodiment.
[0074] FIGS. 3FA to 3FC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
second embodiment.
[0075] FIGS. 3GA to 3GC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
second embodiment.
[0076] FIGS. 4AA to 4AC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating a method for
producing an SGT-including semiconductor device according to a
third embodiment.
[0077] FIGS. 4BA to 4BC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
third embodiment.
[0078] FIGS. 4CA to 4CC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
third embodiment.
[0079] FIGS. 4DA to 4DC are respectively a plan view and
cross-sectional views of an SRAM cell illustrating the method for
producing an SGT-including semiconductor device according to the
third embodiment.
[0080] FIG. 5 is diagram illustrating a CMOS inverter circuit
according to the prior art.
[0081] FIG. 6 is a cross-sectional view of a planar CMOS inverter
circuit according to the prior art.
[0082] FIG. 7A is a schematic diagram illustrating an SGT according
to the prior art.
[0083] FIG. 7B is a cross-sectional view of an SGT-including CMOS
inverter circuit according to the prior art.
[0084] FIG. 8 is a schematic view of a structure in which an
N-channel SGT and a P-channel SGT are respectively formed in a
lower portion and an upper portion of one Si pillar according to
the prior art.
[0085] FIG. 9 is a schematic diagram illustrating a state in which
SGTs are connected with conductive wires in the case where two SGTs
are formed in each Si pillar.
[0086] FIG. 10 is a schematic diagram illustrating a connection
state of SGTs with conductive wires, in which a continuous gate
conductor layer is shared by two SGTs formed in one Si pillar and
connection to a metal terminal wiring is established through one
connecting part.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0087] Referring now to the figures of the drawing in detail, the
following describes SGT-including semiconductor devices and
production methods therefor according to several embodiments of the
present invention.
First Embodiment
[0088] An SGT-including semiconductor device and a production
method therefor according to a first embodiment are described below
with reference to FIGS. 1A to 1C and 2AA to 2WC.
[0089] FIG. 1A is a circuit diagram of a static random access
memory (SRAM) cell circuit according to this embodiment. The SRAM
cell includes two inverter circuits IV1 and IV2. The inverter
circuit IV1 is constituted by a P-channel SGT P1 serving as a load
transistor and two N-channel SGTs N11 and N12 serving as drive
transistors and being connected in parallel. The inverter circuit
IV2 is constituted by a P-channel SGT P2 serving as a load
transistor and two N-channel SGTs N21 and N22 serving as drive
transistors and being connected in parallel. The gate of the
P-channel SGT P1 of the inverter circuit IV1 is connected to the
gates of the N-channel SGTs N11 and N12. The drain of the P-channel
SGT P2 of the inverter circuit IV2 is connected to the drains of
the N-channel SGTs N21 and N22. The gate of the P-channel SGT P2 is
connected to the gates of the N-channel SGTs N21 and N22. The drain
of the P-channel SGT P1 of the inverter circuit IV1 is connected to
the drains of the N-channel SGTs N11 and N12.
[0090] As illustrated in FIG. 1A, the sources of the P-channel SGTs
P1 and P2 are connected to a power supply terminal VDD. The sources
of the N-channel SGTs N11, N12, N21, and N22 are connected to a
ground terminal VSS. Selection N-channel SGTs SN1 and SN2 are
disposed on the two sides of the inverter circuits IV1 and IV2. The
gates of the selection N-channel SGTs SN1 and SN2 are connected to
a word line terminal WLt. The drain and source of the selection
N-channel SGT SN1 are connected to the drains of the N-channel SGTs
N11 and N12 and the P-channel SGT P1 and to an inversion bit line
terminal BLBt. The drain and source of the selection N-channel SGT
SN2 are connected to the drains of the N-channel SGTs N21 and N22
and the P-channel SGT P2 and to the bit line terminal BLt. As such,
a circuit that includes an SRAM cell (hereinafter referred to as an
"SRAM cell circuit") according to this embodiment is constituted by
a total of eight SGTs, namely, two P-channel SGTs P1 and P2 and six
N-channel SGTs N11, N12, N21, N22, SN1, and SN2.
[0091] FIG. 1B is a schematic diagram of the SRAM cell circuit
illustrated in FIG. 1A. The SRAM cell circuit is formed by using
four Si pillars H1, H2, H3, and H4.
[0092] As illustrated in FIG. 1B, a drive N-channel SGT N11 of the
inverter circuit IV1 is formed in a lower portion of the Si pillar
H1 and a selection N-channel SGT SN1 is formed in an upper portion
of the Si pillar H1. A drive N-channel SGT N12 of the inverter
circuit IV1 is formed in a lower portion of the Si pillar H2 and a
P-channel SGT P1 is formed in an upper portion of the Si pillar H2.
A drive N-channel SGT N22 of the inverter circuit IV2 is formed in
a lower portion of the Si pillar H3 and a P-channel SGT P2 is
formed in an upper portion of the Si pillar H3. A drive N-channel
SGT N21 is formed in a lower portion of the Si pillar H4 and a
selection N-channel SGT SN2 is formed in an upper portion of the Si
pillar H4.
[0093] As illustrated in FIG. 1B, in the drive N-channel SGT N11
disposed in the lower portion of the Si pillar H1, a N.sup.+ region
1a, a channel i-layer 2a, and a N.sup.+ region 3a are continuously
disposed next to one another in this order from the lower portion
toward the upper portion of the Si pillar H1. A gate insulating
layer 4a surrounds the channel i-layer 2a. A gate conductor layer
5a surrounds the gate insulating layer 4a.
[0094] In the selection N-channel SGT SN1 disposed in the upper
portion of the Si pillar H1, a N.sup.+ region 6a, a channel i-layer
7a, and a N.sup.+ region 8a are continuously disposed next to one
another in this order from the lower portion toward the upper
portion. A gate insulating layer 9a surrounds the channel i-layer
7a. A gate conductor layer 10a surrounds the gate insulating layer
9a. In the drive N-channel SGT N12 disposed in the lower portion of
the Si pillar H2, a N.sup.+ region 1b, a channel i-layer 2b, and a
N.sup.+ region 3b are continuously disposed next to one another in
this order from the lower portion toward the upper portion of the
Si pillar H2. A gate insulating layer 4b surrounds the channel
i-layer 2b. A gate conductor layer 5b surrounds the gate insulating
layer 4b. In the P-channel SGT P1 disposed in the upper portion of
the Si pillar H2, a P.sup.+ region 6b, a channel i-layer 7b, and a
P.sup.+ region 8b are continuously disposed next to one another in
this order from the lower portion toward the upper portion. A gate
insulating layer 9b surrounds the channel i-layer 7b. A gate
conductor layer 10b surrounds the gate insulating layer 9b.
[0095] As illustrated in FIG. 1B, in the drive N-channel SGT N22
disposed in the lower portion of the Si pillar H3, a N.sup.+ region
1c, a channel i-layer 2c, and a N.sup.+ region 3c are continuously
disposed next to one another in this order from the lower portion
toward the upper portion of the Si pillar H3. A gate insulating
layer 4c surrounds the channel i-layer 2c. A gate conductor layer
5c surrounds the gate insulating layer 4c. In the P-channel SGT P2
disposed in the upper portion of the Si pillar H3, a P.sup.+ region
6c, a channel i-layer 7c, and a P.sup.+ region 8c are continuously
disposed next to one another in this order from the lower portion
toward the upper portion. A gate insulating layer 9c surrounds the
channel i-layer 7c. A gate conductor layer 10c surrounds the gate
insulating layer 9c. In the drive N-channel SGT N21 disposed in the
lower portion of the Si pillar H4, an N.sup.+ region 1d, a channel
i-layer 2d, and an N.sup.+ region 3d are continuously disposed next
to one another in this order from the lower portion toward the
upper portion of the Si pillar H4. A gate insulating layer 4d
surrounds the channel i-layer 2d. A gate conductor layer 5d
surrounds the gate insulating layer 4d. In the selection N-channel
SGT SN2 disposed in the upper portion of the Si pillar H4, a
N.sup.+ region 6d, a channel i-layer 7d, and a N.sup.+ region 8d
are continuously disposed next to one another in that order from
the lower portion toward the upper portion. A gate insulating layer
9d surrounds the channel i-layer 7d. A gate conductor layer 10d
surrounds the gate insulating layer 9d.
[0096] As illustrated in FIG. 1B, the gate conductor layer 10b of
the P-channel SGT P1 of the inverter circuit IV1 is connected to
the gate conductor layer 5b and the gate conductor layer 5a of the
N-channel SGTs N11 and N12. The gate conductor layers 10b, 5b, and
5a are connected to the P.sup.+ region 6c of the P-channel SGT P2
and the N.sup.+ regions 3c and 3d of the drive N-channel SGTs N21
and N22. Likewise, the gate conductor layer 10c of the P-channel
SGT P2 of the inverter circuit IV2 is connected to the gate
conductor layers 5c and 5d of the drive N-channel SGTs N21 and N22.
The gate conductor layers 10c, 5c, and 5d are connected to the
P.sup.+ region 6b of the P-channel SGT P1 and the N.sup.+ regions
3a and 3b of the drive N-channel SGTs N11 and N12.
[0097] As illustrated in FIG. 1B, the P.sup.+ regions 8b and 8c of
the P-channel SGTs P1 and P2 are connected to a power source
terminal VDD. The N.sup.+ regions 1a, 1b, 1c, and 1d of the drive
N-channel SGTs N11, N12, N21, and N22 are connected to a ground
terminal VSS. The gate conductor layers 10a and 10d of the
selection N-channel SGTs SN1 and SN2 are connected to a word line
WLt. The N.sup.+ region 6a of the selection N-channel SGT SN1 is
connected to the N.sup.+ regions 3a and 3b of the N-channel SGTs
N11 and N12 and the P.sup.+ region 6b of the load P-channel SGT P1.
The N.sup.+ region 6d of the selection N-channel SGT SN2 is
connected to the N.sup.+ regions 3c and 3d of the drive N-channel
SGTs N21 and N22. The N.sup.+ region 8a of the selection N-channel
SGT SN1 is connected to an inversion bit line terminal BLBt. The
N.sup.+ region 8d of the selection N-channel SGT SN2 is connected
to a bit line terminal BLt. In the first embodiment, eight SGTs
constituting the SRAM cell are formed in four Si pillars H1, H2,
H3, and H4.
[0098] FIG. 1C is a schematic plan view of the arrangement of the
Si pillars H1, H2, H3, and H4 in the SRAM cell circuit illustrated
in FIGS. 1C and 1B as viewed in the perpendicular direction. As
illustrated in FIG. 1C, one SRAM cell is formed within a broken
line region 11 that includes the Si pillars H1, H2, H3, and H4. The
inverter circuit IV1 and the selection N-channel SGT SN1 are formed
within a two-dot chain line region 12a that includes the Si pillars
H1 and H2. The inverter circuit IV2 and the selection N-channel SGT
SN2 are formed within a two-dot chain line region 12b that includes
the Si pillars H3 and H4. Each of the Si pillars H5 and H6 includes
a drive N-channel SGT and a selection N-channel SGT of the SRAM
cell circuit. The two SGTs are adjacent to and in contact with each
other in the perpendicular direction. The Si pillars H1, H2, and H6
are arranged on a straight line extending in a horizontal
direction. The Si pillars H5, H3, and H4 are arranged on another
straight line extending in a horizontal direction. The Si pillars
H1 and H5 are arranged on a straight line extending in a
perpendicular direction and so are the Si pillars H2 and H3, and
the Si pillars H6 and H4. In a semiconductor device that includes
such an SRAM cell circuit, the SRAM cell in the broken line region
11 is two-dimensionally arranged on a substrate that extends in a
horizontal direction.
[0099] FIGS. 2AA to 2AC are respectively a plan view and
cross-sectional views that show a first production step of a method
for producing an SRAM cell circuit according to this embodiment
(the region shown in the plan view corresponds to the region where
the Si pillars H1 to H6 are arranged in FIG. 1C). FIG. 2AA is a
plan view, FIG. 2AB is a cross-sectional view taken along line X-X'
(corresponding to line X-X' in FIG. 1C), and FIG. 2AC is a
cross-sectional view taken along line Y-Y' (corresponding to line
Y-Y' in FIG. 1C). In FIGS. 2AA to 4DC, the drawings whose reference
ends with A, B, and C also respectively present the same types of
drawings.
[0100] The method for producing an SRAM cell circuit shown in FIGS.
1A, 1B, and 1C will now be described with reference to FIGS. 2AA to
2WC.
[0101] First, as illustrated in FIGS. 2AA to 2AC, a SiO.sub.2 layer
14 is formed on an i-layer substrate 13 by, for example, a thermal
oxidation process. Arsenic ions (As+) are implanted from above the
SiO.sub.2 layer 14 so as to form an N.sup.+ region 15 in a surface
layer portion of the i-layer substrate 13.
[0102] Then, as illustrated in FIGS. 2BA to 2BC, the SiO.sub.2
layer 14 is removed and an i-layer (intrinsic semiconductor layer)
16 is formed on the N.sup.+ region 15 by, for example, a
low-temperature epitaxial growth process. A SiO.sub.2 layer 17 is
formed on the i-layer 16 by, for example, a CVD process. Then
resist layers 18a and 18b are formed on the SiO.sub.2 layer 17 so
as to cover the regions where the Si pillars H5, H1, H4, and H6 are
to be formed. Boron ions (B.sup.+), which are acceptor impurity
ions, are implanted from above the upper surface of the i-layer
substrate 13 so as to form a P.sup.+ region 19 in the portion of
the i-layer 16 not covered with the resist layers 18a and 18b.
[0103] Then, as illustrated in FIGS. 2CA to 2CC, the resist layers
18a and 18b are removed and a resist layer 20 is formed on the
SiO.sub.2 layer 17 so as to cover the region where the Si pillars
H2 and H3 are to be formed. Arsenic ions (As.sup.+) serving as a
donor impurity are implanted from above the surface of the i-layer
substrate 13 so as to form N.sup.+ regions 21a and 21b in the
i-layer 16.
[0104] Then, as illustrated in FIGS. 2DA to 2DC, the SiO.sub.2
layer 17 is removed. An i-layer 22 is formed by, for example, a
low-temperature Si epitaxial growth process on the N.sup.+ regions
21a and 21b and the P.sup.+ region 19 uncovered as a result of
removal of the SiO.sub.2 layer 17. Subsequently, SiO.sub.2 layers
23a, 23b, 23c, 23d, 23e, and 23f are formed on the i-layer 22.
[0105] Then, as illustrated in FIGS. 2EA to 2EC, the i-layer 22,
the N.sup.+ regions 21a and 21b, the P.sup.+ region 19, the N.sup.+
region 15, and the i-layer substrate 13 are etched by, for example,
a reactive ion etching (RIE) process by using the SiO.sub.2 layers
23a, 23b, 23c, 23d, 23e, and 23f as an etching mask. As a result,
Si pillars H1 to H6 are formed (the positional relationship among
the Si pillars H1 to H6 corresponds to the positional relationship
among the Si pillars H1 to H6 in FIG. 1C). Consequently, in the Si
pillar H5, an i-layer 24a, an N.sup.+ region 25a, an N.sup.+ region
26a, an i-layer 27a, and a SiO.sub.2 layer 23a are formed at levels
higher than an i-layer substrate 13a. In the Si pillar H3, an
i-layer 24b, an N.sup.+ region 25b, a P.sup.+ region 26b, an
i-layer 27b, and a SiO.sub.2 layer 23b are formed at levels higher
than the i-layer substrate 13a. In the Si pillar H4, an i-layer
24c, an N.sup.+ region 25c, an N.sup.+ region 26c, an i-layer 27c,
and a SiO.sub.2 layer 23c are formed at levels higher than the
i-layer substrate 13a.
[0106] Next, as illustrated in FIGS. 2FA to 2FC, a SiO.sub.2 layer
is deposited by CVD on the i-layer substrate 13a and the Si pillars
H1 to H6. The entire SiO.sub.2 layer is etched by an isotropic
plasma etching process. As a result, the SiO.sub.2 layer on the
side walls of the Si pillars H1 to H6 are removed but SiO.sub.2
layers 28a, 28b, 28c, and 28d remain on the i-layer substrate 13a.
This process takes an advantage of the phenomenon that when a
SiO.sub.2 film is deposited by CVD, the deposited SiO.sub.2 film is
thinner on the side walls of the Si pillars H1 to H6 than on the
i-layer substrate 13a. Then SiO.sub.2 layers 29a, 29b, 29c, 29d,
29e, and 29f are formed on the outer peripheries of the Si pillars
H1 to H6 by a thermal oxidation process.
[0107] As illustrated in FIGS. 2GA to 2GC, arsenic ion (As.sup.+)
serving as a donor impurity are implanted into the upper surface of
the i-layer substrate 13a from above the i-layer substrate 13a so
as to form N.sup.+ regions 30a, 30b, 30c, and 30d in the surface
layer portion of the i-layer substrate 13a not covered by the Si
pillars H1 to H6. The N.sup.+ region 30a, 30b, 30c, and 30d are
continuously connected to one another in the surface layer portion
of the i-layer substrate 13a located outside the Si pillars H1 to
H6.
[0108] As illustrated in FIGS. 2HA to 2HC, the SiO.sub.2 layers
29a, 29b, 29c, 29d, 29e, and 29f on the outer peripheries of the Si
pillars H1 to H6 are removed and gate SiO.sub.2 layers 34a, 34b,
and 34c are formed on the outer peripheries of the Si pillars H1 to
H6 by a thermal oxidation process. Then a titanium nitride (TiN)
layer 32 serving as a gate conductor layer is formed on the entire
structure by, for example, an atomic layer deposition (ALD) process
and a SiO.sub.2 layer 35 is formed by a CVD process.
[0109] As illustrated in FIG. 2IA, a TiN layer 32b and a SiO.sub.2
layer 35b that cover the Si pillars H3 and H4 and are connected to
each other are formed by a lithographic process and a RIE process.
At the same time as forming the TiN layer 32b and the SiO.sub.2
layer 35b, a TiN layer 32a and a SiO.sub.2 layer 35a that cover the
Si pillar H5 are formed. The same process is conducted on the Si
pillars H1, H2, and H6 shown in FIG. 2IA so as to form TiN layers
32c and 32d and SiO.sub.2 layers 35c and 35d.
[0110] As illustrated in FIGS. 2JA to 2JC, for example, a silicon
nitride (SiN) layer 36 is formed on the i-layer substrate 13a so as
to be at a level lower than the top portions of the Si pillars H1
to H6. The surface of the SiN layer 36 comes within the range of
the length of the N.sup.+ regions 25a, 25b, and 25c of the Si
pillars H1 to H6 in the perpendicular direction.
[0111] As illustrated in FIGS. 2KA to 2KC, a resist layer 37 is
formed on the SiN layer 36. The resist layer 37 is planarized by
performing a heat treatment at about 200.degree. C., for example.
The surface of the resist layer 37 comes within the range of the
length of the N.sup.+ regions 26a and 26c and the P.sup.+ region
26b in the perpendicular direction. Then hydrogen fluoride gas
(hereinafter referred to as HF gas) is fed to the entire structure.
For example, when a heating environment of 180.degree. C. is
created, the HF gas diffuses into the resist layer 37, is ionized
by moisture contained in the resist layer 37, and forms hydrogen
fluoride ions (HF.sub.2.sup.+, hereinafter referred to as HF ions).
The HF ions diffuse into the resist layer 37 and partly etch the
SiO.sub.2 layers 35a and 35b in contact with the resist layer 37.
The parts of the SiO.sub.2 layers 35a and 35b not in contact with
the resist layer 37 are etched with HF ions (HF.sub.2.sup.+). The
parts of the SiO.sub.2 layers 35a and 35b not in contact with the
resist layer 37 are etched slower than the parts of the SiO.sub.2
layers 35a and 35b in contact with the resist layer 37 and thus
remain on the outer peripheries of the Si pillars H1 to H6. The
resist layer 37 is then removed (refer to Tadashi Shibata, Susumu
Kohyama, and Hisakazu lizuka: "A New Field Isolation Technology for
High Density MOS LSI", Japanese Journal of Applied Physics, Vol.
18, pp. 263-267 (1979) for the mechanism of etching described
here).
[0112] As illustrated in FIGS. 2LA to 2LC, the parts of the
SiO.sub.2 layers 35a, 35b, and 35i which have been in contact with
the resist layer 37 are removed by etching. As a result, openings
38a, 38b, and 38c that expose the TiN layers 32a and 32b are formed
on the outer periphery of the Si pillars H5, H3, and H4. At the
same time with formation of the openings 38a, 38b, and 38, the TiN
layers 32c and 32d in contact with the resist layer 37 are exposed
at the outer periphery of the Si pillars H1, H2, and H6 as well. As
a result, the lower portion and the upper portion of the SiO.sub.2
layer 35a are separated from each other in the Si pillar H5, and a
SiO.sub.2 layer 35e is formed in the lower portion. The lower
portion and the upper portion of the SiO.sub.2 layer 35b are
separated from each other in the Si pillar H3 and a SiO.sub.2 layer
35f is formed. The upper portion and the lower portion of the
SiO.sub.2 layer 35i are separated from each other in the Si pillar
H4 and the SiO.sub.2 layer 35f is formed. Similarly, a SiO.sub.2
layer 35g is formed in the lower portions of the Si pillars H1 and
H2 and a SiO.sub.2 layer 35h is formed in the lower portion of the
Si pillar H6.
[0113] As illustrated in FIGS. 2MA to 2MC, the TiN layers 32a, 32b,
32c, and 32d are etched by using the SiO.sub.2 layers 35a, 35b,
35i, 35e, and 35f as an etching mask. In the Si pillar H5, the
lower portion of the TiN layer 32a is separated and a TiN layer 32e
is formed as a result of this etching. In the Si pillar H3, the
lower portion of the TiN layer 32b is separated and a TiN layer 32f
is formed. In the Si pillar H4, the upper portion of the TiN layer
32b is separated and a TiN layer 32i is formed. Likewise, a TiN
layer 32g is formed in the lower portions of the Si pillars H1 and
H2. The TiN layer 32d of the Si pillar H6 is separated into a lower
portion and an upper portion.
[0114] As a result of the process described above, TiN layers 32e,
32f, 32g, and 32d are formed in the Si pillars H1 to H6 as
illustrated in FIG. 2MA.
[0115] Then, as illustrated in FIG. 2MB, the gate SiO.sub.2 layers
34a, 34b, and 34c are etched by using the TiN layers 32a, 32b, 32i,
32e, and 32f as an etching mask. During this etching, the SiO.sub.2
layers 35a, 35b, 35i, 35e, and 35f can be used as an etching mask
in addition to or instead of the TiN layers 32a, 32b, 32i, 32e, and
32f. When the thickness of the SiO.sub.2 layers 35a, 35b, and 35i
are adjusted to be larger than the thickness of the SiO.sub.2
layers 34a, 34b, and 34c, the SiO.sub.2 layers 35a, 35b, and 35i
can remain after etching of the gate SiO.sub.2 layers 34a, 34b, and
34c. Each of the gate SiO.sub.2 layers 34a, 34b, and 34c is
separated into a lower portion and an upper portion. SiO.sub.2
layers 34d, 34e, and 34f are formed in the lower portions.
[0116] Next, as illustrated in 2NB, the exposed portions of the TiN
layers 32a, 32b, 32i, 32e, and 32f are oxidized to form TiO layers
40a, 40b, 40c, 41a, 41b, and 41c composed of titanium oxide. A
SiO.sub.2 layer 42 is formed by CVD over the entire structure. The
deposited SiO.sub.2 layer 42 is relatively thin on the side walls
of the Si pillars H1 to H6 and is relatively thick on the top
portions of the Si pillars H1 to H6 and on the surface of the SiN
layer 36.
[0117] As illustrated in FIGS. 2OA to 2OC, a resist layer 43 is
formed by the same method as the method for forming the resist
layer 37. The upper surface of the resist layer 43 comes within the
length of the N.sup.+ regions 26a and 26c and P.sup.+ region 26b of
the Si pillars H5, H3, and H4 in the perpendicular direction. HF
gas is fed from above the Si pillars H1 to H6. As in the process
described above with reference to FIGS. 2KA to 2KC, the HF gas
absorbed in the resist layer 43 forms HF ions (HF.sub.2.sup.+) in
the resist layer 43 and the HF ions accelerate etching of the part
of the SiO.sub.2 layer 42 in contact with the resist layer 43
compared to etching of the part of the SiO.sub.2 layer 42 not in
contact with the resist layer 43.
[0118] Next, as illustrated in FIGS. 2PA to 2PC, when the resist
layer 43 is removed, the SiO.sub.2 layer 42 which has been in
contact with the resist layer 43 is etched. As a result, openings
44a, 44b, and 44c are formed on the side walls of the N.sup.+
regions 25a, 25b, 25c, 26a, and 26c and the P.sup.+ region 26b in
the Si pillars H5, H3, and H4. In the SiO.sub.2 layer 42, a
SiO.sub.2 layer 42d deposited on the SiN layer 36 is in contact
with the resist layer 43. Since the SiO.sub.2 layer 42d is thicker
than the SiO.sub.2 layers 42a, 42b, and 42c on the side walls of
the Si pillars H1 to H6, the SiO.sub.2 layer 42d remains on the SiN
layer 36.
[0119] Then as illustrated in FIGS. 2QA to 2QC, conductor layers
45a, 45b, 45c, and 45d formed by siliciding poly Si layers, for
example, are formed so as to connect to the N.sup.+ regions 25a,
25b, 25c, 26a, and 26c and the P.sup.+ region 26b. The conductor
layer 45b is formed so as to connect the N.sup.+ region 25b and the
P.sup.+ region 26b of the Si pillar H3 to the N.sup.+ regions 25c
and 26c of the Si pillar H4. The N.sup.+ regions 25a and 26a of the
adjacent Si pillar H5 of the SRAM cell are connected to the
conductor layer 45a. The conductor layer 45c connects the Si pillar
H1 to the Si pillar H2. The conductor layer 45d is connected to the
adjacent Si pillar H6 of the SRAM cell.
[0120] Next, as illustrated in FIGS. 2RA to 2RC, a SiN layer 46,
for example, is formed so that its surface comes at approximately
the center of the i-regions 27a, 27b, and 27c in the upper portions
of the Si pillars H1 to H6.
[0121] Next, as illustrated in FIGS. 2SA to 2SC, a resist layer is
formed by the same method as one described with reference to FIGS.
2KA to 2KC and 2OA to 2OC and HF gas is supplied from the upper
surface of the resist layer. As a result, the SiO.sub.2 layers 35a,
35b, 35c, 42a, 42b, and 42c on the side walls of the Si pillars H5,
H3, and H4 are etched and openings 60a, 60b, and 60c are formed.
Then, for example, conductor layers 47a, 47b, 47c, and 47d formed
by siliciding poly Si layers are formed by the same method as one
described with reference to FIGS. 2QA to 2QC. The conductor layer
47a is connected to the TiN layer 32a in the upper portion of the
Si pillar H5. The conductor layer 47b is connected to the TiN layer
32b in the upper portion of the Si pillar H3. The conductor layer
47d is connected to the TiN layer 32i in the upper portion of the
Si pillar H4. As illustrated in FIG. 2SA, the conductor layer 47a
is formed so as to connect the Si pillar H5 to the Si pillar H1 and
the conductor layer 47d is formed so as to connect the Si pillar H4
to the Si pillar H6.
[0122] As illustrated in FIGS. 2TA to 2TC, a resist layer 48 is
formed so that its surface comes at a position lower than the top
portions of the Si pillars H1 to H6.
[0123] As illustrated in FIGS. 2UA to 2UC, the SiO.sub.2 layers
42a, 42b, 42c, 35a, 35b, and 35c, the TiN layers 32a, 32b, and 32i,
and the gate SiO.sub.2 layers 34a, 34b, and 34c are etched by using
the resist layer 48 as an etching mask and the resist layer 48 is
removed. Ion implantation is conducted by using the SiO.sub.2
layers 42a, 42b, 42c, 35a, 35b, and 35c, the TiN layers 32a, 32b,
and 32i, and the gate SiO.sub.2 layers 34a, 34b, and 34c as ion
implantation stopper layers so as to form N.sup.+ regions 49a, 49c,
49d, and 49f in the top portions of the Si pillars H1, H4, H5, and
H6 and P.sup.+ regions 49b and 49e in the top portions of the Si
pillars H3 and H2.
[0124] As illustrated in FIGS. 2VA to 2VC, a SiO.sub.2 layer 50 is
formed over the entire structure by CVD and a contact hole 51a is
formed on the N.sup.+ region 49a in the top portion of the Si
pillar H5. A contact hole 51b is formed on the TiN layer 32e (the
conductor layer 47b is formed in the upper portion of the TiN layer
32e) in the lower portion connected to the outer periphery of the
Si pillar H3. A contact hole 51c is formed on the P.sup.+ region
49b in the top portion of the Si pillar H3 and a contact hole 51d
is formed on the conductor layer 45b. A contact hole 51e is formed
on the N.sup.+ region 49c in the top portion of the Si pillar H4. A
contact hole 51f is formed on the N.sup.+ region 49d in the top
portion of the Si pillar H1. A contact hole 51g is formed on the
conductor layer 45c, and a contact hole 51h is formed on the
P.sup.+ region 49e in the top portion of the Si pillar H2. Then the
contact hole 51b is formed on the TiN layer 32f (there is a
conductor layer 47c in the upper portion) in the lower portion and
a contact hole 51j is formed on the N.sup.+ region 49f in the top
portion of the Si pillar H6.
[0125] A bit line wiring metal layer BLa connected to the N.sup.+
region 49a in the top portion of the Si pillar H5 through the
contact hole 51a is formed. An inversion bit line wiring metal
layer BLBa connected to the N.sup.+ region 49d in the top portion
of the Si pillar H1 through the contact hole 51f is formed. Then a
metal wiring layer 52a that connects the TiN layer 32e in the lower
portion of the Si pillar H3 to the conductor layers 47b and 45c
through the contact holes 51b and 51g is formed. A power supply
wiring metal layer Vdd that connects the P.sup.+ regions 49b and
49e in the Si pillars H3 and H2 to each other through the contact
holes 51c and 51h is formed. Then a metal wiring layer 52b that
connects the TiN layer 32g in the lower portion of the Si pillar H2
to the conductor layers 47c and 45b through the contact holes 51d
and 51i is formed. A bit line wiring metal layer BLb connected to
the N.sup.+ region 49c in the top portion of the Si pillar H4
through the contact hole 51e is formed. An inversion bit line
wiring metal layer BLBb connected to the N.sup.+ region 49f in the
top portion of the Si pillar H6 through the contact hole 51j is
formed.
[0126] As shown in FIGS. 2WA to 2WC, an SiO.sub.2 layer 53 is
formed by CVD, contact holes 54a and 54b are formed on the
conductor layers 47a and 47d, and a word line metal wiring layer WL
connected to the conductor layers 47a and 47d through the contact
holes 54a and 54b is formed.
[0127] As described above, according to the method for producing a
semiconductor device shown in FIGS. 2AA to 2WC, an SRAM cell
circuit shown in the circuit diagram of FIG. 1A, a schematic
diagram of FIG. 1B, and the Si pillar arrangement diagram of FIG.
1C is formed.
[0128] According to the method for producing a semiconductor device
according to the first embodiment, the following effects 1 to 3 are
obtained, for example. [0129] 1. Openings 44a, 44b, and 44c in
contact with the N.sup.+ regions 25a, 25b, 25c, 26a, and 26c and
the P.sup.+ region 26b can be formed on the side walls of the Si
pillars H5, H3, and H4 (refer to FIGS. 2PA to 2PC) without using a
known lithographic technique for forming contact holes 112a, 112b,
112c, 112d, 114a, 114b, 132a, 132b, and 132c shown in FIGS. 6 and
7B. [0130] 2. Openings 60a, 60b, and 60c in contact with the TiN
layers 32a, 32b and 32i can be formed on the side walls of the Si
pillars H5, H3, and H4 (refer to FIGS. 2SA to 2SC) without using a
known lithographic technology. [0131] 3. TiN layers 32a and 32b on
the outer peripheries of the Si pillars H5, H3, and H4 can be
separated into TiN layers 32a, 32b, 32i, 32e, and 32f (refer to
FIGS. 2MA to 2MC) without using a known lithographic technique.
[0132] According to the method for producing an SRAM cell circuit
according to this embodiment, fine openings are highly accurately
formed by merely uniformly forming the resist layers 37 and 43
above the i-layer substrate. Accordingly, the lithographic process
which has been necessary for fine processing is no longer required
and the production process can be streamlined.
[0133] Formation of fine openings 38a, 38b, 38c, 44a, 44b, and 44c
is possible without using an expensive lithographic machine as has
been required in the related art, by merely adjusting the amount of
the resist applied. Accordingly, semiconductor devices can be
produced at lower costs.
[0134] According to the mechanism of the SiO.sub.2 layer etching by
using hydrogen fluoride (HF) (refer to Hirohisa Kikuyama, Nobuhiro
Miki, Kiyonori Saka, Jun Takano, Ichiro Kawanabe, Masayuki
Miyashita, Tadahiro Ohmi: "Principles of Wet Chemical Processing in
ULSI Microfabrication", IEEE Transactions on Semiconductor
Manufacturing, Vol. 4, No. 1, pp. 26-35 (1991)), HF is ionized in
the HF--H.sub.2O system (aqueous HF solution). HF ions are formed
by the reaction formula below and etch SiO.sub.2:
HF.fwdarw.H.sup.++F.sup.- (1)
HF+F.sup.-.fwdarw.HF.sub.2.sup.- (2)
SiO.sub.2+3HF.sub.2.sup.-+H.sup.+.fwdarw.SiF.sub.6.sup.2-+2H.sub.2O
(3)
[0135] Due to this reaction, HF ions (HF2- in this case) diffuse in
the resist layer 37 and etch parts of the SiO.sub.2 layers 35a,
35b, and 35i in contact with the resist layer 37. In contrast,
parts of the SiO.sub.2 layers 35a, 35b, and 35i not in contact with
the resist layer 37 are etched slowly by HF gas and thus remain on
the outer peripheries of the Si pillars H1 to H6. The resist layer
37 may be a layer composed of a material other than resist as long
as the material absorbs HF gas and allows HF ions generated from
the HF gas to diffuse therein.
Second Embodiment
[0136] A method for producing an SGT-including semiconductor device
according to a second embodiment will now be described with
reference to FIGS. 3AA to 3FC.
[0137] In the second embodiment, the same steps as those
illustrated in FIGS. 2AA to 2JC are performed prior to a step shown
in FIGS. 3AA to 3AC. The description therefor is thus omitted.
Subsequent to the step shown in FIGS. 2JA to 2JC, resist layers
61a, 61b, 61c, and 61d are formed by applying a resist sensitive to
light, an X-ray, or an electron beam and performing lithography, as
shown in FIGS. 3AA to 3AC. The resist layer 61a is formed so as to
surround the outer periphery of the Si pillar H5. The resist layer
61b is formed so as to come into contact with the Si-pillar-H4-side
side wall of the Si pillar H3 and surround the outer periphery of
the Si pillar H4. The resist layer 61c is formed so as to come into
contact with the side wall of the Si pillar H2 and surround the
outer periphery of the Si pillar H1. The resist layer 61d is formed
so as to surround the outer periphery of the Si pillar H6.
[0138] Then, as illustrated in FIGS. 3BA to 3BC, HF gas is supplied
to the reaction system. The HF gas diffuses in the resist layers
61a and 61b as described above and HF ions are generated due to the
moisture contained in the resist layers 61a and 61b. The HF ions
etch parts of the SiO.sub.2 layers 35a, 35b, and 35i in contact
with the resist layers 61a and 61b. The same process is performed
for the resist layer 61c in contact with the Si pillar H1 and the
Si pillar H2 and the resist layer 61d in contact with the Si pillar
H6. The resist layer 61a and the resist layer 61b are then removed.
The TiN layers 32a, 32b, and 32i are etched by using the SiO.sub.2
layers 35a, 35b, and 35i as an etching mask. The gate SiO.sub.2
layers 34a, 34b, and 34c are etched by using the TiN layers 32a,
32b, and 32i as an etching mask.
[0139] As a result, as illustrated in FIGS. 3CA to 3CC, openings
62a and 62c are formed on the outer peripheries of the N.sup.+
regions 25a, 25c, 26a, and 26c of the Si pillar H5 and the Si
pillar H4 and an opening 62b is formed in a part where the N.sup.+
region 25b and the P.sup.+ region 26b have been in contact with the
resist layer 61b, the part being a part of the outer periphery of
the Si pillar H3 in an outer periphery direction.
[0140] As illustrated in FIGS. 3DA to 3DC, the same process as one
described with reference to FIGS. 2NA to 2NC is performed to
oxidize the exposed portions of the TiN layers 32a, 32b, and 32i to
form TiO layers 40a, 65a, 40c, 41a, 65b, and 41c composed of
titanium oxide. Then a SiO.sub.2 layer 42 is deposited over the
entire structure by CVD. Here, the thickness of the deposited
SiO.sub.2 layer 42 is relatively small on the side walls of the Si
pillars H1 to H6 and relatively large on the top portions of the Si
pillars H1 to H6 and the surface of the SiN layer 36.
[0141] Then as illustrated in FIGS. 3EA to 3EC, the same process as
one described with reference to FIGS. 3AA to 3AC is performed to
apply a resist sensitive to light, an X-ray, or an electron beam
and a resist layer 63 is formed by lithography. The resist layer 63
is formed so as to surround the outer periphery of the Si pillar
H5, to be in contact with the Si-pillar-H4-side side wall of the Si
pillar H3, and to surround the outer periphery of the Si pillar H4.
Likewise, the resist layer 63 is formed so as to be in contact with
the side wall of the Si pillar H2 and surround the outer periphery
of the Si pillar H1. The resist layer 63 is formed so as to
surround the outer periphery of the Si pillar H6. Then HF gas is
supplied. The HF gas diffuses into the resist layer 63 and HF ions
are generated due to the moisture contained in the resist layer 63.
The HF ions etch part of the SiO.sub.2 layer 42 in contact with the
resist layer 63. The same process occurs in the resist layer 63 in
contact with the Si pillar H1 and the Si pillar H2 and the resist
layer 63 in contact with the Si pillar H6. The resist layer 63 is
then removed.
[0142] As illustrated in FIGS. 3FA to 3FC, conductor layers 63a,
63b, 63c, and 63d are formed. The conductor layer 63a is formed so
as to contact the N.sup.+ regions 25a and 26a of the Si pillar H5.
The conductor layer 63b is in contact with the N.sup.+ region 25b
and the P.sup.+ region 26b of the Si pillar H3 and the
N.sup.+regions 25c and 26c of the Si pillar H4 and extends across
the Si pillar H3 and the Si pillar H4. The conductor layers 63c and
63d are formed in the similar manner. Then the process illustrated
in FIGS. 2RA to 2RC, 2SA to 2SC, 2TA to 2TC, 2UA to 2UC, and 2VA to
2VC is performed.
[0143] As illustrated in FIGS. 3GA to 3GC, a contact hole 64a is
formed on the conductor layer 47b (in FIGS. 2VA to 2VC of the first
embodiment, the contact hole 51b that corresponds to the contact
hole 64a penetrates through the conductor layer 47b and is formed
on the TiN layer 32e). As a result, as with the method for
producing a semiconductor device according to the first embodiment,
an SRAM cell circuit shown in the circuit diagram of FIG. 1A, a
schematic diagram of FIG. 1B, and a Si pillar arrangement diagram
of FIG. 1C is formed.
[0144] As described above, according to the method for producing a
semiconductor device according to the second embodiment, a single
continuous TiN layer 32b extends across two SGTs located in the
upper portion and the lower portion of the Si pillar H3.
Accordingly, the gate conductor layers of two SGTs formed in upper
and lower portions of a Si pillar can connect to each other without
having a contact hole 64a penetrate through a conductor layer 47b
as in the method for producing a semiconductor device according to
the first embodiment (refer to FIGS. 2VA to 2VC).
Third Embodiment
[0145] A method for producing an SGT-including semiconductor device
according to a third embodiment will now be described with
reference to FIGS. 4AA to 4DC. In this embodiment, the technical
idea of the present invention is applied to an SGT-CMOS inverter
circuit. In FIGS. 4AA to 4DC, a drawing whose reference ends with A
is a plan view, a drawing whose reference ends with B is a
cross-sectional view taken along line X-X', and a drawing whose
reference ends with C is a cross-sectional view taken along line
Y-Y'.
[0146] As illustrated in FIG. 4AA to 4AC, Si pillars H10a and H10b
are formed on an i-layer substrate 66. A SiO.sub.2 layer 67 is
formed around the Si pillars H10a and H10b and on the i-layer
substrate 66. Gate insulating layers 68a and 68b are formed on the
outer peripheries of the Si pillars H10a and H10b and gate
conductor layers 69a and 69b composed of, for example, TiN are
formed on the outer peripheries of the gate insulating layers 68a
and 68b. A resist layer 70 is formed so as to cover the Si pillar
H10b and boron (B) ions are implanted by using the resist layer 70
as a mask. As a result, a P.sup.+ region 72a is formed in a top
portion of the Si pillar H10a and a P.sup.+ region 71a is formed in
a surface layer portion of the i-layer substrate 66 around the Si
pillar H10a.
[0147] As illustrated in FIGS. 4BA to 4BC, a resist layer 73 is
formed so as to cover the Si pillar H10a and arsenic (As) ions are
implanted by using the resist layer 73 as a mask. As a result, an
N.sup.+ region 72b is formed in a top portion of the Si pillar H10b
and an N.sup.+ region 71b is formed in a surface layer portion of
the i-layer substrate 66 around the Si pillar H10b.
[0148] As illustrated in FIGS. 4CA to 4CC, a SiO.sub.2 layer 74 is
deposited over the entire structure. A SiN layer 75 is formed so
that the surface thereof comes near the center portion of the gate
conductor layers 69a and 69b, for example. A resist layer 76 having
a particular thickness is formed on the SiN layer 75. HF gas is
supplied to the entire structure and a heating environment of about
180.degree. C. is created so as to diffuse the HF gas into the
resist layer 76 and ionize the HF gas by moisture inside the resist
layer 76. As a result, HF ions (HF.sub.2.sup.+) are formed. The HF
ions etch part of the SiO.sub.2 layer 74 in contact with the resist
layer 76. The resist layer 76 is removed. This process is the same
process as one described with reference to FIGS. 2JA to 2JC, 2KA to
2KC, and 2LA to 2LC.
[0149] As illustrated in FIGS. 4DA to 4DC, openings 77a and 77b
connecting to the gate conductor layers 69a and 69b are formed and
a conductor layer 78 that comes into contact with the gate
conductor layers 69a and 69b and connects the Si pillar H10a to the
Si pillar H10b is formed. A SiO.sub.2 layer 79 is formed over the
entire structure by CVD, a contact hole 80a is formed on the Si
pillar H10a, a contact hole 80b is formed on the conductor layer
78, a contact hole 80c is formed on the Si pillar H10b, and a
contact hole 80d is formed on the border line between the P.sup.+
region 71a and the N.sup.+ region 71b of the surface of the i-layer
substrate 66. A power supply wiring metal layer Vdd connected to
the P.sup.+ region 72a through the contact hole 80a is formed and
an input wiring metal layer Vin connected to the conductor layer 78
through the contact hole 80b is formed. A ground wiring metal layer
Vss connected to the N.sup.+ region 72b through the contact hole
80c is formed and an output wiring metal layer Vout connected to
the P.sup.+ region 71a and the N.sup.+ region 71b through the
contact hole 80d is formed. As a result, an SGT-including CMOS
inverter circuit is configured.
[0150] In the third embodiment, as illustrated in FIGS. 4AA to 4BC,
the P.sup.+ region 71a and the N.sup.+ region 71b are formed by ion
implantation after forming the gate conductor layers 69a and 69b.
In the first embodiment, as illustrated in FIGS. 2GA to 2GC, the
N.sup.+ region 30a, 30b, 30c, and 30d are formed by arsenic (As)
ion implantation into all parts of the surface after forming the Si
pillars H1 to H6 and the SiO.sub.2 layers 28a, 28b, 28c, 28d, 29a,
29b, and 29c. In the first embodiment, there is a risk that arsenic
ions reflected at the surface of the i-layer substrate 13a would
pass through the SiO.sub.2 layers 29a, 29b, and 29c and penetrate
the i-layers 24a, 24b, 24c, 27a, 27b, and 27c serving as channels,
thereby generating variation in properties of the SGTs. In
contrast, in the third embodiment, the channel Si pillars H10a and
H10b are surrounded by the gate conductor layers 69a and 69b
composed of TiN having a greater stopper effect (refer to FIGS. 4BA
to 4BC) and thus variation in properties of SGTs can be reduced.
The gate conductor layers 69a and 69b can each be formed of a TiN
single layer or a polycrystalline Si layer, or have a multilayer
structure constituted by a TiN layer and a layer of other metals.
Thus, variation in properties of SGTs can be further effectively
reduced.
[0151] As illustrated in FIGS. 4BA to 4BC, in the case where a
P.sup.+ region 71a and an N.sup.+ region 71b are formed by impurity
ion implantation after formation of the gate conductor layers 69a
and 69b and where the gate conductor layers 69a and 69b are
connected to each other with the conductor layer 78 through the
openings 77a and 77b on the side walls of the gate conductor layers
69a and 69b (refer to FIGS. 4DA to 4DC), the gate conductor layers
69a and 69b are formed so as to connect to each other above the
SiO.sub.2 layer 67 and then impurity ion implantation is performed.
In such a case, the P.sup.+ region 71a and the N.sup.+ region 71b
are not formed in the surface layer portion of the i-layer
substrate 66 under the conductor layer formed as a result of
connecting the gate conductor layers 69a and 69b to each other
above the SiO.sub.2 layer 67. Accordingly, the resistance in the
source or drain below the Si pillar H10a and the Si pillar H10b is
increased. In contrast, according to the production method of the
third embodiment, the P.sup.+ region 71a and the N.sup.+ region 71b
are formed in all parts of peripheries of the Si pillars H10a and
H10b and thus the resistance of the source or drain can be
decreased.
[0152] In the embodiments described above, examples in which
silicon (Si) pillars are used as semiconductor pillars are
described. The semiconductor pillars are not limited to these and
the technical idea of the present invention can be applied to
SGT-including semiconductor devices in which semiconductor pillars
composed of a semiconductor material other than silicon are
used.
[0153] In the embodiments described above, the cases in which one
or two SGTs are formed in one Si pillar are described. The
arrangement is not limited to this and the technical idea of the
present invention can be applied to a method for producing an
SGT-semiconductor device in which three or more SGTs are formed in
one semiconductor pillar.
[0154] As shown by the embodiments described above, gate SiO.sub.2
layers (gate insulating layer) 34a, 34b, and 34c are formed on the
outer peripheries of semiconductor pillars such as Si pillars H1 to
H6 and TiN layers (gate conductor layers) 32a, 32b, and 32c are
formed on the outer peripheries of the gate SiO.sub.2 layers 34a,
34b, and 34c to form SGTs. A flash memory element that includes
electrically floating conductor layers between the TiN layers 32a,
32b, and 32c and the gate SiO.sub.2 layers 34a, 34b, and 34c is
also a type of SGTs. Accordingly, the technical idea of the present
invention is also applicable to a method for producing a flash
memory element.
[0155] The technical idea of the present invention is also
applicable to a semiconductor device (for example, refer to
Japanese Unexamined Patent Application Publication No. 2010-232631)
in which an inner side of a semiconductor pillar serves as a first
channel and a semiconductor layer that surrounds the semiconductor
pillar serving as the first channel serves as a second channel.
[0156] In the first embodiment, openings 38a, 38b, and 38c are
formed in the source and drain impurity regions of the Si pillars
H1 to H6 in which SGTs are formed or in side walls of the TiN
layers (gate conductor layers) 32a, 32b, and 32c. However, the
arrangement is not limited to this. The technical idea of the
present invention is also applicable to the case in which the gate
SiO.sub.2 layers 34a, 34b, and 34c are left unetched and the gate
conductor layers 32a, 32b, and 32c are separated from each other
merely by the side walls of the Si pillars H1 to H6 by the process
illustrated in FIGS. 2KA to 2KC and 2LA to 2LC. The same applies to
other embodiments of the present invention. Gate conductor layers
can be separated easily at particular positions in the
perpendicular direction of a semiconductor pillar.
[0157] In the embodiments described above, the case in which only
SGTs are formed in semiconductor pillars (Si pillars H1 to H6) is
described. However, the technical idea of the present invention is
applicable to methods for producing semiconductor devices in which
SGTs and other elements (for example, photodiodes) are
incorporated.
[0158] In FIGS. 2HA to 2HC illustrating the first embodiment, an
example in which a gate conductor layer composed of TiN is used is
described. Alternatively, the gate conductor layer may be composed
of any other metal material. The gate conductor layer may have a
multilayer structure that includes this metal layer and a
polysilicon layer, for example. The same applies to other
embodiments of the present invention.
[0159] In FIGS. 2KA to 2KC illustrating the first embodiment,
formation of a SiN layer 36 having a low etching rate for HF ions
under a resist layer 37 is described. Alternatively, the layer 36
may be composed of any other material that has a low etching rate
for HF ions instead of SiN. The same applies to the SiN layer 46
and to other embodiments of the present invention.
[0160] In FIGS. 2KA to 2KC illustrating the first embodiment, a SiN
layer 36 having a low etching rate for HF ions is formed under the
resist layer 37. Alternatively, the layer 36 may be a SiO.sub.2
layer composed of the same material as the SiO.sub.2 layers 35a,
35b, and 35i. In such a case, the depth the layer 36 composed of
SiO.sub.2 is etched is the same as the depth the SiO.sub.2 layers
35a, 35b, and 35i are etched. Since the thickness of the SiO.sub.2
layers 35a and 35b is small, the depth the SiO.sub.2 layer is
etched is also small and thus the upper surface of the SiO.sub.2
layer after etching comes within the range of the heights of the
N.sup.+ regions 25a, 25b, and 25c in the Si pillars H1 to H6. As
long as an SGT-including semiconductor device according to the
technical idea of the present invention can be realized, the SiN
layer 36 may be replaced by a layer of any other material (for
example, SiO.sub.2) that can be etched by HF ions. This also
applies to other embodiments of the present invention.
[0161] In the embodiments described above, SOI substrates each
constituted by an i-layer substrate and an insulating substrate
attached to the bottom of the i-layer substrate can be used as the
i-layer substrates 13, 13a, and 13b. In such a case, the insulating
substrate and impurity regions formed in the i-layer substrate
surface (in FIGS. 2AA to 2WC, N.sup.+ region 30a, 30b, 30c, and
30d) may be or not be in contact with the insulating substrate.
[0162] In FIGS. 2AA to 2WC illustrating the first embodiment, the
i-layer substrate 13 and other layers are composed of Si.
Alternatively, the technical idea of the present invention is
applicable to the case in which other semiconductor material layers
are used. This applies to other embodiments as well.
[0163] The resist layers 37 and 43 shown in FIGS. 2KA to 2KC and
2OA to 2OC illustrating the first embodiment and the resist layer
76 illustrated in FIGS. 4CA to 4CC need not be subjected to
patterning. Accordingly, the material therefor is not limited to
cyclic rubber materials (negative type) and novolac materials
(positive type) frequently used in photolithography, or resist
materials used in X-ray or electron beam lithography. Usually, most
of organic materials have some degree of water-absorbency. Most of
organic materials can be applied evenly onto objects such as the
SiN layer 36. Any of such organic materials can be used instead of
resist materials such as cyclic rubber materials (negative type)
used in photolithography as long as the organic materials allow
formation and diffusion of HF ions within the layers of the organic
materials. The same applies to other embodiments of the present
invention as well.
[0164] The resist layers 37 and 43 shown in FIGS. 2KA to 2KC and
2OA to 2OC illustrating the first embodiment and the resist layer
76 shown in FIGS. 4CA to 4CC may be composed of an inorganic
material, such as porous polysilicon, as long as the inorganic
material has an appropriate degree of water absorbency. Inorganic
materials that allow formation and diffusion of HF ions within the
layers can also be used. The same applies to other embodiments of
the present invention.
[0165] The patterned resist layers 61a, 61b, 61c, 61d, 63b, 63b,
63c, and 63d shown in FIGS. 3BA to 3BC and 3EA to 3EC illustrating
the second embodiment need not be composed of a resist material
used in light, X-ray, or electron beam lithography and may be
composed of any material as long as the layers can be used to form
openings of the desired shapes. This applies to other embodiments
of the present invention as well.
[0166] In the second embodiment, the HF ions formed within the
resist layers 37 and 43 may be used to etch not only the SiO.sub.2
layers 35a, 35b, and 35c but also oxide films composed of other
materials. Accordingly, oxide films composed of other materials,
such as TiO or TaO, that can be etched with hydrofluoric acid (HF)
can be used instead of the SiO.sub.2 layers 35a, 35b, and 35c.
[0167] In FIGS. 2HA to 2HC illustrating the first embodiment, the
gate SiO.sub.2 layers 34a, 34b, and 34c formed by thermal oxidation
are used as the gate insulating layers. Alternatively, high-K
dielectric layers composed of, for example, hafnium oxide
(HfO.sub.2) can be used as the gate insulating layers. The same
applies to other embodiments of the present invention.
[0168] The SiN layer 36 shown in FIGS. 2JA to 2JC illustrating the
first embodiment may have a two-layer structure constituted by a
SiN layer and a polysilicon layer on the SiN layer. In this case,
the polysilicon that has a lower etching rate for the hydrofluoric
acid comes into contact with the resist layer 37 and thus
separation of the resist layer 37 during etching of the SiO.sub.2
layers 35a, 35b, and 35c is reduced. This applies to other
embodiments of the present invention as well.
[0169] In FIGS. 2AA to 2WC illustrating the first embodiment, the
conductor layers 45a, 45b, 45c, and 45d in contact with the N.sup.+
regions 25a, 25b, 25c, 26a, and 26c and the P.sup.+ region 26b that
lie in the middle portions of the Si pillars H1 to H6 and the
conductor layers 47a, 47b, and 47c in contact with the conductor
layers 32a, 32b, and 32i are formed on the same i-layer substrate
13a. Alternatively, the technical idea of the present invention is
applicable to the case in which the conductor layers 45a, 45b, 45c,
and 45d and/or the conductor layers 32a, 32b, and 32i are
formed.
[0170] Various other embodiments and modifications are possible
without departing from the broad spirit and scope of the present
invention. The embodiments presented above are merely examples of
the present invention and do not limit the scope of the present
invention. The embodiments and modifications can be freely
combined. Omitting some of the features of the embodiments
described above according to need is also within the technical idea
of the present invention.
[0171] According to a method for producing an SGT-including
semiconductor device of the present invention, a highly integrated
semiconductor device can be obtained.
* * * * *