U.S. patent application number 15/244521 was filed with the patent office on 2017-02-09 for method and system for managing a writing cycle of a data in a eeprom memory cell.
The applicant listed for this patent is STMicroelectronics (Rousset) SAS. Invention is credited to Marc Battista, Francois Tailliet.
Application Number | 20170040060 15/244521 |
Document ID | / |
Family ID | 55178051 |
Filed Date | 2017-02-09 |
United States Patent
Application |
20170040060 |
Kind Code |
A1 |
Tailliet; Francois ; et
al. |
February 9, 2017 |
Method and System for Managing a Writing Cycle of a Data in a
EEPROM Memory Cell
Abstract
An operation for writing at least one datum in at least one
memory cell of the electrically erasable and programmable read-only
memory type comprises at least one step of erasing or of
programming of the cell by a corresponding erasing or programming
pulse. The correct or incorrect conducting of the writing operation
is checked by an analysis of the form of the erasing or programming
pulse during the corresponding erasing or programming step. The
result of this analysis is representative of the writing operation
being conducted correctly or incorrectly.
Inventors: |
Tailliet; Francois; (Fuveau,
FR) ; Battista; Marc; (Marseille, FR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics (Rousset) SAS |
Rousset |
|
FR |
|
|
Family ID: |
55178051 |
Appl. No.: |
15/244521 |
Filed: |
August 23, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15055552 |
Feb 27, 2016 |
9455034 |
|
|
15244521 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G11C 16/14 20130101;
G11C 16/30 20130101; G11C 16/3436 20130101; G11C 16/08 20130101;
G11C 16/3445 20130101; G11C 16/3459 20130101; G11C 16/10 20130101;
G11C 16/32 20130101 |
International
Class: |
G11C 16/10 20060101
G11C016/10; G11C 16/08 20060101 G11C016/08; G11C 16/14 20060101
G11C016/14; G11C 16/30 20060101 G11C016/30 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 6, 2015 |
FR |
1557576 |
Claims
1. A method comprising: activating a high voltage generator to
produce a voltage pulse, the high voltage generator receiving its
input voltage from a power source; analyzing a form of the voltage
pulse; and determining whether the input voltage of the high
voltage generator is low or good based on the analyzing the form of
the voltage pulse.
2. The method of claim 1, wherein the analyzing a form of the
voltage pulse comprises determining a time for an output of the
high voltage generator to reach a predetermined voltage
threshold.
3. The method of claim 2, wherein the determining whether the input
voltage of the high voltage generator is low or good comprises:
comparing the determined time with a predetermined time;
determining that the input voltage of the high voltage generator is
low when the determined time is longer than the predetermined time;
and determined that the input voltage of the high voltage generator
is good when the determined time is shorter or equal to the
predetermined time.
4. The method of claim 2, wherein the predetermined voltage
threshold comprises 15 V.
5. The method of claim 1, wherein the analyzing the form of the
voltage pulse comprises determining a time of a plateau of the
voltage pulse.
6. The method of claim 5, wherein the determining whether the input
voltage of the high voltage generator is low or good comprises:
comparing the determined time of the plateau with a predetermined
plateau time: determining that the input voltage of the high
voltage generator is low when the determined time of the plateau is
shorter than the predetermined plateau time; and determined that
the input voltage of the high voltage generator is good when the
determined time of the plateau is longer or equal to the
predetermined plateau time.
7. The method of claim 6, wherein the predetermined plateau time
comprises 80% of a plateau time of a pulse generated with a typical
input voltage.
8. The method of claim 1, wherein the voltage pulse is used to
write a datum to a memory cell.
9. The method of claim 1, further comprising: providing an
indication of whether the input voltage of the high voltage
generator is low or good based on the determining whether the input
voltage of the high voltage generator is low or good.
10. A circuit comprising: a first circuitry: a charge pump
configured to provide a voltage pulse, the charge pump comprising
an input voltage node configured to be coupled to a power source,
and an output voltage node coupled to the first circuitry; and a
check circuitry configured to determine whether a voltage of the
input voltage node is low or good based on a form of the voltage
pulse.
11. The circuit of claim 10, wherein the first circuitry comprises
a memory device.
12. The circuit of claim 11, wherein the voltage pulse is used to
program the memory device.
13. The circuit of claim 10, wherein the check circuitry comprises
a timer.
14. The circuit of claim 13, wherein the timer comprises a digital
timer.
15. The circuit of claim 10, wherein the voltage pulse comprising a
plateau; and the check circuitry is configured to determine whether
the voltage of the input voltage node is low or good based on a
duration of the plateau.
16. The circuit of claim 10, further comprising the power
source.
17. The circuit of claim 16, wherein the power source comprises a
battery.
18. The circuit of claim 17, wherein the check circuitry is further
configured to indicate a level of charge of the battery.
19. A device comprising: a first circuitry; a high voltage
generator coupled to the first circuitry, the high voltage
generator configured to generate a pulse; a battery coupled to the
high voltage generator; and a check circuitry configured to
determine a level of charge of the battery based on a form of the
pulse.
20. The device of claim 19, wherein the first circuitry comprises a
non-volatile memory cell; and the high voltage generator comprises
a charge pump.
21. The device of claim 20, wherein the non-volatile memory cell
comprises an EEPROM.
Description
[0001] This application is a continuation of U.S. patent
application Ser. No. 15/055,552, filed Feb. 27, 2016 which
application claims priority to French Application No. 1557576,
filed on Aug. 6, 2015, which applications are hereby incorporated
herein by reference.
TECHNICAL FIELD
[0002] Implementations and embodiments of the invention relate to
the electrically erasable and programmable read-only memories,
called EEPROM memories, and more particularly the checking of the
correct or incorrect conducting of the writing operation.
SUMMARY
[0003] The invention applies advantageously but in a non-limiting
manner to the checking of the level of charge of a power supply,
for example a battery or battery cells, powering an apparatus
incorporating one or more of these memories. Such is the case for
example with auditory prostheses which prove particularly "greedy"
in battery cells. Also, having an indicator of the level of charge
of these battery cells would make it possible to change them only
when necessary, particularly when the level of charge no longer
makes it possible, for example, to conduct a writing operation in
the EEPROM memory correctly.
[0004] According to one implementation and embodiment, a novel
solution is proposed that is simple to implement, for detecting the
correct or incorrect conducting of a writing operation in a memory
cell of the EEPROM type and thus provide an indication of a level
of charge, low or good, of the power supply powering the memory
cell and its associated circuitry.
[0005] A memory cell of the EEPROM type generally comprises a
transistor having a floating gate that makes it possible to store
the datum, a control gate, a source region and a drain region. Such
a memory cell uses the principle of the non-volatile storage of
charges on the floating gate of the transistor. Conventionally, the
operation or cycle of writing a datum comprises an erasing step
followed by a programming step.
[0006] The programming is done by Fowler-Nordheim effect by using a
voltage pulse comprising a ramp followed by a voltage plateau
having a high value, typically of the order of 13 to 15 volts, and
comprises the injection by electron tunnel effect from the floating
gate to the drain while the erasing, which is also performed by
Fowler-Nordheim effect, comprises an injection by electron tunnel
effect from the drain to the floating gate and is also performed by
using an erasing pulse of a form similar to that of the programming
pulse.
[0007] According to one aspect, a method is proposed for checking
an operation for writing at least one datum in at least one memory
cell of the electrically erasable and programmable read-only memory
type, comprising at least one step of erasing or programming of the
cell by a corresponding erasing or programming pulse.
[0008] In effect, in certain cases, based on the logic value of the
datum or of the word to be written, the writing operation may
comprise only an erasing step or only a programming step.
[0009] Thus, if for example the word to be written contains only
"0"s, then only an erasing step is necessary.
[0010] Similarly, when the word 0F (in hexadecimal notation) has to
be replaced by the word 1F, the erasing step is pointless.
[0011] The method according to this aspect also comprises an
analysis of the form of the erasing or programming pulse during the
corresponding erasing or programming step, the result of this
analysis being representative of the writing operation being
conducted correctly or incorrectly.
[0012] Thus, whereas in the prior art an EEPROM cell is written
"blind", that is to say that the writing operation is
non-algorithmic and without any checking during the actual writing
operation, the method according to this aspect provides for a check
to be performed during the writing operation (erasing step or
programming step) by analysing the form of the corresponding
erasing or programming pulse.
[0013] Also, such an analysis is simpler to implement than a
conventional check of a correct or incorrect write that provides,
after the writing, a rereading of the written datum with modified
reading parameters.
[0014] When the writing operation comprises the step of erasing
followed by the step of programming of the cell, the method further
comprises an analysis of the form of each of the pulses during the
corresponding step, the result of this analysis being
representative of the writing operation being conducted correctly
or incorrectly.
[0015] A nominal erasing pulse and/or a nominal programming pulse
comprises a ramp followed by a plateau having a nominal voltage,
and the form analysis then advantageously comprises a determination
of the duration of the plateau, a plateau having a duration less
than a limit duration being representative of the writing operation
being conducted incorrectly.
[0016] According to one implementation, the determination of the
duration of the plateau comprises a determination of the instant of
occurrence of the plateau and a comparison of this instant of
occurrence with a reference instant corresponding to a percentage
of the duration of the corresponding nominal pulse, an instant of
occurrence less than or equal to the reference instant being
representative of the writing operation being conducted correctly
and an instant of occurrence greater than the reference instant
being representative of the writing operation being conducted
incorrectly.
[0017] The reference instant corresponds, for example, to 80% of
the duration of the nominal pulse.
[0018] According to another aspect, an application of the method as
defined hereinabove is proposed for the checking of the level of
charge of a power supply powering a memory device containing at
least one memory cell of the EEPROM type.
[0019] According to another aspect, a memory device is proposed
that comprises a memory plane containing at least one memory cell
of the electrically erasable and programmable read-only memory type
and check circuitry configured to check the conducting of an
operation for writing at least one datum in the at least one memory
cell comprising at least one step of erasing or of programming of
the cell by a corresponding erasing or programming pulse, the check
circuitry comprising analysis circuitry configured to perform an
analysis of the form of the erasing or programming pulse during the
corresponding erasing or programming step and deliver an indication
representative of the writing operation being conducted correctly
or incorrectly as a function of the result of this analysis.
[0020] According to an embodiment in which the writing operation
comprises the step of erasing followed by the step of programming
of the cell, the analysis circuitry is configured to perform an
analysis of the form of each of the pulses during the corresponding
step, and deliver the indication representative of the writing
operation being conducted correctly or incorrectly as a function of
the result of this analysis.
[0021] According to an embodiment in which a nominal erasing pulse
and/or a nominal programming pulse comprises a ramp followed by a
plateau having a nominal voltage, the analysis circuitry comprises
determination circuitry configured to determine the duration of the
plateau, a plateau having a duration less than a limit duration
being representative of the writing operation being conducted
incorrectly.
[0022] According to an embodiment, the determination circuitry
comprises a detection module configured to detect the instant of
occurrence of the plateau and a comparator configured to compare
this instant of occurrence with a reference instant corresponding
to a percentage of the duration of the corresponding nominal pulse,
an instant of occurrence less than or equal to the reference
instant being representative of the writing operation being
conducted correctly and an instant of occurrence greater than the
reference instant being representative of the writing operation
being conducted incorrectly.
[0023] According to another aspect, an apparatus is proposed that
comprises a memory device as defined hereinabove, a power supply
configured to power the memory device, and a level indicator for
indicating the level of charge of the power supply, the level
indicator incorporating the check circuitry.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Other advantages and features of the invention will become
apparent on studying the detailed description of non-limiting
implementations and embodiments, and the attached drawings in
which:
[0025] FIGS. 1 to 6 schematically illustrate different
implementations and embodiments of the invention.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0026] In FIG. 1, the reference APP denotes an apparatus, for
example an auditory prosthesis, comprising a power supply ALM, for
example a battery or cells, notably powering a non-volatile memory
device DIS of the EEPROM type.
[0027] The memory device DIS also comprises check circuitry MCTRL
configured, as will be seen in more detail hereinbelow, for
checking the conducting of an operation for writing a datum in at
least one memory cell of the memory plane PM of the memory device,
and providing an indication IND representative of the level of
charge of the power supply ALM.
[0028] The apparatus APP also incorporates indication circuitry
MDNCH, incorporating the check circuitry MCTRL and, for example, a
microcontroller, and intended to provide, in the presence of the
indication IND, an audible alert for example, in particular one or
several regular "beeps" using a mini loudspeaker HP.
[0029] In practice, and as a non-limiting example, as long as the
mini loudspeaker is silent, the battery cells need not be changed.
However, when the "beep" or "beeps" is/are emitted, the cells ALM
are to be changed.
[0030] In practice, the microcontroller and the mini loudspeaker
are already generally present in an auditory prosthesis and can
also be associated with a signal processing processor. In this
case, it is easy to embed a "system" sound in the auditory content
delivered in the ear and the audible alert can be not only one or
more "beeps" but also, for example, a specific phrase such as
"please change the batteries".
[0031] The memory plane PM, of a structure that is conventional and
known per se, comprises memory cells CEL of EEPROM type.
[0032] A column decoder XDCD and a row decoder YDCD make it
possible to address the memory plane PM.
[0033] These decoders are themselves addressed by an address shift
register ADRG.
[0034] The memory device DIS also comprises a data shift register
DRG connected to the memory plane by the column decoder XDCD.
[0035] The addresses and data can be entered by the address ADRG
and data DRG registers respectively and the data can be extracted
via the data register DRG.
[0036] The memory device DIS also comprises a status register SRG
linked to the data register DRG.
[0037] All of the circuity is controlled by a control logic LG.
[0038] Finally, high voltage generator MGHV notably comprising a
charge pump and its associated regulation, make it possible to
generate the high voltage, typically of the order of 15 volts, to
allow the operation for writing data in the memory, typically
comprising an erasing step followed by a programming step.
[0039] It is recalled here that a memory cell of the EEPROM type
comprises a transistor that conventionally has a control gate, a
floating gate, a drain region and a source region.
[0040] Such a cell is erasable and programmable by Fowler-Nordheim
effect.
[0041] As indicated hereinabove, the writing of a datum in such a
cell of EEPROM type generally comprises an erasing step preceding a
programming step.
[0042] In the erasing step, the drain and the source of the
transistor are coupled to the ground and a control voltage having
an erasing value, typically of the order of 15 volts, is applied to
the control gate.
[0043] As for the programming of the cell, it is performed
conventionally by linking the control gate to the ground and by
applying a programming voltage to the drain, typically also of the
order of 15 volts. With regard to the source, the source can either
be left floating or precharged to a non-zero precharge voltage.
[0044] Although a memory cell of the EEPROM type has two main
operating modes, namely a reading mode and a writing mode, the
writing operation is the first to be defective when the power
supply voltage Vdd decreases to a very low level. In effect, the
erasing step or the programming step requires the internal
generation of the high voltage, typically 15 volts, through a
number of charge pump stages.
[0045] Thus, while the reading operation may be functionally
correct up to 1.3 volts, the writing operation is generally
considered as correct up to 1.6 volts and can then be degraded from
1.6 volts to 1.4 volts to be immediately considered defective below
1.4 volts.
[0046] Moreover, a cell written in a degraded operating mode may be
read correctly at the instant t=0 and may then be defective just
after.
[0047] FIG. 2 illustrates a writing operation implemented by the
use of an erasing pulse IMP1 followed by a programming pulse IMP2.
The maximum value of the duration of the writing operation,
substantially equal to the sum of the durations of the pulses IMP1
and IMP2, is included in the specifications of the memory.
[0048] Each voltage/time pulse exhibits a ramp which controls the
tunnel current of the cell, followed by a plateau PLT, typically at
a nominal level of 15 volts.
[0049] FIG. 3 is a zoom of one of the pulses IMP1 or IMP2 and this
pulse IMPN here represents a nominal pulse of trapezoidal form
having a plateau of nominal characteristics PLTN. In the nominal
case, the duration of the pulse IMPN is fixed, equal for example to
1.5 ms and the duration of the plateau PLTN is for example equal to
1 ms.
[0050] As indicated above, while the writing operation generally
comprises an erasing step followed by a programming step, it is
possible, in certain cases, for a single erasing or programming
step to be necessary to write a word in the memory.
[0051] Thus, if the word to be written contains only "0"s, then
only an erasing step is necessary.
[0052] Similarly, when the word 0F (in hexadecimal notation) has to
be replaced by the word 1F, the erasing step is pointless.
[0053] As indicated above, the high voltage generation generator
that allows for the generation of the pulses IMP1 and/or IMP2
comprise one or more charge pump stages associated with a charge
pump regulation comprising, for example, an oscillator.
[0054] The regulation makes it possible to check the output voltage
of the charge pump. The oscillator is stopped when the output of
the charge pump exceeds a high reference. The output voltage of the
charge pump then begins to decay because of the charge. As soon as
the output voltage of the charge pump is less than a low reference,
the oscillator restarts. The voltage difference between the low and
high references (hysteresis) ensures the stability. This voltage
difference is for example of the order of 100 millivolts.
[0055] The regulation level of the charge pump is for example the
voltage level of the plateau PLT, for example 15 volts. The charge
ramp is for example generated by an analogue integrator which
receives the plateau voltage as input.
[0056] The duration of the pulse (ramp+plateau) is controlled by an
analogue or digital timer.
[0057] By way of indication, a digital timer can comprise an
oscillator of fixed frequency connected to a counter. The counter
starts when the charge pump starts and the end of the counting
marks the end of the pulse.
[0058] As is the conventional practice, the programming or erasing
pulse, generated by the charge pump stage or stages and the
associated regulation, is applied to a circuit exhibiting a
capacitive charge and leakage currents.
[0059] When the power supply voltage drops, the fan-out from the
charge pump drops greatly.
[0060] Also, when the fan-out from the charge pump is low, its
current can for example be less than the current needed for the
capacitive charge, in which case the ramp takes on an appearance of
the type of that illustrated in FIG. 4, slowing down and taking a
curved form, the plateau being naturally shortened.
[0061] When the fan-out from the charge pump is low, its current
may also be less than the leakage currents and the nominal voltage
of the plateau is not then reached.
[0062] These two alternatives can also be aggregated.
[0063] According to one aspect of the invention, the correct or
incorrect conducting of the operation for writing a datum in a
memory cell, or more generally the correct or incorrect conducting
of the writing of at least one word in the memory plane PM will be
checked by analysing, during the writing operation, the form of the
erasing pulse and/or of the programming pulse during the
corresponding erasing and/or programming step.
[0064] In this respect, this form analysis can advantageously be
implemented by a determination of the duration of the plateau of
the corresponding pulse.
[0065] Thus, a plateau having a duration less than a limit duration
is representative of the writing operation being conducted
incorrectly.
[0066] To determine this plateau duration, it is possible for
example to determine the instant of occurrence of the plateau, that
is to say the instant at which the ramp ends, that is to say the
instant at which the voltage level of the pulse reaches the level
of the plateau.
[0067] Furthermore, this is possible notably because the erasing or
programming pulse generation circuitry makes it possible to detect
the instant at which the plateau is reached, that is to say the
moment when the instantaneous amplitude of the pulse during the
ramp reaches the fixed set point of maximum amplitude of the pulse
(which is that of the plateau).
[0068] It is then possible to compare this instant of occurrence
with a reference instant which corresponds to a percentage of the
duration of the corresponding pulse, for example 80% of the
duration of a nominal pulse.
[0069] Also, if this instant of occurrence is less than or equal to
the reference instant, then the conducting of the writing operation
is considered to be correct whereas, if this instant of occurrence
is greater than the reference instant, then the conducting of the
writing operation is considered to be incorrect.
[0070] This will be illustrated in more detail with reference more
particularly to FIGS. 4 and 5.
[0071] In these figures, it is considered that there is a low power
supply voltage situation leading to a limitation of the charge
pump.
[0072] As explained hereinabove, the ramp is then slower than the
rectilinear ramp of the nominal case and has the form of a charge
curve of a resistive-capacitive circuit RC.
[0073] In these two figures, treg denotes the instant of occurrence
of the plateau and tref denotes the reference instant equal to a
percentage of the nominal duration of a pulse, for example 80% of
1.5 ms.
[0074] In FIG. 4, it can be seen that the instant of occurrence
treg of the plateau PLTB of the pulse IMPB is situated before the
instant tref. In this case, the duration of the plateau PLTB is
considered to be sufficient to ensure a correct writing of the word
in the memory.
[0075] In this situation, the writing operation is therefore
considered to be conducted correctly.
[0076] By contrast, in FIG. 5, the instant of occurrence treg of
the plateau PTM of the pulse IMPM is situated after the reference
instant tref.
[0077] Consequently, the duration of the plateau PLTM is
insufficient to ensure a correct writing of the word in the memory
and therefore the writing operation is considered to be conducted
incorrectly.
[0078] The reference instant tref is for example determined in the
factory during the memory characterization phase.
[0079] In practice, as illustrated in FIG. 6, the analysis
circuitry MAL configured to analyse the form of the erasing and/or
programming pulse comprises a detection module MCM configured to
detect the instant treg from the output voltage of the assembly PCH
(charge pump+regulation).
[0080] At this instant, the value of the counter CPT is read and
stored for example in a flip-flop.
[0081] A comparator CMP then compares this value of the counter to
the reference instant tref and then delivers the indication IND
representative of the writing operation being conducted correctly
or incorrectly.
[0082] This indication IND can for example be a bit taking the
value "1" for the writing operation being conducted incorrectly and
the value "0" for the writing operation being conducted
correctly.
[0083] Thus, if for example the nominal duration of an erasing
and/or writing pulse is reflected by a counter having a value equal
to 1024, the instant tref can be considered to be equivalent to a
counter value equal to 800.
[0084] The value of the bit IND can be accessible via a bus of the
STI type by using, for example, one of the unused bits of a status
word present in the status register SRG.
[0085] This bit IND can be a volatile bit reset to "0" each time
the operation of the apparatus APP is stopped.
[0086] As indicated above, when the microcontroller associated with
the EEPROM memory detects the presence of a bit IND equal to "1" it
can then make the decision to send one or more "beeps" and/or a
specific phrase via the loudspeaker HP indicating to the user that
a battery change is urgently needed. The microcontroller can also
take the decision to prevent any new writing command in the EEPROM
memory in order to avoid any malfunctioning.
* * * * *