U.S. patent application number 15/267450 was filed with the patent office on 2017-01-05 for method for manufacturing semiconductor device.
The applicant listed for this patent is Semiconductor Energy Laboratory Co., Ltd.. Invention is credited to Shunpei YAMAZAKI.
Application Number | 20170005182 15/267450 |
Document ID | / |
Family ID | 44858549 |
Filed Date | 2017-01-05 |
United States Patent
Application |
20170005182 |
Kind Code |
A1 |
YAMAZAKI; Shunpei |
January 5, 2017 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Abstract
A semiconductor device including an oxide semiconductor with
stable electric characteristics and high reliability is provided.
An island-shaped oxide semiconductor layer is formed by using a
resist mask, the resist mask is removed, oxygen is introduced
(added) to the oxide semiconductor layer, and heat treatment is
performed. The removal of the resist mask, introduction of the
oxygen, and heat treatment are performed successively without
exposure to the air. Through the oxygen introduction and heat
treatment, impurities such as hydrogen, moisture, a hydroxyl group,
or hydride are intentionally removed from the oxide semiconductor
layer, whereby the oxide semiconductor layer is highly purified.
Chlorine may be introduced to an insulating layer over which the
oxide semiconductor layer is formed before formation of the oxide
semiconductor layer. By introducing chlorine, hydrogen in the
insulating layer can be fixed, thereby preventing diffusion of
hydrogen from the insulating layer into the oxide semiconductor
layer.
Inventors: |
YAMAZAKI; Shunpei;
(Setagaya, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Semiconductor Energy Laboratory Co., Ltd. |
Atsugi-shi |
|
JP |
|
|
Family ID: |
44858549 |
Appl. No.: |
15/267450 |
Filed: |
September 16, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14316065 |
Jun 26, 2014 |
9449852 |
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15267450 |
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13085812 |
Apr 13, 2011 |
8790960 |
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14316065 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/4908 20130101;
H01L 29/7869 20130101; H01L 21/02664 20130101; H01L 21/02565
20130101; H01L 21/02631 20130101; H01L 29/78606 20130101; H01L
29/66969 20130101; H01L 21/02554 20130101; H01L 21/465 20130101;
H01L 21/477 20130101 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 21/02 20060101 H01L021/02; H01L 21/477 20060101
H01L021/477; H01L 29/786 20060101 H01L029/786 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 28, 2010 |
JP |
2010-103472 |
Claims
1. (canceled)
2. A method for manufacturing a semiconductor device comprising:
forming an oxide semiconductor film containing indium, gallium and
zinc; forming a metal oxide over the oxide semiconductor film; and
introducing oxygen into the oxide semiconductor film from above the
metal oxide, wherein the metal oxide contains at least one metal
element included in the oxide semiconductor film.
3. The method for manufacturing a semiconductor device according to
claim 2, wherein the metal oxide has a thickness of greater than or
equal to 10 nm and less than or equal to 200 nm.
4. A method for manufacturing a semiconductor device comprising:
forming an oxide semiconductor film containing indium, gallium and
zinc; forming a metal oxide over the oxide semiconductor film; and
introducing oxygen into the oxide semiconductor film from above the
metal oxide, wherein the metal oxide contains at least one metal
element included in the oxide semiconductor film, and wherein an
amount of oxygen introduced into the oxide semiconductor film is
larger than an amount of hydrogen contained in the oxide
semiconductor film.
5. The method for manufacturing a semiconductor device according to
claim 4, wherein the metal oxide has a thickness of greater than or
equal to 10 nm and less than or equal to 200 nm.
6. A method for manufacturing a semiconductor device comprising:
forming an oxide semiconductor film containing indium, gallium and
zinc; forming a metal oxide over the oxide semiconductor film; and
introducing oxygen into the oxide semiconductor film from above the
metal oxide, heating the oxide semiconductor film and the metal
oxide to dehydrate or dehydrogenate the oxide semiconductor film,
wherein the metal oxide contains at least one metal element
included in the oxide semiconductor film, and wherein an amount of
oxygen introduced into the oxide semiconductor film is larger than
an amount of hydrogen contained in the oxide semiconductor film
subjected to the dehydration or dehydrogenation.
7. The method for manufacturing a semiconductor device according to
claim 6, wherein the metal oxide has a thickness of greater than or
equal to 10 nm and less than or equal to 200 nm.
8. A method for manufacturing a semiconductor device comprising:
forming a gate insulating film; forming an oxide semiconductor film
containing indium, gallium and zinc over the gate insulating film;
forming a metal oxide over the oxide semiconductor film; and
introducing oxygen into the oxide semiconductor film from above the
metal oxide, wherein the metal oxide contains a same material as
the gate insulating film, and wherein an amount of oxygen
introduced into the oxide semiconductor film is larger than an
amount of hydrogen contained in the oxide semiconductor film.
9. The method for manufacturing a semiconductor device according to
claim 8, wherein the metal oxide has a thickness of greater than or
equal to 10 nm and less than or equal to 200 nm.
Description
TECHNICAL FIELD
[0001] An embodiment of the present invention relates to a
semiconductor device and a method for manufacturing the
semiconductor device.
[0002] Note that in this specification, a semiconductor device
refers to any device that can function by utilizing semiconductor
characteristics, and an image pick-up device, a display device, an
electro-optical device, a power supply device, a semiconductor
circuit, and an electronic device are all semiconductor
devices.
BACKGROUND ART
[0003] Attention has been focused on a technique for forming a
transistor (also referred to as a thin film transistor (TFT)) using
a semiconductor thin film formed over a substrate having an
insulating surface. The transistor is applied to a wide range of
electronic devices such as an integrated circuit (IC) or an image
display device (display device). A silicon-based semiconductor
material is widely known as a material for a semiconductor thin
film applicable to the transistor. As another material, an oxide
semiconductor has been attracting attention.
[0004] For example, a transistor whose active layer includes an
amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn)
and having an electron carrier concentration of less than
10.sup.18/cm.sup.3 is disclosed (see Patent Document 1).
REFERENCE
Patent Document
[0005] [Patent Document 1] Japanese Published Patent Application
No. 2006-165528
[0006] However, the electric conductivity of an oxide semiconductor
changes when deviation from the stoichiometric composition due to
excess or deficiency of oxygen or the like occurs, or hydrogen or
moisture forming an electron donor enters the oxide semiconductor,
during a manufacturing process of a device. Such a phenomenon
becomes a factor of variation in the electric characteristics of a
transistor including an oxide semiconductor.
[0007] In view of the above problems, it is an object to provide a
semiconductor device including an oxide semiconductor, which has
stable electric characteristics and high reliability.
[0008] In order to suppress variation in the electric
characteristics of a transistor including an oxide semiconductor,
impurities such as hydrogen, moisture, a hydroxyl group, or hydride
(also referred to as a hydrogen compound) which cause the variation
are intentionally removed from the oxide semiconductor. In
addition, oxygen which is a main component of the oxide
semiconductor and is reduced in the step of removing the impurities
is supplied. The oxide semiconductor is thus highly purified and
becomes electrically i-type (intrinsic).
[0009] An i-type (intrinsic) oxide semiconductor is an oxide
semiconductor which is made to be i-type (intrinsic) or
substantially i-type (intrinsic) by being highly purified by
removing hydrogen, which is an n-type impurity, from the oxide
semiconductor so that impurities that are not a main component of
the oxide semiconductor are contained as little as possible. In
other words, a feature is that a highly purified i-type (intrinsic)
semiconductor or a semiconductor close thereto is obtained not by
adding an impurity but by removing an impurity such as hydrogen or
water as much as possible. This enables the Fermi level (E.sub.f)
to be at the same level as the intrinsic Fermi level (E.sub.i).
[0010] Oxygen is introduced (added) to a bulk of an oxide
semiconductor and then heat treatment is performed. Through these
steps of oxygen introduction and heat treatment, impurities such as
hydrogen, moisture, a hydroxyl group, or hydride (also referred to
as a hydrogen compound) are intentionally removed from the oxide
semiconductor, whereby the oxide semiconductor is highly purified.
By the introduction of oxygen, a bond between a metal included in
the oxide semiconductor and hydrogen or a bond between the metal
and a hydroxyl group is cut, and the hydrogen or the hydroxyl group
is reacted with oxygen to produce water; this leads to easy
elimination of the hydrogen or the hydroxyl group that is an
impurity as water by the heat treatment performed later. In
addition, through the heat treatment, the structure of the oxide
semiconductor can be ordered, and the number of defect levels in
the energy gap can be reduced. Further, the number of defects
generated at the interface between the oxide semiconductor and an
insulating layer in contact with the oxide semiconductor can be
reduced.
[0011] Note that the term "bulk" is used in order to clarify that
oxygen is added not only to a surface of a thin film but also to
the inside of the thin film. The introduction of oxygen can also be
referred to as "oxygen doping". Note that "oxygen doping" in this
specification means that oxygen (which includes at least one of an
oxygen radical, an oxygen atom, and an oxygen ion) is added to a
bulk.
[0012] The oxygen doping (also referred to as oxygen doping
treatment) can be performed by oxygen plasma doping in which oxygen
that is made into plasma is added to a bulk. Specifically, oxygen
is made into plasma with the use of radio-frequency (RF) power, and
oxygen radicals and/or oxygen ions are introduced to an oxide
semiconductor over a substrate. At this time, it is preferable to
apply a bias to the substrate over which the oxide semiconductor is
formed. By increasing the bias applied to the substrate, oxygen can
be introduced more deeply. The oxygen doping may be performed by an
ion implantation method or an ion doping method.
[0013] In the manufacturing process of a transistor including an
oxide semiconductor, in the oxide semiconductor (bulk), an oxygen
excess region where the amount of oxygen is greater than that in
the stoichiometric proportion can be provided through oxygen doping
treatment. In the oxygen excess region, the amount of oxygen is
preferably greater than that in the stoichiometric proportion and
less than four times of that in the stoichiometric proportion, more
preferably greater than that in the stoichiometric proportion and
less than double of that in the stoichiometric proportion. Here, an
oxide containing excessive oxygen whose amount is greater than that
in the stoichiometric proportion refers to, for example, an oxide
which satisfies 2g>3a+3b+2c+4d+3e+2f when the oxide is
represented by
In.sub.aGa.sub.bZn.sub.cSi.sub.dAl.sub.eMg.sub.jO.sub.g (a, b, c,
d, e, f, g.gtoreq.0). Note that oxygen which is added by the oxygen
doping treatment may exist between lattices of the oxide
semiconductor.
[0014] Note that in the case where an oxide semiconductor has no
defects (oxygen deficiency), the amount of oxygen contained in the
oxide semiconductor may be equal to that in the stoichiometric
proportion. However, in order to ensure reliability, for example,
to suppress variation in the threshold voltage of a transistor, an
oxide semiconductor preferably contains oxygen whose amount is
greater than that in the stoichiometric proportion.
[0015] With dehydration or dehydrogenation by heat treatment
subjected to an oxide semiconductor, a hydrogen atom or an impurity
containing a hydrogen atom such as water in the oxide semiconductor
is removed, so that the oxide semiconductor is highly purified. The
amount of oxygen added by oxygen doping treatment is set to greater
than that of hydrogen in the highly purified oxide semiconductor
which has been subjected to the dehydration or dehydrogenation.
[0016] In addition, a cap layer may be formed on and in contact
with an oxide semiconductor, and oxygen may be introduced to the
oxide semiconductor through the cap layer. By the introduction of
oxygen through the cap layer, excessive damage to the oxide
semiconductor in oxygen doping treatment can be alleviated. When
oxygen is introduced by an ion implantation method or an ion doping
method, the oxygen introduction depth (introduction region) can be
easily controlled, whereby oxygen can be efficiently introduced to
the oxide semiconductor.
[0017] By using gallium oxide for the cap layer, charge buildup at
the introduction of oxygen can be relieved, and excessive damage to
the oxide semiconductor can be further alleviated. Further, by
using a metal oxide including the same kind of component as the
oxide semiconductor for the cap layer, accumulation of hydrogen
ions at the interface between the metal oxide and the oxide
semiconductor and the vicinity thereof can be suppressed or
prevented. Specifically, as the metal oxide, it is preferable to
use a material containing an oxide of one or more of metal elements
selected from constituent elements of the oxide semiconductor.
[0018] When the metal oxide is used for the cap layer and heat
treatment is performed while the oxide semiconductor and the cap
layer are in contact with each other, oxygen which is one of the
main components of the oxide semiconductor and is reduced in the
step of removing impurities, can be supplied from the metal oxide
to the oxide semiconductor. Thus, the oxide semiconductor is more
highly purified to become electrically i-type (intrinsic).
[0019] The electric characteristics of a transistor including a
highly purified oxide semiconductor, such as the threshold voltage
and the on-state current, have almost no temperature dependence.
Further, transistor characteristics hardly change owing to light
deterioration.
[0020] As described above, variation in the electric
characteristics of a transistor including a highly purified and
electrically i-type (intrinsic) oxide semiconductor is suppressed
and the transistor is electrically stable. Consequently, a
semiconductor device including an oxide semiconductor, which has
high reliability and stable electric characteristics, can be
provided.
[0021] In addition, chlorine doping (also referred to as chlorine
doping treatment) may be performed on an insulating layer over
which an oxide semiconductor is formed before formation of the
oxide semiconductor. Specifically, chlorine is made into plasma
with the use of radio-frequency (RF) power, and chlorine radicals
and/or chlorine ions are introduced to the insulating layer over a
substrate. At this time, it is preferable to apply a bias to the
substrate over which the insulating layer is formed. By increasing
the bias applied to the substrate, chlorine can be introduced more
deeply. The chlorine doping may be performed by an ion implantation
method or an ion doping method.
[0022] By introducing chlorine to the insulating layer over which
the oxide semiconductor is formed, hydrogen in the insulating layer
can be fixed, so that diffusion of hydrogen from the insulating
layer into the oxide semiconductor can be prevented. Oxygen may be
introduced at the same time as chlorine.
[0023] According to an embodiment of the present invention, a
method for manufacturing a semiconductor device includes the steps
of: forming a resist mask over an oxide semiconductor layer,
forming an island-shaped oxide semiconductor layer by using the
resist mask, removing the resist mask, introducing oxygen to the
island-shaped oxide semiconductor layer, and performing heat
treatment on the island-shaped oxide semiconductor layer. The step
of removing the resist mask, the step of introducing oxygen to the
island-shaped oxide semiconductor layer, and the step of performing
the heat treatment on the island-shaped oxide semiconductor layer
are successively performed without exposure to the air.
[0024] According to an embodiment of the present invention, a
method for manufacturing a semiconductor device includes the steps
of: performing chlorine doping treatment on an insulating layer
over which an oxide semiconductor layer is formed before formation
of the oxide semiconductor layer, forming a resist mask over the
oxide semiconductor layer, forming an island-shaped oxide
semiconductor layer by using the resist mask, removing the resist
mask, introducing oxygen to the island-shaped oxide semiconductor
layer, and performing heat treatment on the island-shaped oxide
semiconductor layer. The step of removing the resist mask, the step
of introducing oxygen to the island-shaped oxide semiconductor
layer, and the step of performing the heat treatment on the
island-shaped oxide semiconductor layer are successively performed
without exposure to the air.
[0025] According to an embodiment of the present invention, a
method for manufacturing a semiconductor device includes the steps
of: forming a cap layer over an oxide semiconductor layer, forming
a resist mask over the cap layer, forming an island-shaped oxide
semiconductor layer and an island-shaped cap layer by using the
resist mask, removing the resist mask, introducing oxygen to the
island-shaped oxide semiconductor layer through the island-shaped
cap layer, and performing heat treatment on the island-shaped oxide
semiconductor layer. The step of removing the resist mask, the step
of introducing oxygen to the island-shaped oxide semiconductor
layer, and the step of performing the heat treatment on the
island-shaped oxide semiconductor layer are successively performed
without exposure to the air.
[0026] Oxygen introduced to the oxide semiconductor layer includes
an oxygen radical or an oxygen ion.
[0027] In addition, the step of removing the resist mask, the step
of introducing oxygen to the island-shaped oxide semiconductor
layer, and the step of performing the heat treatment on the
island-shaped oxide semiconductor layer are performed in a reduce
pressure atmosphere, an inert gas atmosphere, or an oxygen gas
atmosphere without exposure to the air.
[0028] The effect of the invention disclosed in this specification
can be easily understood in consideration of the following, but the
following description is just one consideration.
[0029] When a positive voltage is applied to a gate electrode of a
transistor, an electric field is generated from a gate electrode
side of an oxide semiconductor layer to a back channel side (the
side opposite to a gate insulating film). Therefore, hydrogen ions
having positive charge which exist in the oxide semiconductor layer
are transferred to the back channel side, and accumulated at the
oxide semiconductor layer side of the interface between the oxide
semiconductor layer and an insulating layer. The positive charge is
transferred from the accumulated hydrogen ions to charge trapping
centers (such as a hydrogen atom, water, or contamination) in the
insulating layer, whereby negative charge is accumulated at the
back channel side of the oxide semiconductor layer. In other words,
a parasitic channel is generated at the back channel side of the
transistor, and the threshold voltage is shifted to the negative
side, so that the transistor tends to be normally-on.
[0030] In this manner, the charge trapping center such as hydrogen
or water in the insulating layer traps the positive charge and the
positive charge is transferred into the insulating layer, whereby
the electrical characteristics of the transistor change.
Accordingly, in order to suppress variation in the electrical
characteristics of the transistor, it is important that there is no
charge trapping centers or the number of the charge trapping
centers is small in the insulating layer. Therefore, when the
insulating layer is formed, a sputtering method which causes less
hydrogen contained in the formed insulating layer is preferably
used. In an insulating layer formed by a sputtering method, there
is no charge trapping centers or a small number of charge trapping
centers, and the transfer of positive charge does not easily occur
as compared to the case of using a CVD method or the like.
Therefore, the shift of the threshold voltage of the transistor can
be suppressed, and the transistor can be normally-off.
[0031] Note that in a top-gate transistor, when an oxide
semiconductor layer is formed over an insulating layer serving as a
base and then heat treatment is performed thereon, not only water
or hydrogen contained in the oxide semiconductor layer but also
water or hydrogen contained in the insulating layer can be removed.
Accordingly, in the insulating layer, there are a small number of
charge trapping centers for trapping positive charge transferred
through the oxide semiconductor layer. In this manner, since the
heat treatment for dehydration or dehydrogenation is also performed
on the insulating layer located below the oxide semiconductor layer
in addition to the oxide semiconductor layer, in the top-gate
transistor, the insulating layer serving as a base may be formed by
a CVD method such as a plasma CVD method.
[0032] Note that in a bottom-gate transistor, when an oxide
semiconductor layer is formed over a gate insulating layer and then
heat treatment is performed thereon, not only water or hydrogen
contained in the oxide semiconductor layer but also water or
hydrogen contained in the gate insulating layer can be removed.
Accordingly, in the gate insulating layer, there are a small number
of charge trapping centers for trapping positive charge transferred
through the oxide semiconductor layer. In this manner, since the
heat treatment for dehydration or dehydrogenation is also performed
on the gate insulating layer located below the oxide semiconductor
layer in addition to the oxide semiconductor layer, in the
bottom-gate transistor, the gate insulating layer may be formed by
a CVD method such as a plasma CVD method.
[0033] In addition, when a negative voltage is applied to the gate
electrode, an electric field is generated from the back channel
side to the gate electrode side in the oxide semiconductor layer.
Thus, hydrogen ions which exist in the oxide semiconductor layer
are transferred to the gate insulating layer side and accumulated
at the oxide semiconductor layer side of the interface between the
oxide semiconductor layer and the gate insulating layer. As a
result, the threshold voltage of the transistor is shifted to the
negative side.
[0034] When the negative voltage is applied to the gate electrode
and then the electric field is stopped and this state is kept, the
positive charge is released from the charge trapping centers, so
that the threshold voltage of the transistor is shifted to the
positive side, thereby returning to the initial state, or the
threshold voltage is shifted to the positive side beyond that in
the initial state in some cases. From these phenomena, it can be
considered that easy-to-transfer ions exist in the oxide
semiconductor layer and hydrogen that is the smallest atom is
transferred most easily.
[0035] In addition, when an oxide semiconductor layer absorbs
light, a bond between a metal element (M) and a hydrogen atom (H)
(also referred to as an M-H bond) in the oxide semiconductor layer
is cut by optical energy. Note that the optical energy of light
having a wavelength of approximately 400 nm equals or substantially
equals to the bond energy of a metal element and a hydrogen atom.
When a negative gate bias is applied to a transistor in which a
bond of a metal element and a hydrogen atom in an oxide
semiconductor layer is cut, a hydrogen ion detached from a metal
element is attracted to a gate electrode side, so that distribution
of charge is changed, the threshold voltage of the transistor is
shifted to the negative side, and the transistor tends to be
normally-on.
[0036] Note that hydrogen ions which are transferred to the
interface with a gate insulating layer by light irradiation and
application of the negative gate bias to the transistor are
returned to the initial state by stopping application of the
voltage. This can be regarded as a typical example of the ion
transfer in the oxide semiconductor layer.
[0037] In order to prevent such a variation in the electric
characteristics by voltage application (BT deterioration) or a
variation in the electric characteristics by light irradiation
(light deterioration), it is most important to remove a hydrogen
atom or an impurity containing a hydrogen atom such as water
thoroughly from an oxide semiconductor layer to highly purify the
oxide semiconductor layer. A charge density of 10.sup.15 cm.sup.-3,
or a charge per unit area of 10.sup.10 cm.sup.-2 does not affect
the transistor characteristics or affects them very slightly.
Therefore, it is preferable that the charge density be less than or
equal to 10.sup.15 cm.sup.-3. When 10% of hydrogen contained in the
oxide semiconductor layer is transferred within the oxide
semiconductor layer, the hydrogen concentration is preferably less
than or equal to 10.sup.16 cm.sup.-3. Further, in order to prevent
entry of hydrogen from the outside after a device is completed, it
is preferable that a silicon nitride layer formed by a sputtering
method be used as a passivation layer to cover the transistor.
[0038] Hydrogen or water can also be removed from the oxide
semiconductor layer by doping with excessive oxygen as compared to
hydrogen contained in the oxide semiconductor layer (such that (the
number of hydrogen atoms)<<(the number of oxygen radicals) or
(the number of oxygen ions)). Specifically, oxygen is made into
plasma by radio-frequency (RF) power, a bias of a substrate is
increased, and doping with or addition of an oxygen radical and/or
an oxygen ion is performed on the oxide semiconductor layer over
the substrate such that the amount of oxygen is larger than that of
hydrogen in the oxide semiconductor layer. The electronegativity of
oxygen is 3.0 which is larger than about 2.0, the electronegativity
of a metal (Zn, Ga, In) in the oxide semiconductor layer. Thus,
excessive oxygen contained as compared to hydrogen, deprives an M-H
bond of a hydrogen atom, so that an OH group is formed. This OH
group may form an M-O--H group by being bonded to M.
[0039] Oxygen doping is preferably performed so that the amount of
oxygen contained in the oxide semiconductor layer is greater than
that in the stoichiometric proportion of the oxide semiconductor.
For example, in the case where an In--Ga--Zn--O-based oxide
semiconductor layer is used as the oxide semiconductor layer, since
an ideal ratio in the case of single crystal is 1:1:1:4
(InGaZnO.sub.4), it is preferable that the number of 0 atoms be
greater than 4 and less than 8 (the amount of oxygen be greater
than that in the stoichiometric proportion and less than double of
that in the stoichiometric proportion) by oxygen doping.
[0040] Optical energy or BT stress detaches a hydrogen ion from an
M-H bond, which causes deterioration; however, in the case where
oxygen is implanted by the above-described doping, implanted oxygen
is bonded to a hydrogen ion, so that an OH group is formed. The OH
group does not discharge a hydrogen ion even by light irradiation
or application of BT stress on the transistor because of its high
bond energy, and is not easily transferred in the oxide
semiconductor layer because of its larger mass than the mass of a
hydrogen ion. Accordingly, an OH group formed by oxygen doping does
not cause deterioration of the transistor or can reduce factors of
the deterioration.
[0041] In addition, it has been confirmed that as the thickness of
an oxide semiconductor layer is increased, variation in the
threshold voltage of a transistor tends to increase. It can be
assumed that this is because an oxygen defect in the oxide
semiconductor layer is one cause of the variation in the threshold
voltage and the number of oxygen defects increases as the thickness
of the oxide semiconductor layer is increased. A step of doping an
oxide semiconductor layer with oxygen in a transistor according to
an embodiment of the present invention is effective not only for
removal of hydrogen or water from the oxide semiconductor layer but
also for compensation of an oxygen defect in the layer.
Accordingly, the variation in the threshold voltage can be
controlled in the transistor according to an embodiment of the
present invention.
[0042] Metal oxide layers each containing the same kind of
component as an oxide semiconductor layer may be provided with the
oxide semiconductor layer provided therebetween, which is also
effective for prevention of variation in the electrical
characteristics. As the metal oxide layer containing the same kind
of component as the oxide semiconductor layer, specifically, a
material containing an oxide of one or more metal elements selected
from constituent elements of the oxide semiconductor layer is
preferably used. Such a material is compatible with the oxide
semiconductor layer, and therefore, provision of the metal oxide
layers with the oxide semiconductor layer provided therebetween
enables the interface between the metal oxide layer and the oxide
semiconductor layer to be kept well. That is, by providing the
metal oxide layer using the above-described material as an
insulating layer which is in contact with the oxide semiconductor
layer, since hydrogen ions are mainly diffused in the metal oxide
layer, accumulation of hydrogen ions at the interface between the
metal oxide layer and the oxide semiconductor layer and in the
vicinity thereof can be suppressed or prevented. Accordingly, as
compared to the case where insulating layers each containing a
different component from that of the oxide semiconductor layer,
such as silicon oxide layers, are provided with the oxide
semiconductor layer provided therebetween, the hydrogen
concentration at the interface of the oxide semiconductor layer,
which affects the threshold voltage of the transistor, can be
sufficiently decreased.
[0043] Gallium oxide is preferably used for the metal oxide layer.
Since gallium oxide has a wide band gap (Eg), by providing gallium
oxide layers with the oxide semiconductor layer provided
therebetween, an energy barrier is formed at the interface between
the oxide semiconductor layer and the metal oxide layer to prevent
carrier transfer at the interface. Consequently, carriers are not
transferred from the oxide semiconductor to the metal oxide, but
are transferred within the oxide semiconductor layer. On the other
hand, hydrogen ions pass through the interface between the oxide
semiconductor layer and the metal oxide layer and are accumulated
in the vicinity of a surface of the metal oxide layer which is
opposite to a surface in contact with the oxide semiconductor
layer, for example. The above region is apart from a region where
carriers flow, which results in no affect or a very slight affect
on the threshold voltage of the transistor. When gallium oxide is
in contact with an In--Ga--Zn--O-based material, the energy barrier
is about 0.8 eV on the conduction band side and about 0.9 eV on the
valence band side.
[0044] A transistor including an oxide semiconductor subjected to
dehydration or dehydrogenation by heat treatment and oxygen doping
treatment is a transistor having high reliability in which the
amount of change in the threshold voltage by the bias-temperature
stress (BT) test can be reduced.
[0045] Consequently, in accordance with an embodiment of the
present invention, a transistor having stable electric
characteristics can be manufactured.
[0046] In addition, in accordance with an embodiment of the present
invention, a semiconductor device including a transistor, which has
favorable electric characteristics and high reliability, can be
manufactured.
BRIEF DESCRIPTION OF DRAWINGS
[0047] FIGS. 1A to 1E illustrate an embodiment of a semiconductor
device and a method for manufacturing the semiconductor device.
[0048] FIGS. 2A to 2E illustrate an embodiment of a semiconductor
device and a method for manufacturing the semiconductor device.
[0049] FIGS. 3A to 3E illustrate an embodiment of a semiconductor
device and a method for manufacturing the semiconductor device.
[0050] FIGS. 4A to 4E illustrate an embodiment of a semiconductor
device and a method for manufacturing the semiconductor device.
[0051] FIGS. 5A to 5D illustrate an embodiment of a semiconductor
device and a method for manufacturing the semiconductor device.
[0052] FIG. 6A is a top view and FIG. 6B is a cross-sectional view
each illustrating an embodiment of a plasma apparatus.
[0053] FIGS. 7A to 7C each illustrate an embodiment of a
semiconductor device.
[0054] FIG. 8 illustrates an embodiment of a semiconductor
device.
[0055] FIG. 9 illustrates an embodiment of a semiconductor
device.
[0056] FIG. 10 illustrates an embodiment of a semiconductor
device.
[0057] FIGS. 11A and 11B illustrate an embodiment of a
semiconductor device.
[0058] FIGS. 12A and 12B illustrate an electronic device.
[0059] FIGS. 13A to 13F each illustrate an electronic device.
BEST MODE FOR CARRYING OUT THE INVENTION
[0060] Hereinafter, embodiments of the present invention will be
described in detail with reference to the accompanying drawings.
However, the present invention is not limited to the description
below, and it is easily understood by those skilled in the art that
modes and details disclosed herein can be modified in various ways.
Therefore, the present invention is not construed as being limited
to the description of the embodiments below.
[0061] A transistor is a kind of semiconductor element and can
achieve amplification of a current or a voltage, switching
operation for controlling conduction or non-conduction, or the
like. A transistor in this specification includes an insulated-gate
field effect transistor (IGFET) and a thin film transistor
(TFT).
[0062] There is no particular limitation on the structure of a
transistor disclosed in this specification or the like. For
example, a staggered type and a planar type of a top-gate structure
or a bottom-gate structure can be used. Further, the transistor may
have a single gate structure including one channel formation
region, a double gate structure including two channel formation
regions, or a triple gate structure including three channel
formation regions.
[0063] In addition, a function of "source" and a function of
"drain" are sometimes interchanged with each other depending on the
operating conditions of a transistor or the like. Therefore, the
terms "source" and "drain" can be interchanged with each other in
this specification.
[0064] Note that the ordinal numbers such as "first" and "second"
in this specification are used for convenience and do not denote
the order of steps and the stacking order of layers. In addition,
the ordinal numbers in this specification do not denote particular
names which specify the invention.
Embodiment 1
[0065] In this embodiment, an embodiment of a semiconductor device
and a method for manufacturing the semiconductor device will be
described with reference to FIGS. 1A to 1E and FIG. 5A. In this
embodiment, as an example of the semiconductor device, a transistor
including an oxide semiconductor for a semiconductor layer in which
a channel is formed will be described in detail.
[0066] A transistor 410 illustrated in FIG. 1E includes, over a
substrate 400, a gate electrode layer 401, a gate insulating layer
402, an oxide semiconductor layer 403, a source electrode layer
405a, and a drain electrode layer 405b. An insulating layer 407
(also referred to as a first insulating layer) and a protective
insulating layer 409 (also referred to as a second insulating
layer) are stacked over the transistor 410 in this order. The
transistor 410 is one of bottom-gate transistors, and is also one
of inverted staggered transistors.
[0067] FIGS. 1A to 1E illustrate an example of a method for
manufacturing the transistor 410.
[0068] First, a conductive layer is formed over the substrate 400,
and then, the gate electrode layer 401 is formed through a first
photolithography step. Note that a resist mask may be formed by an
inkjet method. Formation of the resist mask by an inkjet method
needs no photomask; thus, manufacturing cost can be reduced.
[0069] There is no particular limitation on a substrate which can
be used as the substrate 400, and a glass substrate, a ceramic
substrate, a quartz substrate, a sapphire substrate, a crystallized
glass substrate, or the like can be used.
[0070] Further, a flexible substrate may be used as the substrate
400. In the case where a flexible substrate is used, a transistor
may be directly formed over a flexible substrate. Alternatively, a
transistor may be formed over a manufacturing substrate, and then,
the transistor may be separated from the manufacturing substrate
and transferred to a flexible substrate. Note that in order to
separate the transistor from the manufacturing substrate and
transfer it to the flexible substrate, a separation layer may be
provided between the manufacturing substrate and the
transistor.
[0071] A base layer may be provided between the substrate 400 and
the gate electrode layer 401. The base layer can be formed to have
a single-layer structure or a stacked-layer structure using one or
more of silicon nitride, silicon oxide, silicon nitride oxide, and
silicon oxynitride and has a function of preventing diffusion of
impurity elements from the substrate 400.
[0072] When a halogen element such as chlorine or fluorine is
contained in the base layer, a function of preventing diffusion of
impurity elements from the substrate 400 can be further improved.
The concentration of a halogen element to be contained in the base
layer is measured by secondary ion mass spectrometry (SIMS) and its
peak is preferably greater than or equal to
1.times.10.sup.15/cm.sup.3 and less than or equal to
1.times.10.sup.20/cm.sup.3.
[0073] Gallium oxide may be used for the base layer. Alternatively,
a stacked-layer structure of a gallium oxide layer and the above
insulating layer may be used for the base layer. Gallium oxide is a
material which is hardly charged; therefore, variation in the
threshold voltage due to charge buildup of the insulating layer can
be suppressed.
[0074] The gate electrode layer 401 can be formed to have a
single-layer structure or a stacked-layer structure using a metal
material such as molybdenum (Mo), titanium (Ti), tantalum (Ta),
tungsten (W), aluminum (Al), copper (Cu), chromium (Cr), neodymium
(Nd), scandium (Sc), or magnesium (Mg), or an alloy material
containing any of these as a main component.
[0075] Then, the gate insulating layer 402 is formed over the gate
electrode layer 401 (see FIG. 1A). The gate insulating layer 402
can be formed using silicon oxide, silicon nitride, silicon
oxynitride, silicon nitride oxide, aluminum oxide, aluminum
nitride, aluminum oxynitride, aluminum nitride oxide, tantalum
oxide, gallium oxide, yttrium oxide, hafnium oxide, hafnium
silicate (HfSi.sub.xO.sub.y (x>0, y>0)), hafnium aluminate
(HfAl.sub.xO.sub.y (x>0, y>0)), hafnium silicate to which
nitrogen is added, hafnium aluminate to which nitrogen is added, or
the like by a plasma CVD method, a sputtering method, or the like.
The gate insulating layer 402 is not limited to a single layer, and
a stacked layer of different layers may be used. For example, by a
plasma CVD method, a silicon nitride (SiN.sub.y (y>0)) layer may
be formed as a first gate insulating layer, and a silicon oxide
(SiO.sub.x (x>0)) layer may be formed as a second gate
insulating layer over the first gate insulating layer, so that a
gate insulating layer can be formed.
[0076] An oxide semiconductor described in this embodiment is an
i-type or substantially i-type oxide semiconductor from which
impurities are removed and which is highly purified so as to
contain an impurity that serves as a carrier donor and is a
substance other than the main component of the oxide semiconductor
as little as possible.
[0077] Such a highly purified oxide semiconductor is highly
sensitive to an interface state and interface charge; thus, an
interface between the oxide semiconductor layer and the gate
insulating layer is important. For that reason, the gate insulating
layer that is to be in contact with a highly purified oxide
semiconductor needs to have high quality.
[0078] For example, a high-density plasma CVD method using
microwaves (e.g., a frequency of 2.45 GHz) is preferably adopted
because an insulating layer formed can be dense and can have high
withstand voltage and high quality. The highly purified oxide
semiconductor and the high-quality gate insulating layer are in
close contact with each other, whereby the interface state can be
reduced to obtain favorable interface characteristics.
[0079] Needless to say, another film formation method such as a
sputtering method or a plasma CVD method can be employed as long as
the method enables formation of a good-quality insulating layer as
a gate insulating layer. Further, an insulating layer whose film
quality and characteristics of the interface with the oxide
semiconductor are improved by heat treatment which is performed
after formation of the insulating layer may be used. In any case,
any insulating layer may be used as long as the insulating layer
has characteristics of enabling reduction in interface state
density of the interface with the oxide semiconductor and formation
of a favorable interface as well as having favorable film quality
as a gate insulating layer.
[0080] In addition, an insulating material containing the same kind
of component as the oxide semiconductor is preferably used for the
gate insulating layer 402. This is because such a material is
compatible with the oxide semiconductor, and therefore, the use of
such a material for the gate insulating layer 402 enables a state
of the interface between the gate insulating layer 402 and the
oxide semiconductor to be kept well. Here, containing "the same
kind of component as the oxide semiconductor" means containing one
or more of elements selected from constituent elements of the oxide
semiconductor. For example, in the case where the oxide
semiconductor is formed using an In--Ga--Zn-based oxide
semiconductor material, gallium oxide or the like is given as such
an insulating material containing the same kind of component as the
oxide semiconductor.
[0081] As a far preferable example of a stacked-layer structure for
the gate insulating layer 402, a stacked-layer structure of a layer
(hereinafter referred to as a layer a) formed using the insulating
material containing the same kind of component as the oxide
semiconductor and a layer (hereinafter referred to as a layer b)
formed using a material different from the component material of
the layer a can be given. This is because with a structure in which
the layer a and the layer b are stacked from the oxide
semiconductor layer side in order, charge is preferentially trapped
by a charge trapping center at the interface between the layers a
and b (as compared to the interface between the oxide semiconductor
and the layer a), so that charge trapping at the interface of the
oxide semiconductor can be sufficiently suppressed, leading to
improvement in the reliability of the semiconductor device.
[0082] Further, in order that hydrogen, a hydroxyl group, and
moisture might be contained in the gate insulating layer 402 and
the oxide semiconductor layer as little as possible, it is
preferable that, as pretreatment before formation of the oxide
semiconductor layer, the substrate 400 over which layers up to and
including the gate electrode layer 401 are formed or the substrate
400 over which layers up to and including the gate insulating layer
402 are formed be preheated in a preheating chamber of a sputtering
apparatus so that impurities such as hydrogen and moisture adsorbed
to the substrate 400 are eliminated and removed. As an evacuation
unit provided in the preheating chamber, a cryopump is preferable.
Note that this preheating treatment can be omitted. Further, this
preheating may be similarly performed on the substrate 400 over
which layers up to and including the source electrode layer 405a
and the drain electrode layer 405b are formed, before formation of
the insulating layer 407.
[0083] Next, over the gate insulating layer 402, an oxide
semiconductor layer with a thickness of greater than or equal to 2
nm and less than or equal to 200 nm, preferably greater than or
equal to 5 nm and less than or equal to 30 nm is formed.
[0084] Note that before the oxide semiconductor layer is formed by
a sputtering method, powder substances (also referred to as
particles or dusts) which are attached on a surface of the gate
insulating layer 402 are preferably removed by reverse sputtering
in which an argon gas is introduced and plasma is generated. The
reverse sputtering refers to a method in which an RF power source
is used for application of voltage to a substrate side in an
atmosphere of a rare gas such as argon and plasma is generated
around the substrate to modify a surface. Note that a nitrogen gas,
a helium gas, an oxygen gas, or the like may be used in place of an
argon gas.
[0085] Before formation of the oxide semiconductor layer, chlorine
may be introduced to an insulating layer (the gate insulating layer
402 in this embodiment) over which the oxide semiconductor layer is
formed, by a method similar to oxygen plasma doping described
later, by using a chlorine gas (a gas containing chlorine such as
Cl.sub.2, SiCl.sub.4, or the like) instead of an oxygen gas.
Alternatively, chlorine may be introduced by an ion implantation
method or an ion doping method which will be described in
Embodiment 2.
[0086] By introducing chlorine to the insulating layer over which
the oxide semiconductor layer is formed, hydrogen in the insulating
layer can be fixed, so that diffusion of hydrogen from the
insulating layer into the oxide semiconductor layer can be
prevented. Oxygen may be introduced to the insulating layer at the
same time as chlorine. Note that chlorine or the like is preferably
introduced under the condition where damage to the interface
between the insulating layer and the oxide semiconductor layer can
be minimized.
[0087] A metal oxide containing In, a metal oxide containing In and
Ga, or the like can be used as the oxide semiconductor used for the
oxide semiconductor layer. In addition, the following metal oxides
can also be used: a four-component metal oxide such as an
In--Sn--Ga--Zn--O-based oxide semiconductor; a three-component
metal oxide such as an In--Ga--Zn--O-based oxide semiconductor, an
In--Sn--Zn--O-based oxide semiconductor, an In--Al--Zn--O-based
oxide semiconductor, a Sn--Ga--Zn--O-based oxide semiconductor, an
Al--Ga--Zn--O-based oxide semiconductor, or a Sn--Al--Zn--O-based
oxide semiconductor; a two-component metal oxide such as an
In--Zn--O-based oxide semiconductor, a Sn--Zn--O-based oxide
semiconductor, an Al--Zn--O-based oxide semiconductor, a
Zn--Mg--O-based oxide semiconductor, a Sn--Mg--O-based oxide
semiconductor, an In--Mg--O-based oxide semiconductor, or an
In--Ga--O-based oxide semiconductor; an In--O-based oxide
semiconductor, a Sn--O-based oxide semiconductor, or a Zn--O-based
oxide semiconductor; and the like. Further, SiO.sub.2 may be
contained in the above oxide semiconductor. Here, for example, an
In--Ga--Zn--O-based oxide semiconductor means an oxide containing
indium (In), gallium (Ga), and zinc (Zn), and there is no
particular limitation on the composition ratio thereof.
[0088] For the oxide semiconductor layer, a thin film of a material
expressed by a chemical formula, InMO.sub.3(ZnO).sub.m (m>0),
can be used. Here, M represents one or more metal elements selected
from Ga, Al, Mn, and Co. For example, M can be Ga, Ga and Al, Ga
and Mn, Ga and Co, or the like.
[0089] In this embodiment, the oxide semiconductor layer is formed
using an In--Ga--Zn--O-based oxide target by a sputtering method.
In addition, the oxide semiconductor layer can be formed by a
sputtering method in a rare gas (typically, argon) atmosphere, an
oxygen atmosphere, or a mixed atmosphere containing a rare gas and
oxygen.
[0090] As a target for forming the oxide semiconductor layer by a
sputtering method, for example, an oxide target having a
composition ratio of In.sub.2O.sub.3:Ga.sub.2O.sub.3:ZnO=1:1:1
[molar ratio] is used to form an In--Ga--Zn--O layer. Without
limitation to the material and the component of the target, for
example, an oxide target having a composition ratio of
In.sub.2O.sub.3:Ga.sub.2O.sub.3:ZnO=1:1:2 [molar ratio] may be
used.
[0091] In the case where an In--Zn--O-based material is used as the
oxide semiconductor, a target used has a composition ratio of
In:Zn=50:1 to 1:2 in an atomic ratio (In.sub.2O.sub.3:ZnO=25:1 to
1:4 in a molar ratio), preferably In:Zn=20:1 to 1:1 in an atomic
ratio (In.sub.2O.sub.3:ZnO=1:2 to 10:1 in a molar ratio), more
preferably In:Zn=1.5:1 to 15:1 in an atomic ratio
(In.sub.2O.sub.3:ZnO=3:4 to 15:2 in a molar ratio). For example,
when a target used for forming the In--Zn--O-based oxide
semiconductor has a composition ratio of In:Zn:O.dbd.X:Y:Z in an
atomic ratio, Z>(1.5X+Y).
[0092] Furthermore, the filling rate of an oxide target is greater
than or equal to 90% and less than or equal to 100%, preferably
greater than or equal to 95% and less than or equal to 99.9%. With
the use of a metal oxide target having a high filling rate, a dense
oxide semiconductor can be formed.
[0093] It is preferable to use a high-purity gas from which
impurities such as hydrogen, water, a hydroxyl group, or hydride
are removed as a sputtering gas used when the oxide semiconductor
layer is formed.
[0094] When the oxide semiconductor layer is formed, the substrate
is held in a film formation chamber kept under reduced pressure,
and the substrate temperature is set to a temperature of higher
than or equal to 100.degree. C. and lower than or equal to
600.degree. C., preferably higher than or equal to 200.degree. C.
and lower than or equal to 400.degree. C. By heating the substrate
during film formation, the impurity concentration in the oxide
semiconductor layer formed can be reduced. In addition, damage by
sputtering can be reduced. Then, a sputtering gas from which
hydrogen and moisture have been removed is introduced to the film
formation chamber while moisture remaining therein is removed, and
the oxide semiconductor layer is formed over the substrate 400 with
the use of the above target. In order to remove moisture remaining
in the film formation chamber, an entrapment vacuum pump such as a
cryopump, an ion pump, or a titanium sublimation pump is preferably
used. As an evacuation unit, a turbo molecular pump provided with a
cold trap may be used. In a film formation chamber which is
evacuated with a cryopump, for example, a hydrogen atom, a compound
containing a hydrogen atom, such as water (H.sub.2O), (more
preferably, also a compound containing a carbon atom), and the like
are removed, whereby the concentration of impurities in an oxide
semiconductor layer formed in the film formation chamber can be
reduced.
[0095] As one example of the film formation condition, the distance
between the substrate and the target is 100 mm, the pressure is 0.6
Pa, the power of the direct-current (DC) power source is 0.5 kW,
and the atmosphere is an oxygen atmosphere (the proportion of the
oxygen flow is 100%). Note that a pulsed direct-current power
source is preferably used, in which case powder substances (also
referred to as particles or dusts) that are generated in film
formation can be reduced and the film thickness can be uniform.
[0096] Next, first heat treatment is performed. By the first heat
treatment, excessive hydrogen (including water and a hydroxyl
group) in the oxide semiconductor layer is removed (dehydration or
dehydrogenation) and the structure of the oxide semiconductor layer
is ordered, so that defect levels in the energy gap can be reduced.
In addition, defects at the interface between the oxide
semiconductor layer and the insulating layer in contact with the
oxide semiconductor layer can be reduced.
[0097] The first heat treatment is preferably performed at higher
than or equal to 250.degree. C. and lower than or equal to
750.degree. C., or higher than or equal to 400.degree. C. and lower
than the strain point of the substrate in a reduced pressure
atmosphere, an inert gas atmosphere such as a nitrogen atmosphere
or a rare gas atmosphere, an oxygen gas atmosphere, or an ultra dry
air atmosphere (in air whose moisture content is less than or equal
to 20 ppm (the dew point: -55.degree. C.), preferably less than or
equal to 1 ppm, more preferably less than or equal to ppb in the
case where measurement is performed using a dew-point meter of a
cavity ring-down laser spectroscopy (CRDS) system). For example,
the substrate is put in an electric furnace which is a kind of heat
treatment apparatus, and the oxide semiconductor layer is subjected
to heat treatment at 450.degree. C. for one hour in a nitrogen
atmosphere.
[0098] Note that the heat treatment apparatus is not limited to an
electrical furnace, and may include a device for heating an object
to be processed by heat conduction or heat radiation from a heating
element such as a resistance heating element. For example, an RTA
(rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal
anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus
can be used. An LRTA apparatus is an apparatus for heating an
object to be processed by radiation of light (an electromagnetic
wave) emitted from a lamp such as a halogen lamp, a metal halide
lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium
lamp, or a high pressure mercury lamp. A GRTA apparatus is an
apparatus for heat treatment using a high-temperature gas. As the
high-temperature gas, an inert gas which does not react with an
object to be processed by heat treatment, such as nitrogen or a
rare gas like argon, is used.
[0099] For example, as the first heat treatment, GRTA may be
performed as follows. The substrate is transferred and put in an
inert gas heated to a high temperature of higher than or equal to
650.degree. C. and lower than or equal to 700.degree. C., is heated
for several minutes, and is transferred and taken out of the inert
gas heated to the high temperature.
[0100] When the heat treatment is performed in an atmosphere of an
inert gas such as nitrogen or a rare gas, oxygen, or ultra-dry air,
it is preferable that the atmosphere do not contain water,
hydrogen, or the like. It is also preferable that the purity of
nitrogen, oxygen, or a rare gas which is introduced to the heat
treatment apparatus be set to be greater than or equal to 6N
(99.9999%), preferably greater than or equal to 7N (99.99999%)
(that is, the impurity concentration is less than or equal to 1
ppm, preferably less than or equal to 0.1 ppm).
[0101] Next, through a second photolithography step, the oxide
semiconductor layer is processed into an island-shaped oxide
semiconductor layer 441 (see FIG. 1B). A resist mask 420 for
forming the island-shaped oxide semiconductor layer 441 may be
formed by an inkjet method. A photomask is not used when the resist
mask 420 is formed by an inkjet method, which results in reducing
manufacturing costs.
[0102] In the case where a contact hole is formed in the gate
insulating layer 402, a step of forming the contact hole can be
performed at the same time as processing of the oxide semiconductor
layer.
[0103] Note that the etching of the oxide semiconductor layer may
be dry etching, wet etching, or both dry etching and wet etching.
As an etchant used for wet etching for the oxide semiconductor
layer, for example, a mixed solution of phosphoric acid, acetic
acid, and nitric acid, or the like can be used. Alternatively,
ITO-07N (produced by KANTO CHEMICAL CO., INC.) may be used.
[0104] Then, by performing ashing treatment in an oxygen
atmosphere, the resist mask 420 formed over the oxide semiconductor
layer 441 is decomposed and removed. As the ashing treatment,
photoexcited ashing in which the resist mask is removed by
promoting chemical reaction with oxygen by irradiation with light
such as ultraviolet light in an atmosphere of oxygen such as ozone,
or plasma ashing in which the resist mask is decomposed and removed
by oxygen that is made into plasma by using radio-frequency power
or the like can be used. By removing the resist mask by the ashing
treatment, it is possible that the oxide semiconductor layer 441
contains water, hydrogen, or hydrocarbon as little as possible.
[0105] Then, oxygen 430 is introduced to the oxide semiconductor
layer 441. The introduction of the oxygen 430 can be performed by
oxygen plasma doping. Specifically, the oxygen 430 is made into
plasma with the use of radio-frequency (RF) power, and oxygen
radicals and/or oxygen ions are introduced to the oxide
semiconductor layer over the substrate. At this time, it is
preferable to apply a bias to the substrate over which the oxide
semiconductor layer 441 is formed. By increasing the bias applied
to the substrate, the oxygen 430 can be introduced more deeply.
[0106] Through the oxygen plasma doping, the oxygen 430 is supplied
to the oxide semiconductor layer 441, so that the amount of oxygen
in the oxide semiconductor layer 441 is greater than that in the
stoichiometric proportion of the oxide semiconductor (preferably
less than double of that in the stoichiometric proportion). This is
because, when the amount of oxygen is too large, the oxide
semiconductor layer 441 might absorb hydrogen like a hydrogen
absorbing alloy (hydrogen storing alloy). When the amount of oxygen
in the case of single crystal is Y, the amount of oxygen in the
oxide semiconductor layer 441 is greater than Y, preferably greater
than Y and less than 2Y. Alternatively, by setting the amount of
oxygen Z in the oxide semiconductor in the case where the oxygen
doping treatment is not performed as a reference, the amount of
oxygen in the case where the oxygen doping treatment is performed
can be expressed as follows: "the amount of oxygen is greater than
Z, preferably, greater than Z and less than 2Z". The oxygen 430
introduced to the oxide semiconductor layer 441 by doping includes
an oxygen radical, an oxygen atom, and/or an oxygen ion.
Accordingly, the amount of oxygen is greater than that of hydrogen
in the oxide semiconductor.
[0107] For example, when the composition of the oxide semiconductor
layer 441 is expressed by InGaZnOx, the chemical formula derived
from the single crystal structure of an oxide in which
In:Ga:Zn=1:1:1 is InGaZnO.sub.4; therefore, the oxide semiconductor
layer 441 having an oxygen excess region in which x is greater than
4 and less than 8 is formed. In a similar manner, when the
composition of the oxide semiconductor layer 441 is expressed by
InGaZn.sub.2Ox, the oxide semiconductor layer 441 having an oxygen
excess region in which x is greater than 5 and less than 10 is
formed. Note that the oxygen excess region has only to exist in
part (including the interface) of the oxide semiconductor
layer.
[0108] In the oxide semiconductor layer, oxygen is one of the main
components. Thus, it is difficult to accurately estimate the oxygen
concentration of the oxide semiconductor layer by a method such as
secondary ion mass spectrometry (SIMS). In other words, it is hard
to determine whether oxygen is intentionally added to the oxide
semiconductor layer.
[0109] Isotopes such as O.sup.17 or O.sup.18 exist in oxygen, and
it is known that the existence proportions of them in nature are
about 0.037% and about 0.204% of the whole oxygen atoms. That is to
say, it is possible to measure the concentrations of these isotopes
in the oxide semiconductor layer by a method such as SIMS;
therefore, the oxygen concentration of the oxide semiconductor
layer may be able to be estimated more accurately by measuring the
concentrations of these isotopes. Thus, the concentrations of these
isotopes may be measured to determine whether oxygen is
intentionally added to the oxide semiconductor layer.
[0110] For example, with respect to the concentration of O.sup.18,
the concentration of the isotope of oxygen in an oxygen-added
region D1 (O.sup.18) and the concentration of the isotope of oxygen
in a non-oxygen-added region D2 (O.sup.18) have a relationship
represented by D1 (O.sup.18)>D2 (O.sup.18).
[0111] The oxygen 430 added to (contained in) the oxide
semiconductor layer 441 preferably has at least partly a dangling
bond of oxygen in the oxide semiconductor. This is because, with
the dangling bond, the oxygen 430 can be bonded to hydrogen which
can remain in the layer, so that the hydrogen can be fixed (made to
be an immovable ion).
[0112] Oxygen for the doping (an oxygen radical, an oxygen atom,
and/or an oxygen ion) may be supplied from a plasma generating
apparatus with the use of a gas containing oxygen or from an ozone
generating apparatus. More specifically, for example, the oxygen
430 can be generated with an apparatus for etching treatment on a
semiconductor device, an apparatus for ashing on a resist mask, or
the like to process the oxide semiconductor layer 441.
[0113] An example of a plasma apparatus (also referred to as an
ashing apparatus) for performing the oxygen plasma doping will be
described with reference to FIGS. 6A and 6B. Note that the
apparatus is industrially suitable as compared to an ion
implantation apparatus or the like because the apparatus can be
applicable to a large-sized glass substrate of the fifth generation
or later, for example.
[0114] FIG. 6A is a top view of a single wafer multi-chamber
equipment. FIG. 6B is a cross-sectional view of a plasma apparatus
(also referred to as an ashing apparatus) used for oxygen plasma
doping.
[0115] The single wafer multi-chamber equipment illustrated in FIG.
6A includes three plasma apparatuses 10 each of which is
illustrated in FIG. 6B, a substrate supply chamber 11 including
three cassette ports 14 for holding a substrate to be treated, a
load lock chamber 12, a transfer chamber 13, and the like. A
substrate supplied to the substrate supply chamber is transferred
through the load lock chamber 12 and the transfer chamber 13 to a
vacuum chamber 15 in the plasma apparatus 10 and is subjected to
oxygen plasma doping. The substrate which has been subjected to
oxygen plasma doping is transferred from the plasma apparatus,
through the load lock chamber and the transfer chamber, to the
substrate supply chamber. Note that a transfer robot for
transferring a substrate to be treated is provided in each of the
substrate supply chamber 11 and the transfer chamber 13.
[0116] Referring to FIG. 6B, the plasma apparatus 10 includes the
vacuum chamber 15. A plurality of gas outlets and an ICP coil (an
inductively coupled plasma coil) 16 which is a generation source of
plasma are provided on a top portion of the vacuum chamber 15.
[0117] The twelve gas outlets are arranged in a center portion,
seen from the top of the plasma apparatus 10. Each of the gas
outlets is connected to a gas supply source for supplying an oxygen
gas, through a gas flow path 17. The gas supply source includes a
mass flow controller and the like and can supply an oxygen gas to
the gas flow path 17 at a desired flow (which is greater than 0
sccm and less than or equal to 1000 sccm). The oxygen gas supplied
from the gas supply source is supplied from the gas flow path 17,
through the twelve gas outlets, into the vacuum chamber 15.
[0118] The ICP coil 16 includes a plurality of strip-like
conductors, each of which has a spiral form. One end of each of the
conductors is electrically connected to a first radio-frequency
power source 18 (13.56 MHz) through a matching circuit for
adjusting impedance, and the other end thereof is grounded.
[0119] A substrate stage 19 functioning as a lower electrode is
provided in a lower portion of the vacuum chamber. By an
electrostatic chuck or the like provided for the substrate stage
19, a substrate 20 to be treated is held on the substrate stage so
as to be detachable. The substrate stage 19 is provided with a
heater as a heating system and a He gas flow pass as a cooling
system. The substrate stage is connected to a second
radio-frequency power source 21 (3.2 MHz) for applying a substrate
bias voltage.
[0120] In addition, the vacuum chamber 15 is provided with an
exhaust port and an automatic pressure control valve (also referred
to as an APC) 22. The APC is connected to a turbo molecular pump 23
and further, connected to a dry pump 24 through the turbo molecular
pump 23. The APC controls the inside pressure of the vacuum
chamber. The turbo molecular pump 23 and the dry pump 24 reduce the
inside pressure of the vacuum chamber 15.
[0121] Next, described is an example in which plasma is generated
in the vacuum chamber 15 illustrated in FIG. 6B, and oxygen plasma
doping is performed on an oxide semiconductor layer provided for
the substrate 20 to be treated.
[0122] First, the inside pressure of the vacuum chamber 15 is held
at a desired pressure by operating the turbo molecular pump 23, the
dry pump 24, and the like, and then, the substrate 20 to be treated
is installed on the substrate stage in the vacuum chamber 15. Note
that the substrate 20 to be treated held on the substrate stage has
at least an oxide semiconductor layer. In this embodiment, the
inside pressure of the vacuum chamber 15 is held at 1.33 Pa. Note
that the flow of the oxygen gas supplied from the gas outlets into
the vacuum chamber 15 is set to 250 sccm.
[0123] Next, radio-frequency power is applied from the first
radio-frequency power source 18 to the ICP coil 16, thereby
generating plasma. Then, a state in which plasma is being generated
is kept for a certain period (longer than or equal to 30 seconds
and shorter than or equal to 600 seconds). Note that the
radio-frequency power applied to the ICP coil 16 is greater than or
equal to 1 kW and less than or equal to 10 kW. In this embodiment,
the radio-frequency power is set to 6000 W. At this time, a
substrate bias voltage may be applied from the second
radio-frequency power source 21 to the substrate stage. In this
embodiment, the power of the substrate bias voltage is set to 1000
W.
[0124] In this embodiment, the state in which plasma is being
generated is kept for 60 seconds and then, the substrate 20 to be
treated is transferred from the vacuum chamber 15. In this manner,
oxygen plasma doping can be performed on the oxide semiconductor
layer provided for the substrate 20 to be treated.
[0125] In addition, the introduction of the oxygen 430 can be
performed by an ion implantation method or an ion doping method
described in Embodiment 2.
[0126] When the oxygen is introduced to the oxide semiconductor
layer by the oxygen plasma doping, the removal of the resist mask
and the oxygen plasma doping can be performed successively without
interruption in the same vacuum chamber. That is, the removal of
the resist mask and the oxygen plasma doping can be performed
successively without exposure to the air. In addition, there is a
possibility that components of the resist mask which has been
decomposed and removed remain in the atmosphere inside the vacuum
chamber. In order to remove the residual components from the
atmosphere, after the removal of the resist mask and before the
oxygen plasma doping, generation of oxygen plasma is stopped
temporarily, and filling with and removal of an inert gas or an
oxygen gas are preferably performed at least once, on the vacuum
chamber in which the substrate to be treated is placed.
[0127] When the removal of the resist mask 420 formed over the
oxide semiconductor layer 441 and the introduction of the oxygen
430 to the oxide semiconductor layer 441 are performed in different
vacuum chambers or different apparatuses, the substrate to be
treated is transferred while setting the atmosphere around the
substrate to be treated to a reduced pressure atmosphere, an inert
gas atmosphere, or an oxygen gas atmosphere so that the oxide
semiconductor layer 441 is not exposed to the air while the
substrate to be treated is transferred. In the above manner,
impurities such as water, hydrogen, or hydrocarbon can be prevented
from being attached to the surface of the oxide semiconductor layer
441, so that the impurities can be prevented from entering the
oxide semiconductor during the introduction of the oxygen 430 (see
FIG. 1C).
[0128] The oxygen 430 is introduced to the oxide semiconductor
layer 441, so that the oxide semiconductor layer 441 which contains
excessive oxygen is formed. The electronegativity of oxygen is 3.0
which is larger than about 2.0, the electronegativity of a metal
(Zn, Ga, In) in the oxide semiconductor layer, and thus, excessive
oxygen contained as compared to hydrogen deprives the M-H bond of a
hydrogen atom, so that an OH group is formed. This OH group may
form an M-O--H group by being bonded to M.
[0129] That is, by the introduction of oxygen, a bond between a
metal included in the oxide semiconductor and hydrogen or a bond
between the metal and a hydroxyl group is cut. At the same time,
the hydrogen or the hydroxyl group reacts with oxygen to produce
water. In particular, oxygen having a dangling bond easily reacts
with hydrogen remaining in the oxide semiconductor to produce
water. Consequently, hydrogen or a hydroxyl group which is an
impurity can be easily eliminated as water in second heat treatment
performed later.
[0130] After the introduction of the oxygen 430 to the oxide
semiconductor layer 441, the second heat treatment is performed in
a reduced pressure atmosphere, an inert gas atmosphere, or an
oxygen gas atmosphere without exposure to the air (preferably at
higher than or equal to 200.degree. C. and lower than or equal to
600.degree. C., for example, at higher than or equal to 250.degree.
C. and lower than or equal to 550.degree. C.). For example, the
second heat treatment is performed at 450.degree. C. for one hour
in a nitrogen atmosphere. It is preferable that the above
atmosphere do not contain water, hydrogen, or the like.
[0131] Through the above steps of the introduction of the oxygen
430 and the heat treatment, dehydration or dehydrogenation of the
oxide semiconductor layer can be performed, and impurities
containing hydrogen molecules such as hydrogen, moisture, a
hydroxyl group, or hydride (also referred to as a hydrogen
compound) which cannot be removed thoroughly in the first heat
treatment can be removed from the oxide semiconductor layer 441. In
addition, defects generated at the interface between the oxide
semiconductor layer and the insulating layer in contact with the
oxide semiconductor layer can be reduced. As a result, the oxide
semiconductor layer 441 can be changed into the oxide semiconductor
layer 403 which is highly purified and made electrically
i-type.
[0132] Next, a conductive layer for forming the source electrode
layer 405a and the drain electrode layer 405b (including a wiring
formed in the same layer as the source electrode layer 405a and the
drain electrode layer 405b) is formed over the gate insulating
layer 402 and the oxide semiconductor layer 403. As the conductive
layer for forming the source electrode layer 405a and the drain
electrode layer 405b, for example, a single-layer structure or a
stacked-layer structure can be formed using a metal material
including an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, and
Mg, an alloy material containing any of the above elements as its
main component, or a metal nitride containing any of the above
elements as its component (e.g., titanium nitride, molybdenum
nitride, or tungsten nitride). Alternatively, a refractory metal
film of Ti, Mo, W, or the like or a metal nitride film of any of
these elements (a titanium nitride film, a molybdenum nitride film,
or a tungsten nitride film) may be stacked on one of or both a
lower side and an upper side of a metal layer of Al, Cu, or the
like. Further alternatively, the conductive layer for forming the
source electrode layer 405a and the drain electrode layer 405b may
be formed using a conductive metal oxide. As the conductive metal
oxide, indium oxide (In.sub.2O.sub.3), tin oxide (SnO.sub.2), zinc
oxide (ZnO), indium oxide-tin oxide alloy
(In.sub.2O.sub.3--SnO.sub.2; abbreviated to ITO), indium oxide-zinc
oxide alloy (In.sub.2O.sub.3--ZnO), or any of these metal oxide
materials in which silicon oxide is contained can be used.
[0133] A resist mask is formed over the conductive layer through a
third photolithography step. The conductive layer is etched
selectively, so that the source electrode layer 405a and the drain
electrode layer 405b are formed. Then, the resist mask is
removed.
[0134] The channel length L of the transistor 410 is determined by
the distance between the source electrode layer 405a and the drain
electrode layer 405b which are in contact with the oxide
semiconductor layer 403 (see FIG. 1E).
[0135] In order to reduce the number of photomasks used in a
photolithography step and reduce the number of photolithography
steps, an etching step may be performed with the use of a resist
mask formed using a multi-tone mask which is a light-exposure mask
through which light is transmitted to have a plurality of
intensities. A resist mask formed using a multi-tone mask has a
plurality of thicknesses and further can be changed in shape by
etching; therefore, the resist mask can be used in a plurality of
etching steps for processing into different patterns. Therefore, a
resist mask corresponding to at least two kinds of different
patterns can be formed by using one multi-tone mask. Thus, the
number of light-exposure masks can be reduced and the number of
corresponding photolithography steps can be reduced, whereby
simplification of a process can be realized.
[0136] Note that it is preferable that etching conditions be
optimized so as not to etch and divide the oxide semiconductor
layer 403 when the conductive layer is etched. However, it is
difficult to obtain etching conditions in which only the conductive
layer is etched and the oxide semiconductor layer 403 is not etched
at all. In some cases, only part of the oxide semiconductor layer
403 is etched to obtain an oxide semiconductor layer having a
groove portion (a recessed portion) when the conductive layer is
etched.
[0137] In this embodiment, since a titanium (Ti) film is used as
the conductive layer and an In--Ga--Zn--O-based oxide semiconductor
is used as the oxide semiconductor layer, ammonium hydrogen
peroxide (a solution in which 31 wt. % hydrogen peroxide, 28 wt. %
ammonia water, and water are mixed at a volume ratio of 2:1:1) may
be used as an etchant of the conductive layer.
[0138] Next, the insulating layer 407 is formed over the source
electrode layer 405a and the drain electrode layer 405b to be in
contact with part of the oxide semiconductor layer 403 (see FIG.
1D).
[0139] The insulating layer 407 can be formed to a thickness of at
least 1 nm using a method by which impurities such as water and
hydrogen do not enter the insulating layer 407, such as a
sputtering method, as appropriate. A formation method of the
insulating layer 407 is not particularly limited; for example, a
film formation method such as plasma CVD method or sputtering
method can be used. A sputtering method is appropriate in terms of
low possibility of entry of hydrogen, water, and the like. When
hydrogen is contained in the insulating layer 407, entry of the
hydrogen into the oxide semiconductor layer or extraction of oxygen
from the oxide semiconductor layer by the hydrogen is caused,
thereby making the resistance of the backchannel (a region of a
semiconductor layer which is not on the gate electrode layer side;
in the transistor 410, a region of the oxide semiconductor layer
403 which is around the interface with the insulating layer 407) of
the oxide semiconductor layer low (to have an n-type conductivity),
so that a parasitic channel might be formed. Therefore, it is
important to form the insulating layer 407 by a method by which
hydrogen and an impurity containing hydrogen are not contained
therein.
[0140] As the insulating layer 407, an inorganic insulating
material such as silicon oxide, silicon oxynitride, hafnium oxide,
aluminum oxide, or gallium oxide can be typically used. Gallium
oxide is a material which is hardly charged; therefore, variation
in the threshold voltage due to charge buildup of the insulating
layer can be suppressed. As the insulating layer 407 or an
insulating layer stacked over or under the insulating layer 407, a
metal oxide layer including the same kind of component as the oxide
semiconductor may be formed.
[0141] In this embodiment, a 200-nm-thick silicon oxide film is
formed as the insulating layer 407 by a sputtering method. The
substrate temperature in film formation may be higher than or equal
to room temperature and lower than or equal to 300.degree. C. and
is 100.degree. C. in this embodiment. The silicon oxide layer can
be formed by a sputtering method in a rare gas (typically, argon)
atmosphere, an oxygen atmosphere, or a mixed atmosphere containing
a rare gas and oxygen. As a target, silicon oxide or silicon can be
used. For example, the silicon oxide layer can be formed using
silicon as a target in an atmosphere containing oxygen by a
sputtering method.
[0142] In order to remove remaining moisture from the film
formation chamber at the time of formation of the oxide
semiconductor or the insulating layer 407, an entrapment vacuum
pump (such as a cryopump) is preferably used. When the insulating
layer 407 is formed in the film formation chamber evacuated using a
cryopump, the impurity concentration in the insulating layer 407
can be reduced. In addition, as an evacuation unit for removing
moisture remaining in the film formation chamber of the insulating
layer 407, a turbo molecular pump provided with a cold trap may be
used.
[0143] It is preferable that a high-purity gas from which
impurities such as hydrogen, water, a hydroxyl group, or hydride
are removed be used as a sputtering gas when the insulating layer
407 is formed.
[0144] Then, third heat treatment may be performed in a reduced
pressure atmosphere, an inert gas atmosphere, an oxygen gas
atmosphere, or an ultra-dry air atmosphere (preferably at higher
than or equal to 200.degree. C. and lower than or equal to
600.degree. C., for example, higher than or equal to 250.degree. C.
and lower than or equal to 550.degree. C.). For example, the third
heat treatment may be performed at 450.degree. C. for one hour in a
nitrogen atmosphere. In the third heat treatment, part of the oxide
semiconductor layer (channel formation region) is heated in the
state where it is in contact with the insulating layer 407. It is
preferable that the above atmosphere do not contain water,
hydrogen, or the like.
[0145] In the case where the heat treatment is performed in the
state where the oxide semiconductor layer is in contact with the
insulating layer 407 containing oxygen, oxygen can be further
supplied to the oxide semiconductor layer from the insulating film
407 containing oxygen.
[0146] Through the above steps, the transistor 410 is formed. The
transistor 410 is a transistor including the oxide semiconductor
layer 403 which is highly purified and from which impurities such
as hydrogen, moisture, a hydroxyl group, or hydride (also referred
to as a hydrogen compound) are intentionally removed. Therefore,
variation in the electric characteristics of the transistor 410 is
suppressed and the transistor 410 is electrically stable.
[0147] A protective insulating layer 409 may be formed over the
insulating layer 407. For example, a silicon nitride layer is
formed as the protective insulating layer 409 by a plasma CVD
method, a sputtering method, or the like. An inorganic insulating
material which hardly contains an impurity such as moisture and can
prevent entry of the impurity from the outside, such as silicon
nitride, aluminum nitride, or aluminum oxide is preferably used for
the protective insulating layer 409. In this embodiment, the
protective insulating layer 409 is formed using a silicon nitride
layer (see FIG. 1E).
[0148] A silicon nitride layer used for the protective insulating
layer 409 is formed in such a manner that the substrate 400 over
which layers up to and including the insulating layer 407 are
formed is heated to higher than or equal to 100.degree. C. and
lower than or equal to 400.degree. C., a sputtering gas containing
high-purity nitrogen from which hydrogen and moisture are removed
is introduced, and a target of silicon is used. In this case, the
protective insulating layer 409 is preferably formed while removing
moisture remaining in the treatment chamber, in a manner similar to
that of the insulating layer 407.
[0149] After the transistor 410 is formed, heat treatment may be
further performed in the air at higher than or equal to 100.degree.
C. and lower than or equal to 200.degree. C. for longer than or
equal to 1 hour and shorter than or equal to 30 hours. This heat
treatment may be performed at a fixed temperature. Alternatively,
the following change in temperature is set as one cycle and may be
repeated plural times: the temperature is increased from room
temperature to a heating temperature and then decreased to room
temperature.
[0150] Alternatively, without performing the first heat treatment,
the second heat treatment may be performed under the condition of
the first heat treatment. In that case, the second heat treatment
is performed in a reduced pressure atmosphere, an inert gas
atmosphere, or an oxygen gas atmosphere.
[0151] An example in which a back gate electrode layer 411 is
formed in the transistor 410 is illustrated in FIG. 5A. The back
gate electrode layer 411 is positioned so that the channel
formation region of the semiconductor layer is interposed between
the gate electrode layer and the back gate electrode layer 411. The
back gate electrode layer 411 is formed using a conductive layer
and can function in a manner similar to that of the gate electrode
layer. By changing a potential of the back gate electrode layer,
the threshold voltage of the transistor can be changed.
[0152] The back gate electrode layer 411 can be formed using a
material and a method similar to those of the gate electrode layer
401, the source electrode layer 405a, the drain electrode layer
405b, and the like.
[0153] In FIG. 5A, the back gate electrode layer 411 is formed over
the channel formation region of the oxide semiconductor layer 403
with the insulating layer 407 and the protective insulating layer
409 provided therebetween. Although FIG. 5A illustrates the example
in which the back gate electrode layer 411 is formed over the
protective insulating layer 409, the back gate electrode layer 411
may be formed between the insulating layer 407 and the protective
insulating layer 409.
[0154] The oxide semiconductor used for the semiconductor layer in
this embodiment is an i-type (intrinsic) oxide semiconductor or a
substantially i-type (intrinsic) oxide semiconductor. The i-type
(intrinsic) oxide semiconductor or the substantially i-type
(intrinsic) oxide semiconductor is obtained in such a manner that
hydrogen, which serves as a donor, is removed from an oxide
semiconductor as much as possible, and the oxide semiconductor is
highly purified so as to contain as few impurities that are not a
main component of the oxide semiconductor as possible. In other
words, the oxide semiconductor has a feature in that it is made to
be an i-type or made to be close thereto not by introduction of an
impurity but by being highly purified by removal of an impurity
such as hydrogen or water as much as possible. Accordingly, the
oxide semiconductor layer used for the transistor is an oxide
semiconductor layer which is highly purified and made to be
electrically i-type.
[0155] In addition, it is possible that the highly purified oxide
semiconductor includes extremely few carriers (close to zero), and
the carrier concentration thereof is less than
1.times.10.sup.14/Cm.sup.3, preferably less than
1.times.10.sup.12/cm.sup.3, more preferably less than
1.times.10.sup.11/cm.sup.3.
[0156] Since the oxide semiconductor includes extremely few
carriers, the off-state current of the transistor can be reduced.
The off-state current is preferably as small as possible.
[0157] Specifically, in a transistor including the above-described
oxide semiconductor for a channel formation region, the off-state
current per channel width of 1 .mu.m at room temperature can be
less than or equal to 10 aA (1.times.10.sup.-17 A/.mu.m), further
less than or equal to 1 aA (1.times.10.sup.-18 A/.mu.m), still
further less than or equal to 1 zA (1.times.10.sup.-21 A/.mu.m),
still further less than or equal to 1 yA (1.times.10.sup.-24
A/.mu.m).
[0158] In addition, in the transistor including the above oxide
semiconductor for the channel formation region, the temperature
dependence of the on-state current is hardly observed, and the
variation in the off-state current is extremely small.
[0159] A transistor including the above-described oxide
semiconductor for a channel formation region is a transistor having
high reliability in which the amount of change in threshold voltage
of the transistor by the bias-temperature stress (BT) test can be
reduced.
[0160] In the transistor including the above oxide semiconductor,
relatively high field-effect mobility can be obtained, whereby
high-speed operation is possible. Consequently, when the above
transistor is used in a pixel portion of a semiconductor device
having a display function, high-quality images can be obtained.
Since a driver circuit portion and the pixel portion can be formed
over one substrate with the use of the above transistor, the number
of components of the semiconductor device can be reduced.
[0161] As described above, a semiconductor device including an
oxide semiconductor, which has stable electric characteristics, can
be provided. Therefore, a semiconductor device with high
reliability can be provided.
[0162] This embodiment can be implemented by being combined with
other embodiments as appropriate.
Embodiment 2
[0163] In this embodiment, another embodiment of a semiconductor
device and a method for manufacturing the semiconductor device will
be described with reference to FIGS. 2A to 2E and FIG. 5B. Note
that the same portions or portions having similar functions as in
Embodiment 1 can be formed as in Embodiment 1, and the same steps
or similar steps as in Embodiment 1 can be performed as in
Embodiment 1; therefore, the description is not repeated in this
embodiment. In addition, detailed description of the same portions
is not repeated, either.
[0164] A transistor 450 illustrated in FIG. 2E includes, over a
substrate 400, a gate electrode layer 401, a gate insulating layer
402, an oxide semiconductor layer 403, a channel protective layer
406, a source electrode layer 405a, and a drain electrode layer
405b. A protective insulating layer 409 is formed over the
transistor 450. In addition, an insulating layer 407 may be
provided as in the transistor 410. The transistor 450 has a kind of
bottom-gate structure referred to as a channel-protective type
(channel-stop type) and is also referred to as an inverted
staggered transistor.
[0165] FIGS. 2A to 2E illustrate an example of a method for
manufacturing the transistor 450.
[0166] First, the gate electrode layer 401 is formed over the
substrate 400 through a first photolithography step. Then, the gate
insulating layer 402 is formed over the gate electrode layer 401
(see FIG. 2A). A base layer may be provided between the substrate
400 and the gate electrode layer 401 as in Embodiment 1.
[0167] Next, over the gate insulating layer 402, an oxide
semiconductor layer with a thickness of greater than or equal to 2
nm and less than or equal to 200 nm, preferably greater than or
equal to 5 nm and less than or equal to 30 nm is formed. Then, a
cap layer is formed over the oxide semiconductor layer.
[0168] As in Embodiment 1, before formation of the oxide
semiconductor layer, chlorine or chlorine and oxygen may be
introduced to the insulating layer over which the oxide
semiconductor layer is formed.
[0169] The oxide semiconductor layer and the cap layer are
preferably formed successively without exposing the interface
between the oxide semiconductor layer and the cap layer to the air.
By forming the oxide semiconductor layer and the cap layer
successively without exposure to the air, impurities such as water,
hydrogen, or hydrocarbon can be prevented from being attached to
the interface between the oxide semiconductor layer and the cap
layer.
[0170] In this embodiment, the oxide semiconductor layer is formed
using an In--Ga--Zn--O-based oxide target by a sputtering method.
The cap layer formed over the oxide semiconductor layer can be
formed using a material and a method similar to those of the gate
insulating layer 402. The cap layer formed over the oxide
semiconductor layer preferably has a thickness of greater than or
equal to 10 nm and less than or equal to 200 nm Note that a metal
oxide including the same kind of component as the oxide
semiconductor may be used for the cap layer. By using the metal
oxide including the same kind of component as the oxide
semiconductor for the cap layer, accumulation of hydrogen ions at
the interface between the metal oxide and the oxide semiconductor
and the vicinity thereof can be suppressed or prevented.
Specifically, as the metal oxide, it is preferable to use a
material including an oxide of one or more of metal elements that
are constituent elements of the oxide semiconductor.
[0171] Gallium oxide is preferably used as the metal oxide. Since
gallium oxide has a wide band gap (Eg), by providing gallium oxide
layers with the oxide semiconductor layer provided therebetween, an
energy barrier is formed at the interface between the oxide
semiconductor layer and the metal oxide layer to prevent carrier
transfer at the interface. Consequently, carriers are not
transferred from the oxide semiconductor to the metal oxide, but
are transferred mainly within the oxide semiconductor layer. On the
other hand, hydrogen ions pass through the interface between the
oxide semiconductor layer and the metal oxide layer and are
accumulated in the vicinity of a surface of the metal oxide layer
which is opposite to a surface in contact with the oxide
semiconductor layer, for example. The above region is apart from a
region where carriers flow, which results in no affect or a very
slight affect on the threshold voltage of the transistor. When the
gallium oxide is in contact with the In--Ga--Zn--O-based material,
the energy barrier is about 0.8 eV on the conduction band side and
about 0.9 eV on the valence band side.
[0172] Next, the oxide semiconductor layer is subjected to first
heat treatment. The oxide semiconductor layer can be dehydrated or
dehydrogenated by this first heat treatment. In addition, defects
generated at the interface between the oxide semiconductor layer
and the insulating layer in contact with the oxide semiconductor
layer can be reduced. The first heat treatment can be performed by
using a condition and a method similar to those in Embodiment
1.
[0173] Then, through a second photolithography step, the oxide
semiconductor layer and the cap layer are processed into an
island-shaped oxide semiconductor layer 441 and an island-shaped
cap layer 404 (see FIG. 2B). Note that the etching of the oxide
semiconductor layer and the cap layer may be performed using either
dry etching or wet etching, or using both dry etching and wet
etching. For example, the cap layer 404 may be formed by dry
etching, and then, the oxide semiconductor layer 441 may be formed
by wet etching.
[0174] Then, by performing ashing treatment in an oxygen
atmosphere, a resist mask 420 formed over the cap layer 404 is
decomposed and removed.
[0175] After the removal of the resist mask, oxygen 430 is
introduced to the oxide semiconductor layer 441 through the cap
layer 404. The introduction of the oxygen 430 can be performed by
an ion implantation method or an ion doping method. Alternatively,
the introduction of the oxygen 430 can be performed by the oxygen
plasma doping described in Embodiment 1. By introducing the oxygen
430 to the oxide semiconductor layer 441 through the cap layer 404
stacked over the oxide semiconductor layer 441, excessive damage to
the oxide semiconductor layer 441 through the introduction of the
oxygen 430 can be reduced. Further, the oxygen introduction depth
(introduction region) can be easily controlled, whereby oxygen can
be efficiently introduced to the oxide semiconductor layer 441.
[0176] By using gallium oxide for the cap layer 404, charge buildup
at the introduction of the oxygen 430 can be relieved, and
excessive damage to the oxide semiconductor layer 441 can be
further reduced.
[0177] When the step of removing the resist mask and the step of
introducing the oxygen 430 to the oxide semiconductor layer 441 are
successively performed in a reduced pressure atmosphere, an inert
gas atmosphere, or an oxygen gas atmosphere without exposure to the
air, impurities such as water, hydrogen, or hydrocarbon can be
prevented from being attached to the surface of the cap layer 404
and from entering the oxide semiconductor due to ion impact at the
introduction of the oxygen 430 (see FIG. 2C). It is preferable that
the above atmosphere do not contain water, hydrogen, or the
like.
[0178] In an ion implantation method, a source gas is made into
plasma, ion species included in this plasma are extracted and
mass-separated, and ion species with predetermined mass are
accelerated and implanted into an object to be processed as an ion
beam. In an ion doping method, a source gas is made into plasma,
ion species are extracted from this plasma by an operation of a
predetermined electric field, the extracted ion species are
accelerated without mass separation and implanted into an object to
be processed as an ion beam. When the introduction of oxygen is
performed using an ion implantation method involving
mass-separation, an impurity such as a metal element can be
prevented from being introduced to the oxide semiconductor layer,
together with oxygen. On the other hand, an ion doping method
enables ion-beam irradiation to a larger area than an ion
implantation method, and therefore, when the introduction of oxygen
is performed using an ion doping method, the takt time can be
shortened.
[0179] The oxygen introduction depth (introduction region) or the
oxygen concentration can be controlled by appropriately setting
introduction conditions such as the acceleration voltage and the
dose or the thickness of the cap layer. For example, in the case
where an oxygen gas is used and oxygen is introduced by an ion
implantation method, the dose may be set to greater than or equal
to 1.times.10.sup.13 ions/cm.sup.2 and less than or equal to
5.times.10.sup.15 ions/cm.sup.2. It is preferable that the peak of
the concentration of the introduced oxygen in the oxide
semiconductor layer 441 be greater than or equal to
1.times.10.sup.18/cm.sup.3 and less than or equal to
3.times.10.sup.20/cm.sup.3 (more preferably, greater than or equal
to 1.times.10.sup.18/cm.sup.3 and less than or equal to
1.times.10.sup.20/cm.sup.3).
[0180] In particular, it is important to remove impurities such as
hydrogen, water, a hydroxyl group, or hydride from the channel
formation region of the oxide semiconductor layer. Therefore, the
peak of the concentration of the oxygen which has been introduced
is preferably positioned in the oxide semiconductor layer 441
around the interface between the oxide semiconductor layer 441 and
the gate insulating layer 402.
[0181] Next, second heat treatment is performed on the oxide
semiconductor layer 441. The step of introducing oxygen to the
oxide semiconductor layer 441 and the second heat treatment are
preferably performed successively in a reduced pressure atmosphere,
an inert gas atmosphere, or an oxygen gas atmosphere without
exposure to the air. The oxide semiconductor layer 441 can be
dehydrated or dehydrogenated by the second heat treatment. In
addition, defects generated at the interface between the oxide
semiconductor layer and the insulating layer in contact with the
oxide semiconductor layer can be reduced. The second heat treatment
can be performed by using a condition and a method similar to those
in Embodiment 1.
[0182] By the introduction of oxygen and the heat treatment, the
oxide semiconductor layer can be dehydrated or dehydrogenated,
whereby impurities such as hydrogen, moisture, a hydroxyl group, or
hydride can be removed from the oxide semiconductor layer. As a
result, the oxide semiconductor layer 441 can be the oxide
semiconductor layer 403 which is highly purified and made
electrically i-type.
[0183] Instead of the second heat treatment, heat treatment may be
performed on the substrate provided with the oxide semiconductor
layer 441 at a temperature of higher than or equal to 250.degree.
C. and lower than or equal to 700.degree. C. (or a temperature of
lower than or equal to the strain point of a glass substrate) while
the introduction of the oxygen 430 to the oxide semiconductor layer
441 is performed.
[0184] Then, the cap layer 404 is processed through a third
photolithography step, so that the channel protective layer 406
covering the channel formation region of the oxide semiconductor
layer 403 is formed. Note that during the step of processing the
cap layer 404, part of the oxide semiconductor layer 403 is removed
in some cases depending on the processing conditions. In this case,
the thickness of a region of the oxide semiconductor layer 403
which is not covered with the channel protective layer 406 becomes
small.
[0185] Note that the channel length L of the transistor 450 is
determined by the width of the channel protective layer 406 in
contact with the oxide semiconductor layer 403 in a direction
parallel with a carrier flow direction (see FIG. 2E).
[0186] Next, after a conductive layer is formed over the oxide
semiconductor layer 403 and the channel protective layer 406, the
source electrode layer 405a and the drain electrode layer 405b are
formed through a fourth photolithography step. The source electrode
layer 405a and the drain electrode layer 405b can be formed by
using a material and a method similar to those of the source
electrode layer 405a and the drain electrode layer 405b described
in Embodiment 1.
[0187] Through the above process, the transistor 450 is formed. The
transistor 450 is a transistor including the oxide semiconductor
layer 403 which is highly purified and from which impurities such
as hydrogen, moisture, a hydroxyl group, or hydride (also referred
to as a hydrogen compound) are intentionally removed. Therefore,
variation in the electric characteristics of the transistor 450 is
suppressed and the transistor 450 is electrically stable.
[0188] The protective insulating layer 409 which prevents entry of
impurities such as moisture or hydrogen from the outside is
preferably formed over the channel protective layer 406, the source
electrode layer 405a, and the drain electrode layer 405b so that
these impurities do not enter the oxide semiconductor layer 403
(see FIG. 2E). The protective insulating layer 409 can be formed in
a manner similar to that in Embodiment 1.
[0189] In addition, a gallium oxide film may be formed as the
protective insulating layer 409 or an insulating layer stacked over
or under the protective insulating layer 409. Gallium oxide is a
material which is hardly charged; therefore, variation in the
threshold voltage due to charge buildup of the insulating layer can
be suppressed.
[0190] After the transistor 450 is formed, heat treatment may be
further performed in the air at a temperature of higher than or
equal to 100.degree. C. and lower than or equal to 200.degree. C.
for longer than or equal to 1 hour and shorter than or equal to 30
hours. This heat treatment may be performed at a fixed temperature.
Alternatively, the following change in temperature is set as one
cycle and may be repeated plural times: the temperature is
increased from room temperature to a heating temperature and then
decreased to room temperature.
[0191] Alternatively, without performing the first heat treatment,
the second heat treatment may be performed under the condition of
the first heat treatment. In that case, the second heat treatment
is performed in a reduced pressure atmosphere, an inert gas
atmosphere, or an oxygen gas atmosphere.
[0192] An example in which a back gate electrode layer 411 is
formed in the transistor 450 is illustrated in FIG. 5B. The back
gate electrode layer 411 is formed over the channel formation
region of the oxide semiconductor layer 403 with the protective
insulating layer 409 provided therebetween. Although FIG. 5B
illustrates the example in which the back gate electrode layer 411
is formed over the protective insulating layer 409, the back gate
electrode layer 411 may be formed over the channel protective layer
406 by using the same layer as the source electrode layer 405a and
the drain electrode layer 405b. By changing a potential of the back
gate electrode layer 411, the threshold voltage of the transistor
can be changed.
[0193] In addition, in the transistor including the oxide
semiconductor for the channel formation region, the temperature
dependence of the on-state current is hardly observed, and the
variations in the off-state current are extremely small.
[0194] A transistor including the above-described oxide
semiconductor for a channel formation region is a transistor having
high reliability in which the amount of change in threshold voltage
of the transistor by the bias-temperature stress (BT) test can be
reduced.
[0195] In the transistor including the oxide semiconductor,
relatively high field-effect mobility can be obtained, whereby
high-speed operation is possible. Consequently, when the above
transistor is used in a pixel portion of a semiconductor device
having a display function, high-quality images can be obtained. In
addition, since a driver circuit portion and the pixel portion can
be formed over one substrate, the number of components of the
semiconductor device can be reduced.
[0196] As described above, a semiconductor device including an
oxide semiconductor, which has stable electric characteristics, can
be provided. Therefore, a semiconductor device with high
reliability can be provided.
[0197] This embodiment can be implemented by being combined with
other embodiments as appropriate.
Embodiment 3
[0198] In this embodiment, another embodiment of a semiconductor
device and a method for manufacturing the semiconductor device will
be described with reference to FIGS. 3A to 3E and FIG. 5C. Note
that the same portions or portions having similar functions as in
the above embodiment can be formed as in the above embodiment, and
the same steps or similar steps as in the above embodiment can be
performed as in the above embodiment; therefore, the description is
not repeated in this embodiment. In addition, detailed description
of the same portions is not repeated, either.
[0199] A transistor 460 illustrated in FIG. 3E includes, over a
substrate 400, a source electrode layer 405a, a drain electrode
layer 405b, an oxide semiconductor layer 403, a gate insulating
layer 402, and a gate electrode layer 401. A base layer 436 is
formed between the substrate 400 and the oxide semiconductor layer
403. A protective insulating layer 409 is provided over the
transistor 460. A cap layer 404 is formed over the oxide
semiconductor layer 403. The cap layer 404 also functions as a gate
insulating layer. The transistor 460 is referred to as a staggered
transistor which is one of top-gate structures.
[0200] FIGS. 3A to 3E illustrate an example of a method for
manufacturing the transistor 460.
[0201] First, the base layer 436 is formed over the substrate 400.
The base layer 436 can be formed in a manner similar to that of the
base layer described in Embodiment 1. By using a metal oxide
including the same kind of component as the oxide semiconductor for
the base layer 436, accumulation of hydrogen ions at the interface
between the metal oxide and the oxide semiconductor and the
vicinity thereof can be suppressed or prevented. Specifically, as
the metal oxide, it is preferable to use a material including an
oxide of one or more of metal elements that are constituent
elements of the oxide semiconductor.
[0202] Next, after a conductive layer is formed over the base layer
436, the source electrode layer 405a and the drain electrode layer
405b are formed through a first photolithography step. The source
electrode layer 405a and the drain electrode layer 405b can be
formed by using a material and a method similar to those of the
source electrode layer 405a and the drain electrode layer 405b
described in Embodiment 1 (see FIG. 3A).
[0203] Light exposure at the time of the formation of the resist
mask in the first photolithography step may be performed using
ultraviolet light, KrF laser light, or ArF laser light. The channel
length L of the transistor 460 is determined by the distance
between the source electrode layer 405a and the drain electrode
layer 405b which are in contact with the oxide semiconductor layer
403 (see FIG. 3E). In the case where light exposure is performed
for a channel length L of less than 25 nm, the light exposure at
the time of the formation of the resist mask in the third
photolithography step may be performed using extreme ultraviolet
light having an extremely short wavelength of greater than or equal
to several nanometers and less than or equal to several tens of
nanometers. In the light exposure by using extreme ultraviolet
light, the resolution is high and the focus depth is large.
Therefore, the channel length L of the transistor to be formed
later can be greater than or equal to 10 nm and less than or equal
to 1000 nm, whereby operation speed of a circuit can be
increased.
[0204] Next, over the base layer 436, the source electrode layer
405a, and the drain electrode layer 405b, an oxide semiconductor
layer with a thickness of greater than or equal to 2 nm and less
than or equal to 200 nm, preferably greater than or equal to 5 nm
and less than or equal to 30 nm is formed. Then, a cap layer is
formed over the oxide semiconductor layer. The oxide semiconductor
layer and the cap layer are preferably formed successively without
exposing the interface between the oxide semiconductor layer and
the cap layer to the air. By forming the oxide semiconductor layer
and the cap layer successively without exposure to the air,
impurities such as water, hydrogen, or hydrocarbon can be prevented
from being attached to the interface between the oxide
semiconductor layer and the cap layer.
[0205] As in Embodiment 1, before formation of the oxide
semiconductor layer, chlorine or chlorine and oxygen may be
introduced to the insulating layer (corresponding to the base layer
436 in this embodiment) over which the oxide semiconductor layer is
formed. The introduction of chlorine or chlorine and oxygen may be
performed before formation of the source electrode layer 405a and
the drain electrode layer 405b as long as it is before the
formation of the oxide semiconductor layer.
[0206] In this embodiment, the oxide semiconductor layer is formed
using an In--Ga--Zn--O-based oxide target by a sputtering method.
The cap layer formed over the oxide semiconductor layer can be
formed using a material and a method similar to those in Embodiment
2.
[0207] Next, the oxide semiconductor layer is subjected to first
heat treatment. The oxide semiconductor layer can be dehydrated or
dehydrogenated by the first heat treatment. In addition, defects
generated at the interface between the oxide semiconductor layer
and the insulating layer in contact with the oxide semiconductor
layer can be reduced. The first heat treatment can be performed by
using a condition and a method similar to those in Embodiment
1.
[0208] Then, through a second photolithography step, the oxide
semiconductor layer and the cap layer are processed in to an
island-shaped oxide semiconductor layer 441 and an island-shaped
cap layer 404 (see FIG. 3B). Note that the etching of the oxide
semiconductor layer and the cap layer may be performed using either
dry etching or wet etching, or using both dry etching and wet
etching. For example, the cap layer 404 may be formed by dry
etching, and then, the oxide semiconductor layer 441 may be formed
by wet etching.
[0209] Then, by performing ashing treatment in an oxygen
atmosphere, a resist mask 420 formed over the cap layer 404 is
decomposed and removed.
[0210] After the removal of the resist mask, oxygen 430 is
introduced to the oxide semiconductor layer 441 through the cap
layer 404. The introduction of the oxygen 430 can be performed by
an ion implantation method or an ion doping method. Alternatively,
the introduction of the oxygen 430 can be performed by the oxygen
plasma doping described in Embodiment 1. By introducing the oxygen
430 to the oxide semiconductor layer 441 through the cap layer 404
stacked over the oxide semiconductor layer 441, excessive damage to
the oxide semiconductor layer 441 through the introduction of the
oxygen 430 can be reduced. Further, the oxygen introduction depth
(introduction region) can be easily controlled, whereby oxygen can
be efficiently introduced to the oxide semiconductor layer 441.
[0211] By using gallium oxide for the cap layer 404, charge buildup
at the introduction of the oxygen 430 can be relieved, and
excessive damage to the oxide semiconductor layer 441 can be
further reduced.
[0212] When the step of removing the resist mask and the step of
introducing the oxygen 430 to the oxide semiconductor layer 441 are
successively performed in a reduced pressure atmosphere, an inert
gas atmosphere, or an oxygen gas atmosphere without exposure to the
air, impurities such as water, hydrogen, or hydrocarbon can be
prevented from being attached to the surface of the oxide
semiconductor layer 441, whereby entry of the impurities into the
oxide semiconductor due to ion impact at the introduction of the
oxygen 430 can be prevented (see FIG. 3C).
[0213] In order to simplify the process, as described in Embodiment
1, the oxygen 430 may be introduced to the oxide semiconductor
layer 441 without providing the cap layer 404, but it is preferable
to provide the cap layer 404 for the above reason.
[0214] When the oxygen 430 is introduced by an ion implantation
method or an ion doping method, the oxygen introduction depth
(introduction region) or the oxygen concentration can be controlled
by appropriately setting introduction conditions such as the
acceleration voltage and the dose. For example, in the case where
an oxygen gas is used and oxygen is introduced by an ion
implantation method, the dose may be set to greater than or equal
to 1.times.10.sup.13 ions/cm.sup.2 and less than or equal to
5.times.10.sup.15 ions/cm.sup.2. It is preferable that the peak of
the concentration of the introduced oxygen in the oxide
semiconductor layer 441 be greater than or equal to
1.times.10.sup.18/cm.sup.3 and less than or equal to
3.times.10.sup.20/cm.sup.3 (more preferably, greater than or equal
to 1.times.10.sup.18/cm.sup.3 and less than or equal to
1.times.10.sup.20/cm.sup.3).
[0215] In particular, it is important to remove impurities such as
hydrogen, water, a hydroxyl group, or hydride from a channel
formation region of the oxide semiconductor layer, so that in the
transistor 460 having a top-gate structure, a large amount of
oxygen is preferably introduced to the vicinity of the interface
between the cap layer 404 and the oxide semiconductor layer 441 in
the oxide semiconductor layer 441.
[0216] Next, second heat treatment is performed on the oxide
semiconductor layer 441. The step of introducing oxygen to the
oxide semiconductor layer 441 and the second heat treatment are
preferably performed successively in a reduced pressure atmosphere,
an inert gas atmosphere, or an oxygen gas atmosphere without
exposure to the air. The oxide semiconductor layer 441 can be
dehydrated or dehydrogenated by the second heat treatment. In
addition, defects generated at the interface between the oxide
semiconductor layer and the insulating layer in contact with the
oxide semiconductor layer can be reduced. The second heat treatment
can be performed in a condition similar to that of Embodiment
1.
[0217] By the introduction of oxygen and the heat treatment, the
oxide semiconductor layer can be dehydrated or dehydrogenated,
whereby impurities such as hydrogen, moisture, a hydroxyl group, or
hydride can be removed from the oxide semiconductor layer. As a
result, the oxide semiconductor layer 403 which is highly purified
and made electrically i-type can be obtained.
[0218] Instead of the second heat treatment, heat treatment may be
performed on the substrate provided with the oxide semiconductor
layer 441 at a temperature of higher than or equal to 250.degree.
C. and lower than or equal to 700.degree. C. (or a temperature of
lower than or equal to the strain point of a glass substrate) while
the introduction of the oxygen 430 to the oxide semiconductor layer
441 is performed.
[0219] Then, the gate insulating layer 402 is formed. The cap layer
404 may be removed before formation of the gate insulating layer
402. The gate insulating layer 402 can be formed using a material
and a method which are similar to those of the gate insulating
layer 402 in Embodiment 1.
[0220] Then, a conductive layer is formed over the gate insulating
layer 402, and then, the gate electrode layer 401 is formed through
a third photolithography step. The gate electrode layer 401 can be
formed in a manner similar to that of the gate electrode layer 401
described in Embodiment 1.
[0221] Through the above-described steps, the transistor 460 is
manufactured. The transistor 460 is a transistor including the
oxide semiconductor layer 403 which is highly purified and from
which impurities such as hydrogen, moisture, a hydroxyl group, or
hydride (also referred to as a hydrogen compound) are intentionally
removed. Therefore, variation in the electric characteristics of
the transistor 460 is suppressed and the transistor 460 is
electrically stable.
[0222] The protective insulating layer 409 which prevents entry of
impurities such as moisture or hydrogen from the outside is
preferably formed over the gate electrode layer 401 and the gate
insulating layer 402 so that these impurities do not enter the
oxide semiconductor layer 403 (see FIG. 3E). The protective
insulating layer 409 can be formed in a manner similar to that in
Embodiment 1.
[0223] In addition, a gallium oxide layer may be formed as the
protective insulating layer 409 or an insulating layer stacked over
or under the protective insulating layer 409. Gallium oxide is a
material which is hardly charged; therefore, variation in the
threshold voltage due to charge buildup of the insulating layer can
be suppressed.
[0224] After the transistor 460 is formed, heat treatment may be
further performed in the air at a temperature of higher than or
equal to 100.degree. C. and lower than or equal to 200.degree. C.
for longer than or equal to 1 hour and shorter than or equal to 30
hours. This heat treatment may be performed at a fixed temperature.
Alternatively, the following change in temperature is set as one
cycle and may be repeated plural times: the temperature is
increased from room temperature to a heating temperature and then
decreased to room temperature.
[0225] Alternatively, without performing the first heat treatment,
the second heat treatment may be performed under the condition of
the first heat treatment. In that case, the second heat treatment
is performed in a reduced pressure atmosphere, an inert gas
atmosphere, or an oxygen gas atmosphere.
[0226] An example in which a back gate electrode layer 411 is
formed in the transistor 460 is illustrated in FIG. 5C. The back
gate electrode layer 411 is formed in a region overlapping with the
channel formation region of the oxide semiconductor layer 403 with
the base layer 436 provided therebetween. By changing a potential
of the back gate electrode layer 411, the threshold voltage of the
transistor can be changed.
[0227] In addition, in the transistor including the oxide
semiconductor for the channel formation region, the temperature
dependence of the on-state current is hardly observed, and the
variations in the off-state current are extremely small.
[0228] A transistor including the above-described oxide
semiconductor for a channel formation region is a transistor having
high reliability in which the amount of change in threshold voltage
of the transistor by the bias-temperature stress (BT) test can be
reduced.
[0229] In the transistor including the oxide semiconductor,
relatively high field-effect mobility can be obtained, whereby
high-speed operation is possible. Consequently, when the above
transistor is used in a pixel portion of a semiconductor device
having a display function, high-quality images can be obtained. In
addition, since a driver circuit portion and the pixel portion can
be formed over one substrate, the number of components of the
semiconductor device can be reduced.
[0230] As described above, a semiconductor device including an
oxide semiconductor, which has stable electric characteristics, can
be provided. Therefore, a semiconductor device with high
reliability can be provided.
[0231] This embodiment can be implemented by being combined with
other embodiments as appropriate.
Embodiment 4
[0232] In this embodiment, another embodiment of a semiconductor
device and a method for manufacturing the semiconductor device will
be described with reference to FIGS. 4A to 4E and FIG. 5D. Note
that the same portions or portions having similar functions as in
the above embodiment can be formed as in the above embodiment, and
the same steps or similar steps as in the above embodiment can be
performed as in the above embodiment; therefore, the description is
not repeated in this embodiment. In addition, detailed description
of the same portions is not repeated, either.
[0233] A transistor 470 illustrated in FIG. 4E includes, over a
substrate 400 having an insulating surface, a gate electrode layer
401, a gate insulating layer 402, an oxide semiconductor layer 403,
a source electrode layer 405a, and a drain electrode layer 405b. An
insulating layer 407 and a protective insulating layer 409 are
stacked over the transistor 470 in this order. A cap layer 404 is
formed over the oxide semiconductor layer 403. The transistor 470
is one of bottom-gate transistors.
[0234] FIGS. 4A to 4E illustrate an example of a method for
manufacturing the transistor 470.
[0235] First, the gate electrode layer 401 is formed over the
substrate 400 through a first photolithography step. Then, the gate
insulating layer 402 is formed over the gate electrode layer 401
(see FIG. 4A). A base layer may be provided between the substrate
400 and the gate electrode layer 401 as in Embodiment 1.
[0236] Next, a conductive layer is formed over the gate insulating
layer 402, and then, a second photolithography step is performed to
form the source electrode layer 405a and the drain electrode layer
405b. The source electrode layer 405a and the drain electrode layer
405b can be formed by using a material and a method similar to
those of the source electrode layer 405a and the drain electrode
layer 405b described in Embodiment 1 (see FIG. 4B). The channel
length L of the transistor 470 is determined by the distance
between the source electrode layer 405a and the drain electrode
layer 405b which are in contact with the oxide semiconductor layer
403 formed later (see FIG. 4E).
[0237] Next, over the gate insulating layer 402, the source
electrode layer 405a, and the drain electrode layer 405b, an oxide
semiconductor layer with a thickness of greater than or equal to 2
nm and less than or equal to 200 nm, preferably greater than or
equal to 5 nm and less than or equal to 30 nm is formed. Then, a
cap layer is formed over the oxide semiconductor layer. The oxide
semiconductor layer and the cap layer are preferably formed
successively without exposing the interface between the oxide
semiconductor layer and the cap layer to the air. By forming the
oxide semiconductor layer and the cap layer successively without
exposure to the air, impurities such as water, hydrogen, or
hydrocarbon can be prevented from being attached to the interface
between the oxide semiconductor layer and the cap layer.
[0238] As in Embodiment 1, before formation of the oxide
semiconductor layer, chlorine or chlorine and oxygen may be
introduced to the insulating layer over which the oxide
semiconductor layer is formed. The introduction of chlorine or
chlorine and oxygen may be performed before formation of the source
electrode layer 405a and the drain electrode layer 405b as long as
it is before the formation of the oxide semiconductor layer.
[0239] In this embodiment, the oxide semiconductor layer is formed
using an In--Ga--Zn--O-based oxide target by a sputtering method.
The cap layer formed over the oxide semiconductor layer can be
formed using a material and a method similar to those in Embodiment
2.
[0240] Next, the oxide semiconductor layer is subjected to first
heat treatment. The oxide semiconductor layer can be dehydrated or
dehydrogenated by this first heat treatment. In addition, defects
generated at the interface between the oxide semiconductor layer
and the insulating layer in contact with the oxide semiconductor
layer can be reduced. The first heat treatment can be performed by
using a condition and a method similar to those in Embodiment
1.
[0241] Then, through a third photolithography step, the oxide
semiconductor layer and the cap layer are processed in to an
island-shaped oxide semiconductor layer 441 and an island-shaped
cap layer 404 (see FIG. 4C). Note that the etching of the oxide
semiconductor layer and the cap layer may be performed using either
dry etching or wet etching, or using both dry etching and wet
etching. For example, the cap layer 404 may be formed by dry
etching, and then, the oxide semiconductor layer 441 may be formed
by wet etching.
[0242] Then, by performing ashing treatment in an oxygen
atmosphere, a resist mask 420 formed over the cap layer 404 is
decomposed and removed.
[0243] After the removal of the resist mask 420, oxygen 430 is
introduced to the oxide semiconductor layer 441 through the cap
layer 404. The introduction of the oxygen 430 can be performed by
an ion implantation method or an ion doping method described in
Embodiment 2. Alternatively, the introduction of the oxygen 430 can
be performed by the oxygen plasma doping described in Embodiment 1.
By introducing the oxygen 430 to the oxide semiconductor layer 441
through the cap layer 404 stacked over the oxide semiconductor
layer 441, excessive damage to the oxide semiconductor layer 441
through the introduction of the oxygen 430 can be reduced. Further,
the oxygen introduction depth (introduction region) can be easily
controlled, whereby oxygen can be efficiently introduced to the
oxide semiconductor layer 441.
[0244] By using gallium oxide for the cap layer 404, charge buildup
at the introduction of the oxygen 430 can be relieved, and
excessive damage to the oxide semiconductor layer 441 can be
further reduced.
[0245] When the step of removing the resist mask and the step of
introducing the oxygen 430 to the oxide semiconductor layer 441 are
successively performed in a reduced pressure atmosphere, an inert
gas atmosphere, or an oxygen gas atmosphere without exposure to the
air, impurities such as water, hydrogen, or hydrocarbon can be
prevented from being attached to the surface of the oxide
semiconductor layer 441, whereby entry of the impurities into the
oxide semiconductor due to ion impact at the introduction of the
oxygen 430 can be prevented (see FIG. 4D).
[0246] In order to simplify the process, as described in Embodiment
1, the oxygen 430 may be introduced to the oxide semiconductor
layer 441 without providing the cap layer 404, but it is preferable
to provide the cap layer 404 for the above reason.
[0247] Next, second heat treatment is performed on the oxide
semiconductor layer 441. The step of introducing oxygen to the
oxide semiconductor layer 441 and the second heat treatment are
preferably performed successively in a reduced pressure atmosphere,
an inert gas atmosphere, or an oxygen gas atmosphere without
exposure to the air. The oxide semiconductor layer 441 can be
dehydrated or dehydrogenated by the second heat treatment. In
addition, defects generated at the interface between the oxide
semiconductor layer and the insulating layer in contact with the
oxide semiconductor layer can be reduced. The second heat treatment
can be performed by using a condition similar to that in Embodiment
1.
[0248] By the introduction of oxygen and the heat treatment, the
oxide semiconductor layer can be dehydrated or dehydrogenated,
whereby impurities such as hydrogen, moisture, a hydroxyl group, or
hydride can be removed from the oxide semiconductor layer. As a
result, the oxide semiconductor layer 403 which is highly purified
and made electrically i-type can be obtained.
[0249] Instead of the second heat treatment, heat treatment may be
performed on the substrate provided with the oxide semiconductor
layer 441 at a temperature of higher than or equal to 250.degree.
C. and lower than or equal to 700.degree. C. (or a temperature of
lower than or equal to the strain point of a glass substrate) while
the introduction of the oxygen 430 to the oxide semiconductor layer
441 is performed.
[0250] Then, the insulating layer 407 is formed over the cap layer
404, the source electrode layer 405a, and the drain electrode layer
405b. Before formation of the insulating layer 407, plasma
treatment with the use of a gas such as N.sub.2O, N.sub.2, or Ar
may be performed to remove water or the like adsorbed on the
surfaces of the cap layer 404, the source electrode layer 405a, and
the drain electrode layer 405b. When the plasma treatment is
performed, the insulating layer 407 is formed successively without
exposure to the air (see FIG. 4E). The insulating layer 407 can be
formed by using a condition and a method similar to those in
Embodiment 1.
[0251] Then, third heat treatment may be performed in a reduced
pressure atmosphere, an inert gas atmosphere, an oxygen gas
atmosphere, or an ultra-dry air atmosphere (preferably at a
temperature of higher than or equal to 200.degree. C. and lower
than or equal to 600.degree. C., for example, a temperature of
higher than or equal to 250.degree. C. and lower than or equal to
550.degree. C.). For example, the third heat treatment may be
performed at 450.degree. C. for one hour in a nitrogen atmosphere.
In the third heat treatment, part of the oxide semiconductor layer
(channel formation region) is heated in the state where it is in
contact with the insulating layer 407.
[0252] Through the above steps, oxygen which is one of main
components of the oxide semiconductor and which is reduced together
with impurities such as hydrogen, moisture, a hydroxyl group, or
hydride (also referred to as a hydrogen compound) through the
second heat treatment performed on the oxide semiconductor layer
can be supplied.
[0253] Through the above process, the transistor 470 is formed. The
transistor 470 is a transistor including the oxide semiconductor
layer 403 which is highly purified and from which impurities such
as hydrogen, moisture, a hydroxyl group, or hydride (also referred
to as a hydrogen compound) are intentionally removed. Therefore,
variation in the electric characteristics of the transistor 470 is
suppressed and the transistor 470 is electrically stable.
[0254] The protective insulating layer 409 may be formed over the
insulating layer 407. For example, a silicon nitride layer is
formed as the protective insulating layer 409 by a plasma CVD
method, a sputtering method, or the like. The protective insulating
layer 409 can be formed by using a condition and a method similar
to those in Embodiment 1 (see FIG. 4E).
[0255] After the transistor 410 is formed, heat treatment may be
further performed in the air at a temperature of higher than or
equal to 100.degree. C. and lower than or equal to 200.degree. C.
for longer than or equal to 1 hour and shorter than or equal to 30
hours. This heat treatment may be performed at a fixed temperature.
Alternatively, the following change in temperature is set as one
cycle and may be repeated plural times: the temperature is
increased from room temperature to a heating temperature and then
decreased to room temperature.
[0256] Alternatively, without performing the first heat treatment,
the second heat treatment may be performed under the condition of
the first heat treatment. In that case, the second heat treatment
is performed in a reduced pressure atmosphere, an inert gas
atmosphere, or an oxygen gas atmosphere.
[0257] An example in which a back gate electrode layer 411 is
formed over the transistor 470 is illustrated in FIG. 5D. The back
gate electrode layer 411 is positioned so that the channel
formation region of the semiconductor layer is interposed between
the gate electrode layer and the back gate electrode layer 411. The
back gate electrode layer 411 is formed using a conductive layer
and is made to function in a manner similar to that of the gate
electrode layer. By changing a potential of the back gate electrode
layer 411, the threshold voltage of the transistor can be
changed.
[0258] The back gate electrode layer 411 can be formed using a
material and a method similar to those of the gate electrode layer
401, the source electrode layer 405a, and the drain electrode layer
405b.
[0259] In FIG. 5D, the back gate electrode layer 411 is formed over
the channel formation region of the oxide semiconductor layer 403
with the insulating layer 407 and the protective insulating layer
409 provided therebetween. Although FIG. 5D illustrates the example
in which the back gate electrode layer 411 is formed over the
protective insulating layer 409, the back gate electrode layer 411
may be formed between the insulating layer 407 and the protective
insulating layer 409.
[0260] In addition, in the transistor including the oxide
semiconductor for the channel formation region, the temperature
dependence of the on-state current is hardly observed, and the
variations in the off-state current are extremely small.
[0261] A transistor including the above-described oxide
semiconductor for a channel formation region is a transistor having
high reliability in which the amount of change in threshold voltage
of the transistor by the bias-temperature stress (BT) test can be
reduced.
[0262] In the transistor including the oxide semiconductor,
relatively high field-effect mobility can be obtained, whereby
high-speed operation is possible. Consequently, when the above
transistor is used in a pixel portion of a semiconductor device
having a display function, high-quality images can be obtained. In
addition, since a driver circuit portion and the pixel portion can
be formed over one substrate, the number of components of the
semiconductor device can be reduced.
[0263] As described above, a semiconductor device including an
oxide semiconductor, which has stable electric characteristics, can
be provided. Therefore, a semiconductor device with high
reliability can be provided.
[0264] This embodiment can be implemented by being combined with
other embodiments as appropriate.
Embodiment 5
[0265] A semiconductor device with a display function (also
referred to as a display device) can be manufactured by using the
transistor whose example is described in any of the above
embodiments. In addition, part of or entire driver circuit which
includes the transistor can be formed over a substrate where a
pixel portion is formed, whereby a system-on-panel can be obtained.
In this embodiment, an example of a display device including the
transistor whose example is described in any of the above
embodiments will be described with reference to FIGS. 7A to 7C,
FIG. 8, FIG. 9, and FIG. 10. FIG. 8, FIG. 9, and FIG. 10 correspond
to cross-sectional views along line M-N in FIG. 7B.
[0266] In FIG. 7A, a sealant 4005 is provided so as to surround a
pixel portion 4002 provided over a first substrate 4001, and the
pixel portion 4002 is sealed by using a second substrate 4006. In
FIG. 7A, a scan line driver circuit 4004 and a signal line driver
circuit 4003 are each formed using a single crystal semiconductor
or a polycrystalline semiconductor over a substrate prepared
separately, and mounted in a region different from the region
surrounded by the sealant 4005 over the first substrate 4001.
Further, a variety of signals and potentials are supplied to the
signal line driver circuit 4003, the scan line driver circuit 4004,
and the pixel portion 4002 from flexible printed circuits (FPCs)
4018a and 4018b.
[0267] In FIGS. 7B and 7C, the sealant 4005 is provided so as to
surround the pixel portion 4002 and the scan line driver circuit
4004 which are provided over the first substrate 4001. The second
substrate 4006 is provided over the pixel portion 4002 and the scan
line driver circuit 4004. Consequently, the pixel portion 4002 and
the scan line driver circuit 4004 are sealed together with a
display element, by the first substrate 4001, the sealant 4005, and
the second substrate 4006. In FIGS. 7B and 7C, the signal line
driver circuit 4003 which is formed using a single crystal
semiconductor or a polycrystalline semiconductor over a substrate
separately prepared is mounted in a region that is different from
the region surrounded by the sealant 4005 over the first substrate
4001. In FIGS. 7B and 7C, a variety of signals and potentials are
supplied to the signal line driver circuit 4003, the scan line
driver circuit 4004, and the pixel portion 4002 from an FPC
4018.
[0268] Although FIGS. 7B and 7C each illustrate the example in
which the signal line driver circuit 4003 is formed separately and
mounted on the first substrate 4001, the present invention is not
limited to this structure. The scan line driver circuit may be
separately formed and then mounted, or only part of the signal line
driver circuit or part of the scan line driver circuit may be
separately formed and then mounted.
[0269] Note that a connection method of a separately formed driver
circuit is not particularly limited, and a chip on glass (COG)
method, a wire bonding method, a tape automated bonding (TAB)
method, or the like can be used. FIG. 7A illustrates the example in
which the signal line driver circuit 4003 and the scan line driver
circuit 4004 are mounted by a COG method. FIG. 7B illustrates the
example in which the signal line driver circuit 4003 is mounted by
a COG method. FIG. 7C illustrates the example in which the signal
line driver circuit 4003 is mounted by a TAB method.
[0270] The display device includes in its category a panel in which
a display element is sealed, and a module in which an IC including
a controller or the like is mounted on the panel.
[0271] Note that a display device in this specification means an
image display device, a display device, or a light source
(including a lighting device). Furthermore, the display device also
includes the following modules in its category: a module to which a
connector such as an FPC, a TAB tape, or a TCP is attached; a
module having a TAB tape or a TCP at the tip of which a printed
wiring board is provided; and a module in which an integrated
circuit (IC) is directly mounted on a display element by a COG
method.
[0272] Further, the pixel portion and the scan line driver circuit
which are provided over the first substrate each include a
plurality of transistors, to which the transistor whose example is
described in any of the above embodiments can be applied.
[0273] As the display element provided in the display device, a
liquid crystal element (also referred to as a liquid crystal
display element) or a light-emitting element (also referred to as a
light-emitting display element) can be used. The light-emitting
element includes, in its category, an element whose luminance is
controlled by a current or a voltage, and specifically includes, in
its category, an inorganic electroluminescent (EL) element, an
organic EL element, and the like. Furthermore, a display medium
whose contrast is changed by an electric effect, such as electronic
ink, can be used.
[0274] As illustrated in FIG. 8, FIG. 9, and FIG. 10, the
semiconductor device includes a connection terminal electrode 4015
and a terminal electrode 4016. The connection terminal electrode
4015 and the terminal electrode 4016 are electrically connected to
a terminal included in the FPC 4018 through an anisotropic
conductive layer 4019.
[0275] The connection terminal electrode 4015 is formed from the
same conductive layer as a first electrode layer 4030, and the
terminal electrode 4016 is formed from the same conductive layer as
a source electrode layer and a drain electrode layer of transistors
4010 and 4011.
[0276] Each of the pixel portion 4002 and the scan line driver
circuit 4004 which are provided over the first substrate 4001
includes a plurality of transistors. In FIG. 8, FIG. 9, and FIG.
10, the transistor 4010 included in the pixel portion 4002 and the
transistor 4011 included in the scan line driver circuit 4004 are
illustrated as an example. In FIG. 8, an insulating layer 4020 and
an insulating layer 4024 are provided over the transistors 4010 and
4011, and in FIG. 9 and FIG. 10, an insulating layer 4021 is
further provided. Note that an insulating layer 4023 is an
insulating layer serving as a base layer.
[0277] In this embodiment, the transistor described in any of the
above embodiments can be applied to the transistors 4010 and
4011.
[0278] In the transistors 4010 and 4011, the oxide semiconductor
layer is an oxide semiconductor layer which is highly purified and
from which impurities such as hydrogen, moisture, a hydroxyl group,
or hydride (also referred to as a hydrogen compound) are
intentionally removed by introducing oxygen through the insulating
layer 4020 stacked over the oxide semiconductor layer and
performing heat treatment. By introduction of oxygen, a bond
between a metal included in the oxide semiconductor and hydrogen or
a bond between the metal and a hydroxyl group is cut, and the
hydrogen or the hydroxyl group is reacted with oxygen to produce
water; this leads to easy elimination of the hydrogen or the
hydroxyl group that is an impurity as water by heat treatment
performed later.
[0279] Oxygen is introduced to the oxide semiconductor layer
through the insulating layer 4020 stacked over the oxide
semiconductor layer, so that the oxygen introduction depth
(introduction region) can be controlled and thus oxygen can be
efficiently introduced to the oxide semiconductor layer.
[0280] The oxide semiconductor layer and the insulating layer 4020
containing oxygen are in contact with each other when being
subjected to the heat treatment; thus, oxygen, which is one of the
main components of the oxide semiconductor and is reduced in the
step of removing impurities, can be supplied from the insulating
layer 4020 containing oxygen to the oxide semiconductor layer.
Thus, the oxide semiconductor layer is more highly purified to
become electrically i-type (intrinsic).
[0281] Consequently, variation in the electric characteristics of
the transistors 4010 and 4011 each including the highly purified
oxide semiconductor layer is suppressed and the transistors 4010
and 4011 are electrically stable. As described above, a
semiconductor device with high reliability can be provided as the
semiconductor devices illustrated in FIG. 8, FIG. 9, and FIG.
10.
[0282] In this embodiment, examples are shown in which a conductive
layer is provided over the insulating layer so as to overlap with a
channel formation region of the oxide semiconductor layer of the
transistor 4011 for the driver circuit. The conductive layer is
provided so as to overlap with the channel formation region of the
oxide semiconductor layer, whereby the amount of change in the
threshold voltage of the transistor 4011 before and after a BT test
can be further reduced. The conductive layer may have the same
potential as or a potential different from that of a gate electrode
layer of the transistor 4011, and can function as a second gate
electrode layer. The potential of the conductive layer may be GND,
0V, or in a floating state.
[0283] In addition, the conductive layer functions to block an
external electric field, that is, to prevent an external electric
field (particularly, to prevent static electricity) from effecting
the inside (a circuit portion including a thin film transistor). A
blocking function of the conductive layer can prevent variation in
the electrical characteristics of the transistor due to the effect
of an external electric field such as static electricity.
[0284] The transistor 4010 included in the pixel portion 4002 is
electrically connected to a display element to form a display
panel. There is no particular limitation on the kind of the display
element as long as display can be performed, and various kinds of
display elements can be employed.
[0285] An example of a liquid crystal display device using a liquid
crystal element as a display element is illustrated in FIG. 8. In
FIG. 8, a liquid crystal element 4013 which is a display element
includes the first electrode layer 4030, a second electrode layer
4031, and a liquid crystal layer 4008. Note that insulating layers
4032 and 4033 serving as alignment films are provided so that the
liquid crystal layer 4008 is interposed therebetween. The second
electrode layer 4031 is provided on the second substrate 4006 side,
and the first electrode layer 4030 and the second electrode layer
4031 are stacked, with the liquid crystal layer 4008 interposed
therebetween.
[0286] A columnar spacer denoted by reference numeral 4035 is
obtained by selective etching of an insulating layer and is
provided in order to control the thickness of the liquid crystal
layer 4008 (a cell gap). Alternatively, a spherical spacer may be
used.
[0287] In the case where a liquid crystal element is used as the
display element, a thermotropic liquid crystal, a low-molecular
liquid crystal, a high-molecular liquid crystal, a polymer
dispersed liquid crystal, a ferroelectric liquid crystal, an
anti-ferroelectric liquid crystal, or the like can be used. Such a
liquid crystal material exhibits a cholesteric phase, a smectic
phase, a cubic phase, a chiral nematic phase, an isotropic phase,
or the like depending on conditions.
[0288] Alternatively, liquid crystal exhibiting a blue phase for
which an alignment film is unnecessary may be used. A blue phase is
one of liquid crystal phases, which is generated just before a
cholesteric phase changes into an isotropic phase while the
temperature of cholesteric liquid crystal is increased. Since the
blue phase appears only in a narrow temperature range, a liquid
crystal composition in which 5 wt. % or more of a chiral material
is mixed is used for the liquid crystal layer in order to improve
the temperature range. The liquid crystal composition which
includes a liquid crystal showing a blue phase and a chiral agent
has a short response time of less than or equal to 1 msec, has
optical isotropy, which makes the alignment process unneeded, and
has a small viewing angle dependence. In addition, since an
alignment film does not need to be provided and rubbing treatment
is unnecessary, electrostatic discharge damage caused by the
rubbing treatment can be prevented and defects and damage of the
liquid crystal display device can be reduced in the manufacturing
process. Thus, productivity of the liquid crystal display device
can be increased. A transistor that includes an oxide semiconductor
layer has a possibility that the electric characteristics may
fluctuate significantly by the influence of static electricity and
deviate from the designed range. Therefore, it is more effective to
use a liquid crystal material exhibiting a blue phase for a liquid
crystal display device including a transistor which includes an
oxide semiconductor layer.
[0289] The specific resistivity of the liquid crystal material is
greater than or equal to 1.times.10.sup.9 .OMEGA.cm, preferably
greater than or equal to 1.times.10.sup.11 .OMEGA.cm, more
preferably greater than or equal to 1.times.10.sup.12 .OMEGA.cm.
Note that the specific resistivity in this specification is
measured at 20.degree. C.
[0290] The size of a storage capacitor formed in the liquid crystal
display device is set considering the leakage current of the
transistor provided in the pixel portion or the like so that charge
can be held for a predetermined period. The size of the storage
capacitor may be set considering the off-state current of a
transistor or the like. By using a transistor including a
high-purity oxide semiconductor layer, it is enough to provide a
storage capacitor having a capacitance that is less than or equal
to 1/3, preferably less than or equal to 1/5 of a liquid crystal
capacitance of each pixel.
[0291] In the transistor used in this embodiment, which includes a
highly purified oxide semiconductor layer, the current in an off
state (the off-state current) can be made small. Accordingly, an
electrical signal such as an image signal can be held for a longer
period, and a writing interval can be set longer in an on state.
Accordingly, frequency of refresh operation can be reduced, which
leads to an effect of suppressing power consumption.
[0292] In a transistor including the oxide semiconductor,
relatively high field-effect mobility can be obtained, whereby
high-speed operation is possible. Consequently, when the above
transistor is used in a pixel portion of a semiconductor device
having a display function, high-quality images can be obtained. In
addition, since a driver circuit portion and the pixel portion can
be formed over one substrate, the number of components of the
semiconductor device can be reduced.
[0293] For the liquid crystal display device, a twisted nematic
(TN) mode, an in-plane-switching (IPS) mode, a fringe field
switching (FFS) mode, an axially symmetric aligned micro-cell (ASM)
mode, an optical compensated birefringence (OCB) mode, a
ferroelectric liquid crystal (FLC) mode, an antiferroelectric
liquid crystal (AFLC) mode, or the like can be used.
[0294] A normally-black liquid crystal display device such as a
transmissive liquid crystal display device utilizing a vertical
alignment (VA) mode is preferable. The vertical alignment mode is a
method of controlling alignment of liquid crystal molecules of a
liquid crystal display panel, in which liquid crystal molecules are
aligned vertically to a panel surface when no voltage is applied.
Some examples are given as the vertical alignment mode. For
example, a multi-domain vertical alignment (MVA) mode, a patterned
vertical alignment (PVA) mode, an advanced super view (ASV) mode,
and the like can be given. Moreover, it is possible to use a method
called domain multiplication or multi-domain design, in which a
pixel is divided into some regions (subpixels) and molecules are
aligned in different directions in their respective regions.
[0295] In the display device, a black matrix (a light-blocking
layer), an optical member (an optical substrate) such as a
polarizing member, a retardation member, or an anti-reflection
member, and the like are provided as appropriate. For example,
circular polarization may be obtained by using a polarizing
substrate and a retardation substrate. In addition, a backlight, a
side light, or the like may be used as a light source.
[0296] As a display method in the pixel portion, a progressive
method, an interlace method, or the like can be employed. Further,
color elements controlled in a pixel at the time of color display
are not limited to three colors: R, G, and B (R, G, and B
correspond to red, green, and blue, respectively). For example, R,
G, B, and W (W corresponds to white); R, G, B, and one or more of
yellow, cyan, magenta, and the like; or the like can be used.
Further, the sizes of display regions may be different between
respective dots of color elements. The present invention is not
limited to the application to a display device for color display
but can also be applied to a display device for monochrome
display.
[0297] Alternatively, as the display element included in the
display device, a light-emitting element utilizing
electroluminescence can be used. Light-emitting elements utilizing
electroluminescence are classified according to whether a
light-emitting material is an organic compound or an inorganic
compound. In general, the former is referred to as an organic EL
element, and the latter is referred to as an inorganic EL
element.
[0298] In an organic EL element, by application of voltage to a
light-emitting element, electrons and holes are separately injected
from a pair of electrodes into a layer containing a light-emitting
organic compound, and current flows. The carriers (electrons and
holes) are recombined, and thus, the light-emitting organic
compound is excited. The light-emitting organic compound returns to
a ground state from the excited state, thereby emitting light.
Owing to such a mechanism, this light-emitting element is referred
to as a current-excitation light-emitting element.
[0299] The inorganic EL elements are classified according to their
element structures into a dispersion-type inorganic EL element and
a thin-film inorganic EL element. A dispersion-type inorganic EL
element has a light-emitting layer where particles of a
light-emitting material are dispersed in a binder, and its light
emission mechanism is donor-acceptor recombination type light
emission that utilizes a donor level and an acceptor level. A
thin-film inorganic EL element has a structure in which a
light-emitting layer is sandwiched between dielectric layers, which
are further sandwiched between electrodes, and its light emission
mechanism is localized type light emission that utilizes
inner-shell electron transition of metal ions. Note that an example
of an organic EL element is described as a light-emitting
element.
[0300] In order to extract light emitted from the light-emitting
element, at least one of a pair of electrodes may be transparent. A
transistor and a light-emitting element are formed over a
substrate. The light-emitting element can have any of the following
structures: a top emission structure in which light is extracted
through the surface opposite to the substrate; a bottom emission
structure in which light is extracted through the surface on the
substrate side; or a dual emission structure in which light is
extracted through the surface opposite to the substrate and the
surface on the substrate side.
[0301] An example of a light-emitting device including a
light-emitting element as a display element is illustrated in FIG.
9. A light-emitting element 4513 which is a display element is
electrically connected to the transistor 4010 provided in the pixel
portion 4002. The structure of the light-emitting element 4513 is
not limited to the stacked-layer structure including the first
electrode layer 4030, an electroluminescent layer 4511, and the
second electrode layer 4031, which is illustrated in FIG. 9. The
structure of the light-emitting element 4513 can be changed as
appropriate depending on a direction in which light is extracted
from the light-emitting element 4513, or the like.
[0302] A partition wall 4510 can be formed using an organic
insulating material or an inorganic insulating material. It is
particularly preferable that the partition wall 4510 be formed
using a photosensitive resin material to have an opening over the
first electrode layer 4030 so that a sidewall of the opening is
formed as a tilted surface with continuous curvature.
[0303] The electroluminescent layer 4511 may be formed using a
single layer or a plurality of layers stacked.
[0304] A protective layer may be formed over the second electrode
layer 4031 and the partition wall 4510 in order to prevent entry of
oxygen, hydrogen, moisture, carbon dioxide, or the like into the
light-emitting element 4513. As the protective layer, a silicon
nitride film, a silicon nitride oxide film, a DLC film, or the like
can be formed. In addition, in a space which is formed with the
first substrate 4001, the second substrate 4006, and the sealant
4005, a filler 4514 is provided for sealing. It is preferable that
the light-emitting device be packaged (sealed) with a protective
film (such as a laminate film or an ultraviolet curable resin film)
or a cover material with high air-tightness and little
degasification so that the device is not exposed to the outside
air, in this manner.
[0305] As the filler 4514, as well as an inert gas such as nitrogen
or argon, an ultraviolet curable resin or a thermosetting resin can
be used, and polyvinyl chloride (PVC), an acrylic resin, polyimide,
an epoxy resin, a silicone resin, polyvinyl butyral (PVB), ethylene
vinyl acetate (EVA), or the like can be used. For example, nitrogen
may be used for the filler.
[0306] In addition, if needed, an optical film, such as a
polarizing plate, a circularly polarizing plate (including an
elliptically polarizing plate), a retardation plate (a quarter-wave
plate or a half-wave plate), or a color filter, may be provided as
appropriate on a light-emitting surface of the light-emitting
element. Further, a polarizing plate or a circularly polarizing
plate may be provided with an anti-reflection layer. For example,
anti-glare treatment by which reflected light can be diffused by
projections and depressions on the surface so as to reduce the
glare can be performed.
[0307] Further, an electronic paper in which electronic ink is
driven can be provided as the display device. The electronic paper
is also called an electrophoretic display device (electrophoretic
display) and has advantages in that it has the same level of
readability as regular paper, it has less power consumption than
other display devices, and it can be set to have a thin and light
form.
[0308] An electrophoretic display device can have various modes. An
electrophoretic display device includes a plurality of
microcapsules dispersed in a solvent or a solute, each microcapsule
containing first particles which are positively charged and second
particles which are negatively charged. By applying an electric
field to the microcapsules, the particles in the microcapsules move
in opposite directions to each other and only the color of the
particles gathering on one side is displayed. Note that the first
particles and the second particles each contain pigment and do not
move without an electric field. Moreover, the first particles and
the second particles have different colors (which may be
colorless).
[0309] Thus, an electrophoretic display device is a display that
utilizes a so-called dielectrophoretic effect by which a substance
having a high dielectric constant moves to a high-electric field
region.
[0310] A solution in which the above microcapsules are dispersed in
a solvent is referred to as electronic ink. This electronic ink can
be printed on a surface of glass, plastic, cloth, paper, or the
like. Furthermore, by using a color filter or particles that have a
pigment, color display can also be achieved.
[0311] Note that the first particles and the second particles in
the microcapsules may each be formed of a single material selected
from a conductive material, an insulating material, a semiconductor
material, a magnetic material, a liquid crystal material, a
ferroelectric material, an electroluminescent material, an
electrochromic material, and a magnetophoretic material, or formed
of a composite material of any of these.
[0312] As the electronic paper, a display device using a twisting
ball display system can be used. The twisting ball display system
refers to a method in which spherical particles each colored in
black and white are arranged between a first electrode layer and a
second electrode layer which are electrode layers used for a
display element, and a potential difference is generated between
the first electrode layer and the second electrode layer to control
orientation of the spherical particles, so that display is
performed.
[0313] FIG. 10 illustrates an active matrix electronic paper as an
embodiment of a semiconductor device. The electronic paper in FIG.
10 is an example of a display device in which a twisting ball
display system is employed.
[0314] Between the first electrode layer 4030 connected to the
transistor 4010 and the second electrode layer 4031 provided on the
second substrate 4006, spherical particles 4613 each of which
includes a black region 4615a, a white region 4615b, and a cavity
4612 which is filled with liquid around the black region 4615a and
the white region 4615b, are provided. A space around the spherical
particles 4613 is filled with a filler 4614 such as a resin. The
second electrode layer 4031 corresponds to a common electrode
(counter electrode). The second electrode layer 4031 is
electrically connected to a common potential line.
[0315] In FIG. 8, FIG. 9, and FIG. 10, as the first substrate 4001
and the second substrate 4006, flexible substrates, for example,
plastic substrates having a light-transmitting property or the like
can be used, in addition to glass substrates. As plastic, a
fiberglass-reinforced plastic (FRP) plate, a polyvinyl fluoride
(PVF) film, a polyester film, or an acrylic resin film can be used.
In addition, a sheet with a structure in which an aluminum foil is
sandwiched between PVF films or polyester films can be used.
[0316] The insulating layer 4020 can be formed using a material
including an inorganic insulating material such as silicon oxide,
silicon oxynitride, hafnium oxide, aluminum oxide, or gallium
oxide. There is no particular limitation on the method for forming
the insulating layer 4020, and for example, the insulating layer
4020 can be formed by a deposition method such as a plasma CVD
method or a sputtering method. A sputtering method is appropriate
in terms of low possibility of entry of hydrogen, water, and the
like.
[0317] Note that the insulating layer 4024 prevents contaminant
impurities such as an organic substance, a metal, or water vapor
included in the air from entering; thus, a dense film is preferably
used for the insulating layer 4024. The insulating layer 4024 can
be formed with a single-layer structure or a stacked-layer
structure using one or more of a silicon nitride film, a silicon
nitride oxide film, an aluminum oxide film, an aluminum nitride
film, an aluminum oxynitride film, and an aluminum nitride oxide
film by a sputtering method. The insulating layer 4024 functions as
a protective film of the transistor.
[0318] The insulating layer 4021 which functions as a planarizing
insulating layer can be formed using an organic material having
heat resistance, such as an acrylic resin, polyimide, a
benzocyclobutene-based resin, polyamide, or an epoxy resin. Other
than such organic materials, it is also possible to use a
low-dielectric constant material (a low-k material), a
siloxane-based resin, PSG (phosphosilicate glass), BPSG
(borophosphosilicate glass), or the like. Note that the insulating
layer may be formed by stacking a plurality of insulating layers
formed of any of these materials.
[0319] There is no particular limitation on the method for forming
the insulating layer 4020, the insulating layer 4024, and the
insulating layer 4021, and the insulating layers can be formed,
depending on the material, by a sputtering method, a spin coating
method, a dipping method, spray coating, a droplet discharge method
(e.g., an inkjet method, screen printing, or offset printing), roll
coating, curtain coating, knife coating, or the like.
[0320] The display device displays an image by transmitting light
from a light source or a display element. Therefore, the substrate
and the thin films such as the insulating layer and the conductive
layer provided for the pixel portion where light is transmitted
have light-transmitting properties with respect to light in the
visible-light wavelength range.
[0321] The first electrode layer and the second electrode layer
(each of which may be called a pixel electrode layer, a common
electrode layer, a counter electrode layer, or the like) for
applying voltage to the display element may have light-transmitting
properties or light-reflecting properties, which depends on the
direction in which light is extracted, the position where the
electrode layer is provided, the pattern structure of the electrode
layer, and the like.
[0322] The first electrode layer 4030 and the second electrode
layer 4031 can be formed using a light-transmitting conductive
material such as indium oxide containing tungsten oxide, indium
zinc oxide containing tungsten oxide, indium oxide containing
titanium oxide, indium tin oxide containing titanium oxide, indium
zinc oxide, ITO, or ITO to which silicon oxide is added.
[0323] The first electrode layer 4030 and the second electrode
layer 4031 can be formed of one or more kinds of materials selected
from metals such as tungsten (W), molybdenum (Mo), zirconium (Zr),
hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium
(Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt),
aluminum (Al), copper (Cu), silver (Ag), and magnesium (Mg); alloys
of these metals; and nitrides of these metals.
[0324] A conductive composition containing a conductive high
molecule (also referred to as a conductive polymer) can be used for
the first electrode layer 4030 and the second electrode layer 4031.
As the conductive high molecule, a so-called 7c-electron conjugated
conductive polymer can be used. For example, polyaniline or a
derivative thereof, polypyrrole or a derivative thereof,
polythiophene or a derivative thereof, a copolymer of two or more
of aniline, pyrrole, and thiophene or a derivative thereof, or the
like can be given.
[0325] Since the transistor is easily broken owing to static
electricity or the like, a protective circuit for protecting the
driver circuit is preferably provided. The protective circuit is
preferably formed using a nonlinear element.
[0326] As described above, by using any of the transistors
described in the above embodiments, a semiconductor device having a
variety of functions can be provided.
Embodiment 6
[0327] By using the transistor whose example is described in any of
the above embodiments, a semiconductor device having an image
sensor function for reading data of an object can be
manufactured.
[0328] FIGS. 11A and 11B illustrate an example of a semiconductor
device having an image sensor function. FIG. 11A is an equivalent
circuit diagram of a photosensor, and FIG. 11B is a cross-sectional
view of part of the photosensor.
[0329] In FIG. 11A, one electrode of a photodiode 602 is
electrically connected to a photodiode reset signal line 658, and
the other electrode of the photodiode 602 is electrically connected
to a gate of a transistor 640. One of a source and a drain of the
transistor 640 is electrically connected to a photosensor reference
signal line 672, and the other of the source and the drain thereof
is electrically connected to one of a source and a drain of a
transistor 656. A gate of the transistor 656 is electrically
connected to a gate signal line 659, and the other of the source
and the drain thereof is electrically connected to a photosensor
output signal line 671.
[0330] Note that in circuit diagrams in this specification, a
transistor including an oxide semiconductor layer is denoted by a
symbol "OS" so that it can be identified as a transistor including
an oxide semiconductor layer. In FIG. 11A, the transistor 640 and
the transistor 656 are transistors including an oxide semiconductor
layer.
[0331] FIG. 11B is a cross-sectional view of the photodiode 602 and
the transistor 640 in the photosensor. The photodiode 602
functioning as a sensor and the transistor 640 are provided over a
substrate 601. A substrate 613 is provided over the photodiode 602
and the transistor 640 with an adhesive layer 608 interposed
therebetween.
[0332] An insulating layer 631, a protective insulating layer 632,
an interlayer insulating layer 633, and an interlayer insulating
layer 634 are provided over the transistor 640. The photodiode 602
is provided over the interlayer insulating layer 633. In the
photodiode 602, a first semiconductor layer 606a, a second
semiconductor layer 606b, and a third semiconductor layer 606c are
stacked in that order over the interlayer insulating layer 633. The
first semiconductor layer 606a is electrically connected to an
electrode layer 641 which is provided over the interlayer
insulating layer 633, and the third semiconductor layer 606c is
electrically connected to an electrode layer 642 which is provided
over the interlayer insulating layer 634.
[0333] The electrode layer 641 is electrically connected to a
conductive layer 643 which is formed in the interlayer insulating
layer 634, and the electrode layer 642 is electrically connected to
a gate electrode layer 645 through an electrode layer 644. The gate
electrode layer 645 is electrically connected to a gate electrode
layer of the transistor 640, that is, the photodiode 602 is
electrically connected to the transistor 640.
[0334] Here, a pin photodiode in which a semiconductor layer having
a p-type conductivity as the first semiconductor layer 606a, a
high-resistance semiconductor layer (i-type semiconductor layer) as
the second semiconductor layer 606b, and a semiconductor layer
having an n-type conductivity as the third semiconductor layer 606c
are stacked is illustrated as an example.
[0335] The first semiconductor layer 606a is a p-type semiconductor
layer and can be formed using an amorphous silicon film containing
an impurity element imparting p-type conductivity. The first
semiconductor layer 606a is formed by a plasma CVD method with the
use of a semiconductor source gas containing an impurity element
belonging to Group 13 (such as boron (B)). As the semiconductor
source gas, silane (SiH.sub.4) may be used. Alternatively,
Si.sub.2H.sub.6, SiH.sub.2Cl.sub.2, SiHCl.sub.3, SiCl.sub.4,
SiF.sub.4, or the like may be used. Further alternatively, an
amorphous silicon film which does not contain an impurity element
may be formed, and then, an impurity element may be introduced to
the amorphous silicon film with the use of a diffusion method or an
ion implantation method. Heating or the like may be conducted after
introducing the impurity element by an ion implantation method or
the like in order to diffuse the impurity element. In this case, as
a method of forming the amorphous silicon film, an LPCVD method, a
vapor deposition method, a sputtering method, or the like may be
employed. The first semiconductor layer 606a is preferably formed
to have a thickness of greater than or equal to 10 nm and less than
or equal to 50 nm.
[0336] The second semiconductor layer 606b is an i-type
semiconductor layer (intrinsic semiconductor layer) and is formed
using an amorphous silicon film. As for formation of the second
semiconductor layer 606b, an amorphous silicon film is formed with
the use of a semiconductor source gas by a plasma CVD method. As
the semiconductor source gas, silane (SiH.sub.4) may be used.
Alternatively, Si.sub.2H.sub.6, SiH.sub.2Cl.sub.2, SiHCl.sub.3,
SiCl.sub.4, SiF.sub.4, or the like may be used. The second
semiconductor layer 606b may be alternatively formed by an LPCVD
method, a vapor deposition method, a sputtering method, or the
like. The second semiconductor layer 606b is preferably formed to
have a thickness of greater than or equal to 200 nm and less than
or equal to 1000 nm. Ideally, an intrinsic semiconductor layer
refers to a semiconductor layer which does not contain an impurity
and whose Fermi level is positioned substantially in the center of
a forbidden band; however, the second semiconductor layer 606b may
be formed using a semiconductor into which an impurity serving as a
donor (e.g., phosphorus (P) or the like) or an impurity serving as
an acceptor (e.g., boron (B) or the like) is added in order that
the Fermi level is positioned substantially in the center of the
forbidden band.
[0337] The third semiconductor layer 606c is an n-type
semiconductor layer and is formed using an amorphous silicon film
containing an impurity element imparting n-type conductivity. The
third semiconductor layer 606c is formed by a plasma CVD method
with the use of a semiconductor source gas containing an impurity
element belonging to Group 15 (e.g., phosphorus (P)). As the
semiconductor source gas, silane (SiH.sub.4) may be used.
Alternatively, Si.sub.2H.sub.6, SiH.sub.2Cl.sub.2, SiHCl.sub.3,
SiCl.sub.4, SiF.sub.4, or the like may be used. Further
alternatively, an amorphous silicon film which does not contain an
impurity element may be formed, and then, an impurity element may
be introduced to the amorphous silicon film with use of a diffusion
method or an ion implantation method. Heating or the like may be
conducted after introducing the impurity element by an ion
implantation method or the like in order to diffuse the impurity
element. In this case, as a method of forming the amorphous silicon
film, an LPCVD method, a vapor deposition method, a sputtering
method, or the like may be employed. The third semiconductor layer
606c is preferably formed to have a thickness of greater than or
equal to 20 nm and less than or equal to 200 nm.
[0338] The first semiconductor layer 606a, the second semiconductor
layer 606b, and the third semiconductor layer 606c are not
necessarily formed using an amorphous semiconductor, and they may
be formed using a polycrystalline semiconductor, a microcrystalline
semiconductor, or a semiamorphous semiconductor (SAS).
[0339] Considering Gibbs free energy, the microcrystalline
semiconductor is in a metastable state that is intermediate between
an amorphous state and a single crystal state. That is, the
microcrystalline semiconductor is a semiconductor having a third
state which is stable in terms of free energy and has a short range
order and lattice distortion. Columnar-like or needle-like crystals
grow in a normal direction with respect to a substrate surface. The
Raman spectrum of microcrystalline silicon, which is a typical
example of a microcrystalline semiconductor, is located in lower
wave numbers than 520 cm.sup.-1, which represents a peak of the
Raman spectrum of single crystal silicon. That is, the peak of the
Raman spectrum of the microcrystalline silicon exists between 520
cm.sup.-1 which represents single crystal silicon and 480 cm.sup.-1
which represents amorphous silicon. In addition, microcrystalline
silicon contains hydrogen or halogen of at least 1 at. % in order
to terminate a dangling bond. Moreover, microcrystalline silicon
contains a rare gas element such as helium, argon, krypton, or neon
to further promote lattice distortion, so that stability is
increased and a favorable microcrystalline semiconductor can be
obtained.
[0340] This microcrystalline semiconductor can be formed by a
radio-frequency plasma CVD method with a frequency of greater than
or equal to several tens of megahertz and less than or equal to
several hundreds of megahertz, or a microwave plasma CVD apparatus
with a frequency of greater than or equal to 1 GHz. Typically, the
microcrystalline semiconductor can be formed using silicon hydride
such as SiH.sub.4, Si.sub.2H.sub.6, SiH.sub.2Cl.sub.2, SiHCl.sub.3,
SiCl.sub.4, or SiF.sub.4, which is diluted with hydrogen. With a
dilution with one or plural kinds of rare gas elements selected
from helium, argon, krypton, and neon in addition to silicon
hydride and hydrogen, the microcrystalline semiconductor can be
formed.
[0341] In the dilution of silicon hydride, the flow ratio of
hydrogen to silicon hydride is set to 5:1 to 200:1, preferably,
50:1 to 150:1, more preferably, 100:1. Further, a carbide gas such
as CH.sub.4 or C.sub.2H.sub.6, a germanium gas such as GeH.sub.4 or
GeF.sub.4, F.sub.2, or the like may be mixed into a gas containing
silicon.
[0342] In addition, since the mobility of holes generated by the
photoelectric effect is lower than that of electrons, a pin
photodiode has better characteristics when a surface on the p-type
semiconductor layer side is used as a light-receiving surface.
Here, an example in which light 622 received by the photodiode 602
from a surface of the substrate 601, over which the pin photodiode
is formed, is converted into electric signals will be described.
Light from the semiconductor layer side having a conductivity type
opposite to that of the semiconductor layer side on the
light-receiving surface is disturbance light; therefore, the
electrode layer is preferably formed from a light-blocking
conductive layer. Note that a surface of the n-type semiconductor
layer side can alternatively be used as the light-receiving
surface.
[0343] The insulating layer 631, the protective insulating layer
632, the interlayer insulating layer 633, and the interlayer
insulating layer 634 can be formed using an insulating material by
a sputtering method, a spin coating method, a dipping method, spray
coating, a droplet discharge method (e.g., an ink-jet method,
screen printing, or offset printing), roll coating, curtain
coating, knife coating, or the like depending on the material.
[0344] As the insulating layer 631, a single layer or a
stacked-layer of an oxide insulating layer such as a silicon oxide
layer, a silicon oxynitride layer, an aluminum oxide layer, an
aluminum oxynitride layer, or the like can be used.
[0345] As an inorganic insulating material of the protective
insulating layer 632, a single layer or a stacked-layer of a
nitride insulating layer such as a silicon nitride layer, a silicon
nitride oxide layer, an aluminum nitride layer, an aluminum nitride
oxide layer, or the like can be used. High-density plasma CVD with
the use of microwaves (2.45 GHz) is preferably employed since
formation of a dense and high-quality insulating layer having high
withstand voltage is possible.
[0346] For reduction of the surface roughness, an insulating layer
functioning as a planarizing insulating layer is preferably used as
the interlayer insulating layers 633 and 634. The interlayer
insulating layers 633 and 634 can be formed using an organic
material having heat resistance such as an acrylic resin,
polyimide, a benzocyclobutene-based resin, polyamide, or an epoxy
resin. In addition to such organic materials, it is possible to use
a single layer or a stacked layer of a low-dielectric constant
material (a low-k material), a siloxane-based resin,
phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and
the like.
[0347] When the light 622 that enters the photodiode 602 is
detected, data on an object to be detected can be read. Note that a
light source such as a backlight can be used at the time of reading
data on an object to be detected.
[0348] A transistor described as an example in the above embodiment
can be used as the transistor 640. A transistor including an oxide
semiconductor layer that is highly purified by intentionally
eliminating impurities such as hydrogen, moisture, a hydroxyl
group, or hydride (also referred to as a hydrogen compound) has a
suppressed variation in the electric characteristics and is
electrically stable. Therefore, a semiconductor device with high
reliability can be provided.
[0349] This embodiment can be implemented in appropriate
combination with the structure described in any of other
embodiments.
Embodiment 7
[0350] In this embodiment, examples of electronic devices each
including the display device described in the above embodiment will
be described.
[0351] FIG. 12A illustrates an electronic book reader (also
referred to as an e-book reader) which can include housings 9630, a
display portion 9631, operation keys 9632, a solar battery 9633,
and a charge and discharge control circuit 9634. The electronic
book reader is provided with the solar battery 9633 and a display
panel so that the solar battery 9633 and the display panel can be
opened and closed freely. In the electronic book reader, power from
the solar battery is supplied to the display panel or a video
signal processing portion. The electronic book reader illustrated
in FIG. 12A can have a function of displaying various kinds of data
(e.g., a still image, a moving image, and a text image) on the
display portion, a function of displaying a calendar, a date, the
time, or the like on the display portion, a touch-input function of
operating or editing the data displayed on the display portion by
touch input, a function of controlling processing by various kinds
of software (programs), and the like. Note that in FIG. 12A, a
structure including a battery 9635 and a DCDC converter
(hereinafter abbreviated as a converter 9636) is illustrated as an
example of the charge and discharge control circuit 9634.
[0352] The display portion 9631 is a reflective liquid crystal
display device having a touch-input function with the use of photo
sensors and is used in a comparatively bright environment.
Therefore, the structure illustrated in FIG. 12A is preferable
because power generation by the solar battery 9633 and charge in
the battery 9635 can be performed efficiently. Note that a
structure in which the solar battery 9633 is provided on each of a
surface and a rear surface of the housing 9630 is preferable in
order to charge the battery 9635 efficiently. When a lithium ion
battery is used as the battery 9635, there is an advantage of
downsizing or the like.
[0353] The structure and the operation of the charge and discharge
control circuit 9634 illustrated in FIG. 12A are described with
reference to a block diagram in FIG. 12B. The solar battery 9633,
the battery 9635, the converter 9636, a converter 9637, switches
SW1 to SW3, and the display portion 9631 are illustrated in FIG.
12B, and the battery 9635, the converter 9636, the converter 9637,
and the switches SW1 to SW3 correspond to the charge and discharge
control circuit 9634.
[0354] First, an example of the operation in the case where power
is generated by the solar battery 9633 using external light is
described. The voltage of power generated by the solar battery is
raised or lowered by the converter 9636 so that the power has a
voltage for charging the battery 9635. Then, when the power from
the solar battery 9633 is used for the operation of the display
portion 9631, the switch SW1 is turned on and the voltage of the
power is raised or lowered by the converter 9637 so as to be a
voltage needed for the display portion 9631. In addition, when
display on the display portion 9631 is not performed, the switch
SW1 is turned off and the switch SW2 is turned on so that charge of
the battery 9635 may be performed.
[0355] Note that although the solar battery 9633 is described as an
example of a means for charge, charge of the battery 9635 may be
performed with another means. In addition, a combination of the
solar battery 9633 and another means for charge may be used.
[0356] FIG. 13A illustrates a laptop personal computer, which
includes a main body 3001, a housing 3002, a display portion 3003,
a keyboard 3004, and the like. By using the semiconductor device
described in any of the above embodiments, a highly reliable laptop
personal computer can be obtained.
[0357] FIG. 13B is a personal digital assistant (PDA) including a
display portion 3023, an external interface 3025, an operation
button 3024, and the like in a main body 3021. A stylus 3022 is
included as an accessory for operation. By using the semiconductor
device described in any of the above embodiments, a highly reliable
personal digital assistant (PDA) can be obtained.
[0358] FIG. 13C illustrates an example of an electronic book
reader. For example, the electronic book reader includes two
housings, a housing 2701 and a housing 2703. The housing 2701 and
the housing 2703 are combined with a hinge 2711 so that the
electronic book reader 2700 can be opened and closed with the hinge
2711 as an axis. With such a structure, the electronic book reader
2700 can operate like a paper book.
[0359] A display portion 2705 and a display portion 2707 are
incorporated in the housing 2701 and the housing 2703,
respectively. The display portion 2705 and the display portion 2707
may display one image or different images. In the case where the
display portion 2705 and the display portion 2707 display different
images, for example, a display portion on the right side (the
display portion 2705 in FIG. 13C) can display text and a display
portion on the left side (the display portion 2707 in FIG. 13C) can
display images. By using the semiconductor device described in any
of the above embodiments, a highly reliable electronic book reader
can be obtained.
[0360] FIG. 13C illustrates an example in which the housing 2701
includes an operation portion and the like. For example, the
housing 2701 is provided with a power supply terminal 2721,
operation keys 2723, a speaker 2725, and the like. With the
operation key 2723, pages can be turned. Note that a keyboard, a
pointing device, or the like may also be provided on the surface of
the housing, where the display portion is provided. Furthermore, an
external connection terminal (an earphone terminal, a USB terminal,
or the like), a recording medium insertion portion, and the like
may be provided on the rear surface or the side surface of the
housing. Further, the electronic book reader may have a function of
an electronic dictionary.
[0361] The electronic book reader may transmit and receive data
wirelessly. Through wireless communication, desired book data or
the like can be purchased and downloaded from an electronic book
server.
[0362] FIG. 13D is a mobile phone, which includes two housings, a
housing 2800 and a housing 2801. The housing 2801 includes a
display panel 2802, a speaker 2803, a microphone 2804, a pointing
device 2806, a camera lens 2807, an external connection terminal
2808, and the like. In addition, the housing 2800 includes a solar
battery 2810 having a function of charge of the mobile phone, an
external memory slot 2811, and the like. Further, an antenna is
incorporated in the housing 2801.
[0363] Further, the display panel 2802 includes a touch panel. A
plurality of operation keys 2805 which are displayed as images are
indicated by dashed lines in FIG. 13D. Note that a boosting circuit
by which a voltage output from the solar battery 2810 is increased
to be sufficiently high for each circuit is also included.
[0364] In the display panel 2802, the display direction can be
appropriately changed depending on a usage pattern. Further, the
display device is provided with the camera lens 2807 on the same
surface as the display panel 2802, and thus it can be used as a
video phone. The speaker 2803 and the microphone 2804 can be used
for videophone calls, recording and playing sound, and the like as
well as voice calls. Furthermore, the housings 2800 and 2801 which
are developed as illustrated in FIG. 13D can overlap with each
other by sliding; thus, the size of the mobile phone can be
decreased, which makes the mobile phone suitable for being
carried.
[0365] The external connection terminal 2808 can be connected to an
AC adapter and various types of cables such as a USB cable, and
charge and data communication with a personal computer or the like
are possible. Moreover, a large amount of data can be stored by
inserting a storage medium into the external memory slot 2811 and
can be moved.
[0366] Further, in addition to the above functions, an infrared
communication function, a television reception function, or the
like may be provided. By using the semiconductor device described
in any of the above embodiments, a highly reliable mobile phone can
be provided.
[0367] FIG. 13E illustrates a digital video camera which includes a
main body 3051, a display portion A 3057, an eyepiece 3053, an
operation switch 3054, a display portion B 3055, a battery 3056,
and the like. By using the semiconductor device described in any of
the above embodiments, a highly reliable digital video camera can
be provided.
[0368] FIG. 13F illustrates an example of a television set. In the
television set, a display portion 9603 is incorporated in a housing
9601. The display portion 9603 can display images. Here, the
housing 9601 is supported by a stand 9605. By using the
semiconductor device described in any of the above embodiments, a
highly reliable television set can be provided.
[0369] The television set can be operated by an operation switch of
the housing 9601 or a separate remote controller. Further, the
remote controller may be provided with a display portion for
displaying data output from the remote controller.
[0370] Note that the television set is provided with a receiver, a
modem, and the like. With the use of the receiver, general
television broadcasting can be received. Moreover, when the display
device is connected to a communication network with or without
wires via the modem, one-way (from a sender to a receiver) or
two-way (between a sender and a receiver or between receivers) data
communication can be performed.
[0371] This embodiment can be implemented in appropriate
combination with the structure described in any of other
embodiments.
[0372] This application is based on Japanese Patent Application
serial No. 2010-103472 filed with Japan Patent Office on Apr. 28,
2010, the entire contents of which are hereby incorporated by
reference.
* * * * *