U.S. patent application number 14/755663 was filed with the patent office on 2017-01-05 for method of using a sacrifical gate structure to make a metal gate finfet transistor.
The applicant listed for this patent is STMicroelectronics, Inc.. Invention is credited to Nicolas Loubet, Pierre Morin.
Application Number | 20170005169 14/755663 |
Document ID | / |
Family ID | 57684070 |
Filed Date | 2017-01-05 |
United States Patent
Application |
20170005169 |
Kind Code |
A1 |
Loubet; Nicolas ; et
al. |
January 5, 2017 |
METHOD OF USING A SACRIFICAL GATE STRUCTURE TO MAKE A METAL GATE
FINFET TRANSISTOR
Abstract
A self-aligned SiGe FinFET device features a relaxed channel
region having a high germanium concentration. Instead of first
introducing germanium into the channel and then attempting to relax
the resulting strained film, a relaxed channel is formed initially
to accept the germanium. In this way, a presence of germanium can
be established without straining or damaging the lattice. Gate
structures are patterned relative to intrinsic silicon fins, to
ensure that the gates are properly aligned, prior to introducing
germanium into the fin lattice structure. After aligning the gate
structures, the silicon fins are segmented to elastically relax the
silicon lattice. Then, germanium is introduced into the relaxed
silicon lattice, to produce a SiGe channel that is substantially
stress-free and also defect-free. Using the method described,
concentration of germanium achieved in a structurally stable film
can be increased to a level greater than 85%.
Inventors: |
Loubet; Nicolas;
(Guilderland, NY) ; Morin; Pierre; (Albany,
NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics, Inc. |
Coppell |
TX |
US |
|
|
Family ID: |
57684070 |
Appl. No.: |
14/755663 |
Filed: |
June 30, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/0623 20130101;
H01L 29/785 20130101; H01L 29/66545 20130101; H01L 2029/7858
20130101; H01L 29/1054 20130101; H01L 29/66795 20130101; H01L
29/161 20130101; H01L 29/6656 20130101; H01L 29/41791 20130101;
H01L 29/495 20130101; H01L 27/0886 20130101; H01L 29/7849 20130101;
H01L 29/0649 20130101 |
International
Class: |
H01L 29/10 20060101
H01L029/10; H01L 29/161 20060101 H01L029/161; H01L 29/66 20060101
H01L029/66; H01L 29/06 20060101 H01L029/06; H01L 29/417 20060101
H01L029/417; H01L 29/78 20060101 H01L029/78 |
Claims
1. A method, comprising: forming a plurality of fins extending
vertically outward from a surface of a substrate comprised of a
first semiconductor material, each of the fins being a contiguous
single crystal member extending from the substrate and also being
comprised of the first semiconductor material; forming a plurality
of gate structures in contact with three sides of each of the fins,
each gate structure including a sacrificial gate member; relaxing
the fins elastically by segmenting each of the fins into a
respective plurality of fin segments, the segmenting exposing
sidewalls of each of the fin segments; removing sacrificial gate
members from the gate structures; incorporating a second
semiconductor material into the fin segments; forming metal gates
in the gate structures, each metal gate substantially centered over
one of the plurality of fin segments and extending on at least
three sides of the respective fin segment; and forming source and
drain regions on the exposed sidewalls of the fin segments, with a
channel region being within respective fin segments.
2. The method of claim 1 wherein forming the source and drain
regions entails forming epitaxial extensions on portions of the
fins outside the gate structures.
3. The method of claim 2, further comprising forming contacts to
the source and drain regions via the epitaxial extensions.
4. The method of claim 1 wherein the substrate includes a buried
oxide layer.
5. The method of claim 1 wherein the second semiconductor material
is germanium and a concentration of the second semiconductor
material in the relaxed fins exceeds 85%.
6. The method of claim 1 wherein the relaxed fins are substantially
free of crystalline structure defects.
7. The method of claim 1 wherein the sacrificial gate members are
made of polysilicon.
8. The method of claim 1 wherein incorporating the second
semiconductor material into the relaxed fins is accomplished using
one or more of selective epitaxy, non-selective epitaxy, an
oxidation process, a condensation process, and a diffusion
process.
9. The method of claim 1 wherein the second semiconductor material
includes one or more of germanium, indium, phosphorous, gallium,
and arsenic.
10. The method of claim 1 wherein relaxing the fins elastically
includes: cutting the fins to form fin segments aligned with the
gate structures, the fin segments spaced apart by inter-fin gaps;
and filling the inter-fin gaps with an insulator.
11. A method, comprising: forming a silicon fin as a contiguous
single crystal member extending from a silicon substrate; aligning
gate structures to the silicon fin, each gate structure including a
gate dielectric, a sacrificial polysilicon gate, and a pair of
sidewall spacers; cutting the silicon fin to form a plurality of
silicon fin segments; removing the sacrificial polysilicon gate
from the gate structures; transforming the silicon fin segments
into germanium-rich SiGe fin segments, using an oxidizing
condensation process; depositing metal gates between the sidewall
spacers of each pair of sidewall spacers, the metal gates extending
on at least three sides of a respective fin segment; and forming
source and drain regions on the fin segments with a channel region
being within the fin.
12. The method of claim 11 wherein the forming the source and drain
regions includes selectively growing epitaxial extensions.
13. The method of claim 12 wherein the epitaxial extensions are
substantially diamond shaped.
14. The method of claim 12 wherein the epitaxial extensions include
one of more of silicon, germanium, carbon, gallium, arsenic,
indium, phosphorous, and combinations thereof.
15. The method of claim 11 wherein the silicon substrate is one of
a silicon on insulator (SOI) substrate, a silicon
germanium-on-insulator (SiGe-O-I) substrate, and a strained
silicon-on-insulator (sSOI) substrate.
16-20. (canceled)
21. A method, comprising: forming a plurality of at least three
fins spaced at regular intervals on a surface of a substrate
comprised of silicon, the fins including germanium having a
concentration that exceeds 85% and a silicon concentration that is
greater than 5% but less than 14%; cutting the fins to form a
plurality of fin segments; forming a plurality of gate structures
arranged in a transverse direction relative to the fin segments,
each gate structure including a metal gate substantially centered
over one of the plurality of fin segments and extending on at least
three sides of the respective fin segment; and forming epitaxial
source and drain extensions that expand the fin segments at acute
angles relative to a vertical axis of the fin segment, a channel
region being within the fin.
22. The method of claim 21 wherein the silicon substrate includes a
buried oxide layer.
23. The method of claim 21 wherein forming the fin segments
includes forming structures having aspect ratios greater than
5.0.
24. The method of claim 21 wherein forming the fin segments
includes forming structures having footprints smaller than 1000
nm.sup.2.
25. The method of claim 21 wherein the fin segments are
substantially free of lattice defects.
Description
BACKGROUND
[0001] 1. Technical Field
[0002] The present disclosure generally relates to techniques for
fabricating an array of high performance FinFET devices.
[0003] 2. Description of the Related Art
[0004] Advanced integrated circuits often feature strained channel
transistors, silicon-on-insulator (SOI) substrates, FinFET
structures, or combinations thereof, in order to continue scaling
transistor gate lengths below 20 nm. Such technologies allow the
channel length of the transistor to shrink while minimizing
detrimental consequences such as current leakage and other short
channel effects.
[0005] A FinFET is an electronic switching device in which a
conventional planar semiconducting channel is replaced by a
semiconducting fin that extends outward from the substrate surface.
In such a device, the gate, which controls current flow in the fin,
wraps around three sides of the fin so as to influence current flow
from three surfaces instead of one. The improved control achieved
with a FinFET design results in faster switching performance and
reduced current leakage than is possible with a planar transistor.
FinFETs are described in further detail in U.S. Pat. No. 8,759,874,
and U.S. Patent Application Publication U.S. 2014/0175554, assigned
to the same assignee as the present patent application.
[0006] Strained silicon transistors have been developed to increase
mobility of charge carriers, i.e., electrons or holes, passing
through a semiconductor lattice. Incorporating strain into the
channel of a semiconductor device stretches the crystal lattice,
thereby increasing charge carrier mobility in the channel so that
the device becomes a more responsive switch. Introducing a
compressive strain into a PFET transistor tends to increase hole
mobility in the channel, resulting in a faster switching response
to changes in voltage applied to the transistor gate. Likewise,
introducing a tensile strain into an NFET transistor tends to
increase electron mobility in the channel, also resulting in a
faster switching response.
[0007] There are many ways to introduce tensile or compressive
strain into transistors, for both planar devices and FinFETs. Such
techniques typically entail incorporating into the device epitaxial
layers of one or more materials having crystal lattice dimensions
or geometries that differ slightly from those of the silicon
substrate. The epitaxial layers can be made of doped silicon or
silicon germanium (SiGe), for example. Such epitaxial layers can be
incorporated into source and drain regions, into the transistor
gate that is used to modulate current flow in the channel, or into
the channel itself, which is a portion of the fin. For example, one
way to introduce strain is to replace bulk silicon from the source
and drain regions, or from the channel, with silicon compounds such
as silicon germanium. Because Si-Ge bonds are longer than Si-Si
bonds, there is more open space in a SiGe lattice. Electrons thus
move more freely through a lattice that contains elongated Si-Ge
and Ge-Ge bonds than through a lattice that contains shorter Si-Si
bonds. The presence of germanium atoms having longer bonds tends to
stretch the lattice, causing internal strain. Replacing silicon
atoms with SiGe atoms can be accomplished, for example, during a
controlled process of epitaxial crystal growth, in which a new SiGe
crystal layer is grown from the surface of a bulk silicon crystal,
while maintaining the same crystal structure of the underlying bulk
silicon crystal. Alternatively, strain can be induced in the fin
from below the device by using various types of SOI substrates. An
SOI substrate features a buried insulator, typically a buried oxide
layer (BOX) underneath the active area. SOI FinFET devices have
been disclosed in patent applications assigned to the present
assignee, for example, U.S. patent application Ser. No. 14/231,466,
entitled "SOI FinFET Transistor with Strained Channel," which is
hereby incorporated by reference in its entirety.
BRIEF SUMMARY
[0008] Strain and mobility effects in the channel of a FinFET can
be tuned by controlling the size and the elemental composition of
the fins. It is advantageous for SiGe films to contain a high
concentration of germanium, e.g., in the range of at least 25%-40%,
to provide enhanced electron mobility compared with lower
concentration SiGe films. Carrier mobility in the channel region
determines overall transistor performance. Consequently, it is
desirable to increase to a level as high as possible the percent
concentration of germanium atoms in the fins of a SiGe FinFET.
[0009] While a strained silicon lattice is beneficial, creating
strain by incorporating germanium atoms using existing methods
tends to damage the crystal lattice. As a result, the lattice
structures of germanium-rich films tend to be mechanically
unstable, especially if they contain a high number of structural
defects such as faults, or dislocations. Furthermore, such a
mechanically unstable fin may be structurally limited with regard
to its aspect ratio, or height:width ratio. Such a limitation is
undesirable because one advantage of a FinFET is that the fin,
being a vertical structure, has a small footprint. Dislocation
defects that cause such instability can be avoided by creating a
germanium-rich film that is relaxed, as an alternative to a
strained film. A self-aligned SiGe FinFET device described herein
features a relaxed channel region having a high germanium
concentration. Instead of first introducing germanium into the
channel and then attempting to relax the resulting strained film, a
relaxed channel is formed initially to accept the germanium. Thus,
a presence of germanium can be established without straining or
damaging the lattice. In the CMOS FinFET fabrication method
described herein, sacrificial gate structures are patterned
relative to intrinsic silicon fins, to ensure that the gates are
properly aligned, prior to introducing germanium into the fin
lattice structure. After aligning the gate structures, the silicon
fins are segmented to elastically relax the silicon lattice. Then,
germanium is introduced into the relaxed silicon lattice, to
produce a SiGe channel that is substantially stress-free and also
defect-free. Because stress cannot build up in a segmented fin that
has a small volume, lattice defects simply do not emerge when the
germanium is introduced. In this way, the concentration of
germanium achieved in a structurally stable film can be increased
to a level greater than 85%, producing a film that is nearly pure
germanium.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0010] In the drawings, identical reference numbers identify
similar elements or acts. The sizes and relative positions of
elements in the drawings are not necessarily drawn to scale.
[0011] FIG. 1 is a flow diagram summarizing a sequence of
processing steps in a method that can be used to fabricate
self-aligned FinFETs having SiGe channels that are substantially
free of crystalline structure defects, according to one embodiment
as described herein.
[0012] FIGS. 2A-10C are different views of a FinFET array after
completing each processing step of the method illustrated in FIG.
1. FIGS. 2B, 3B, 4B, 5B, 6B, 8B, 9B, and 10B are top plan views of
the FinFET array. FIGS. 2A, 3A, 4A, 5A, 6A, 8A, 9A, and 10A are
corresponding cross-sectional views of the FinFET array, cut across
the fins. FIGS. 2C, 3C, 4C, 5C, 6C, 8C, 9C, and 10C are
corresponding cross-sectional views of the FinFET array, cut along
the fins.
[0013] FIGS. 2A-2C show the FinFET array following formation of
three fins according to one embodiment as described herein.
[0014] FIGS. 3A-3C show the FinFET array following formation of
four gate structures that wrap around three sides of each fin
according to one embodiment as described herein.
[0015] FIGS. 4A-4C show the FinFET array after segmenting the fins
to create channel regions having a relaxed lattice, according to
one embodiment as described herein.
[0016] FIGS. 5A-5C show the FinFET array after filling spaces
between the gate structures with an oxide, according to one
embodiment as described herein.
[0017] FIGS. 6A-6C show the FinFET array after removal of
sacrificial polysilicon gates from the gate structures, according
to one embodiment as described herein. FIG. 7A is a cross-sectional
view of the FinFET array, cut across the fins, after formation of
an overlying film that contains germanium, according to one
embodiment as described herein.
[0018] FIG. 7B is a cross-sectional view of the FinFET array, cut
across the fins, after germanium is incorporated into the fin
segments, according to one embodiment as described herein.
[0019] FIGS. 8A-8C show the FinFET array after replacing the
polysilicon gates with metal gates.
[0020] FIGS. 9A-9C show the FinFET array after formation of source
and drain regions that include epitaxial extensions. FIGS. 10A-100
show the FinFET array after formation of source and drain
contacts.
DETAILED DESCRIPTION
[0021] In the following description, certain specific details are
set forth in order to provide a thorough understanding of various
aspects of the disclosed subject matter. However, the disclosed
subject matter may be practiced without these specific details. In
some instances, well-known structures and methods of semiconductor
processing comprising embodiments of the subject matter disclosed
herein have not been described in detail to avoid obscuring the
descriptions of other aspects of the present disclosure.
[0022] Unless the context requires otherwise, throughout the
specification and claims that follow, the word "comprise" and
variations thereof, such as "comprises" and "comprising" are to be
construed in an open, inclusive sense, that is, as "including, but
not limited to."
[0023] Reference throughout the specification to "one embodiment"
or "an embodiment" means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment. Thus, the appearance of the
phrases "in one embodiment" or "in an embodiment" in various places
throughout the specification are not necessarily all referring to
the same aspect. Furthermore, the particular features, structures,
or characteristics may be combined in any suitable manner in one or
more aspects of the present disclosure. Reference throughout the
specification to integrated circuits is generally intended to
include integrated circuit components built on semiconducting
substrates, whether or not the components are coupled together into
a circuit or able to be interconnected. Throughout the
specification, the term "layer" is used in its broadest sense to
include a thin film, a cap, or the like and one layer may be
composed of multiple sub-layers.
[0024] Reference throughout the specification to conventional thin
film deposition techniques for depositing silicon nitride, silicon
dioxide, metals, or similar materials include such processes as
chemical vapor deposition (CVD), low-pressure chemical vapor
deposition (LPCVD), metal organic chemical vapor deposition
(MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma
vapor deposition (PVD), atomic layer deposition (ALD), molecular
beam epitaxy (MBE), electroplating, electro-less plating, and the
like. Specific embodiments are described herein with reference to
examples of such processes. However, the present disclosure and the
reference to certain deposition techniques should not be limited to
those described. For example, in some circumstances, a description
that references CVD may alternatively be done using PVD, or a
description that specifies electroplating may alternatively be
accomplished using electro-less plating. Furthermore, reference to
conventional techniques of thin film formation may include growing
a film in-situ. For example, in some embodiments, controlled growth
of an oxide to a desired thickness can be achieved by exposing a
silicon surface to oxygen gas or to moisture in a heated
chamber.
[0025] Reference throughout the specification to conventional
photolithography techniques, known in the art of semiconductor
fabrication for patterning various thin films, includes a
spin-expose-develop process sequence typically followed by an etch
process. Alternatively or additionally, photoresist can also be
used to pattern a hard mask (e.g., a silicon nitride hard mask),
which, in turn, can be used to pattern an underlying film.
Reference throughout the specification to conventional etching
techniques known in the art of semiconductor fabrication for
selective removal of polysilicon, silicon nitride, silicon dioxide,
metals, photoresist, polyimide, or similar materials includes such
processes as wet chemical etching, reactive ion (plasma) etching
(RIE), washing, wet cleaning, pre-cleaning, spray cleaning,
chemical-mechanical planarization (CMP) and the like. Specific
embodiments are described herein with reference to examples of such
processes. However, the present disclosure and the reference to
certain deposition techniques should not be limited to those
described. In some instances, two such techniques may be
interchangeable. For example, stripping photoresist may entail
immersing a sample in a wet chemical bath or, alternatively,
spraying wet chemicals directly onto the sample.
[0026] Specific embodiments are described herein with reference to
self-aligned SiGe FinFET devices that have been produced; however,
the present disclosure and the reference to certain materials,
dimensions, and the details and ordering of processing steps are
exemplary and should not be limited to those shown.
[0027] Turning now to the figures, FIG. 1 shows an exemplary
sequence of steps in a method 200 of fabricating a self-aligned
SiGe FinFET, according to one embodiment. Steps 202-218 in the
method 200 are illustrated in FIGS. 2A-10C and described below. In
each set of Figures, B is a top plan view, A is a cross-sectional
view along a fin, and C is a cross-sectional view across the fins,
as indicated by cut lines shown in the top plan view.
[0028] At 202, fins 304 are formed on a silicon-on-insulator
substrate, according to one embodiment as shown in FIGS. 2A-2C. The
SOI substrate includes an active layer over a buried oxide (BOX)
layer 302, on a silicon substrate 300. The thickness of the active
layer can be anywhere within a wide range of about 5-500 nm. SOI
wafers are standard starting materials commonly used in the
semiconductor industry. Alternatively, the BOX layer 302 can be
formed on a bulk silicon wafer by growing, in a diffusion furnace,
a thick oxide, typically 80-120 nm, as is well known in the art.
Or, the substrate starting material can be a pre-strained SOI
(sSOI) substrate or a SiGe-on-insulator (SGOI) substrate, in which
the active layer is SiGe instead of silicon.
[0029] The fins 304 can be patterned from the active layer in a
conventional fashion using direct photolithography and etching with
SiN hard mask.
[0030] Alternatively, the fins 304 can be formed using, for
example, a sidewall image transfer (SIT) process as described in
greater detail in U.S. Patent Application Publication No.
2014/0175554, assigned to the same assignee as the present patent
application.
[0031] The sidewall image transfer process is capable of defining
very high aspect ratio fins 304 using silicon nitride (SiN)
sidewall spacers as a hard mask, instead of patterning the fins 304
using a photolithography mask. According to the sidewall image
transfer technique, a mandrel, or temporary structure, is formed
first, and then silicon nitride is deposited conformally over the
mandrel and planarized to form sidewall spacers on the sides of the
mandrel. Then the mandrel is removed, leaving behind a pair of
narrow sidewall spacers that serve as a mask to create a pair of
silicon fins 304. By either method, the fins 304 extend vertically
outward from a top surface of the substrate as shown in FIG. 2C.
The height of the fins 304 is desirably in the range of about
20-200 nm. In one embodiment, the fins formed on an SOI wafer are
50 nm tall. In another embodiment, fins formed on a bulk silicon
wafer are 100 nm tall. The width of the fins 304 is desirably in
the range of about 5-20 nm. Accordingly, corresponding aspect
ratios of the fins are in the range of about 4-10. The resulting
high aspect ratio fins 304 are shown in FIGS. 2A, 2B, and 2C.
[0032] At 204, dummy gate structures 316 are formed in a transverse
direction relative to the fins 304, according to one embodiment, as
shown in FIGS. 3A-3C. Formation of the dummy gate structures 316 is
part of a replacement metal gate (RMG) process well known in the
art of semiconductor processing. In the RMG process, the dummy gate
structures 316, made of polysilicon, are later replaced with a
permanent metal gate structure. An RMG process is described in
greater detail in U.S. Patent Application Publication No.
2014/0175554.
[0033] The dummy gate structures 316 include a thin gate oxide 308,
a sacrificial gate 310, a hard mask cap 312, and a pair of sidewall
spacers 314.
[0034] First, the gate oxide 308 is conformally deposited to cover
the fins 304. The gate oxide 308 is desirably made of a 3-5 nm
thick high-k gate material such as, for example, SiO.sub.2 or
HfO.sub.2, as is well known in the art. Next, a layer of amorphous
silicon or polysilicon is deposited and patterned using a silicon
nitride hard mask to form the sacrificial gates 310. If amorphous
silicon is used in the sacrificial gates 310, the amorphous silicon
material can be transformed into polysilicon by annealing at a
later step. The dummy gate structures 316 are then aligned to the
fins 304 such that the dummy gate structures 316 are in contact
with three sides of the fins, as shown in FIG. 3C. The sacrificial
gate 310 has a height in the range of about 50-100 nm and a width
in the range of about 15-25 nm, desirably about 20 nm. The hard
mask used to pattern the sacrificial gate 310 is in the range of
20-100 nm thick. The dummy gate structures 316 are shown in FIGS.
3A, 3B, and 3C, covered by the hard mask cap 312 and sidewall
spacers 314. The sidewall spacers 314 are formed on the sacrificial
gate 310 by depositing and patterning a layer of dielectric
material, e.g., silicon dioxide (SiO.sub.2), silicon nitride (SiN),
SiBCN, silicon oxynitride (SiON), SiOCN, silicon carbonate (SiOC),
or the like. In one embodiment, SiN sidewall spacers 314 are formed
on the sides of the sacrificial gate 310 by atomic layer deposition
(ALD). The ALD process deposits SiN conformally over the
sacrificial gate 310, and on top of the fins 304. Following
deposition, the SiN can be etched anisotropically in the usual way
using an RIE process to remove SiN on the horizontal surfaces
between the gate structures 316 while leaving the SiN cap 312 on
top of the sacrificial gates 310 and SiN on the sidewalls of the
sacrificial gates 310. The SiN sidewall spacer thickness is
desirably in the range of about 5-20 nm.
[0035] At 206, the fins 304 are segmented, according to one
embodiment, as shown in FIGS. 4A-4C. Segmentation of the fins 304
can be accomplished by conventional etching with an etching
chemistry that is selective to the dielectric sidewall spacers 314
or, alternatively, by a SIT process as described above. The fin
segments 313 are cut so as to be spaced at regular intervals as
shown in
[0036] FIGS. 4A, 4B, and 4C, such that the dummy gate structures
316 are centered on the fin segments 313. The fin segment lengths
are in the range of about 20-100 nm, and the fin segments 313 are
spaced apart by gaps 315 of about 10 nm. Accordingly, the footprint
area of a fin segment 313 is in the range of about 100-2000
nm.sup.2. The resulting fin segments 313 have an elastically
relaxed silicon lattice in which dislocation defects will not tend
to accumulate. Even if the fin is made of strained silicon or SiGe,
the fin may be fully relaxed following segmentation. Unstrained
silicon fins will tend to remain fully relaxed.
[0037] At 208, the gaps 315 separating the fin segments 313 are
filled with oxide 318 according to one embodiment, as shown in
FIGS. 5A-5C. The oxide 318 is planarized using a conventional CMP
process that stops on the sacrificial gates 310, thereby removing
the hard mask caps 312. At 210, the sacrificial gates 310 are
removed, according to one embodiment, as shown in FIGS. 6A-6C.
Removal of the sacrificial gates 310 can be accomplished using a
conventional wet chemical etchant such as, for example, hot
ammonia, followed by an HF treatment to remove the gate oxide 308
as well.
[0038] At 212, the silicon in segments 313 are transformed into
SiGe-rich fin segments 322 using an oxidizing condensation process,
according to one embodiment, as shown in FIGS. 7A and 7B. First, a
cladding 320 is deposited over the silicon fin segments 313 as
shown in FIG. 7A. Alternatively, the cladding 320 can be
epitaxially grown outward from the top and the sides of the fin
segments 313. The cladding 320 can be, for example, a crystalline
or amorphous form of SiGe that will serve as a source of germanium
for creating the SiGe-rich fin segments 322. Next, the cladding 320
is exposed to an oxygen-rich environment that forms GeO.sub.2 at
the surface of the silicon fin segments 313. However, the chemical
bonds of GeO.sub.2 tend to be unstable, allowing the underlying
silicon in the fin segments 313 to react with the GeO.sub.2 to form
SiGe and SiO.sub.2. This oxidation reaction effectively causes the
germanium to condense into the silicon fin segments 313, producing
SiGe fin segments 322 that are rich in SiGe and surrounded by oxide
324, as shown in FIG. 7B. The resulting SiGe-rich fin segments 322
have a substantially uniform structure in which germanium atoms are
incorporated throughout the silicon crystal lattice with a
concentration that exceeds 85%.
[0039] Alternatively, the cladding 320 can be made of pure
germanium, or a III-V material such as, for example, indium
phosphide (InP), indium gallium arsenide (InGaAs), or the like.
[0040] More generally, fin segments 322 that incorporate a second
semiconductor material can be produced by other processes such as
epitaxial growth, a combination of epitaxy and the condensation
process described above, or a combination of epitaxy and diffusion.
Regardless of the technique used to introduce new materials into
channels, the resulting fin segments 322 remain fully relaxed
because stress cannot accumulate within the small volume of the
small footprint, high aspect ratio fins.
[0041] At 214, a thin low-k dielectric material such as, for
example, HfO.sub.2, and metal gates 326 are formed on the new fin
segments 322 according to one embodiment as shown in FIGS. 8A-8C.
The metal gates 326 are deposited between the pairs of sidewall
spacers 314 in a self-aligned process. The gate stack metals may
include those typically used in metal gate processes, e.g.,
tungsten (W), titanium (Ti), titanium nitride (TiN), work function
materials, and the like. A hard mask cap 328 is formed over the
metal gates 326. During subsequent contact formation, the oxide 318
separating the gates is recessed down to the base of the fin
segments 322. It is noted that each metal gate 326 is substantially
centered over a fin segment 322. Portions of the fin segments 322
that are located directly underneath the metal gates 326 will serve
as transistor channels, while portions of the fin segments 322
outside the influence of the metal gates 326 will serve as source
and drain regions of the devices.
[0042] At 216, source and drain extensions 330 are grown
epitaxially on the sidewalls of the fin segments 322. First, the
SiN sidewall spacers 314 are trimmed using a wet chemical process
such as, for example, phosphoric acid (H.sub.3PO.sub.4), which will
remove SiN selectively to oxide and silicon. Alternatively, an
HF-EG wet etch process can be used in which hydrofluoric acid (HF)
and ethylene glycol (EG) are combined to form a chemical mixture
that removes both SiN and SiO.sub.2 at substantially equal rates.
The HF-EG formulation is advantageous in that it has a slow etch
rate compared with HF alone that provides superior process control
when etching either SiN or SiO.sub.2. If HF-EG is used, a small
amount of the BOX, approximately 5 nm, may be eroded without
substantial impact on the device integrity.
[0043] Then, the source and drain extensions 330 are formed by
selective epitaxy of SiGe, silicon carbide (SiC), or group V
materials from sidewalls of the fin segments 322. The source and
drain extensions 330 extend outward from the ends of each fin
segment 322, expanding the fin segment at acute angles relative to
a vertical axis of the fin segment 322 to produce diamond-shaped
structures, as shown in FIG. 10A. The source and drain extensions
330 may be doped in-situ with boron (B), phosphorous (P), or
arsenic (As), to produce p-type or n-type devices, respectively, in
the usual way.
[0044] At 218, metal contacts 332 to the source and drain regions
and to the source and drain extensions 330 are formed according to
one embodiment, as shown in FIGS. 10A-100. Formation of the metal
contacts 332 uses conventional methods in which a metal liner is
first deposited and reacts with the silicon to form a metal
silicide. Then, a bulk contact metal is deposited in the usual way,
and planarized to stop on the hard mask cap 328.
[0045] It will be appreciated that, although specific embodiments
of the present disclosure are described herein for purposes of
illustration, various modifications may be made without departing
from the spirit and scope of the present disclosure. Accordingly,
the present disclosure is not limited except as by the appended
claims.
[0046] These and other changes can be made to the embodiments in
light of the above-detailed description. In general, in the
following claims, the terms used should not be construed to limit
the claims to the specific embodiments disclosed in the
specification and the claims, but should be construed to include
all possible embodiments along with the full scope of equivalents
to which such claims are entitled. Accordingly, the claims are not
limited by the disclosure.
[0047] The various embodiments described above can be combined to
provide further embodiments. All of the U.S. patents, U.S. patent
application publications, U.S. patent applications, foreign
patents, foreign patent applications and non-patent publications
referred to in this specification and/or listed in the Application
Data Sheet are incorporated herein by reference, in their entirety.
Aspects of the embodiments can be modified, if necessary to employ
concepts of the various patents, applications and publications to
provide yet further embodiments.
* * * * *