U.S. patent application number 14/958432 was filed with the patent office on 2017-01-05 for sub word line driver of a semiconductor memory device.
The applicant listed for this patent is SK hynix Inc.. Invention is credited to Han Kyu LEE.
Application Number | 20170005096 14/958432 |
Document ID | / |
Family ID | 57683016 |
Filed Date | 2017-01-05 |
United States Patent
Application |
20170005096 |
Kind Code |
A1 |
LEE; Han Kyu |
January 5, 2017 |
SUB WORD LINE DRIVER OF A SEMICONDUCTOR MEMORY DEVICE
Abstract
A sub word line driver of a semiconductor memory device
including a sub word line driver is disclosed. The sub word line
driver of a semiconductor memory device comprising: a semiconductor
substrate including an active region extended in a first direction;
a plurality of gate electrodes extended in a second direction
perpendicular to the active region; first and second metal contacts
formed over the active region between the gate electrodes; a
plurality of metal pads coupled to the first metal contacts; and a
plurality of metal signal lines coupled to the second metal
contacts, extended in the second direction, and bent at specific
parts adjacent to the metal pads.
Inventors: |
LEE; Han Kyu; (Seoul,
KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Gyeonggi-do |
|
KR |
|
|
Family ID: |
57683016 |
Appl. No.: |
14/958432 |
Filed: |
December 3, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/0207 20130101;
H01L 27/10891 20130101; H01L 29/42356 20130101; H01L 27/092
20130101; G11C 8/14 20130101; H01L 27/105 20130101; G11C 8/08
20130101 |
International
Class: |
H01L 27/105 20060101
H01L027/105; H01L 29/423 20060101 H01L029/423; H01L 27/092 20060101
H01L027/092; H01L 27/02 20060101 H01L027/02 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 30, 2015 |
KR |
10-2015-0093466 |
Claims
1. A sub word line driver of a semiconductor memory device
comprising: a semiconductor substrate including a PMOS region and a
NMOS region, wherein an active region is formed to extended in a
first direction in the PMOS section; a first metal contacts formed
over an edge of the active region; a second metal contact formed
over a middle of the active region; a gate electrode extended in a
second direction perpendicular to the first direction, and formed
to include a hole through which a part of the active region is
exposed; a metal pads formed over the first metal contact and
coupled to the first metal contacts; and a metal signal lines
coupled to the second metal contacts, extended in the second
direction, and bent in the first direction at a specific parts
adjacent to the metal pads, wherein the second metal contact is
formed over the exposed active region inside the hole of the gate
electrode with a gap between the second metal contact and the gate
electrode. wherein the sub word line driver is repeatedly arranged
in the first direction, and wherein the bent part of the metal
signal line of the sub word line driver is arranged to overlap with
a first adjacent sub word line driver. and the bent part of the
metal signal line of a second adjacent sub word line driver is
arranged to overlap with the sub word line driver such that an
upper portion of the gap in the first direction has substantially a
same size as a lower portion of the gap in the first direction.
2. (canceled)
3. The sub word line driver of claim 1, wherein the sub word line
driver is arranged between a plurality of cell regions of the
semiconductor memory device.
4. The sub word line driver of claim 1, further comprising a PMOS
transistor region and a NMOS transistor region.
5. The sub word line driver of claim 4, wherein a critical
dimension of the gate electrode arranged in the PMOS transistor
region is larger in size than a critical dimension of the gate
electrode arranged in the NMOS transistor region.
6-7. (canceled)
8. The sub word line driver of claim 1, wherein one or more of the
metal signal lines arranged at an outermost part of an upper
portion of the sub word line driver are bent along upper outer
walls of the metal pads, and one or more of the metal signal lines
arranged at an outermost part of an lower portion of the sub word
line driver are bent along lower outer walls of the metal pads.
9-20. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims priority of Korean patent
application No. 10-2015-0093466, filed on 30 Jun. 2015, the
disclosure of which is hereby incorporated in its entirety by
reference.
BACKGROUND OF THE INVENTION
[0002] Embodiments of the present disclosure relate to a
semiconductor memory device and, more particularly, to a sub word
line driver of a semiconductor memory device with a pitched layout
that is repeated.
[0003] A semiconductor memory device may write or read data to or
from memory cells coupled to a word line and a bit line. Memory
cells coupled to a word line may form a single row and operate
according to a voltage applied to the word line.
[0004] With increasing storage capacity in semiconductor memory
devices, a speed delay problem has arisen when a word line voltage
is applied to a word line and its memory cells.
[0005] In order to address the speed delay problem, an improved
scheme has been proposed in which a single word line is divided
into sub word lines and each sub word line is driven by a sub word
line driver. The sub word line driver array includes multiple sub
word line drivers repeatedly arranged between cell regions, and
includes a pitched layout in which a plurality of metal signal
lines repeat in a regular manner.
[0006] The sub word lines include active regions and gate
electrodes. Metal contacts are arranged at both sides and the
center of the active regions, and metal pads are coupled to the
meta contacts.
[0007] In addition, other metal contacts not coupled to the meta
pads may be coupled to a single metal signal line.
[0008] The metal pads may be arranged in the same column at both
sides and the center of the active regions. Since the metal pads
are arranged in a single line, metal signal lines may also be
arranged in a single line with respect to the metal pads.
BRIEF SUMMARY OF THE INVENTION
[0009] Various embodiments of the present disclosure are directed
to a layout of a semiconductor memory device in which part of
arranged metal signal lines of a sub word line driver (SWD) are
bent with respect to a metal pad and therefore distance between a
gate and a metal contact of the sub word line driver (SWD) is
uniform, resulting in improvement of a mismatch among the sub word
line drivers (SWDs).
[0010] In accordance with an aspect of the present disclosure, A
sub word line driver of a semiconductor memory device comprising: a
semiconductor substrate including an active region extended in a
first direction; a plurality of gate electrodes extended in a
second direction perpendicular to the active region; first and
second metal contacts formed over the active region between the
gate electrodes; a plurality of metal pads coupled to the first
metal contacts; and a plurality of metal signal lines coupled to
the second metal contacts, extended in the second direction, and
bent at specific parts adjacent to the metal pads.
[0011] The sub word line driver is repeatedly arranged in a column
direction of the semiconductor memory device.
[0012] The sub word line driver is arranged between a plurality of
cell regions of the semiconductor memory device.
[0013] Further comprising a PMOS transistor region and a NMOS
transistor region.
[0014] A critical dimension of the gate electrode arranged in the
PMOS transistor region is larger in size than a critical dimension
of the gate electrode arranged in the NMOS transistor region.
[0015] The first metal contacts are arranged at both sides and a
center part of the active region.
[0016] Distances between the gate electrodes and the second metal
contacts are uniform.
[0017] One or more of the metal signal lines arranged at an
outermost part of an upper portion of the sub word line driver are
bent along upper outer walls of the metal pads, and one or more of
the metal signal lines arranged at an outermost part of an lower
portion of the sub word line driver are bent along lower outer
walls of the metal pads.
[0018] Bent portions of the metal signal lines of first sub word
line drivers are arranged to overlap with second sub word line
drivers neighboring with the first sub word line driver.
[0019] In accordance with another aspect of the present disclosure,
A sub word line driver of a semiconductor memory device comprising:
a semiconductor substrate including an active region extended in a
first direction; a plurality of gate electrodes extended in a
second direction perpendicular to the active region, and formed to
include rectangular holes through which parts of the active region
are exposed; first metal contacts formed over the active region
between the gate electrodes; second metal contacts formed over the
active region exposed by the holes; a plurality of metal pads
coupled to the first metal contacts; and a plurality of metal
signal lines coupled to the second metal contacts, extended in the
second direction, and bent at specific parts adjacent to the metal
pads.
[0020] The sub word line driver is repeatedly arranged in a column
direction of the semiconductor memory device, and wherein bent
portions of the metal signal lines of first sub word line drivers
are arranged to overlap with second sub word line drivers
neighboring with the first sub word line driver.
[0021] Distances between the gate electrodes and the second metal
contacts are uniform.
[0022] One or more of the metal signal lines arranged at an
outermost part of an upper portion of the sub word line driver are
bent along upper outer walls of the metal pads, and one or more of
the metal signal lines arranged at an outermost part of a lower
portion of the sub word line driver are bent along lower outer
walls of the metal pads.
[0023] In accordance with another aspect of the present disclosure,
A sub word line driver of a semiconductor memory device comprising:
a NMOS transistor region; a semiconductor substrate including one
or more active regions extended in a first direction; a plurality
of gate electrodes extended in a second direction perpendicular to
the active regions; first and second metal contacts formed over the
active regions between the gate electrodes; a plurality of metal
pads coupled to the first metal contacts; and a plurality of metal
signal lines coupled to the second metal contacts, extended in the
second direction, and bent at specific parts adjacent to the metal
pads.
[0024] The sub word line driver is repeatedly arranged in a column.
direction of the semiconductor memory device.
[0025] Neighboring active regions are arranged in pairs, and
wherein the neighboring active regions of each pair are connected
at center parts thereof.
[0026] Four of the gate electrodes are arranged to pass through the
active regions, and wherein two of the four gate electrodes
arranged at center parts of the active regions are coupled to each
other by sides thereof.
[0027] Distances between the gate electrodes and the second metal
contacts are uniform.
[0028] One or more of the metal signal lines arranged at an
outermost part of an upper portion of the sub word line driver are
bent along upper outer walls of the metal pads, and one or more of
the metal signal lines arranged at an outermost part of a lower
portion of the sub word line driver are bent along lower outer
walls of the metal pads.
[0029] Bent portions of the metal signal line of first sub word
line drivers are arranged to overlap with second sub word line
drivers neighboring with the first sub word line driver.
[0030] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are intended to provide further explanation of
the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] FIG. 1 is a layout diagram illustrating a semiconductor
memory device including a sub word line driver (SWD) according to a
comparative example.
[0032] FIG. 2 is a circuit diagram illustrating a driving circuit
of a semiconductor memory device including a sub word line driver
(SWD) according to an embodiment of the present disclosure.
[0033] FIGS. 3A to 3C are layout diagrams illustrating a
semiconductor memory device including a sub word line driver (SWD)
according to an embodiment of the present disclosure.
[0034] FIG. 4 is a layout diagram illustrating a semiconductor
memory device including a sub word line driver (SWD) according to
an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0035] Reference will now be made in detail to embodiments,
examples of which are illustrated in the accompanying drawings.
Wherever possible, the same reference numbers will be used
throughout the drawings to refer to the same or like parts. In the
following description, related known configurations or functions
incorporated herein will be omitted when it may make the subject
matter less clear.
[0036] FIG. is a layout diagram illustrating a semiconductor memory
device including a sub word line driver (SWD) according to a
comparative example.
[0037] Referring to FIG. 1, the sub word line driver (SWD) includes
a PMOS transistor region and an NMOS transistor region. Each of the
PMOS transistor region and the NMOS transistor region includes a
plurality of active regions (100a, 100b), a plurality of gate
electrodes (120a, 120b), a plurality of metal contacts (130, 133,
135, 137), a plurality of metal pads (not shown), and a plurality
of metal signal lines (not shown).
[0038] The active regions (100a, 100b) are formed in a bar shape
extended in a first direction, and are repeatedly arranged in a
second direction. The gate electrodes (120a, 120b) are formed in a
line extended in a second direction perpendicular to the active
regions (100a, 100b). In this case, the gate electrode (120a) of
the PMOS transistor region includes rectangular holes, and two gate
electrodes 120a pass the single active region (100a).
[0039] In addition, four gate electrodes 120b of the NMOS
transistor region are arranged to pass through the single active
region (100b), and two gate electrodes (120b) passing through the
center part of the active region (100b) are connected to each other
by sides thereof.
[0040] The metal contacts (135, 137) arranged at both sides and the
center part of each active region (100a,100b) are coupled to the
metal pads, and each of the remaining metal contacts (130, 133)
other than the metal contacts (135, 137) are connected to one of
the metal signal lines.
[0041] In this case, the metal pads are arranged in the same line
at both sides and the center parts of the active regions (100a,
100b). Since the metal pads are arranged in a single line, the
metal signal lines are also arranged in a single line with respect
to the metal pads.
[0042] As shown in FIG. 1, distances (D1, D2) between the gate
electrodes (120a, 120b) and the metal contacts (130, 133, 135, 137)
located in the pitched layout of the sub word line driver (SWD) are
different, and thus a mismatch among the sub word line drivers
(SWDs) may occur.
[0043] As can be seen from FIG. 1, the metal contacts (130, 133,
135, 137) are not formed in a line and are shifted by a
predetermined distance. However, the metal pads must be arranged in
a single line, and the metal signal lines are also arranged in a
line along the metal pads. As a result, it becomes difficult to
guarantee a process margin among the metal signal lines, the metal
pads, and the metal contacts, and thus there arises a mismatch
among the sub word line drivers (SWDs).
[0044] In addition, the respective distances D1 and D2 between the
gate electrodes (120a, 120b) and the metal contacts (130, 133, 135,
137) varies. Therefore it is impossible to extend the spacing
between each gate electrode and each metal contact, and to extend a
critical dimension (CD) of the gate electrode, which leads to
difficulty in gate patterning.
[0045] FIG. 2 is an equivalent circuit diagram illustrating
semiconductor memory device including a sub word line driver (SWD)
according to an embodiment of the present disclosure. FIG. 2
exemplarily shows 8 SWDs (SWD(1) to SWD(8)) a number of which may
vary according to circuit design.
[0046] Referring to FIG. 2, 4 sub word line drivers (SWD(1),
SWD(2), SWD(3), SWD(4)) in a single row among 8 SWDs (SWD(1) to
SWD(8)) may be coupled to a single metal line M0.
[0047] The remaining 4 SWDs (SWD(5), SWD(6), SWD(7), SWD(8)) in
another single row may be coupled to another single metal line M1.
The 4 SWDs (SWD(1) to SWD(4)) coupled to the metal line M0 and the
4 SWDs (SWD(5) to SWD(8)) coupled to the metal line M1 may be
arranged in different rows.
[0048] The 4 SWDs (SWD(1) to SWD(4)) sharing the metal line M0
extended in a line along a first direction, for example a row
direction, are located in the same row, and the 4 SWDs (SWD(1) to
SWD(4)) will hereinafter be referred to as first SWDs. In addition,
the remaining 4 SWDs (SWD(5) to SWD(8)) coupled to the metal line
M1 extended in a line along the first direction will hereinafter be
referred to as second SWDs.
[0049] The first. SWDs SWD(1) to SWD(4)) and the second SWDs
(SWD(5) to SWD(8)) may be repeatedly disposed in a column direction
in alternate manner.
[0050] Each of the first and second SWDs (SWD(1) to SWD(8)) may
include a single PMOS transistor and two NMOS transistors.
[0051] Gate input signals of the first SWDs (SWD(1) to SWD(4)) may
be a metal line signal M0, and selection inversion signals PB0,
PB2, PB4, and PB6. Source input signals of the first SWDs (SWD(1)
to SWD(4)) may be selection signals (P0, P2, P4, P6, and PGND).
[0052] In addition, Output signal of the first SWDs (SWD(1) to
SWD(4)) may be metal signal lines (S0, S2, S4, S6).
[0053] Gate input signals of the second SWDs (SWD(5) to SWD(8)) may
be a metal line signal M1 the selection inversion signals (PB0,
PB2, PB4, and PB6). Source input signals of the second SWDs (SWD(5)
to SWD(8)) may be the selection signals (P0, P2, P4, P6, and
PGND).
[0054] In addition, output signals of the second SWDs SWD(5) to
SWD(8)) may be metal signal lines (S8, S10, S12, S14).
[0055] FIGS. 3A to 3C are layout diagrams illustrating a
semiconductor memory device including a sub word line driver (SWD)
according to an embodiment of the present disclosure.
[0056] Each of first and second SWDs shown in FIGS. 3A to 3C may
include a PMOS transistor region and an NMOS transistor region.
[0057] The first and second SWDs shown in FIGS. 3A to 3C may
correspond to the first SWDs (SWD(1) to SWD(4)) and the second SWDs
(SWD(5) to SWD(8)) described with reference to FIG. 2,
respectively.
[0058] The first SWD and the second SWD may be arranged in a manner
such that the active region and the gate electrode are vertically
symmetrical.
[0059] Referring to FIG. 3A, each SWD may include a device
isolation region. Each SWD may be isolated by the device isolation
region, and may include a plurality of active regions (10a, 10b,
10c, 10d, 15a, 15b) extended in a first direction.
[0060] The active regions (10, 15) may be repeatedly arranged in a
second direction. A pair of active regions (10c, 10d) adjacent to
the other pair of active regions (10a, 10b) in the second direction
may be shifted by a predetermined distance W in the first
direction.
[0061] A pair of active regions (15a, 15b) may be interconnected in
the center part of the active regions (15) in the NMOS transistor
region.
[0062] A plurality of gate electrodes (20a, 20b) extended in the
second direction perpendicular to the active regions (10, 15) may
be arranged.
[0063] Two gate electrodes (20a) may pass through the PMOS
transistor region. In more detail, each of the two gate electrodes
(20a) may pass through each of the first SWD and the second SWD.
The gate electrode (20a) formed in the PMOS transistor region may
include a plurality of rectangular holes H through which parts of
the active region (10) are exposed.
[0064] In addition, four gate electrodes (20b) may pass through the
NMOS transistor region. In more detail, each pair of four gate
electrodes (20b) may pass through each of the first SWD and the
second SWD. Each pair of four gate electrodes (20b) adjacent to
each other in the second direction at a boundary surface between
the first SWD and the second SWD may be connected to each other by
sides thereof.
[0065] In this case, a critical dimension (CD) of the gate
electrode (20a) arranged in the PMOS transistor region may be
larger in size than the CD of the gate electrode (20b) arranged in
the NMOS transistor region.
[0066] First metal contacts (30a, 30b, 30c, 30d) may be located
over the active region (10) exposed by the holes H of the gate
electrode (20a) of the PMOS transistor region, and second metal
contacts (33a, 33b, 33c, 33d) may be located at both sides of the
edge part and at the center part of the active region (10).
[0067] In addition, first metal contacts (35a, 35b, 35c, 35d) may
be located over the active region (15) disposed between the gate
electrodes (20b) of the NMOS transistor region, and second metal
contacts (37a, 37b, 37c, 37d) may be located at both sides of the
edge part and at the center part of the active region (15). Third
metal contacts (36a, 36b) connected to the gate electrode (20b)
formed in the center part of the active region (15) may be
arranged.
[0068] In this case, the distances D1 and D2 between the first
metal contacts (30, 35) and the gate electrodes (20a, 20b) may be
uniform. Therefore, a minimum distance between the first metal
contacts (30, 35) and the gate electrodes (20a, 20b) is extended
such that a process margin of the metal signal lines to be formed
in a subsequent process may be guaranteed. In addition, a bridge
between the gate electrode and the metal contact may be prevented,
and the CD of the gate electrode may be extended such that the
extended CD may be beneficial to the gate patterning process.
[0069] The arrangement of the metal signal line and the metal pad
will hereinafter be described with reference to FIG. 3B. For
convenience, the elements described with reference to FIG. 3A will
herein be omitted, and only the metal pads and the metal signal
lines will be described.
[0070] First, metal pads (P0, P2, P4, P6) may be arranged in the
PMOS transistor region of the SWD. In this case, each pair of the
metal pads (P0, P2) and the metal pads (P4, P6) may be located in
each row, and the pair of the metal pads (P4, P6) may be shifted
from the neighboring pair of the metal pads (P0, P2) by a
predetermined distance in the second direction. Each of the pairs
of the metal pads (P0, P2, P4, P6) may be contained in neighboring
SWD regions in the second direction. In more detail, the pair of
the metal pads (P0, P2) may be disposed at the outermost region of
a lower portion of the first SWD, and the other pair of the metal
pads (P2, P4) may be disposed at the outermost region of an upper
portion of the second SWD adjacent to the first SWD.
[0071] In addition, metal pads (PB0, PB2, PB4, PB6, PGND) may be
arranged in the NMOS transistor region. Each pair of the metal pads
(PB0, PB2) and the metal pads (PB4, PB6) may be located in each
row, and the pair of the metal pads (PB0, PB2) may be shifted from
the other pair of the metal pads (PB4, PB6 by a predetermined
distance in the second direction.
[0072] Metal signal lines S0 to S14 may be formed in a line
extended in the second direction. The metal signal lines (S0, S2,
S4, S6, S8, S10, S12, S14) may be arranged in a first sub word line
region and a second sub word line region. In more detail, the metal
signal lines (S0, S2, S4, S6) may be sequentially arranged in the
first sub word line region, and the metal signal lines (S8, S10,
S12, S14) may be sequentially arranged in the second sub word line
region in the same manner as in the first sub word line region.
[0073] The metal signal lines (S0, S8) of the PMOS transistor
region may be bent upward along the metal pads (P4, P6) at a
specific part `A` adjacent to the metal pads (P4, P6).
[0074] The metal signal lines (S0, S8) of the NMOS transistor
region may be bent upward along the metal pads (PB4, PB6, PGND) at
a specific part `B` adjacent to the metal pads (PB4, PB6,
PGND).
[0075] In addition, the metal signal lines (S6, S14) of the PMOS
transistor region may be bent downward along the metal pads (P0,
P2) at a specific part `C` adjacent to the metal pads (P0, P2).
[0076] Accordingly, the bent part of the metal signal lines (S0,
S8, S6, S14) which are formed at the outermost regions of one of
the first and second SWDs, may be arranged at the outermost regions
of the other one of the first and second SWDs, which is adjacent to
the one of the first and second SWDs. For example, the bent part of
the metal signal lines (S0 and S8), which are formed at the
outermost regions of the first SWD, may be arranged at the
outermost regions of the second SWD, which is adjacent to the first
SWD. For example, the bent part of the metal signal lines (S6, S14)
which are formed at the outermost regions of the second SWD, may be
arranged at the outermost regions of the first SWD, which is
adjacent to the second SWD.
[0077] FIG. 3C is a layout diagram illustrating the active region
(10), the gate (20), and the metal contacts (30, 33, 35, 37) of
FIG. 3A and the metal pads (P0, P2, P4, P6, PB0, PB2, PB4, PB6,
PGND) and the metal signal lines (S0 to S14) of FIG. 3B. The
arrangement of the metal contacts (30, 33, 35, 37) and the metal
pads (P0, P2, P4, and P6 and PB0, PB2, PB4, PB6, PGND), and the
arrangement of the metal contacts (30, 33, 35, 37) and the metal
signal line (S0 to S14) will hereinafter be described with
reference to FIG. 3C.
[0078] The metal pads (P0, P2, P4, P6) of the PMOS transistor
region may be coupled to the second metal contacts (33d, 33d, 33b,
33a) which are arranged at both sides and the center parts of the
active regions (10d, 10c, 10b, and 10a).
[0079] The metal pads (PB0, PB2, PB4, PB6) of the NMOS transistor
region may be coupled to the third metal contacts (36a, 36b, 36c,
36d) connected to the gate electrode (20b) formed at the center
parts of the active regions (15a, 15b). The metal pad (PGND) of the
NMOS transistor region may be coupled to the second metal contacts
(37a, 37b, 37c, 37d) formed in both edge parts of the active
regions (15a, 15b).
[0080] In addition, the metal signal lines (S0, S8) may be coupled
to the first metal contact (30d) of the PMOS transistor region, and
may be coupled to the first metal contact (35a) of the NMOS
transistor region. The metal signal lines (S2, S10) may be coupled
to the first metal contact (30c) of the PMOS transistor region, and
may be coupled to the first metal contact (35b) of the NMOS
transistor region.
[0081] The metal signal lines (S4, S12) may be coupled to the first
metal contact (30b) of the PMOS transistor region, and may be
coupled to the first metal contact (35c) of the NMOS transistor
region. The metal signal lines (S6, S14) may be coupled to the
first metal contact (30a) of the PMOS transistor region, and may be
coupled to the first metal contact (35d) of the NMOS transistor
region.
[0082] Referring back to FIG. 3A, the distances D1 and D2 between
the first metal contacts (30, 35) and the gate electrodes (20a,
20b) may be uniform. Therefore, a minimum distance between the
first metal contacts (30, 35) and the gate electrodes (20a, 20b)
may be extended, such that a process margin between the metal
signal lines can be guaranteed.
[0083] FIG. 4 is a layout diagram illustrating a semiconductor
memory device including a sub word line driver (SWD) array
according to an embodiment of the present disclosure.
[0084] Referring to FIG. 4, the sub word line driver (SWD) array
may include a plurality of sub word line drivers (SWDs) repeatedly
arranged between the cell regions, and may include the pitched
layout structure in which a plurality of metal signal lines are
regularly repeated.
[0085] For convenience, a (1.times.3) array, in which the sub word
line driver (SWD) described with reference to FIG. 3C is extended
and repeatedly arranged, will hereinafter be described. As can be
seen from FIG. 3C, the sub word line driver (SWD) may include the
PMOS transistor region and the NMOS transistor region, and may
include the plurality of active regions (10, 15), the plurality of
metal contacts (30, 33, 35, 37), the plurality of metal pads (P0,
P2, P4, P6, PB0, PB2, PB4, PB6, PGND), and the plurality of metal
signal lines (S0, S2, S4, S6, S8, S10, S12, S14).
[0086] The metal signal lines (S0 to S14) may be bent along the
metal pads (P0, P2, P4, P6, PB0, PB2, PB4, PB6, PGND) at the
specific part adjacent to the metal pads (P0, P2, P4, P6, PB0, PB2,
PB4, PB6, PGND) such that the metal signal lines (S0 to S14)
deviating from the outermost region of each of the SWDs may overlap
with the neighboring SWDs.
[0087] The metal signal lines (S0, S14) arranged at the outermost
region of each of the sub word line driver (SWD) may be bent upward
or downward along the metal pads (P4, P6, PGND). Also, the sub word
line drivers (SWDs) may be repeatedly arranged as shown in FIG. 4.
Therefore, the metal signal line S0 arranged at the outermost
region of an upper portion of each SWD may be arranged in an empty
space formed by the bent metal signal line S14 in the neighboring
SWD adjacent to the SWD of the metal line S0 in an upper direction.
Therefore, when the SWDs are repeatedly arranged, the metal signal
lines may be arranged across the neighboring SWDs, such that
additional space is not required even though some parts of the meta
signal lines are bent.
[0088] As described above, parts of the metal signal lines are bent
with respect to the metal pads, such that the distances D1 and D2
between the gate and the metal contact of each SWD located in the
pitched layout may be uniform. Therefore, the mismatch among the
SWDs may be improved.
[0089] In addition, a minimum distance between the gate and the
metal contact is extended so that a bridge between the gate and the
metal contact is prevented. As a result, the critical dimension
(CD) of the gate may be extended so that the gate patterning
process margin may be guaranteed.
[0090] As is apparent from the above description, the embodiments
of the present disclosure allow some metal signal lines of a sub
wordline driver (SWD) to be bent on the basis of a metal pad, such
that the embodiments can provide the following effects.
[0091] First, a uniform distance between a gate electrode and a
metal contact of each sub word line driver (SWD) can be maintained,
such that the mismatch between a plurality of sub word line drivers
SWDs) can be improved.
[0092] Second, a minimum distance between a gate electrode and a
metal contact is increased, such that a process margin between the
gate electrode and the metal contact is guaranteed, and the
occurrence of a bridge between the gate electrode and the metal
contact can be prevented. Further, a critical dimension (CD) of
each gate electrode may be extended, such that gate patterning may
be precisely performed.
[0093] Those skilled in the art will appreciate that embodiments of
the present disclosure may be carried out in other ways than those
set forth herein without departing from the scope and
characteristics of these embodiments. The above embodiments are
therefore to be construed in all aspects as illustrative and not
restrictive.
[0094] The above embodiments of the present disclosure are
illustrative and not limitative. Various alternatives and
equivalents are possible. The invention is not limited by the type
of deposition, etching polishing, and patterning steps described
herein. Nor are embodiments limited to any specific type of
semiconductor devices. For example, embodiments may be implemented
in a dynamic random access memory (DRAM) device or non-volatile
memory device. Other additions, subtractions, or modifications are
obvious in view of the present disclosure and are intended to fall
within the scope of the appended claims.
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