U.S. patent application number 15/131470 was filed with the patent office on 2017-01-05 for shift register unit and driving method thereof, gate driving circuit and display apparatus.
The applicant listed for this patent is BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.. Invention is credited to Yipeng CHEN, Minghua XUAN, Yi ZHANG.
Application Number | 20170004775 15/131470 |
Document ID | / |
Family ID | 54032826 |
Filed Date | 2017-01-05 |
United States Patent
Application |
20170004775 |
Kind Code |
A1 |
CHEN; Yipeng ; et
al. |
January 5, 2017 |
SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING
CIRCUIT AND DISPLAY APPARATUS
Abstract
Embodiments of the present disclosure provide a shift register
unit and a driving method thereof, a gate driving circuit and a
display apparatus. The shift register unit includes a reset signal
sub-unit and a scan signal sub-unit. The reset signal sub-unit
includes a first input module, a first output module, and a first
control module. The scan signal sub-unit includes a second input
module, a second output module, and a second control module. The
first input module is connected with the first control module, the
first output module, and a signal input terminal. Both the first
output module and the first control are connected with the scan
signal sub-unit and a reset signal terminal. The second input
module is also connected with the second output module and the
second control module. Both the second output module and the second
control module are connected with a signal output terminal.
Inventors: |
CHEN; Yipeng; (Beijing,
CN) ; ZHANG; Yi; (Beijing, CN) ; XUAN;
Minghua; (Beijing, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
BOE TECHNOLOGY GROUP CO., LTD.
ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. |
Beijing
Ordos |
|
CN
CN |
|
|
Family ID: |
54032826 |
Appl. No.: |
15/131470 |
Filed: |
April 18, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G09G 3/3233 20130101;
G11C 19/184 20130101; G09G 2310/08 20130101; G09G 3/3266 20130101;
G09G 3/3677 20130101; G09G 2310/0286 20130101; G11C 19/28
20130101 |
International
Class: |
G09G 3/3266 20060101
G09G003/3266; G09G 3/3225 20060101 G09G003/3225; G11C 19/28
20060101 G11C019/28 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 1, 2015 |
CN |
201510379790.3 |
Claims
1. A shift register unit including: a reset signal sub-unit and a
scan signal sub-unit; wherein, the reset signal sub-unit includes:
a first input module, a first output module, and a first control
module; the first input module being connected with a signal input
terminal, a first clock signal terminal, the first control module,
and the first output module, used for outputting a signal at the
signal input terminal to the first output module and the first
control module under the control of the first clock signal
terminal; the first output module being also connected with a
second clock signal terminal, a first voltage terminal, a reset
signal terminal, and the scan signal sub-unit, used for outputting
a signal at the second clock signal terminal to the scan signal
sub-unit and the reset signal terminal under the control of the
first voltage terminal and the first input module; the first
control module being also connected with the first voltage
terminal, the first clock signal terminal, a second voltage
terminal, the reset signal terminal, and the scan signal sub-unit,
used for outputting a voltage signal at the second voltage terminal
to the scan signal sub-unit and the reset signal terminal under the
control of the first voltage terminal, the first clock signal
terminal and the first input module; the scan signal sub-unit
includes: a second input module, a second output module, and a
second control module; the second input module being connected with
the first output module, the first control module, the reset signal
terminal, the second clock signal terminal, the second output
module, and the second control module, used for outputting a signal
at the first output module, the first control module, or the reset
signal terminal to the second output module and the second control
module under the control of the second clock signal terminal; the
second output module being also connected with the first clock
signal terminal, the first voltage terminal, and a signal output
terminal, used for outputting a signal at the first clock signal
terminal to the signal output terminal under the control of the
first voltage terminal and the second input module; the second
control module being also connected with the second voltage
terminal, the first voltage terminal, the second clock signal
terminal, and the signal output terminal, used for outputting a
voltage signal at the second voltage terminal to the signal output
terminal under the control of the first voltage terminal, the
second clock signal terminal, and the second input module.
2. The shift register unit of claim 1, wherein the first input
module includes: a first transistor, having a gate connected with
the first clock signal terminal, a first electrode connected with
the signal input terminal, and a second electrode connected with
the first output module and the first control module.
3. The shift register unit of claim 1, wherein the first output
module includes: a second transistor, a third transistor, and a
first capacitor; the second transistor having a gate connected with
the first voltage terminal, a first electrode connected with the
first input module, and a second electrode connected with a gate of
the third transistor; the third transistor having a first electrode
connected with the second clock signal terminal and a second
electrode connected with the scan signal sub-unit and the reset
signal terminal; the first capacitor having one terminal connected
with the gate of the third transistor, and another terminal
connected with the second electrode of the third transistor.
4. The shift register unit of claim 1, wherein the first control
module includes: a fourth transistor, a fifth transistor, a sixth
transistor, and a second capacitor; the fourth transistor having a
gate connected with the first input module, a first electrode
connected with the first clock signal terminal, and a second
electrode connected with a second electrode of the fifth
transistor; the fifth transistor having a gate connected with the
first clock signal terminal and a first electrode connected with
the first voltage terminal; the sixth transistor having a gate
connected with the second electrode of the fourth transistor, a
first electrode connected with the second voltage terminal, and a
second electrode connected with the scan signal sub-unit and the
reset signal terminal; the second capacitor having one terminal
connected with the gate of the sixth transistor and another
terminal connected with the first electrode of the sixth
transistor.
5. The shift register unit of claim 1, wherein the second input
module includes: a seventh transistor, having a gate connected with
the second clock signal terminal, and a first electrode connected
with the first output module, the first control module, and the
reset signal terminal.
6. The shift register unit of claim 1, wherein the second output
module includes: a eighth transistor, a ninth transistor, and a
third capacitor; the eighth transistor having a gate connected with
the first voltage terminal, a first electrode connected with the
second input module, and a second connected with a gate of the
ninth transistor; the ninth transistor having a first electrode
connected with the first clock signal terminal, and a second
connected with the signal output terminal; the third capacitor
having one terminal connected with the gate of the ninth transistor
and another terminal connected with the second electrode of the
ninth transistor.
7. The shift register unit of claim 1, wherein the second control
module includes: a tenth transistor, an eleventh transistor, a
twelfth transistor, and a fourth capacitor; the tenth transistor
having a gate connected with the second input module, a first
electrode connected with the second clock signal terminal, and a
second electrode connected with a second electrode of the eleventh
transistor; the eleventh transistor having a gate connected with
the second clock signal terminal and a first electrode connected
with the first voltage terminal; the twelfth transistor having a
gate connected with the second electrode of the tenth transistor, a
first electrode connected with the second voltage terminal, and a
second electrode connected with the signal output terminal; the
fourth capacitor having one terminal connected with the gate of the
twelfth transistor and another terminal connected with the first
electrode of the twelfth transistor.
8. A gate driving circuit, including at least two stages of shift
register units, each of which is the shift register unit of claim
1; a first stage of shift register unit in the at least two stages
of shift register units having a signal input terminal connected
with an initial signal terminal; except the first stage of shift
register unit, every other shift register unit in the at least two
stages of shift register units having a signal input terminal
connected with a signal output terminal of its adjacent previous
stage of shift register unit.
9. The gate driving circuit of claim 8, wherein the first input
module includes: a first transistor, having a gate connected with
the first clock signal terminal, a first electrode connected with
the signal input terminal, and a second electrode connected with
the first output module and the first control module.
10. The gate driving circuit of claim 8, wherein the first output
module includes: a second transistor, a third transistor, and a
first capacitor; the second transistor having a gate connected with
the first voltage terminal, a first electrode connected with the
first input module, and a second electrode connected with a gate of
the third transistor; the third transistor having a first electrode
connected with the second clock signal terminal and a second
electrode connected with the scan signal sub-unit and the reset
signal terminal; the first capacitor having one terminal connected
with the gate of the third transistor, and another terminal
connected with the second electrode of the third transistor.
11. The gate driving circuit of claim 8, wherein the first control
module includes: a fourth transistor, a fifth transistor, a sixth
transistor, and a second capacitor; the fourth transistor having a
gate connected with the first input module, a first electrode
connected with the first clock signal terminal, and a second
electrode connected with a second electrode of the fifth
transistor; the fifth transistor having a gate connected with the
first clock signal terminal and a first electrode connected with
the first voltage terminal; the sixth transistor having a gate
connected with the second electrode of the fourth transistor, a
first electrode connected with the second voltage terminal, and a
second electrode connected with the scan signal sub-unit and the
reset signal terminal; the second capacitor having one terminal
connected with the gate of the sixth transistor and another
terminal connected with the first electrode of the sixth
transistor.
12. The gate driving circuit of claim 8, wherein the second input
module includes: a seventh transistor, having a gate connected with
the second clock signal terminal, and a first electrode connected
with the first output module, the first control module, and the
reset signal terminal.
13. The gate driving circuit of claim 8, wherein the second output
module includes: a eighth transistor, a ninth transistor, and a
third capacitor; the eighth transistor having a gate connected with
the first voltage terminal, a first electrode connected with the
second input module, and a second connected with a gate of the
ninth transistor; the ninth transistor having a first electrode
connected with the first clock signal terminal, and a second
connected with the signal output terminal; the third capacitor
having one terminal connected with the gate of the ninth transistor
and another terminal connected with the second electrode of the
ninth transistor.
14. The gate driving circuit of claim 8, wherein the second control
module includes: a tenth transistor, an eleventh transistor, a
twelfth transistor, and a fourth capacitor; the tenth transistor
having a gate connected with the second input module, a first
electrode connected with the second clock signal terminal, and a
second electrode connected with a second electrode of the eleventh
transistor; the eleventh transistor having a gate connected with
the second clock signal terminal and a first electrode connected
with the first voltage terminal; the twelfth transistor having a
gate connected with the second electrode of the tenth transistor, a
first electrode connected with the second voltage terminal, and a
second electrode connected with the signal output terminal; the
fourth capacitor having one terminal connected with the gate of the
twelfth transistor and another terminal connected with the first
electrode of the twelfth transistor.
15. A display apparatus, including the gate driving circuit of
claim 8.
16. The display apparatus of claim 15, wherein the first input
module includes: a first transistor, having a gate connected with
the first clock signal terminal, a first electrode connected with
the signal input terminal, and a second electrode connected with
the first output module and the first control module.
17. The display apparatus of claim 15, wherein the first output
module includes: a second transistor, a third transistor, and a
first capacitor; the second transistor having a gate connected with
the first voltage terminal, a first electrode connected with the
first input module, and a second electrode connected with a gate of
the third transistor; the third transistor having a first electrode
connected with the second clock signal terminal and a second
electrode connected with the scan signal sub-unit and the reset
signal terminal; the first capacitor having one terminal connected
with the gate of the third transistor, and another terminal
connected with the second electrode of the third transistor.
18. The display apparatus of claim 15, wherein the first control
module includes: a fourth transistor, a fifth transistor, a sixth
transistor, and a second capacitor; the fourth transistor having a
gate connected with the first input module, a first electrode
connected with the first clock signal terminal, and a second
electrode connected with a second electrode of the fifth
transistor; the fifth transistor having a gate connected with the
first clock signal terminal and a first electrode connected with
the first voltage terminal; the sixth transistor having a gate
connected with the second electrode of the fourth transistor, a
first electrode connected with the second voltage terminal, and a
second electrode connected with the scan signal sub-unit and the
reset signal terminal; the second capacitor having one terminal
connected with the gate of the sixth transistor and another
terminal connected with the first electrode of the sixth
transistor.
19. The display apparatus of claim 15, wherein the second input
module includes: a seventh transistor, having a gate connected with
the second clock signal terminal, and a first electrode connected
with the first output module, the first control module, and the
reset signal terminal.
20. A driving method of a shift register unit, the shift register
unit including a reset signal sub-unit and a scan signal sub-unit,
the reset signal sub-unit including a first input module, a first
output module, and a first control module, and the scan signal
sub-unit including a second input module, a second output module,
and a second control module, and the driving method including: a
first phase, a first input module outputting a signal at a signal
input terminal to a first output module and a first control module;
the first output module storing a signal at the signal input
terminal and outputting a signal at a second clock signal terminal
to a second input module and a reset signal terminal; the first
control module storing a signal at a first clock signal terminal
and outputting a voltage signal at a second voltage terminal to the
second input module and the reset signal terminal; the second input
module being turned off with no signal inputted to a second output
module and a second control module and no signal outputted at a
signal output terminal; a second phase, the first input module
being turned off, and the first output module outputting a signal
at the second clock signal terminal to the second input module and
the reset signal terminal under the control of the signal stored in
the first phase; the first control unit having no signal to output
to the second input module and the reset signal terminal; the
second input module outputting a received signal at the second
clock signal terminal to the second output module and the second
control module; the second output module storing a signal at the
second clock signal terminal and outputting a signal at the first
clock signal terminal to the signal output terminal under the
control of the second clock signal terminal; the second control
module storing a signal at the second clock signal terminal and
outputting a voltage signal at the second voltage terminal to the
signal output terminal under the control of the second clock signal
terminal; a third phase, the first input module outputting a signal
at the signal input terminal to the first output module and the
first control module; the first output module storing a signal at
the signal input terminal; the first control module storing a
voltage signal at the first voltage terminal and outputting a
voltage signal at the second voltage terminal to the second input
module and the reset signal terminal under the control of the first
voltage terminal; the second input module being turned off, and the
second output module outputting a signal at the first clock signal
terminal to the signal output terminal under the control of the
signal stored in the second phase; the second control module having
no signal to output to the signal output terminal; a fourth phase,
the first input module being turned off, and the first output
module having no signal to output to the second input module under
the control of the signal stored in the third phase; the first
control module storing a voltage signal at the first voltage
terminal under the control of the first clock signal terminal and
outputting a voltage signal at the second voltage terminal to the
second input module and the reset signal terminal under the control
of the first voltage terminal; the second input module outputting a
received signal at the second voltage terminal to the second output
module and the second control module; the second output module
having no signal to output to the signal output terminal under the
control of the second voltage terminal; the second control module
outputting a signal at the second voltage terminal to the signal
output terminal under the control of the second voltage terminal
and the first voltage terminal.
Description
[0001] This application claims the benefit under 35 U.S.C.
.sctn.119(a) of Chinese Patent Application No. 201510379790.3,
filed on Jul. 1, 2015, the entire disclosures of which are
incorporated herein by references for all purposes.
TECHNICAL FIELD
[0002] The present disclosure relates to a technical field of
display technology, and particularly to a shift register unit and a
driving method thereof, a gate driving circuit and a display
apparatus.
BACKGROUND ART
[0003] With the rapid development of display technology,
semiconductor element technology has made progress in leaps and
bounds therewith as the core of a display apparatus. As to existing
display apparatuss, the OLED (Organic Light Emitting Diode), which
is a current mode light-emitting device, is more and more applied
to the field of high performance display, due to its
characteristics of autoluminescence, quick response, wide angle of
view, capability of being made on a flexible substrate, etc.
[0004] An OLED display panel constituted by OLED devices is a
current driving device. A brightness of a pixel unit is controlled
by controlling a current flowing into the OLED device in every
pixel unit. In the pixel unit, there set a pixel circuit, which, as
shown in FIG. 1, may at least include a switch transistor M1 (TFT,
Thin Film Transistor) for receiving a line scan signal GATE, a
driving transistor M2 for driving an OLED device to emit light, and
a storage capacitor C' for storing charges. Particularly, when the
switch transistor M1 is turned on, a data signal DATA may be output
to a gate of the driving transistor M2, and the driving transistor
M2 is made to drive the OLED device to emit light under the
function of a supply voltage VDD.
[0005] In a display process of the OLED panel, in order to avoid an
impact on the display of present frame of picture caused by
voltages remained at the gate of the driving transistor M2 and
across the storage capacitor C', it's required to input a reset
signal RESET to the above pixel circuit so as to release the
voltages at the gate of the driving transistor M2 and across the
storage capacitor C'. Bonding technology is required, through which
a driving circuit capable of providing the reset signal RESET needs
to be bonded to a non-display area of the OLED display panel while
a driving circuit capable of providing the above line scan signal
GATE is bonded to the non-display area of the OLED display panel.
And it's also necessary to provide voltage signal and clock signal
respectively for the above two driving circuits. Therefore, it may
result in a complex circuit structure of the driving part and an
increasing cost, and is also adverse to a design of narrow
frame.
SUMMARY
[0006] Embodiments of the present disclosure provide a shift
register unit and a driving method thereof, a gate driving circuit
and a display apparatus, which are able to solve problems of cost
increase and being adverse to narrow frame design caused by
adopting bonding technology in an OLED display device.
[0007] In order to achieve the above purpose, embodiments of the
present disclosure adopt technical solutions as below.
[0008] In a first aspect of embodiments of the present disclosure,
a shift register unit is provided. The shift register unit may
include a reset signal sub-unit and a scan signal sub-unit. The
reset signal sub-unit may include a first input module, a first
output module and a first control module. The first input module is
connected with a signal input terminal, a first clock signal
terminal, the first control module, and the first output module,
and is used for outputting a signal at the signal input terminal to
the first output module and the first control module under the
control of the first clock signal terminal. The first output module
is also connected with a second clock signal terminal, a first
voltage terminal, a reset signal terminal, and the scan signal
sub-unit, and is used for outputting a signal at the second clock
signal terminal to the scan signal sub-unit and the reset signal
terminal under the control of the first voltage terminal and the
first input module. The first control module is further connected
with the first voltage terminal, the first clock signal terminal, a
second voltage terminal, the reset signal terminal, and the scan
signal sub-unit, and is used for outputting a voltage signal at the
second voltage terminal to the scan signal sub-unit and the reset
signal terminal under the control of the first voltage terminal,
the first clock signal terminal and the first input module. The
scan signal sub-unit may include a second input module, a second
output module and a second control module. The second input module
is connected with the first output module, the first control
module, the reset signal terminal, the second clock signal
terminal, the second output module, and the second control module,
and is used for outputting a signal at the first output module, the
first control module, or the reset signal terminal to the second
output module and the second control module under the control of
the second clock signal terminal. The second output module is also
connected with the first clock signal terminal, the first voltage
terminal, and a signal output terminal, and is used for outputting
a signal at the first clock signal terminal to the signal output
terminal under the control of the first voltage terminal and the
second input module. The second control module is also connected
with the second voltage terminal, the first voltage terminal, the
second clock signal terminal, and the signal output terminal, and
is used for outputting a voltage signal at the second voltage
terminal to the signal output terminal under the control of the
first voltage terminal, the second clock signal terminal and the
second input module.
[0009] In combination with the first aspect and in one
implementation thereof, the first input module may include a first
transistor. The first transistor has a gate connected with the
first clock signal terminal, a first electrode connected with the
signal input terminal, and a second electrode connected with the
first output module and the first control module.
[0010] In combination with the first aspect and the above
implementation, in another implementation of the first aspect, the
first output module may include: a second transistor, a third
transistor and a first capacitor. The second transistor has a gate
connected with the first voltage terminal, a first electrode
connected with the first input module, and a second electrode
connected with a gate of the third transistor. The third transistor
has a first electrode connected with the second clock signal
terminal, and a second electrode connected with the scan signal
sub-unit and the reset signal terminal. The first capacitor has one
terminal connected with the gate of the third transistor, and
another terminal connected with the second electrode of the third
transistor.
[0011] In combination with the first aspect and the above
implementation, in yet another implementation of the first aspect,
the first control module may include: a fourth transistor, a fifth
transistor, a sixth transistor and a second capacitor. The fourth
transistor has a gate connected with the first input module, a
first electrode connected with the first clock signal terminal, and
a second electrode connected with a second electrode of the fifth
transistor. The fifth transistor has a gate connected with the
first clock signal terminal, a first electrode connected with the
first voltage terminal. The sixth transistor has a gate connected
with the second electrode of the fourth transistor, a first
electrode connected with the second voltage terminal, a second
electrode connected with the scan signal sub-unit and the reset
signal terminal. The second capacitor has one terminal connected
with the gate of the sixth transistor, and another terminal
connected with the first electrode of the sixth transistor.
[0012] In combination with the first aspect and the above
implementation, in yet another implementation of the first aspect,
the second input module may include: a seventh transistor, which
has a gate connected with the second clock signal terminal, a first
electrode connected with the first output module, the first control
module, and the reset signal terminal.
[0013] In combination with the first aspect and the above
implementation, in yet another implementation of the first aspect,
the second output module may include: a eighth transistor, a ninth
transistor and a third capacitor. The eighth transistor has a gate
connected with the first voltage terminal, a first electrode
connected with the second input module, and a second electrode
connected with a gate of the ninth transistor. The ninth transistor
has a first electrode connected with the first clock signal
terminal, and a second electrode connected with the signal output
terminal. The third capacitor has one terminal connected with the
gate of the ninth transistor, and another terminal connected with
the second electrode of the ninth transistor.
[0014] In combination with the first aspect and the above
implementation, in yet another implementation of the first aspect,
the second control module may include: a tenth transistor, an
eleventh transistor, a twelfth transistor and a fourth capacitor.
The tenth transistor has a gate connected with the second input
module, a first electrode connected with the second clock signal
terminal, and a second electrode connected with a second electrode
of the eleventh transistor. The eleventh transistor has a gate
connected with the second clock signal terminal, a first electrode
connected with the first voltage terminal. The twelfth transistor
has a gate connected with the second electrode of the tenth
transistor, a first electrode connected with the second voltage
terminal, a second electrode connected with the signal output
terminal. The fourth capacitor has one terminal connected with the
gate of the twelfth transistor, and another terminal connected with
the first electrode of the twelfth transistor.
[0015] According to a second aspect of embodiments of the present
disclosure, a gate driving circuit is provided. The gate driving
circuit includes at least two stages of any shift register unit as
mentioned above. A signal input terminal of a first stage of shift
register unit is connected with an initial signal terminal. Except
the first stage of shift register unit, a signal input terminal of
every other shift register unit is connected with a signal output
terminal of its adjacent previous stage of shift register unit.
[0016] According to a third aspect of embodiments of the present
disclosure, a display apparatus including the above gate driving
circuit is provided.
[0017] According to a fourth aspect of embodiments of the present
disclosure, a driving method of a shift register unit is provided.
The driving method includes: a first phase, a second phase, a third
phase, and a fourth phase.
[0018] In the first phase, a first input module outputs a signal at
a signal input terminal to a first output module and a first
control module; the first output module stores a signal at the
signal input terminal and outputs a signal at a second clock signal
terminal to a second input module and a reset signal terminal; the
first control module stores a signal at a first clock signal
terminal and outputs a voltage signal at a second voltage terminal
to the second input module and the reset signal terminal; the
second input module is turned off with no signal inputted to a
second output module and a second control module and no signal
outputted at a signal output terminal.
[0019] In the second phase, the first input module is turned off,
and the first output module outputs a signal at the second clock
signal terminal to the second input module and the reset signal
terminal under the control of the signal stored in the first phase;
the first control unit has no signal to output to the second input
module and the reset signal terminal; the second input module
outputs a received signal at the second clock signal terminal to
the second output module and the second control module; the second
output module stores a signal at the second clock signal terminal
and outputs a signal at the first clock signal terminal to the
signal output terminal under the control of the second clock signal
terminal; the second control module stores a signal at the second
clock signal terminal and outputs a voltage signal at the second
voltage terminal to the signal output terminal under the control of
the second clock signal terminal.
[0020] In the third phase, the first input module outputs a signal
at the signal input terminal to the first output module and the
first control module; the first output module stores a signal at
the signal input terminal; the first control module stores a
voltage signal at the first voltage terminal and outputs a voltage
signal at the second voltage terminal to the second input module
and the reset signal terminal under the control of the first
voltage terminal; the second input module is turned off, and the
second output module outputs a signal at the first clock signal
terminal to the signal output terminal under the control of the
signal stored in the second phase; the second control module has no
signal to output to the signal output terminal.
[0021] In the fourth phase, the first input module is turned off,
and the first output module has no signal to output to the second
input module under the control of the signal stored in the third
phase; the first control module stores a voltage signal at the
first voltage terminal under the control of the first clock signal
terminal and outputs a voltage signal at the second voltage
terminal to the second input module and the reset signal terminal
under the control of the first voltage terminal; the second input
module outputs a received signal at the second voltage terminal to
the second output module and the second control module; the second
output module has no signal to output to the signal output terminal
under the control of the second voltage terminal; the second
control module outputs a signal at the second voltage terminal to
the signal output terminal under the control of the second voltage
terminal and the first voltage terminal.
[0022] By utilizing the technical solutions of embodiments of the
present disclosure, on one hand, the reset signal sub-unit may
output a reset signal to the reset signal terminal according to a
signal input at the signal input terminal, so as to reset a gate of
a driving transistor and two terminals of a storage capacitor in a
pixel unit connected with the shift register unit, avoiding an
impact on the display of present frame of image caused by voltages
remained at the gate of the driving transistor and across the
storage capacitor C'; on the other hand, since the output terminal
of the reset signal sub-unit is connected with the scan signal
sub-unit, the above reset signal may also be used as an input
signal for the scan signal sub-unit, making the scan signal
sub-unit output a line scan signal to the signal output terminal
according to the input signal, so as to scan a pixel unit connected
with the shift register unit. In summary, the above shift register
unit can not only provide a line scan signal for a pixel circuit
connected with it, but also provide a reset signal, and the shift
register unit can simultaneously provide the reset signal sub-unit
and the scan signal sub-unit with clock signals only with two clock
signal terminals. Thus, the circuit has a simple structure, in
favor of cost reduction and narrow frame design.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions
of embodiments of the present disclosure or the prior art, drawings
necessary for the description of embodiments or the prior art are
briefly introduced below. The drawings described below are merely
some embodiments of the present disclosure, a person of ordinary
skill in the art can also obtain other drawings according to these
drawings.
[0024] FIG. 1 is a schematic structural diagram of a pixel circuit
provided by the prior art.
[0025] FIG. 2 is a schematic structural diagram of a shift register
unit provided by an embodiment of the present disclosure.
[0026] FIG. 3 is a signal timing diagram for controlling the shift
register unit shown in FIG. 2 provided by an embodiment of the
present disclosure.
[0027] FIG. 4 is a schematic diagram of detailed structure of the
shift register unit shown in FIG. 2.
[0028] FIG. 5 is an equivalent circuit diagram of the shift
register unit shown in FIG. 4 in a first phase P1 in FIG. 3.
[0029] FIG. 6 is an equivalent circuit diagram of the shift
register unit shown in FIG. 4 in a second phase P2 in FIG. 3.
[0030] FIG. 7 is an equivalent circuit diagram of the shift
register unit shown in FIG. 4 in a third phase P3 in FIG. 3.
[0031] FIG. 8 is an equivalent circuit diagram of the shift
register unit shown in FIG. 4 in a fourth phase P4 in FIG. 3.
[0032] FIG. 9 is a schematic structural diagram of a gate driving
circuit formed by cascading the shift register unit shown in FIG.
2.
[0033] 10--a reset signal sub-unit; 101--a first input module;
102--a first output module; 103--a first control module; 20--a scan
signal sub-unit; 201--a second input module; 202--a second output
module; 203--a second control module.
DETAILED DESCRIPTION
[0034] The technical solutions of embodiments of the present
disclosure will be described clearly and completely below in
combination with the drawings in the embodiments of the present
disclosure. The described embodiments are merely part of
embodiments of the present disclosure, but not all embodiments.
Based on embodiments of the present disclosure, all the other
embodiments that a person of ordinary skill in the art may obtain
belong to the protection scope of the present disclosure.
[0035] An embodiment of the present disclosure provides a shift
register unit as shown in FIG. 2. The shift register unit may
include: a reset signal sub-unit 10 and a scan signal sub-unit
20.
[0036] The reset signal sub-unit 10 may include: a first input
module 101, a first output module 102, and a first control module
103.
[0037] The first input module 101 is connected with a signal input
terminal INPUT, a first clock signal terminal CK, a first control
module 103, and a first output module 102. The first input module
101 outputs a signal at the signal input terminal INPUT to the
first output module 102 and the first control module 103 under the
control of the first clock signal terminal CK.
[0038] The first output module 102 is also connected with a second
clock signal terminal CKB, a first voltage terminal VGL, a reset
signal terminal RESET, and a scan signal sub-unit 20. The first
output module 102 outputs a signal at the second clock signal
terminal CKB to the scan signal sub-unit 20 and the reset signal
terminal RESET under the control of the first voltage terminal VGL
and the first input module 101.
[0039] The first control module 103 is also connected with the
first voltage terminal VGL, the clock signal terminal CK, the
second voltage terminal VGH, the reset signal terminal RESET, and
the scan signal sub-unit 20. The first control module 103 outputs a
voltage signal at the second voltage terminal VGH to the scan
signal sub-unit 20 and the reset signal terminal RESET under the
control of the first voltage terminal VGL, the first clock signal
terminal CK, and the first input module 101.
[0040] The scan signal sub-unit 20 may include: a second input
module 201, a second output module 202, and a second control module
203.
[0041] The second input module 201 is connected with the first
output module 102, the first control module 103, the reset signal
terminal RESET, the second clock signal terminal CKB, the second
output module 202, and the second control module 203. The second
input module 201 outputs signals at the first output module 102,
the first control module 103, or the reset signal terminal RESET to
the second output module 202 and the second control module 203
under the control of the second clock signal terminal CKB.
[0042] The second output module 202 is also connected with the
first clock signal terminal CK, the first voltage terminal VGL, and
a signal output terminal OUTPUT. The second output module 202
outputs a signal at the first clock signal terminal CK to the
signal output terminal OUTPUT under the control of the first
voltage terminal VGL and the second input module 201.
[0043] The second control module 202 is also connected with the
second voltage terminal VGH, the first voltage terminal VGL, the
second clock signal terminal CKB, and the signal output terminal
OUTPUT. The second control module 202 outputs a voltage signal at
the second voltage VGH to the signal output terminal OUTPUT under
the control of the first voltage terminal VGL, the second clock
signal terminal CKB, and the second input module 201.
[0044] It should be noted that, firstly, the embodiment of the
present disclosure takes it as example that a low level is input to
the first voltage terminal VGL, which is otherwise grounded, and a
high level is input to the second voltage terminal VGH; secondly, a
signal input to the first clock signal terminal CK has the same
width as and the opposite direction to that input to the second
clock signal terminal CKB, as shown in FIG. 3.
[0045] The shift register unit provided by the embodiment of the
present disclosure includes a reset signal sub-unit and a scan
signal sub-unit. The reset signal sub-unit includes: a first input
module, a first output module, and a first control module. The
first input module is connected with a signal input terminal, a
first clock signal terminal, the first control module, and the
first output module, and is used for outputting a signal at the
signal input terminal to the first output module and the first
control module under the control of the first clock signal
terminal. The first output module is also connected with a second
clock signal terminal, a first voltage terminal, a reset signal
terminal, and the scan signal sub-unit, and is used for outputting
a signal at the second clock signal terminal to the scan signal
sub-unit and the reset signal terminal under the control of the
first voltage terminal and the first input module. The first
control module is also connected with the first voltage terminal,
the first clock signal terminal, a second voltage terminal, the
reset signal terminal, and the scan signal sub-unit, and is used
for outputting a voltage signal at the second voltage terminal to
the scan signal sub-unit and the reset signal terminal under the
control of the first voltage terminal, the first clock signal
terminal and the first input module. The scan signal sub-unit
includes: a second input module, a second output module and a
second control module. The second input module is connected with
the first output module, the first control module, the reset signal
terminal, the second clock signal terminal, the second output
module, and the second control module, and is used for outputting a
signal at the first output module, the first control module or the
reset signal terminal to the second output module and the second
control module under the control of the second clock signal
terminal. The second output module is also connected with the first
clock signal terminal, the first voltage terminal and a signal
output terminal, and is used for outputting a signal at the first
clock signal terminal to the signal output terminal under the
control of the first voltage terminal and the second input module.
The second control module is also connected with the second voltage
terminal, the first voltage terminal, the second clock signal
terminal, and the signal output terminal, and is used for
outputting a voltage signal at the second voltage terminal to the
signal output terminal under the control of the first voltage
terminal, the second clock signal terminal and the second input
module.
[0046] On one hand, the reset signal sub-unit may output a reset
signal to the reset signal terminal according to a signal input at
the signal input terminal, so as to reset a gate of a driving
transistor and two terminals of a storage capacitor in a pixel unit
connected with the shift register unit, avoiding an impact on the
display of the present frame of image caused by voltages remained
at the gate of the driving transistor and across the storage
capacitor C'. On the other hand, since the output terminal of the
reset signal sub-unit is connected with the scan signal sub-unit,
the above reset signal may also be used as an input signal for the
scan signal sub-unit, making the scan signal sub-unit output a line
scan signal to the signal output terminal, according to the input
signal, so as to scan a pixel unit connected with the shift
register unit. In summary, the above shift register unit can not
only provide a line scan signal for a pixel circuit connected with
it, but also provide a reset signal, and the shift register unit
can simultaneously provide the reset signal sub-unit and the scan
signal sub-unit with clock signals only with two clock signal
terminals. Thus, the circuit has a simple structure, in favor of
cost reduction and narrow frame design.
[0047] Examples are given below for detailed illustration of the
structure of the shift register unit.
[0048] Particularly, a first input module 101, as shown in FIG. 4,
may include a first transistor T1, which has a gate connected with
a first clock signal terminal CK, a first electrode connected with
a signal input terminal INPUT, and a second electrode connected
with a first output module 102 and a first control module 103.
[0049] The first output module 102 may include: a second transistor
T2, a third transistor T3, and a first capacitor C1.
[0050] The second transistor T2 has a gate connected with a first
voltage terminal VGL, a first electrode connected with the first
input module 101, and a second electrode connected with a gate of
the third transistor T3. When the first input module 101 has a
structure as mentioned above, the first electrode of the second
transistor T2 is connected to the second electrode of the first
transistor T1.
[0051] The third transistor T3 has a first electrode connected with
a second clock signal terminal CKB, and a second electrode
connected with a scan signal sub-unit 20 and a reset signal
terminal RESET.
[0052] The first capacitor C1 has one terminal connected with the
gate of the third transistor T3, and another terminal connected
with the second electrode of the third transistor T3.
[0053] The control module 103 may include: a fourth transistor T4,
a fifth transistor T5, a sixth transistor T6, and a second
capacitor C2.
[0054] The fourth transistor T4 has a gate connected with the first
input module 101, a first electrode connected with the first clock
signal terminal CK, a second electrode connected with a second
electrode of the fifth transistor T5. When the first input module
101 has a structure as mentioned above, the gate of the fourth
transistor T4 is connected to the second electrode of the first
transistor T1.
[0055] The fifth transistor T5 has a gate connected with the first
clock signal terminal CK, and a first electrode connected with the
first voltage terminal VGL.
[0056] The sixth transistor T6 has a gate connected with the second
electrode of the fourth transistor T4, a first electrode connected
with a second voltage terminal VGH, and a second electrode
connected with the scan signal sub-unit 20 and the reset signal
terminal RESET.
[0057] The second capacitor C2 has one terminal connected with the
gate of the sixth transistor T6, and another terminal connected
with the first electrode of the sixth transistor T6.
[0058] A second input module 201 may include a seventh transistor
T7, which has a gate connected with the second clock signal
terminal CKB, a first electrode connected with the first input
module 102, the reset signal terminal RESET, and the first control
module 103. When the first output module 102 and the first control
module 103 have structures as mentioned above, the gate of the
seventh transistor T7 is connected to the second electrode of the
sixth transistor T6 and the second electrode of the third
transistor T3.
[0059] A second output module 202 may include: an eighth transistor
T8, a ninth transistor T9, and a third capacitor C3.
[0060] The eighth transistor T8 has a gate connected with the first
voltage terminal VGL, a first electrode connected with the second
input module 201, and a second electrode connected with a gate of
the ninth transistor T9. When the second input module 201 has a
structure as mentioned above, the first electrode of the eighth
transistor T8 is connected to the second electrode of the seventh
transistor T7.
[0061] The ninth transistor T9 has a first electrode connected with
the first clock signal terminal CK, and a second electrode
connected with a signal output terminal OUTPUT.
[0062] The third capacitor C3 has one terminal connected with the
gate of the ninth transistor T9, and another terminal connected
with the second electrode of the ninth transistor T9.
[0063] A second control module 203 may include: a tenth transistor
T10, an eleventh transistor T11, a twelfth transistor T12, and a
fourth capacitor C4.
[0064] The tenth transistor T10 has a gate connected with the
second input module 201, a first electrode connected with the
second clock signal terminal CKB, and a second electrode connected
with a second electrode of the eleventh transistor T11. When the
second input module 201 has a structure as mentioned above, the
gate of the tenth transistor T10 is connected to the second
electrode of the seventh transistor T7.
[0065] The eleventh transistor T11 has a gate connected with the
second clock signal terminal CKB, and a first electrode connected
with the first voltage terminal VGL.
[0066] The twelfth transistor T12 has a gate connected with the
second electrode of the tenth transistor T10, a first electrode
connected with the second voltage terminal VGH, and a second
electrode connected with the signal output terminal OUTPUT.
[0067] The fourth capacitor C4 has one terminal connected with the
gate of the twelfth transistor T12, and another terminal connected
with the first electrode of the twelfth transistor T12.
[0068] On this basis, the working principle of the above shift
register unit is described in detail according to the signal timing
diagram shown in FIG. 3.
[0069] In a first phase P1, INPUT=0; CK=0; CKB=1; RESET=1;
OUTPUT=1. It should be noted that in the following embodiment, "0"
represents a low level; "1" represents a high level. Furthermore, a
turned-on circuit is represented with solid line, and a turned-off
circuit is represented with dash line.
[0070] In this case, an equivalent circuit diagram is shown in FIG.
5. All the transistors in the reset signal sub-unit 10: the first
transistor T1, the second transistor T2, the third transistor T3,
the fifth transistor T5, and the sixth transistor T6 are all in On
state; thereby, a high level output at the second clock signal
terminal CKB and a high level output at the second voltage terminal
VGH can be respectively output to the reset signal terminal RESET
and the first electrode of the seventh transistor T7 through the
third transistor T3 and the sixth transistor T6. Moreover, a low
level input at the signal input terminal INPUT may be stored to the
first capacitor C1 through the first transistor T1 and the second
transistor T2; a low level input at the first clock signal terminal
CK may be stored to the second capacitor C2 through the fourth
transistor T4.
[0071] Moreover, since the seventh transistor is in Off state,
there is no signal at the input terminal of the scan signal
sub-unit 20; thereby, there is no signal output at the signal
output terminal OUTPUT. Therefore, in the first phase, the shift
register unit will not output a line scan signal GATE to a pixel
unit connected with the shift register unit.
[0072] In a second phase P2, INPUT=1; CK=1; CKB=0; RESET=0;
OUTPUT=1.
[0073] In this case, an equivalent circuit diagram is shown in FIG.
6. The first transistor T1 is turned off. The first capacitor C1
outputs the low level stored in the first phase P1 to the gate of
the fourth transistor T4 through a node A and the second transistor
T2, thereby turning on the fourth transistor T4. At this time, a
high level output at the first clock signal terminal CK is output
to the gates of the fifth transistor T5 and the sixth transistor
T6, and the fifth transistor T5 and the sixth transistor T6 are
turned off. Furthermore, the low level stored in the first
capacitor C1 is output to the gate of the third transistor T3
through the node A so that the third transistor T3 is in On state,
thereby outputting a low level at the second clock signal terminal
CKB to the reset signal terminal RESET and the first electrode of
the seventh transistor T7.
[0074] Since there is a low level at the reset signal terminal
RESET, a reset signal can be input to a pixel circuit of a pixel
unit connected with the shift register, so as to release voltages
at the gate of the driving transistor M2 and across the storage
capacitor C', thereby avoiding an impact on the display of the
present frame of image caused by voltages remained at the gate of
the driving transistor M2 and across the storage capacitor C'.
[0075] At the same time, since a low level is input to the second
clock signal terminal CKB, the seventh transistor T7 is turned on.
In this case, the reset signal sub-unit 10 outputs a low level
output at the reset signal terminal RESET to the scan signal
sub-unit 20, and all the transistors (T7, T8, T9, T10, T11, and
T12) in the scan signal sub-unit 20 are in On state. At this time,
a low level input at the first electrode of the seventh transistor
T7 is stored to the third capacitor C3 through the eighth
transistor T8. And a high level input at the first clock signal
terminal CK is output to the signal output terminal OUTPUT through
the ninth transistor T9.
[0076] Furthermore, a low level input at the second clock signal
terminal CKB is stored to the fourth capacitor C4 through the tenth
transistor T10, and a low level input at the first voltage terminal
VGL is stored to the fourth capacitor C4 through the eleventh
transistor T11. And a high level input at the second voltage
terminal VGH is output to the signal output terminal OUTPUT through
the twelfth transistor 112.
[0077] In summary, since a low level is output at the reset signal
terminal RESET in the second phase, the shift register is used for
inputting a reset signal to a pixel unit connected with it. A high
level is output at the signal output terminal OUTPUT, so the shift
register unit will not output a line scan signal GATE to a pixel
unit connected with it in the second phase.
[0078] In a third phase P3, INPUT=1; CK=0; CKB=1; RESET=1;
OUTPUT=0.
[0079] In this case, an equivalent circuit diagram is shown in FIG.
7, and the first transistor T1 and the second transistor T2 are in
On state so that a high level input at the signal input terminal
INPUT is stored to the first capacitor C1 and output to the gate of
the third transistor T3, making the third transistor T3 in Off
state. Moreover, a high level input at the signal input terminal
INPUT makes the fourth transistor T4 in Off state. The fifth
transistor T5 is turned on, and a low level input at the first
voltage terminal VGL is stored to the second capacitor C2; then,
the sixth transistor T6 is turned on so that a high level input at
the second voltage terminal VGH is output to the reset signal
terminal RESET and the first electrode of the seventh transistor
T7.
[0080] In this case, since the seventh transistor T7 is in Off
state, a high level at the first electrode of the seventh
transistor T7 is unable to be input to the scan signal sub-unit 20.
At this time, the eighth transistor T8 is turned on, and the third
capacitor C3 outputs the low level stored in the second phase P2 to
the gate of the tenth transistor T10 through a node E and the
eighth transistor T8 so that the tenth transistor T10 is in On
state; thus, a high level input at the second clock signal terminal
CKB is output to the gate of the twelfth transistor T12 through the
tenth transistor T10 so that the twelfth transistor T12 is turned
off. At the same time, the third capacitor C3 outputs the low level
stored in the second phase P2 to the gate of the ninth transistor
T9 through the node E so that a low level input at the first clock
signal terminal CK is output to the signal output terminal OUTPUT
through the ninth transistor T9. Furthermore, the eleventh
transistor T11 is in Off state.
[0081] In summary, since a low level is output at the signal output
terminal OUTPUT in the third phase, a line scan signal GATE can be
output to a pixel unit connected with the shift register unit.
[0082] In a fourth phase P4, INPUT=1; CK=1; CKB=0; RESET=1;
OUTPUT=1.
[0083] In this case, an equivalent circuit diagram is shown in FIG.
8. The first transistor T1 is in Off state, and the second
transistor T2 is turned on. The first capacitor C1 outputs the high
level stored in the third phase P3 to the third transistor T3
through the node A so that the third transistor is in Off state. At
the same time, the first capacitor C1 outputs the high level stored
in the third phase P3 to the gate of the fourth transistor T4
through the node A and the second transistor T2 so that the fourth
transistor T4 is in Off state. Since the first clock signal
terminal CK outputs a high level, the fifth transistor T5 is in Off
state. Furthermore, the second capacitor C2 outputs the low level
stored in the third phase P3 to the gate of the sixth transistor T6
so that the sixth transistor T6 is turned on, thereby outputting a
high level input at the second voltage terminal VGH to the reset
signal terminal RESET and the first electrode of the seventh
transistor T7.
[0084] Furthermore, the seventh transistor T7 and the eighth
transistor T8 are in On state; thus, the above high level is output
to the gate of the ninth transistor T9 through the seventh
transistor T7 and the eighth transistor T8, and the ninth
transistor T9 is turned off. At the same time, a high level input
to the first electrode of the seventh transistor T7 is also output
to the gate of the tenth transistor T10 so that the tenth
transistor is in Off state. Since the second clock signal terminal
inputs a low level, the eleventh transistor T11 is turned on. A low
level input at the first voltage terminal VGL is stored to the
fourth capacitor C4 through a node D, and the low level is output
to the gate of the twelfth transistor T12; thus, the twelfth
transistor T12 is turned on, through which a high level input at
the second voltage terminal VGH is output to the signal output
terminal OUTPUT.
[0085] In summary, in the fourth phase, both the reset signal
terminal RESET and the signal output terminal OUTPUT of the shift
register unit output high levels. Thus, the shift register unit
will output neither a reset signal nor a line scan signal to a
pixel unit connected with it.
[0086] Thereafter, before the display of the next frame of image,
both the reset signal terminal RESET and the signal output terminal
OUTPUT of the shift register unit output high levels.
[0087] It should be noted that the above embodiment of the present
disclosure takes it as example that all the transistors in a shift
register unit and a pixel unit connected with the shift register
unit are P type transistors. Of course, all the transistors
provided by the embodiment of the present disclosure can be N type.
In this case, the modules or transistors connected with the first
voltage terminal VGL in FIG. 2 and FIG. 4 need to be connected to
the second voltage terminal VGH, and the modules or transistors
connected with the second voltage terminal VGH need to be connected
to the first voltage terminal VGL. Furthermore, the control signal
in FIG. 4 needs to be reversed. When the above transistors are all
N type, the shift register unit has the same working process as the
case when all the transistors are P type, which will not be
repeated any more.
[0088] On this basis, a gate driving circuit (GOA circuit for short
below) may consist of at least two stages of above shift register
units.
[0089] Particularly, as shown in FIG. 9, a signal input terminal
INPUT of a first stage of shift register unit RS1 is connected with
an initial signal terminal STV. When the initial signal terminal
STV inputs an initial signal, it represents that a frame of image
starts to display, and the GOA circuit implements progressive scan
to every gate line.
[0090] Except the first stage of shift register unit RS1, the input
signal terminal of every other shift register unit (RS2, RS3, . . .
, RSn) is connected with the signal output terminal OUTPUT of its
adjacent previous stage of shift register unit.
[0091] Thus, every stage of shift register unit may provide a line
scan signal GATE and a reset signal RESET to a pixel unit on the
same line. For example, the first stage of shift register unit RS1
may provide a line scan GATE1 and a reset signal RESET1 to a pixel
unit on the first line, thereby driving pixel units to emit light
line by line.
[0092] It should be noted that the shift register unit in the above
gate driving circuit has the same structure and beneficial effects
as the shift register unit provided by the aforementioned
embodiment. Since the structure and advantages of the shift
register unit have been described in detail in the aforementioned
embodiment, it won't be repeated any more.
[0093] An embodiment of the present disclosure provides a display
apparatus, including a gate driving circuit as mentioned above. It
has the same structure and beneficial effects as the gate driving
circuit provided by the aforementioned embodiment. Since the
structure and advantages of the gate driving circuit have been
described in detail in the aforementioned embodiment, it won't be
repeated any more.
[0094] It should be noted that in the embodiment of the present
disclosure, a display apparatus may specifically include an OLED
display apparatus. For example, the display apparatus may be any
product or component with the function of display, such as a
television, a digital photo frame, a mobile phone, or a tablet,
etc.
[0095] An embodiment of the present disclosure provides a driving
method of a shift register unit. The shift register unit may have a
structure in combination with the description in FIG. 2 or FIG. 4.
The driving method may include a first phase to a fourth phase in
combination with the description in FIG. 3.
[0096] In a first phase P1 as shown in FIG. 3, a first input module
101, as shown in FIG. 2, outputs a signal at the signal input
terminal INPUT to a first output module 102 and a first control
module 103. The first output module 102 stores the signal at the
signal input INPUT and outputs a signal at a second clock signal
terminal CKB to a second input module 201 and a reset signal
terminal RESET. The first control module 103 stores a signal at a
first clock signal terminal CK and outputs a voltage signal at s
second voltage terminal VGH to the second input module and the
reset signal terminal RESET.
[0097] The second input module 201 is turned off. There is no
signal input to a second module 202 and a second control module
203, and there is no signal output at a signal output terminal
OUTPUT.
[0098] In a second phase P2, the first input module 101 is turned
off, and the first output module 102 outputs a signal at the second
clock signal terminal CKB to the second input module 201 and the
reset signal terminal RESET under the signal stored in the first
phase P1; the first control unit 103 has no signal to output to the
second input module 201 and the reset signal terminal RESET.
[0099] In the second phase, when the transistors in a pixel circuit
connected with the shift register unit are all P type transistors,
the second clock signal terminal CKB outputs a low level so that
the shift register unit inputs a low level to the pixel circuit
connected with the shift register unit through the reset signal
terminal RESET, to reset the pixel circuit. When the transistors in
a pixel circuit connected with the shift register unit are all N
type transistors, the direction of the control signal as shown in
FIG. 3 can be reversed, and the shift register unit has the same
working principle as above.
[0100] The second input module 201 outputs a received signal at the
second clock signal terminal CKB to the second output module 202
and the second control module 203. The second output module 202
stores a signal at the second clock signal terminal CKB and outputs
a signal at the first clock signal terminal CK to the signal output
terminal OUTPUT under the control of the second clock signal
terminal CKB. The second control module 203 stores a signal at the
second clock signal terminal CKB and outputs a voltage signal at
the second voltage terminal VGH to the signal output terminal
OUTPUT under the control of the second clock signal terminal
CKB.
[0101] In summary, the shift register unit can output a reset
signal to a pixel circuit connected with it in this phase.
[0102] In a third phase P3, the first input module 101 outputs a
signal at the signal input terminal INPUT to the first output
module 102 and the first control module 103. The first output
module 102 stores a signal at the signal input terminal INPUT. The
first control module 103 stores a voltage signal at the first
voltage terminal VGL and outputs a voltage signal at the second
voltage terminal VGH to the second input module 201 and the reset
signal terminal RESET under the control of the first voltage
terminal VGL.
[0103] The second input module 210 is turned off, and the second
output module 202 outputs a signal at the first clock signal
terminal CK to the signal output terminal OUTPUT under the control
of the signal stored in the second phase P2. The second control
module 203 has no signal to output to the signal output terminal
OUTPUT.
[0104] As shown in FIG. 3, in the third phase, the first clock
signal terminal CK outputs a low level, and the signal output
terminal OUTPUT outputs a low level so that the shift register unit
can output a line scan signal GATE to a pixel circuit connected
with it.
[0105] In a fourth phase P4, the first input module 101 is turned
off, and the first output module 102 has no signal to output to the
second input module 201 under the control of the signal stored in
the third phase P3. The first control module 103 stores a voltage
signal at the first voltage terminal VGL under the control of the
first clock signal terminal CK and outputs a voltage signal at the
second voltage terminal VGH to the second input module 201 and the
reset signal terminal RESET under the control of the first voltage
terminal VGL. Since the second voltage terminal VGH outputs a high
level, the reset signal terminal RESET of the shift register unit
outputs a high level in the phase.
[0106] The second input module 201 outputs a received voltage
signal at the second voltage terminal VGH to the second output
module 202 and the second control module 203. The second output
module 202 has no signal to output to the signal output terminal
OUTPUT under the control of the second voltage terminal VGH. The
second control module 203 outputs a signal at the second voltage
terminal VGH to the signal output terminal OUTPUT under the control
of the second voltage terminal VGH and the first voltage terminal
VGL. Since the second voltage terminal VGH outputs a high level,
the signal output terminal OUTPUT of the shift register unit
outputs a high level in the fourth phase.
[0107] Thereafter, before the display of the next frame of image,
the reset signal terminal RESET and the signal output terminal
OUTPUT of the shift register unit output high levels.
[0108] By utilizing the driving method provided by the embodiment
of the present disclosure, on one hand, a reset signal may be
outputted to a reset signal terminal of a shift register according
to a signal at a signal input terminal, so as to reset a gate of a
driving transistor and two terminals of a storage capacitor in a
pixel unit connected with the shift register unit, avoiding an
impact on the display of the present frame of image caused by
voltages remained at the gate of the driving transistor and across
the storage capacitor C'; on the other hand, since the above reset
signal terminal is connected with the second input module, the
above reset signal may also be used as an input signal for the
second input module, making the shift register unit output a line
scan signal to the signal output terminal, according to the input
signal, so as to scan a pixel unit connected with the shift
register unit. In summary, the above shift register unit can not
only provide a line scan signal for a pixel circuit connected with
it, but also provide a reset signal, and the shift register unit
can simultaneously provide a reset signal sub-unit and a scan
signal sub-unit with clock signals only with two clock signal
terminals. Thus, the circuit has a simple structure, in favor of
cost reduction and narrow frame design.
[0109] What is described above is only specific embodiments of the
present disclosure, but the protection scope of the present
disclosure is not limited thereto. Any person skilled in the art
may readily think of variations or alternatives within the
technology scope disclosed by the present disclosure, which should
all be contained in the protection scope of the present disclosure.
Therefore, the protection scope of the present disclosure should be
in accordance with the claimed protection scope.
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