U.S. patent application number 15/257139 was filed with the patent office on 2016-12-29 for light emitting diode having well and/or barrier layers with superlattice structure.
The applicant listed for this patent is Seoul Viosys Co., Ltd.. Invention is credited to Joo Won CHOI, Gyu Beom KIM, Dong Sun Lee, Sang Joon LEE.
Application Number | 20160380149 15/257139 |
Document ID | / |
Family ID | 39472627 |
Filed Date | 2016-12-29 |
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United States Patent
Application |
20160380149 |
Kind Code |
A1 |
CHOI; Joo Won ; et
al. |
December 29, 2016 |
LIGHT EMITTING DIODE HAVING WELL AND/OR BARRIER LAYERS WITH
SUPERLATTICE STRUCTURE
Abstract
A light emitting diode includes an N-type GaN-based
semiconductor compound layer, a P-type GaN-based semiconductor
compound layer, and an active region disposed between the P-type
and N-type layers, the active region comprising alternately
laminated well layers and barrier layers. The well layers comprise
Al.sub.xIn.sub.yGa.sub.1-(x+y)N, where 0.ltoreq.x, y.ltoreq.1, the
barrier layers comprise Al.sub.xIn.sub.yGa.sub.1-(x+y)N, where
0.ltoreq.x, y.ltoreq.1, and at least one of the barrier layers
comprises first and second layers having different
compositions.
Inventors: |
CHOI; Joo Won; (Ansan-si,
KR) ; Lee; Dong Sun; (Ansan-si, KR) ; KIM; Gyu
Beom; (Ansan-si, KR) ; LEE; Sang Joon;
(Ansan-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Seoul Viosys Co., Ltd. |
Ansan-si |
|
KR |
|
|
Family ID: |
39472627 |
Appl. No.: |
15/257139 |
Filed: |
September 6, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12057842 |
Mar 28, 2008 |
9466761 |
|
|
15257139 |
|
|
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|
Current U.S.
Class: |
257/13 |
Current CPC
Class: |
H01L 33/32 20130101;
H01L 33/12 20130101; H01S 5/34333 20130101; B82Y 20/00 20130101;
H01L 33/06 20130101 |
International
Class: |
H01L 33/06 20060101
H01L033/06; H01L 33/32 20060101 H01L033/32 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 29, 2007 |
KR |
10-2007-0030872 |
Mar 30, 2007 |
KR |
10-2007-0032010 |
Claims
1. A light emitting diode (LED) comprising: an N-type GaN-based
semiconductor compound layer; a P-type GaN-based semiconductor
compound layer; and an active region disposed between the P-type
and N-type layers, the active region comprising alternately
laminated well layers and barrier layers, wherein: the well layers
comprise Al.sub.xIn.sub.yGa.sub.1-(x+y)N, where 0.ltoreq.x,
y.ltoreq.1; the barrier layers comprise
Al.sub.xIn.sub.yGa.sub.1-(x+y)N, where 0.ltoreq.x, y.ltoreq.1; and
at least one of the barrier layers comprises first and second
layers having different compositions.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation of U.S. patent
application Ser. No. 12/057,842, filed on Mar. 28, 2008, and claims
priority from and the benefit of Korean Patent Application No.
10-2007-0030872, filed on Mar. 29, 2007, and Korean Patent
Application No. 10-2007-0032010, filed on Mar. 30, 2007, which are
hereby incorporated by reference for all purposes as if fully set
forth herein.
BACKGROUND OF THE INVENTION
[0002] Field of the Invention
[0003] The present invention relates to a light emitting diode, and
more particularly, to a light emitting diode having well and/or
barrier layers with a superlattice structure.
[0004] Description of the Related Art
[0005] In general, since Group-III-element nitrides, such as GaN,
AlN and InGaN, have an excellent thermal stability and a
direct-transition-type energy band structure, they have recently
come into the spotlight as materials for light emitting diodes
(LEDs) in blue and ultraviolet regions. Particularly, an InGaN
compound semiconductor has been considerably noticed due to its
narrow band gap. LEDs using such a GaN-based compound semiconductor
are used in various applications such as large-sized full-color
flat panel displays, backlight sources, traffic lights, indoor
illumination, high-density light sources, high-resolution output
systems and optical communications. Further, LEDs emitting near
ultraviolet are used in forgery identification, resin cure,
ultraviolet therapy and the like, and can implement visible light
with various colors through combination with phosphors.
[0006] FIG. 1 is a sectional view illustrating a conventional
LED.
[0007] Referring to FIG. 1, the LED comprises an N-type
semiconductor layer 17, a P-type semiconductor layer 21 and an
active region 19 interposed between the N-type and P-type
semiconductor layers 17 and 21. The N-type and P-type semiconductor
layers include Group-III-element nitride semiconductor layers,
i.e., (Al, In, Ga)N-based compound semiconductor layers. Meanwhile,
the active region 19 is formed to have a single quantum well
structure having a single well layer, or a multiple quantum well
structure having a plurality of well layers, as shown in this
figure. The active region with a multiple quantum well structure is
formed by alternately laminating InGaN well layers 19a and GaN or
AlGaN barrier layers 19b. The well layer 19a includes a
semiconductor layer with a smaller band gap than the N-type and
P-type semiconductor layers 17 and 21 and the barrier layer 19b,
thereby providing quantum wells in which electrons and holes are
recombined with each other.
[0008] Such a Group-III-element nitride semiconductor layer is
grown on a different-type is substrate 11, such as sapphire with a
hexagonal system structure or SiC, using a method, such as organic
chemical vapor deposition (MOCVD). However, if a Group-III-element
nitride semiconductor layer is grown on the different-type
substrate 11, a crack or warpage occurs in the semiconductor layer
and dislocation is produced due to the difference of lattice
constants and thermal expansion coefficients between the
semiconductor layer and the substrate.
[0009] In order to prevent these problems, a buffer layer is formed
on the substrate 11. The buffer layer generally includes a
low-temperature buffer layer 13 and a high-temperature buffer layer
15. The low-temperature buffer layer 13 is generally formed of
Al.sub.xGa.sub.1-xN(0.ltoreq.x.ltoreq.1) at a temperature of 400 to
800.degree. C. using a method, such as MOCVD. The high-temperature
buffer layer 15 is then formed on the low-temperature buffer layer
13. The high-temperature buffer layer 15 is formed of a GaN layer
at a temperature of 900 to 1200.degree. C. Accordingly, crystal
defects in the N-type GaN layer 17, the active region 19 and the
P-type GaN layer 21 can be considerably removed.
[0010] However, although the buffer layers 13 and 15 are employed,
crystal defect density in the active region 19 is still high.
Particularly, in order to enhance a recombination efficiency of
electrons and holes, the active region 19 includes a semiconductor
layer with a smaller band gap than the N-type and P-type GaN layers
17 and 21. In addition, the well layer 19a includes a semiconductor
layer with a smaller band gap than the barrier layer 19b, and
generally contains a larger amount of In. Since In is relatively
larger than Ga and Al, the lattice constant of a well layer is
relatively greater than that of a barrier layer. Therefore, lattice
mismatch occurs between the well layer 19a and the barrier layer
19b and between the well layer 19a and the N-type semiconductor
layer 17. Such lattice mismatch between the layers causes pin
holes, surface roughness and the like, and degrades crystal quality
of the well layer, is thereby restricting the light efficiency.
SUMMARY OF THE INVENTION
[0011] An object of the present invention is to provide an LED
capable of reducing occurrence of crystal defects caused by lattice
mismatch between a well layer and a barrier layer in an active
region.
[0012] Another object of the present invention is to provide a
near-ultraviolet LED, in which occurrence of crystal defects in an
active region is reduced and surface roughness of the active region
is improved.
[0013] According to an aspect of the present invention for
achieving the objects, there is provided a light emitting diode
having a well layer with a superlattice structure. The LED
according to the aspect of the present invention has an active
region between an N-type GaN-based semiconductor compound layer and
a P-type GaN-based semiconductor compound layer, wherein the active
region comprises a well layer with a superlattice structure and a
barrier layer. As the well layer with a superlattice structure is
employed, it is possible to reduce occurrence of defects caused by
lattice mismatch between the well layer and the barrier layer.
[0014] The well layer may have a superlattice structure formed by
alternately growing InN and GaN, and the barrier layer may be
formed of GaN. The composition of In within the well layer is
controlled, thereby implementing light in a near-ultraviolet or
visible light region.
[0015] The well layer may have a superlattice structure in which
In.sub.xGa.sub.1-xN and In.sub.yGa.sub.1-yN are alternately
laminated, where 0.ltoreq.x, y<1, and x>y.
[0016] The barrier layer may also have a superlattice structure.
Accordingly, it is possible to reduce occurrence of defects caused
by lattice mismatch between the well layer and is the barrier
layer.
[0017] The barrier layer may have a superlattice structure formed
by alternately growing InN and GaN. Further, the barrier layer may
have a superlattice structure in which In.sub.uGa.sub.1-xN and
In.sub.vGa.sub.1-xN are alternately laminated, where 0.ltoreq.u,
v.ltoreq.1, and u>v.
[0018] The In.sub.vGa.sub.1-vN has a bandgap relatively greater
than the well layer with a superlattice structure. For example,
In.sub.vGa.sub.1-vN contains less In as compared with
In.sub.xGa.sub.1-xN in the well layer.
[0019] According to another aspect of the present invention, there
is provided a near-ultraviolet LED having a barrier layer with a
superlattice structure. The near-ultraviolet LED according to the
other aspect of the present invention has an active region between
an N-type GaN-based semiconductor compound layer and a P-type
GaN-based semiconductor compound layer, wherein the active region
comprises a well layer and a barrier layer with a superlattice
structure, and near ultraviolet having a wavelength range of 360 to
410 nm is emitted. As the s barrier layer with a superlattice
structure is employed, it is possible to reduce occurrence of
defects caused by lattice mismatch between the well layer and the
barrier layer.
[0020] The well layer may be formed of InGaN, and the barrier layer
may be formed to have a superlattice structure in which InGaN and
GaN are alternately laminated. InGaN in the well layer contains a
larger amount of In as compared with InGaN in the barrier layer.
Accordingly, the composition of In within the well layer is
controlled, thereby providing a near-ultraviolet LED emitting light
with various wavelengths in a near-ultraviolet region.
[0021] Meanwhile, as InGaN in the barrier layer contains a large
amount of In, the number of pin holes is reduced, but hillrocks may
be produced. It is understood that this is because pin holes are
filled with In to prevent them from occurring, but if In is
excessively is increased, hillrocks are produced by surplus In.
Accordingly, the In content in InGaN of the barrier layer is
appropriately selected to prevent pin holes and hillrocks from
occurring.
[0022] In some embodiments, the well layer may be formed of
In.sub.xGa.sub.(1-x)N, and the barrier layer comprises a lower
superlattice having In.sub.yGa.sub.(y-1)N and GaN alternately
laminated; an upper superlattice having In.sub.yGa.sub.(1-y)N and
GaN alternately laminated; and a middle superlattice interposed
between the lower and upper superlattices, the middle superlattice
having In.sub.zGa.sub.(1-z)N and GaN alternately laminated, where
0<x<0.5, 0<y<0.05, 0<z<0.1 and y<z<x.
According to these embodiments, a superlattice with a large In
content is disposed between superlattices with a small In content.
Accordingly, superlattices with different In contents are
laminated, thereby preventing pin holes and hillrocks from
occurring.
[0023] In another embodiments, composition ratios of InGaN in the
well layer and the barrier layer with the superlattice structure
may be 0<x<0.5, 0<y<0.1, 0<z<0.05 and
z<y<x. That is, unlike the aforementioned embodiments, a
superlattice structure with a small In content is disposed between
superlattice structures with a large In content to thereby prevent
pin holes and hillrocks from occurring.
[0024] Each layer within a superlattice structure has a thickness
of 30 .ANG. or less. In these embodiments, each of
In.sub.yGa.sub.(1-y)N, GaN and In.sub.zGa.sub.(1-z)N in the barrier
layer may be laminated to have a thickness of 2.5 to 20 .ANG..
Further, the respective layers in the barrier layer may be formed
to have almost the same thickness.
[0025] The lower superlattice may have In.sub.yGa.sub.(1-y)N and
GaN alternately laminated 4 to 10 times, the middle superlattice
may have In.sub.zGa.sub.(1-z)N and GaN alternately laminated 6 to
20 times, and the upper superlattice may have In.sub.yGa.sub.(1-y)N
and GaN alternately laminated 4 to 10 times. The number of
laminated InGaN and GaN may be set such that the thickness of the
barrier layer is not excessively increased and pin holes and
hillrocks are prevented from occurring.
[0026] Meanwhile, the active region may be formed to have a single
or multiple quantum well structure. In case of the multiple quantum
well structure, the well layers and the barrier layers with a
superlattice structure may be alternately laminated.
[0027] In addition, the well layers may be interposed between the
barrier layers with a superlattice structure. Accordingly, it is
possible to reduce strain caused by the lattice mismatch between
the N-type or P-type compound semiconductor layer and the well
layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The above and other objects, features and advantages of the
present invention will become apparent from the following
description of preferred embodiments given in conjunction with the
accompanying drawings, in which:
[0029] FIG. 1 is a sectional view illustrating a conventional
LED;
[0030] FIG. 2 is a sectional view illustrating an LED having a well
layer with a superlattice structure according to an embodiment of
the present invention;
[0031] FIG. 3 is a sectional view illustrating a well layer with a
superlattice structure according to embodiments of the present
invention;
[0032] FIG. 4 is a sectional view illustrating an LED according to
another embodiment of the present invention;
[0033] FIG. 5 is a sectional view illustrating a near-ultraviolet
LED having a barrier layer with a superlattice structure according
to a further embodiment of the present invention;
[0034] FIG. 6 is a sectional view illustrating the barrier layer
with the superlattice structure according to the further embodiment
of the present invention; and
[0035] FIG. 7 is a sectional view illustrating a near-ultraviolet
LED having a barrier layer with a superlattice structure according
to a still further embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0036] Hereinafter, exemplary embodiments of the present disclosure
will be described in detail with reference to the accompanying
drawings. Throughout the specification, like reference numerals
denote like elements having the same or similar functions. Detailed
description of components or functions apparent to those skilled in
the art will be omitted for clarity. It should be understood that
the following exemplary embodiments are provided by way of example
and that the present disclosure is not limited to the embodiments
disclosed herein and can be implemented in different forms by those
skilled in the art.
[0037] In the accompanying figures, the size and relative sizes of
layers, films, panels, regions, etc., may be exaggerated for
clarity and descriptive purposes. Also, like reference numerals
denote like elements.
[0038] When an element or layer is referred to as being "on,"
"connected to," or "coupled to" another element or layer, it may be
directly on, connected to, or coupled to the other element or layer
or intervening elements or layers may be present. When, however, an
element or layer is referred to as being "directly on," "directly
connected to," or "directly coupled to" another element or layer,
there are no intervening elements or layers present. For the
purposes of this disclosure, "at least one of X, Y, and Z" and "at
least one selected from the group consisting of X, Y, and Z" may be
construed as X only, Y only, Z only, or any combination of two or
more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ.
Like numbers refer to like elements throughout. As used herein, the
term "and/or" includes any and all combinations of one or more of
the associated listed items.
[0039] Although the terms first, second, etc. may be used herein to
describe various elements, components, regions, layers, and/or
sections, these elements, components, regions, layers, and/or
sections should not be limited by these terms. These terms are used
to distinguish one element, component, region, layer, and/or
section from another element, component, region, layer, and/or
section. Thus, a first element, component, region, layer, and/or
section discussed below could be termed a second element,
component, region, layer, and/or section without departing from the
teachings of the present disclosure.
[0040] Spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper," and the like, may be used herein for
descriptive purposes, and, thereby, to describe one element or
feature's relationship to another element(s) or feature(s) as
illustrated in the drawings. Spatially relative terms are intended
to encompass different orientations of an apparatus in use,
operation, and/or manufacture in addition to the orientation
depicted in the drawings. For example, if the apparatus in the
drawings is turned over, elements described as "below" or "beneath"
other elements or features would then be oriented "above" the other
elements or features. Thus, the exemplary term "below" can
encompass both an orientation of above and below. Furthermore, the
apparatus may be otherwise oriented (e.g., rotated 90 degrees or at
other orientations), and, as such, the spatially relative
descriptors used herein interpreted accordingly.
[0041] The terminology used herein is for the purpose of describing
particular embodiments and is not intended to be limiting. As used
herein, the singular forms, "a," "an," and "the" are intended to
include the plural forms as well, unless the context clearly
indicates otherwise. Moreover, the terms "comprises," "comprising,"
"includes," and/or "including," when used in this specification,
specify the presence of stated features, integers, steps,
operations, elements, components, and/or groups thereof, but do not
preclude the presence or addition of one or more other features,
integers, steps, operations, elements, components, and/or groups
thereof
[0042] Various exemplary embodiments are described herein with
reference to sectional illustrations that are schematic
illustrations of idealized exemplary embodiments and/or
intermediate structures. As such, variations from the shapes of the
illustrations as a result, for example, of manufacturing techniques
and/or tolerances, are to be expected. Thus, exemplary embodiments
disclosed herein should not be construed as limited to the
particular illustrated shapes of regions, but are to include
deviations in shapes that result from, for instance, manufacturing.
For example, an implanted region illustrated as a rectangle will,
typically, have rounded or curved features and/or a gradient of
implant concentration at its edges rather than a binary change from
implanted to non-implanted region. Likewise, a buried region formed
by implantation may result in some implantation in the region
between the buried region and the surface through which the
implantation takes place. Thus, the regions illustrated in the
drawings are schematic in nature and their shapes are not intended
to illustrate the actual shape of a region of a device and are not
intended to be limiting.
[0043] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art to which this
disclosure is a part. Terms, such as those defined in commonly used
dictionaries, should be interpreted as having a meaning that is
consistent with their meaning in the context of the relevant art
and will not be interpreted in an idealized or overly formal sense,
unless expressly so defined herein.
[0044] FIG. 2 is a sectional view illustrating an LED according to
an embodiment of the present invention.
[0045] Referring to FIG. 2, an N-type compound semiconductor layer
57 is positioned on a substrate 51. In addition, a buffer layer may
be interposed between the substrate 51 and the N-type compound
semiconductor layer 57. The buffer layer may include a
low-temperature buffer layer 53 and a high-temperature buffer layer
55. The substrate 51 is not particularly limited, but may be, for
example, a sapphire substrate, a spinel substrate, a SiC substrate,
or the like. Meanwhile, the low-temperature buffer layer 53 may be
generally formed of Al.sub.xGa.sub.1-xN(0<x<1), and the
high-temperature buffer layer 55 may be formed of, for example,
undoped GaN or n-type GaN doped with n-type impurities.
[0046] A P-type compound semiconductor layer 61 is positioned on
the N-type compound semiconductor layer 57, and an active region 59
is interposed between the N-type and P-type compound semiconductor
layers 57 and 61. The N-type compound semiconductor layer, the
active region and the P-type compound semiconductor layer include
(Al, In, Ga)N-based Group-III nitride semiconductor layers. For
example, the N-type and P-type compound semiconductor layers 57 and
61 may include N-type GaN and P-type GaN, or N-type AlGaN and
P-type AlGaN, respectively.
[0047] Meanwhile, the active region 59 comprises well layers 59a
with a superlattice structure and barrier layers 59b. The active
region 59 may have a single quantum well structure having a single
well layer 59a. As shown in this figure, the active region 59 may
be formed to have a multiple quantum well structure in which the
well layers 59a with a superlattice structure and the barrier
layers 59b are alternately laminated. That is, in the active region
59 with a multiple quantum well structure, the well layers 59a with
a superlattice structure and the barrier layers 59b are alternately
laminated on the N-type compound semiconductor layer 57. The
barrier layer 59b may be formed of GaN or AlGaN.
[0048] The well layer 59a is formed to have a superlattice
structure, thereby preventing crystal defects such as dislocation
and pin holes from occurring due to the lattice mismatch between
the well layer and the barrier layer.
[0049] FIG. 3 is an enlarged sectional view of the active region in
FIG. 2, illustrating a well layer with a superlattice structure
according to embodiments of the present invention.
[0050] Referring to FIG. 3, the well layer 59a may have a
superlattice structure formed by alternately growing InN and GaN.
For example, using an MOCVD process, InN is grown by introducing In
and N sources into a chamber, GaN is subsequently grown by stopping
the introduction of the In source and introducing a Ga source into
the chamber, and InN is then grown by stopping the introduction of
the Ga source and introducing the In source into the chamber, which
are repeated, thereby growing the well layer 59a with a
superlattice structure.
[0051] At this time, while growing InN, the Ga source remaining in
the chamber may react with the In and N sources, so that an
In.sub.xGa.sub.1-xN layer 71a may be formed. Further, while growing
GaN, the In source remaining in the chamber may react with the Ga
and N sources, so that an In.sub.yGa.sub.1-yN layer 71b may be
formed. Here, 0<x, y<1, and x>y. The In.sub.xGa.sub.1-xN
and In.sub.yGa.sub.1-yN layers 71a and 71b may be repeatedly
formed, for example, in a thickness of 2.5 to 20 .ANG. at 800 to
900.degree. C. using an MOCVD method, and the composition of In in
the In.sub.xGa.sub.1-xN layer 71a is controlled, thereby
implementing light in a near-ultraviolet or visible light
region.
[0052] In these embodiments, the well layer 59a is formed to have a
superlattice structure, thereby preventing crystal defects from
occurring due to the lattice mismatch between the well layer 59a
and the barrier layer 59b.
[0053] Meanwhile, although it is illustrated in this embodiment
that the well layer 59a is first formed on the N-type semiconductor
layer 57, the barrier layer 59b may be first formed on the N-type
semiconductor layer 57, and then, the well layer 59a may be formed
on the barrier layer 59b. Further, although it is illustrated that
the In.sub.xGa.sub.1-xN layer 71a is first formed and the
In.sub.yGa.sub.1-yN layer 71b is then formed, the order thereof may
be changed.
[0054] FIG. 4 is a sectional view illustrating an LED according to
another embodiment of the present invention.
[0055] Referring to FIG. 4, a buffer layer, an N-type compound
semiconductor layer 57 and a P-type compound semiconductor layer 61
are positioned on a substrate, and an active region 59 is
interposed between the N-type and P-type compound semiconductor
layers 57 and 61, as described with reference to FIGS. 2 and 3. The
active region 59 comprises well layers 59a with a superlattice
structure and barrier layers 59b. However, in this embodiment, the
barrier layers 59b also have a superlattice structure.
[0056] The barrier layer 59b may have a superlattice structure
formed by alternately growing InN and GaN as described with
reference to FIG. 3. For example, using an MOCVD process, InN is
grown by introducing In and N sources into a chamber, GaN is
subsequently grown by stopping the introduction of the In source
and introducing a Ga source into the chamber, and InN is then grown
by stopping the introduction of the Ga source and introducing the
In source into the chamber, which are repeated, thereby growing the
barrier layer 59b with a superlattice structure.
[0057] At this time, while growing InN, the Ga source remaining in
the chamber reacts with the In and N sources, so that an
In.sub.uGa.sub.1-uN layer 73a may be formed. Further, while growing
GaN, the In source remaining in the chamber reacts with the Ga and
N sources, so that an In.sub.vGa.sub.1-vN layer 73b may be formed.
Here, 0.ltoreq.u, v.ltoreq.1, and u>v. The In.sub.uGa.sub.1-uN
and In.sub.vGa.sub.1-vN layers 73a and 73b may be repeatedly
formed, for example, in a thickness of 2.5 to 20 .ANG. at 800 to
900.degree. C. using an MOCVD method.
[0058] Meanwhile, the barrier layer 59b has a bandgap broader than
the well layer 59a. Generally, as the In composition ratio within
an InGaN layer decreases, the bandgap of the InGaN layer increases.
Thus, the In.sub.vGa.sub.1-vN layer 73b is grown so that the In
composition ratio "v" of the In.sub.vGa.sub.1-vN layer 73b has a
value relatively smaller than the In composition ratio "x" of the
In.sub.xGa.sub.1-xN layer 71a (see FIG. 3).
[0059] In this embodiment, the barrier layer 59b is formed to have
a superlattice structure, thereby preventing crystal defects from
occurring due to the lattice mismatch between the well layer 59a
and the barrier layer 59b.
[0060] Meanwhile, although it is illustrated and described in this
embodiment that the In.sub.uGa.sub.1-uN layer 73a is first formed
and the In.sub.vGa.sub.1-vN layer 73b is then formed, the order
thereof may be changed.
[0061] In addition, according to embodiments of the present
invention, the positions of the N-type and P-type compound
semiconductor layers 57 and 61 may be changed with each other.
[0062] FIG. 5 is a sectional view illustrating a near-ultraviolet
LED according to a further embodiment of the present invention.
[0063] Referring to FIG. 5, an N-type compound semiconductor layer
157 is positioned on a substrate 151, a buffer layer may be
interposed between the substrate 151 and the N-type compound
semiconductor layer 157 as described with reference to FIG. 2. The
buffer layer comprises a low-temperature buffer layer 153 and a
high-temperature buffer layer 155. In addition, a P-type compound
semiconductor layer 161 is positioned on the N-type compound
semiconductor layer 157, and an active region 159 is interposed
between the N-type and P-type compound semiconductor layers 157 and
161. The N-type and P-type compound semiconductor layers may
include (Al, In, Ga)N-based Group-III nitride semiconductor layers.
For example, the N-type and P-type compound semiconductor layers
157 and 161 may include N-type GaN and P-type GaN, or N-type AlGaN
and P-type AlGaN, respectively.
[0064] Meanwhile, the active region 159 comprises well layers 159a
and barrier layers 159b with a superlattice structure. The active
region 159 may have a single quantum well structure having a single
well layer 159a. At this time, the barrier layer 159b with a
superlattice structure is positioned on the upper and/or lower
portion of the well layer 159a. As shown in this figure, the active
region 159 may be formed to have a multiple quantum well structure
in which the well layers 159a and the barrier layers 159b with a
superlattice structure are alternately laminated. That is, the
InGaN well layers 159a and the barrier layers 159b are alternately
laminated on the N-type compound semiconductor layer 157, and the
barrier layer 159b has a superlattice structure in which InGaN and
GaN are alternately laminated. In InGaN of the well layer 159a, an
In content is selected so that light having a wavelength range of
360 to 410 nm is emitted, and quantum wells are formed so that more
In is contained as compared with InGaN within the barrier layer
159b.
[0065] The barrier layer 159b is formed to have a superlattice
structure, thereby preventing crystal defects such as dislocation
and pin holes from occurring due to the lattice mismatch between
the well layer and the barrier layer. In addition, the barrier
layer 159b is formed to have an InGaN/GaN superlattice structure,
thereby reducing the lattice mismatch that occurs between the
conventional InGaN well layer and AlGaN barrier layer. Meanwhile,
if the
[0066] In content of InGaN in the barrier layer 159b is increased,
it is possible to prevent pin holes from being produced, but
hillrocks occur. It is understood that this is because the
hillrocks are formed due to surplus In remaining on an InGaN layer.
Accordingly, pin holes and hillrocks can be prevented from
occurring by appropriately controlling the In content in the
barrier layer 159b, and the composition ratio of In can be adjusted
in a range of 0.01 to 0.1.
[0067] Meanwhile, in some embodiments of the present invention, a
barrier layer with a superlattice structure for preventing pin
holes and hillrocks from occurring may include InGaNs having
different In contents. This will be described in detail below.
[0068] FIG. 6 is an enlarged sectional view of the active region in
FIG. 5 for illustrating a barrier layer with a superlattice
structure including InGaNs with different In contents according to
an embodiment of the present invention.
[0069] Referring to FIG. 6, the well layer 159a may be expressed by
InxGa(1-x)N, where 0<x<0.5. The In content is selected so
that near ultraviolet having a wavelength range of 360 to 410 nm is
emitted. Meanwhile, the barrier layer 159b with a superlattice
structure comprises a lower superlattice 171 having InyGa(1-y)N
layers 171a and GaN layers 171b alternately laminated, an upper
superlattice 175 having InyGa(1-y)N layers 175a and GaN layers 175b
alternately laminated, and a middle superlattice 173 interposed
between the lower and upper superlattices 171 and 175. The middle
superlattice 173 is formed by alternately laminating InzGa(1-z)N
layers 173a and GaN layers 173b. Here, 0<x<0.5,
0<y<0.05, 0<z<0.1 and y<z<x.
[0070] The In.sub.yGa.sub.(1-y)N layer 171a or 175a in each of the
lower and upper superlattices has a smaller In content than the
In.sub.zGa.sub.(1-z)N layer 173a in the middle superlattice. Hence,
fine pin holes may be formed in a process of forming the lower
superlattice 171. However, the middle superlattice 173 formed
thereafter contains surplus In, thus filling the pin holes with the
surplus In to thereby remove the pin holes. Meanwhile, the surplus
In in the middle superlattice 173 may generate hillrocks. Such
surplus In is removed by the upper superlattice 175. According to
this embodiment, pin holes and hillrocks can be prevented from
occurring by employing a superlattice structure containing InGaNs
with a small In content and a superlattice structure containing
InGaN with a great In content.
[0071] InGaN and GaN in each of the lower, middle and upper
superlattices 171, 173 and 175 are alternately laminated. A pair of
InGaN and GaN may be repeatedly laminated 4 to 10 times in the
lower superlattice 171, 6 to 20 times in the middle superlattice
173 and 4 to 10 times in the upper superlattice 175. The number of
laminated InGaN and GaN may be varied depending on thicknesses of
InGaN and GaN and the In content in InGaN, and is set to control
the occurrence of pin holes and hillrocks.
[0072] Although it has been described in this embodiment that the
InGaN layer in the lower and upper superlattices 171 and 175 has a
smaller In content than the InGaN layer in the middle superlattice
73, the InGaN layer in the lower and upper superlattices 171 and
175 may have a greater In content than the InGaN layer in the
middle superlattice 173. That is, In composition ratios in the well
layer and the barrier layer may satisfy 0<x<0.5,
0<y<0.1, 0<z<0.05 and z<y<x.
[0073] InGaN and GaN in each of the lower, middle and upper
superlattices 171, 173 and 175 may be formed at a temperature of
800 to 900.degree. C. using an MOCVD method. Each of InGaN and GaN
in the barrier layer 159b may be laminated to have a thickness of
2.5 to 20 .ANG., and they may be formed to have almost the same
thickness.
[0074] Meanwhile, although it has been shown in FIG. 6 that the
N-type compound semiconductor layer 157 and the well layer 159a are
in contact with each other, the barrier layer 159b with a
superlattice structure as described with reference to FIG. 6 may be
interposed between the N-type compound semiconductor layer 157 and
the well layer 159a as shown in FIG. 7. The barrier layer 159b
interposed between the N-type compound semiconductor layer 157 and
the well layer 159a reduces strain caused by the lattice mismatch
between the N-type compound semiconductor layer 157 and the well
layer 159a, thereby preventing crystal defects from occurring in
the well layer 159a.
[0075] In the embodiments of the present invention, the positions
of the N-type and P-type compound semiconductor layers 157 and 161
may be changed with each other.
[0076] According to embodiments of the present invention, there is
provided an LED, wherein well and/or barrier layers with a
superlattice structure are employed, so that occurrence of crystal
defects such as dislocation and pin holes due to lattice mismatch
in an active region can be reduced, and surface roughness can be
improved, thereby enhancing light efficiency. Further, there is
provided a near-ultraviolet LED, wherein lattice mismatch between
barrier and well layers can be reduced by employing a barrier layer
with a superlattice structure in which InGaN and GaN are
alternately laminated.
* * * * *