U.S. patent application number 14/745545 was filed with the patent office on 2016-12-22 for calibration of digital-to-time converter.
The applicant listed for this patent is Silicon Laboratories Inc.. Invention is credited to Aaron J. Caffee, Brian G. Drost.
Application Number | 20160373120 14/745545 |
Document ID | / |
Family ID | 57588501 |
Filed Date | 2016-12-22 |
United States Patent
Application |
20160373120 |
Kind Code |
A1 |
Caffee; Aaron J. ; et
al. |
December 22, 2016 |
CALIBRATION OF DIGITAL-TO-TIME CONVERTER
Abstract
A technique for calibrating a digital-to-time converter includes
an apparatus including a digital-to-time converter configured to
generate an output signal based on a digital code, an input signal,
and a gain calibration signal. The output signal has edges linearly
delayed from corresponding edges of the input signal based on the
digital code. The digital code vacillates between an evaluation
code and a calibration code. The apparatus includes a reference
signal generator configured to provide a delayed version of the
input signal. The delay of the reference signal generator is
matched to a delay of the digital-to-time converter. The apparatus
includes a calibration circuit configured to generate the gain
calibration signal based on the output signal and the delayed
version of the input signal. The calibration code may alternate
between a first calibration delay code and a second calibration
delay code.
Inventors: |
Caffee; Aaron J.;
(Scappoose, OR) ; Drost; Brian G.; (Corvallis,
OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Silicon Laboratories Inc. |
Austin |
TX |
US |
|
|
Family ID: |
57588501 |
Appl. No.: |
14/745545 |
Filed: |
June 22, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03K 5/135 20130101;
H03L 7/0814 20130101; H03L 7/0891 20130101; H03L 7/081 20130101;
H03L 7/1976 20130101; H03L 7/091 20130101; H03L 7/183 20130101;
G06F 1/022 20130101; G06F 1/08 20130101; H03L 7/093 20130101 |
International
Class: |
H03L 7/091 20060101
H03L007/091; H03L 7/089 20060101 H03L007/089; H03L 7/183 20060101
H03L007/183 |
Claims
1. An apparatus comprising: a digital-to-time converter configured
to generate an output signal based on a digital code, an input
signal, and a gain calibration signal, the output signal having
edges linearly delayed from corresponding edges of the input signal
based on the digital code, the digital code vacillating between an
evaluation code and a calibration code; a reference signal
generator configured to provide a delayed version of the input
signal, the delay of the reference signal generator being matched
to a delay of the digital-to-time converter; and a calibration
circuit configured to generate the gain calibration signal based on
the output signal and the delayed version of the input signal.
2. The apparatus, as recited in claim 1, wherein the calibration
code alternates between a first calibration delay code and a second
calibration delay code.
3. The apparatus, as recited in claim 1, further comprising: an
integer frequency divider configured to generate the input signal
and the evaluation code based on a reference clock signal and a
digital divider code.
4. The apparatus, as recited in claim 3, wherein the
digital-to-time converter is configured as a subrange data
converter with respect to the integer frequency divider, a first
delay code of the calibration code corresponding to a minimum delay
and the second delay code of the calibration code corresponding to
the minimum delay plus a delay of the integer frequency divider
corresponding to the least-significant bit of the digital divider
code.
5. The apparatus, as recited in claim 1, wherein the calibration
circuit comprises: a phase detector configured to generate a phase
difference signal based on the output signal and the delayed
version of the input signal; and a loop filter configured to
generate the gain calibration signal based on the phase difference
signal.
6. The apparatus, as recited in claim 1, wherein the calibration
circuit comprises: a phase detector configured to generate an up
down output signal based on the output signal and the delayed
version of the input signal; a charge pump circuit configured to
generate an output based on the phase difference signal; and a
switched capacitor circuit configured to generate the gain
calibration signal based on the output of the charge pump circuit
and a control signal.
7. The apparatus, as recited in claim 6, wherein the calibration
circuit generates a skew correction signal based on the output of
the charge pump circuit, the skew correction signal being
indicative of skew between the output signal and the delayed
version of the input signal.
8. The apparatus, as recited in claim 1, further comprising: a
select circuit configured to provide the evaluation code based on
digital quantization error of the input signal in response to a
first value of a control signal and to provide the calibration code
in response to a second value of the control signal.
9. The apparatus, as recited in claim 1, wherein the calibration
code has a first calibration value during a first calibration
interval and a second calibration value during a second calibration
interval.
10. The apparatus, as recited in claim 1, further comprising: a
control circuit configured to generate a control signal to enable
calibration time interleaved with signal generation based on
digital quantization error.
11. The apparatus, as recited in claim 1, wherein the reference
signal generator comprises: a calibration digital-to-time converter
configured to generate a first signal based on the input signal and
the digital code; and a delay element configured to generate the
delayed version of the input signal based on the first signal, the
delay element having a delay matched to a delay of the
digital-to-time converter.
12. The apparatus, as recited in claim 1, wherein the
digital-to-time converter comprises: a circuit configured to
generate an output signal having a pulse width based on a digital
code, the pulse width being based on the digital code, comprising:
a first node selectively coupled to a first reference signal; a
second node configured to receive a second reference signal; a
capacitive digital-to-analog converter configured to generate a
voltage on the first node in response to the digital code; a
comparator configured to generate the output signal based on a
first signal on the first node and the second reference signal on
the second node; and a current source selectively coupled to the
first node and responsive to the gain control signal.
13. A method performed by an apparatus, the method comprising:
generating an output signal based on a digital code, an input
signal, and a gain calibration signal, the output signal having an
edge linearly delayed from a corresponding edge of the input signal
based on the digital code, the digital code vacillating between an
evaluation code and a calibration code; generating a first phase
error between the delayed signal having a first calibration delay
based on the digital code having a first calibration value of the
calibration code and the first signal during a first calibration
interval; generating a second phase error between the delayed
signal having a second calibration delay based on the digital code
having a second calibration value of the calibration code and the
first signal during a second calibration interval; and generating
the gain calibration signal based on the first phase error and the
second phase error.
14. The method, as recited in claim 13, further comprising:
generating a skew correction signal based on a common mode of the
first phase error and the second phase error.
15. The method, as recited in claim 13, further comprising:
adjusting a gain of a digital-to-time converter based on the gain
calibration signal.
16. The method, as recited in claim 13, wherein generating the
output comprises: interleaving transmitting a first edge of a first
evaluate operation with a calibration operation; interleaving
transmitting a second edge of a second evaluate operation with a
second calibration operation; and combining the first and second
edges to generate the output having a 50% duty cycle.
17. The method, as recited in claim 13, further comprising:
generating the input signal and the digital code based on a
reference clock signal and a digital divider code.
18. The method, as recited in claim 17, wherein the first delay
code corresponds to zero delay and the second delay code
corresponds to a delay equivalent to delay defined by a
least-significant bit delay of an integer range of the digital
divider code.
19. An apparatus comprising: means for generating an output signal
based on a digital code, an input signal, and a gain calibration
signal, the output signal having edges delayed from corresponding
edges of the input signal based on the digital code, the digital
code vacillating between an evaluation code and a calibration code;
means for generating a delayed version of the input signal based on
the calibration code having a first calibration value and the
calibration code having a second calibration value; and means for
generating a gain calibration signal based on phase errors between
the output signal and the delayed version of the input signal,
generating based on the calibration code having a first calibration
value and the calibration code having a second calibration
value.
20. The apparatus, as recited in claim 19, further comprising:
means for generating the input signal and the evaluation value of
the digital code by frequency dividing a reference clock signal
based on a digital divider code, the evaluation value of the
digital code corresponding to an error value of the means for
generating, wherein the first calibration value corresponds to zero
delay and the second calibration value corresponds to a delay
equivalent to delay defined by a least-significant bit delay of an
integer range of the digital divider code.
Description
BACKGROUND
[0001] Field of the Invention
[0002] The present invention is related to data converters and more
particularly to digital-to-analog converters.
[0003] Description of the Related Art
[0004] In general, a digital-to-time converter is a
digital-to-analog data converter that generates an output signal
having a period or edge delay based on a digital control word and a
reference clock signal. For example, a clock divider circuit is a
digital-to-time period converter that generates an output clock
signal based on a reference clock signal and a digital control word
indicating a divide ratio (e.g. an integer divide ratio or a
fractional divide ratio). The analog output is the period of the
output clock signal. The output clock period is based on the
digital control word and the clock period of the reference clock
signal. The output clock signal has a digitally-defined, full-scale
range and a least-significant bit clock period.
[0005] A typical integer clock frequency divider is a
digital-to-time period converter that generates an output clock
signal having a period based on an integer multiplication of the
input clock period and has a static and bounded quantization error
and random jitter based on thermal noise. The fractional clock
frequency divider is a dithering modulus clock frequency divider
generating output clock signals having an average output clock
period that is based on a fractional multiplication of the input
clock period. A particular digital control word has an integer
portion and a fractional portion. The dithering modulus clock
divider provides a noise-shaped integer control signal to an
integer clock divider that receives a reference clock signal. The
noise-shaped integer control signal dithers between integer clock
divider values causing the integer divider to generate an output
clock signal having a period that, on average, is the target
fractional clock period. The analog quantization error of the
dithering noise-shaped integer control signal causes substantial
deterministic jitter that dominates the jitter performance.
[0006] Digital-to-time period converters are used in clock
synthesizer applications. Integer-based PLLs have been used
extensively in clock multiplication applications that demand
superior spurious performance. In order to generate fractional
output frequencies, a prescaler digital-to-time converter (DivP) is
used in the reference path of the PLL while a separate
digital-to-time converter is used in the feedback path (DivN). In
this way, the reference clock frequency can be multiplied by N/P.
While this technique has proved useful in industry, the frequency
resolution supported by the clock multiplier directly constrains
the maximum achievable bandwidth to about f.sub.ref/(10.times.P).
As a result, the system is more dependent on voltage-controlled
oscillator phase noise performance which can often translate into
higher power consumption. In addition, the low loop bandwidth of
the clock synthesizer reduces its usefulness in data communication
applications to supporting significantly lower data rates than
might otherwise be desired.
[0007] Referring to FIG. 1, an exemplary clock synthesizer utilizes
phase-locked loop (PLL) 100, which includes a phase/frequency
detector 102, a charge pump loop filter 104, and a
voltage-controlled oscillator (VCO) 106. Voltage controlled
oscillator 106 may be implemented as a ring oscillator, an LC
oscillator, or other suitable oscillator structure. Phase/frequency
detector 102 receives reference clock signal ck.sub.in, which may
be provided by a fixed source, such as a crystal oscillator, a
microelectromechanical structure (MEMS) oscillator, or other
suitable source. Fractional divider 108 introduces a digital
quantization error that causes phase noise (i.e., jitter) in the
feedback clock signal, ck.sub.fb. For example, ck.sub.fb may have
jitter of up to one cycle of the VCO output ck.sub.vco.
[0008] A reference signal having a frequency f.sub.in supplied to
PLL 100 is multiplied based on a divider value to generate a
synthesized clock signal ck.sub.vco. Frequency f.sub.out of the
output clock signal, ck.sub.out, can be determined by a divider
value D.sub.fb of the feedback divider in the PLL, and in
embodiments including output divider 110, a divider value D.sub.out
of output divider 110:
f out = f in D fb D out . ##EQU00001##
The feedback divider includes a digital-to-time converter that may
be a fractional-N feedback divider 108 that receives clock signal
ck.sub.vco as the reference clock signal and digital control word
D.sub.fb. Digital control word D.sub.fb is a divide value sequence
of integers corresponding to a target fractional divider ratio. The
synthesized clock signal ck.sub.vco may be further divided by an
output divider, which may be an integer clock divider including a
digital-to-time period converter that generates the output clock
signal ck.sub.out based on clock signal ck.sub.vco as the reference
clock signal and integer divide value D.sub.out. In applications
with demanding spur specifications, another integer clock divider
(not shown) receives an input clock and a divide value D.sub.in and
generates reference clock signal ck.sub.in provided to phase
frequency detector 102. Note that in such embodiments an integer
clock divider may be used instead of fractional divider 108 and
D.sub.in, D.sub.fb, and D.sub.out have integer values to generate
output clock signal ck.sub.out a signal having a frequency:
f out = f in D fb D in D out . ##EQU00002##
However, an input integer divider provides frequency resolution at
the expense of phase noise. Using a fractional-based digital word
for D.sub.fb and fractional divider 108 instead of an integer input
divider and an integer feedback divider, supports higher output
frequency resolution. The PLL behaves like a digital-to-analog
converter reconstruction filter and reduces or eliminates
high-frequency quantization noise. The higher PLL bandwidths
improve VCO noise suppression but introduce deterministic
jitter.
[0009] As the frequencies of ck.sub.in and ck.sub.out increase, the
target clock period decreases and jitter introduced by the
digital-to-time converter circuits become a larger fraction of the
target clock period, thereby causing output clock signals from
conventional clock synthesizer designs to fail to meet target
performance specifications. Accordingly, improved techniques for
digital-to-time conversion are desired.
SUMMARY OF EMBODIMENTS OF THE INVENTION
[0010] In at least one embodiment of the invention, an apparatus
includes a digital-to-time converter configured to generate an
output signal based on a digital code, an input signal, and a gain
calibration signal. The output signal has edges linearly delayed
from corresponding edges of the input signal based on the digital
code. The digital code vacillates between an evaluation code and a
calibration code. The apparatus includes a reference signal
generator configured to provide a delayed version of the input
signal. The delay of the reference signal generator is matched to a
delay of the digital-to-time converter. The apparatus includes a
calibration circuit configured to generate the gain calibration
signal based on the output signal and the delayed version of the
input signal. The calibration code may alternate between a first
calibration delay code and a second calibration delay code. The
apparatus may include an integer frequency divider configured to
generate the input signal and the evaluation code based on a
reference clock signal and a digital divider code. The
digital-to-time converter may be configured as a subrange data
converter with respect to the integer frequency divider. The first
delay code of the calibration code may correspond to a minimum
delay and the second delay code of the calibration code may
correspond to the minimum delay plus a delay of the integer
frequency divider corresponding to the least-significant bit of the
digital divider code. The calibration circuit may generate a skew
correction signal based on the output of the charge pump circuit.
The skew correction signal may be indicative of skew between the
output signal and the delayed version of the input signal. The
apparatus may include a select circuit configured to provide the
evaluation code based on digital quantization error of the input
signal in response to a first value of a control signal and to
provide the calibration code in response to a second value of the
control signal. The digital-to-time converter may include a circuit
configured to generate an output signal having a pulse width based
on a digital code. The pulse width may be based on the digital
code. The circuit may include a first node selectively coupled to a
first reference signal, a second node configured to receive a
second reference signal, and a capacitive digital-to-analog
converter configured to generate a voltage on the first node in
response to the digital code. The circuit may include a comparator
configured to generate the output signal based on a first signal on
the first node and the second reference signal on the second node
and a current source selectively coupled to the first node and
responsive to the gain control signal.
[0011] In at least one embodiment of the invention, a method
includes generating an output signal based on a digital code, an
input signal, and a gain calibration signal. The output signal has
an edge linearly delayed from a corresponding edge of the input
signal based on the digital code. The digital code vacillates
between an evaluation code and a calibration code. The method
includes generating a first phase error between the delayed signal
having a first calibration delay based on the digital code having a
first calibration value of the calibration code and the first
signal during a first calibration interval. The method includes
generating a second phase error between the delayed signal having a
second calibration delay based on the digital code having a second
calibration value of the calibration code and the first signal
during a second calibration interval. The method includes
generating the gain calibration signal based on the first phase
error and the second phase error. The method may include generating
a skew correction signal based on a common mode of the first phase
error and the second phase error. The method may include adjusting
a gain of a digital-to-time converter based on the gain calibration
signal. Generating the output may include interleaving transmitting
a first edge of a first evaluate operation with a calibration
operation, interleaving transmitting a second edge of a second
evaluate operation with a second calibration operation, and
combining the first and second edges to generate the output having
a 50% duty cycle. The first delay code may correspond to zero delay
and the second delay code may correspond to a delay equivalent to
delay defined by a least-significant bit delay of an integer range
of the digital divider code.
[0012] A technique for improving PLL bandwidth for fractional clock
multiplier values utilizes fractional-N PLL clock synthesizers.
This technique uses a programmable feedback divider that, by
dynamically dithering between different divide values, implements
an average effective feedback divide value that supports fractional
clock multiplication without the need for a prescaler. Accordingly,
the technique improves PLL bandwidth as compared to integer
implementations by a factor of the prescaler value P. However,
since the divider dynamically switches between different divide
values, large phase errors at the phase detector input result in
excessive control voltage ripple and, as a result, substantially
degrade spurious performance.
[0013] A technique for reducing the control voltage ripple includes
reducing the bandwidth of the PLL. However, that solution detracts
from the advantage of a clock synthesizer using a fractional-N PLL
over an integer-based clock synthesizer. Another technique for
reducing control voltage ripple includes using current-mode phase
interpolation at the output of the charge pump of the PLL. Still
referring to FIG. 1, a technique for reducing deterministic jitter
and supporting higher PLL bandwidths for a particular deterministic
jitter specification compensates for noise at the output of charge
pump 104. Fractional divider 108 provides digital signal D.sub.Q,fb
to an auxiliary charge pump-based digital-to-analog converter (not
shown) and charge pump loop filter 104 subtracts the error in the
charge domain. The control signal that dithers the feedback divider
to achieve a particular fractional multiplication may be used as
the most-significant bit of the multiplier and, by tracking the
instantaneous divider error, the error residue in the form of a
digital word may be provided to a higher resolution current-mode
digital-to-analog converter that perfectly cancels the
deterministic ripple on the control voltage. This implementation
may be complex and impracticable (e.g. requires a linear phase
frequency detector and charge pump loop filter that is matched to
the fractional divider 108 for effective cancellation), does not
cancel the quantization noise at the source, causes excessive
charge pump output thermal noise due to greater turn-on times, and
is not easily adapted for reducing deterministic jitter in the
output divider (e.g., integer divider 110).
[0014] Digital-based quantization noise cancellation techniques
have similar drawbacks: those techniques cancel quantization noise
at a digital loop filter input, not at the fractional divider
source, require linear element matching to the fractional divider
gain for effective cancellation, cause excessive thermal noise due
to greater turn-on times, and are not easily adapted for output
dividers. In addition, digital loop elements (e.g., phase detector,
loop filter) introduce additional quantization noise. Accordingly,
improved techniques for clock synthesis are desired.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The present invention may be better understood, and its
numerous objects, features, and advantages made apparent to those
skilled in the art by referencing the accompanying drawings.
[0016] FIG. 1 illustrates a functional block diagram of an
exemplary system for generating a clock signal using fractional
frequency synthesis.
[0017] FIG. 2 illustrates a functional block diagram of an
exemplary system for generating a clock signal using an
interpolative divider.
[0018] FIG. 3 illustrates a functional block diagram of an
exemplary interpolative divider of FIG. 2.
[0019] FIG. 4 illustrates timing waveforms for the exemplary
interpolative divider of FIG. 3.
[0020] FIG. 5 illustrates a circuit diagram of a digital-to-time
converter cell of an exemplary phase interpolator of FIG. 3.
[0021] FIG. 6 illustrates a circuit diagram of a digital-to-time
converter cell of an exemplary phase interpolator of FIG. 3.
[0022] FIG. 7 illustrates timing waveforms for the exemplary
digital-to-time converter cell of FIG. 5.
[0023] FIG. 8 illustrates a circuit diagram of an exemplary slew
rate based delay control digital-to-time converter cell.
[0024] FIG. 9 illustrates timing waveforms for the exemplary slew
rate based delay control digital-to-time converter cell of FIG.
8.
[0025] FIG. 10 illustrates a circuit diagram of an exemplary reset
voltage based delay control digital-to-time converter cell
consistent with at least one embodiment of the invention.
[0026] FIG. 11 illustrates timing waveforms for the exemplary reset
voltage based delay control digital-to-time converter of FIG.
10.
[0027] FIG. 12 illustrates a circuit diagram of an exemplary
pedestal voltage based delay control digital-to-time converter
consistent with at least one embodiment of the invention.
[0028] FIG. 13 illustrates a circuit diagram of an exemplary
capacitive based voltage digital-to-analog converter circuit of
FIG. 12.
[0029] FIG. 14 illustrates timing waveforms for the exemplary
pedestal voltage based delay control digital-to-time converter of
FIG. 12.
[0030] FIG. 15 illustrates an exemplary voltage-to-current
generator circuit including a switched-capacitor resistor of the
exemplary pedestal voltage based delay control digital-to-time
converter of FIG. 12.
[0031] FIG. 16 illustrates an exemplary voltage-to-current
generator circuit of the exemplary pedestal voltage based delay
control digital-to-time converter of FIG. 12.
[0032] FIG. 17 illustrates a functional block diagram of an
exemplary digital-to-time converter and gain calibration system
consistent with at least one embodiment of the invention.
[0033] FIG. 18 illustrates an exemplary edge generation circuit of
FIG. 17 consistent with at least one embodiment of the
invention.
[0034] FIG. 19 illustrates a functional block diagram of an
exemplary time-to-digital converter and analog gain calibration
system consistent with at least one embodiment of the
invention.
[0035] FIG. 20 illustrates a functional block diagram of an
exemplary time-to-digital converter and digital gain calibration
system consistent with at least one embodiment of the
invention.
[0036] FIG. 21 illustrates a functional block diagram of an
exemplary phase interpolator and phase interpolator gain
calibration circuit consistent with at least one embodiment of the
invention.
[0037] FIG. 22 illustrates a functional block diagram of exemplary
time reference generator circuits of FIG. 21 consistent with at
least one embodiment of the invention.
[0038] FIG. 23 illustrates timing waveforms for the exemplary phase
interpolator and phase interpolator gain calibration circuit and
time reference generator circuits of FIGS. 21 and 22.
[0039] FIG. 24 illustrates a functional block diagram of an
exemplary phase interpolator and phase interpolator gain
calibration circuit consistent with at least one embodiment of the
invention.
[0040] FIG. 25 illustrates timing waveforms for the exemplary phase
interpolator and phase interpolator gain calibration circuits of
FIGS. 21 and 24.
[0041] FIG. 26 illustrates a functional block diagram of an
exemplary phase interpolator and phase interpolator gain
calibration circuit consistent with at least one embodiment of the
invention.
[0042] FIG. 27 illustrates a functional block diagram of an
exemplary gain error detection and correction circuit consistent
with at least one embodiment of the invention.
[0043] FIG. 28 illustrates a functional block diagram of an
exemplary gain error and skew detection and correction circuit
consistent with at least one embodiment of the invention.
[0044] FIG. 29 illustrates a functional block diagram of an
exemplary gain error detection and correction circuit consistent
with at least one embodiment of the invention.
[0045] FIG. 30 illustrates a functional block diagram of an
exemplary gain error detection and correction circuit including a
bang-bang phase detector consistent with at least one embodiment of
the invention.
[0046] FIG. 31 illustrates a functional block diagram of an
exemplary gain error detection and correction circuit including
pre-charge voltage buffers consistent with at least one embodiment
of the invention.
[0047] FIG. 32 illustrates a functional block diagram of an
exemplary gain error detection and correction circuit having
reduced charge sharing consistent with at least one embodiment of
the invention.
[0048] FIG. 33 illustrates a functional block diagram of an
exemplary time interleaving interpolative divider consistent with
at least one embodiment of the invention.
[0049] FIG. 34 illustrates a functional block diagram of an
exemplary time-to-digital converter consistent with at least one
embodiment of the invention.
[0050] FIG. 35 illustrates a functional block diagram of an
exemplary successive approximation time-to-digital converter
consistent with at least one embodiment of the invention.
[0051] FIG. 36 illustrates a functional block diagram of an
exemplary high-resolution time-to-digital converter consistent with
at least one embodiment of the invention.
[0052] The use of the same reference symbols in different drawings
indicates similar or identical items.
DETAILED DESCRIPTION
[0053] A technique that reduces control voltage ripple without
narrowing the bandwidth of the PLL in a clock synthesizer uses a
time-domain digital-to-analog converter (i.e., digital-to-time
converter) in series with a dynamic feedback divider. Similar to
the current-mode phase interpolation technique, the time-domain
digital-to-analog converter receives an error residue that attempts
to adjust for phase errors introduced by the dynamic feedback
divider. This approach addresses the phase error early in the
signal path, causes the downstream phase detector and associated
charge pump loop filter circuitry of the PLL to see a much smaller
signal, and as a result, operate more linearly than other
implementations.
[0054] Referring to FIGS. 1 and 2, a technique for reducing jitter
in PLL 100 includes delay-based quantization noise cancellation.
The technique includes adjusting the phase of the frequency-divided
signal at the output of a fractional divider, according to an error
control signal D.sub.Q, generated by fractional divider 108. The
technique applies the error control signal D.sub.Q to phase
interpolator 204 and performs the subtraction in the time domain.
Accordingly, any linearity requirement imposed by the quantization
noise cancellation is limited to phase interpolator 204. This
technique reduces phase errors seen by the front-end of PLL 200
(e.g., phase detector 102) as compared to the phase errors seen by
the front-end of PLL 100. In addition, ratio-metric techniques may
be used to reduce phase interpolator gain error. Moreover, the
delay-based quantization noise compensation is easily adapted to
output divider configurations. Interpolative divider techniques for
reducing noise associated with a fractional-N divider are described
in U.S. Pat. No. 7,417,510, filed Oct. 17, 2006, entitled "Direct
Digital Interpolative Synthesis," naming Yunteng Huang as inventor,
which application is hereby incorporated by reference.
[0055] Referring to FIG. 2, interpolative divider 202 includes
fractional divider 108 and phase interpolator 204. Fractional
divider 108 may include a dithering modulus divider (e.g., a
typical first order sigma-delta modulator or higher-order
sigma-delta modulator) that generates noise-shaped clock signal
ck.sub.DMD and digital quantization error signal D.sub.Q. Phase
interpolator 204 adjusts the phase of clock signal ck.sub.DMD
according to the digital quantization error signal to reduce error
in the feedback clock signal ck.sub.fb, thereby introducing a phase
adjustment prior to phase/frequency detector 102 of PLL 200.
Interpolative divider 202 is a sub-ranging digital-to-time period
converter that generates an output signal with an average
fractional period resolution. Phase interpolator 204 is a
digital-to-time converter that uses digital quantization error
signal D.sub.Q to divide output quantization noise by up to
2.sup.N.sup.frac depending on N.sub.PI with respect to N.sub.frac,
where N.sub.PI is the number of bits by which phase interpolator
204 reduces the quantization noise, N.sub.frac is the number of
bits used to represent the fractional portion of the divide ratio,
i.e., the fractional portion bit-width and N.sub.PI is less than or
equal to N.sub.frac. Error of phase interpolator 204 limits the
resolution of the digital-to-analog conversion of interpolative
divider 202.
[0056] Referring to FIG. 3, in at least one embodiment, fractional
divider 108 of interpolative divider 202 includes finite-state
machine 302 that generates digital code D.sub.N, which dithers
between different divide values, and an associated digital
quantization error signal D.sub.Q. Counter 304 generates a gating
signal that is used to select and stretch pulses of clock signal
ck.sub.ref (e.g., by digitally gating clock signal ck.sub.ref with
the gating signal using AND-gate 306 or other suitable logic
circuit) to generate clock signal ck.sub.DMD.
[0057] Ideally, the phase interpolator transfer function, i.e., the
output time delay as a function of digital quantization error
signal D.sub.Q, is:
T.sub.PI(D.sub.Q)=T.sub.PI,DAC+T.sub.PI,OS
where
T PI , DAC = T ref 2 N PI D Q , ##EQU00003##
and T.sub.PI,OS is an output delay offset. The output delay offset
is not a function of digital quantization error signal D.sub.Q, but
rather is affected by environmental factors, and may be assumed to
be zero with respect to deterministic jitter. The full-scale range
of the phase interpolator delay is ideally one dithering modulus
divider bit, i.e., one least-significant bit of digital code
D.sub.N, which corresponds to reference clock period T.sub.ref,
which is one period of reference clock ck.sub.ref. For example, for
a two-bit phase interpolator, digital quantization error signal
D.sub.Q may have values 00, 01, 10, and 11, which correspond to
discrete T.sub.PI,DAC values of 0, T.sub.ref/4,
2.times.T.sub.ref/4, and 3.times.T.sub.ref/4. A delay of
4.times.T.sub.ref/4 corresponds to an entire period of reference
clock signal ck.sub.ref, i.e., reference clock period T.sub.ref.
The phase interpolator error includes difference in phase
interpolator output from the expected discrete T.sub.PI,DAC values.
The component of phase interpolator error that is linearly related
to digital quantization error signal D.sub.Q is referred to as gain
error and a component of phase interpolator error that is randomly
related to digital quantization error signal D.sub.Q is referred to
as mismatch error. In addition, higher order gain error may be
present (e.g., systematic non-linearities). Both gain error and
mismatch error affect peak-to-peak deterministic jitter.
[0058] Referring to FIGS. 3 and 4, for an exemplary fractional
divide ratio of 3.5, D.sub.period=(11.10).sub.2, the noise-shaped
integer divider value, digital code D.sub.N dithers between 3 and 4
and the digital quantization error signal D.sub.Q dithers between
2.sup.N.sup.frac.sup.-1 and 0. Integer divider 110 generates clock
signal ck.sub.DMD that has a period of three times the period of
reference clock signal ck.sub.ref when digital code D.sub.N=3
(e.g., between time t.sub.1 and t.sub.2) and has a period of four
times the period of reference clock signal ck.sub.ref when digital
code D.sub.N=4 (e.g., between times t.sub.2 and t.sub.3). Then,
phase interpolator 204 delays the edge of clock signal ck.sub.DMD
according to the digital quantization error signal to generate
output clock signal ck.sub.out, having a period that is 3.5 times
the period of reference clock signal ck.sub.ref. Note that the
period between times t.sub.1, and t'.sub.2, the period between
times t'.sub.2 and t.sub.3, and the period between times t.sub.3
and t'.sub.4 is 3.5 times the period of reference clock signal
ck.sub.ref. However, the output duty cycle of output clock signal
ck.sub.out is not 50%. In at least one embodiment, a divide by two
may be used to generate an output signal having a 50% output duty
cycle. The deterministic jitter of clock signal ck.sub.DMD at
t.sub.2 and t.sub.4 is half of reference clock period, T.sub.ref/2
and is cancelled by phase interpolator 204.
[0059] As discussed above, a typical phase interpolator circuit is
a digital-to-time converter that delays an input edge signal to
generate an output edge signal based on an analog reference signal
(e.g., a voltage, current) and digital control word D.sub.Q
indicating the amount of delay to be applied. The full-scale range
and least significant bit delay tend to be determined by analog
components. Referring to FIGS. 5 and 7, in typical unit cell 500 of
a digital-to-time converter, in response to a reset control signal,
capacitor C.sub.s is coupled to reference voltage V.sub.rst to
store an initial charge on capacitor C.sub.s, which resets the
voltage on node V.sub.s to the level of reference voltage
V.sub.rst. In response to the reset signal being deasserted and a
slew control signal being asserted, the charge stored by capacitor
C.sub.s increases by charge delivered from current source I.sub.s.
When the voltage on node V.sub.s reaches trip voltage V.sub.t of
comparator 508, at time t.sub.trip, the comparator output signal
transitions, e.g., from low to high, generating a rising edge of
ck.sub.out. The time that it takes for node V.sub.s to charge from
reference voltage V.sub.rst to trip voltage V.sub.t is time delay
T.sub.delay. Note that comparator delay T.sub.comp ideally has no
dependence on the control code and introduces negligible
deterministic jitter. Time delay T.sub.delay of delay cell 500 is
typically controlled by adjusting the slew rate of the voltage on
node V.sub.s. Referring to FIG. 6, in at least one embodiment,
delay cell 500 includes an inverter-based comparator and the
reference voltage is derived from the trip-point of inverter 510
and no additional trip voltage is needed. Note that since low
frequency noise affects charge stored on capacitor C.sub.s, an
auto-zeroing technique (e.g., correlated double sampling) is used
to effectively reduce or eliminate flicker noise.
[0060] Referring to FIGS. 8 and 9, the slew rate of the voltage on
node V.sub.s of unit cell 700 of a digital-to-time converter may be
changed by selectively adjusting one or more of the current output
by current source 702 or the capacitance C.sub.s of capacitor 704.
When controlling the current provided by current source 702 based
on digital control word D.sub.Q, individual current sources
I.sub.LSB may be enabled to obtain:
T PI ( D Q ) = C S I S ( V t - V rst ) + T comp = C S D Q I LSB ( V
t - V rst ) + T comp . ##EQU00004##
Note that in this case, time delay T.sub.PI is a non-linear
function of digital control word D.sub.Q. For the greatest value of
digital control word D.sub.Q, the slew rate is the fastest, the
trip voltage is reached soonest, at time t.sub.trip1, and the delay
of the rising clock edge of ck.sub.out is the smallest, as
illustrated by V.sub.s(t) curve 802. For the smallest value of
digital control word D.sub.Q, the slew rate is the slowest, the
trip voltage is reached latest at time t.sub.trip3 and the delay of
the rising clock edge of output clock signal ck.sub.out is the
greatest, as illustrated by V.sub.s(t) curve 806. The
code-dependent slew rate results in a complex gain variability that
may be difficult to calibrate. Controlling the slew rate using
selectively enabled current sources, in particular, is susceptible
to substantial random mismatch due to use of active devices, and
trades off deterministic jitter with random jitter.
[0061] When controlling slew rate by varying target capacitance
C.sub.s, individual capacitors C.sub.LSB may be selectively coupled
via switches to obtain the target capacitance C.sub.s and thus a
target delay period:
T PI ( D Q ) = C S I S ( V t - V rst ) + T comp = D Q C LSB I S ( V
t - V rst ) + T comp . ##EQU00005##
Note that T.sub.PI(D.sub.Q) is a linear function of digital control
word D.sub.Q.
[0062] However, variable slew rate affects the delay of the voltage
comparator that receives signals from this node and, ultimately,
causes nonlinearity in the delay control. While nonlinearity of a
digital-to-time converter may be acceptable in some applications,
other applications, such as frequency synthesis, are not as
tolerant. Therefore, it is desirable to eliminate variable slew
rate as a source of error. Although trim at production test can
reduce or eliminate gain error at a particular temperature and age,
variation over temperature and age will ultimately degrade
performance. Accordingly, high performance applications require
active gain error calibration, which substantially increases
complexity.
[0063] Rather than use a variable slew rate delay cell, a
digital-to-time converter includes a fixed slew rate delay cell. It
is desirable to maintain a constant slew rate as an input node
passes through a trip point of the voltage comparator. By changing
the initial voltage, V.sub.initial, on a fixed capacitor,
C.sub.slew, and then initiating slewing with a constant current,
Islew, a variable delay element whose delay depends on
V initial .times. C slew I slew ##EQU00006##
is formed. If this initial voltage level is sufficiently far away
from the comparator trip point voltage level, then the
digital-to-time converter should have minimal modulation of
comparator delay and, therefore, a more linear delay versus control
characteristic. Various different techniques may be used to realize
the initial capacitor voltage. An exemplary digital approach uses a
capacitor digital-to-analog converter. In addition, by deriving the
slewing current from a voltage-to-current generator loaded by a
switched-capacitor resistor, a difference in delay between
digital-to-analog converter codes will be ratio-metric to
capacitance. Furthermore, a current generator that uses a voltage
that is proportional to the voltage reference used by the capacitor
digital-to-analog converter causes the difference in delay between
digital-to-analog converter codes to be ratio-metric in voltage and
proportional to the frequency used to drive the switched-capacitor
resistor. Thus, the difference in delay between any two
digital-to-analog converter codes will, using ideal elements, be
directly proportional to the difference in codes used. Note that
conversion gain from voltage-to-time delay may also be trimmed by
adjusting the capacitance and/or voltage ratio. Other noise-shaping
techniques such as chopping, auto-zeroing, delta-sigma modulation,
dynamic element matching (either white or high-pass noise-shaped),
and current-copier mirroring techniques may be used to further
improve upon the accuracy of the design depending on the
application.
[0064] Referring to FIGS. 10 and 11, digital-to-time converter 900
includes constant current source 502, which provides constant
current I.sub.S, and predetermined capacitor 506, which provides
constant capacitance C.sub.S. Digital-to-time converter 900 is
configured to generate a selectively controllable reset voltage,
V.sub.rst based on a digital control word D.sub.Q and reference
voltage V.sub.ref. During a first time interval, e.g., the time
interval during which the reset control signal closes switch 504
and evaluate control signal ck.sub.DMD opens switch 507,
digital-to-time converter 900 applies reset voltage V.sub.rst to
charge fixed capacitor C.sub.s to a level determined according to a
particular reset voltage level selected based on digital control
word D.sub.Q. Note that the digital control word D.sub.Q may
include multiple bits having digital voltage levels that are
thermometer coded, binary coded, or coded using other suitable
techniques. During a second time interval, switch 504 is open
according to the reset control signal and switch 507 is closed
according to clock signal ck.sub.DMD. Digital-to-time converter 900
applies the constant current generated by current source 502 to
node V.sub.S, causing the voltage level on node V.sub.S to increase
from the selected reset voltage level to a second level, V.sub.C,
with linear delay control, as illustrated by V.sub.S (t) curves
1002, 1004, and 1006 for increasing digital control word D.sub.Q
and decreasing V.sub.rst. The resulting phase interpolator delay
is:
T PI ( D Q ) = C S I S ( V t - V rst ) + T comp = C S I S V t + T
comp - C S I S V rst 2 N PI D Q , where T PI , OS = C S I S V t + T
comp and T PI , DAC = - C S I S V rst 2 N PI D Q . ##EQU00007##
Digital-to-analog converter 902 of digital-to-time converter 900
may include passive elements (e.g., resistors and capacitors) that
are easily matched by manufacturing techniques. In at least one
embodiment, digital-to-time converter 900 includes only one current
source and one slew control switch, which reduces or eliminates
code-dependent switching errors. Digital-to-time converter 900
includes comparator 508 having a simple, fixed, code-independent
delay. However, the code-dependent reset charge injection of
digital-to-time converter 900 may cause complex gain and non-linear
current variations.
[0065] To address the reset charge injection of digital-to-time
converter 900, digital-to-time converter 1100 has a
code-independent charge injection topology as illustrated in FIGS.
12-14. Digital-to-time converter 1100 includes comparator 508
having a simple, fixed, code-independent delay. After a reset
interval charges node V.sub.s to a fixed reset voltage V.sub.rst,
digital-to-time converter 1100 subtracts a fixed pedestal voltage
V.sub.ped from that reset voltage on node V.sub.s to provide
code-independent charge injection. As a result, digital-to-time
converter 1100 provides a ratio-metric topology having linear delay
control and code-independent charge injection. Accordingly:
T PI ( D Q ) = C S I S ( V t - V rst ) + T comp + C S I S V ref 2 N
PI D Q , ##EQU00008##
where
T PI , OS = C S I S ( V t - V rst ) + T comp and T PI , DAC = C S I
S V ref 2 N PI D Q . ##EQU00009##
Digital-to-analog converter 1102 may include capacitor-based units
that provide improved matching over current source-based units of
other phase interpolator topologies. Since digital-to-time
converter 1100 uses code-independent reset charge injection, phase
interpolator errors due to charge injection are reduced or
eliminated. For all values of digital control word D.sub.Q,
digital-to-analog converter 1102 charges the voltage on node
V.sub.s to the same, predetermined reset voltage level. In response
to deassertion of the reset control signal, digital-to-analog
converter 1102 applies a pedestal voltage to the sense node of
comparator 508 according to digital control word D.sub.Q. In at
least one embodiment, digital-to-analog converter 1102 logically
combines digital control word D.sub.Q with the reset control signal
to generate a gated version of digital control word D.sub.Q,
D.sub.cap, individual bits of which are coupled to corresponding
bit cells 1204, 1206, and 1208 for proper pedestal voltage
generation following the reset phase. In at least one embodiment of
digital-to-analog converter 1102, each of the bit cells 1204
includes corresponding inverter 1210 and corresponding pedestal
capacitor 1212 that separately charges or discharges the sense node
to realize a combined voltage on the sense node of
V.sub.rst-V.sub.ped(D.sub.Q). As D.sub.Q increases,
V.sub.ped(D.sub.Q) increases, thereby increasing the time between
the slew start time t.sub.start to the trip point t.sub.trip of
comparator 508 and thus increasing the delay of ck.sub.out. For
example, D.sub.Q associated with V.sub.ped1 and t.sub.trip1 is less
than the value of D.sub.Q associated with V.sub.ped2 and
t.sub.trip2 and the value of digital control word D.sub.Q
associated with V.sub.ped3 and t.sub.trip3, as illustrated by
corresponding V.sub.s (t) curves 1302, 1304, and 1306,
respectively.
[0066] Referring to FIG. 15, in at least one embodiment of a
digital-to-time converter, current source 502 is a ratio-metric
voltage-to-current converter. Current source 502 generates a fixed
current using switched-capacitor resistor 1410 controlled by
reference clock signal ck.sub.R. Switched-capacitor resistor 1410
is used instead of an integrated circuit resistor for ratio-metric
operation of the digital-to-time converter (e.g., phase
interpolator). The resistance is a function of the reference clock,
which is provided by a high precision frequency source (e.g.,
accurate within a few parts per million). Current source 502
provides a constant current I.sub.S using precision current mirror
techniques:
I.sub.Sf.sub.RC.sub.RV.sub.ref,
where C.sub.R is the capacitance of a capacitor in
switched-capacitor resistor 1410 and f.sub.R is the frequency of
reference clock signal ck.sub.R. Ratio-metric operation is achieved
by using the same reference voltage V.sub.ref used by
digital-to-analog converter 1102. If the period of the reference
clock T.sub.R is set to be equal to N.sub.ref.times.T.sub.ref, and
the capacitor is trimmed to have C.sub.R=N.sub.ref C.sub.S
(assuming a current mirror ratio of one) then:
T PI ( D Q ) = T ref V t - V rst V ref + T comp + T ref 2 N PI D Q
, ##EQU00010##
Trimming may reduce or eliminate gain error at production test
although variation due to environmental factors remains.
Current-copier techniques may also be used to reduce or eliminate
current mirror errors. Increasingly ratio-metric behavior that
reduces deterministic jitter and random jitter may be achieved by
deriving V.sub.t and V.sub.rst from V.sub.ref. In at least one
embodiment of current source 502, the current I.sub.s may be
digitally controlled according to the value of digital current
control signal D.sub.mirror, which may be a binary coded-signal or
a thermometer-coded signal that selectively enables devices within
current mirror 1405 to generate a current I.sub.S having a
corresponding level. The resistance of resistor 1407 may be trimmed
to reduce or eliminate gain error of an associated digital-to-time
converter with respect to temperature variation. For example,
resistor 1407 includes resistances having different temperature
coefficients (e.g., p-type or n-type polysilicon resistors, p-type
or n-type diffusion resistors, metal resistors, or other suitable
resistors). The resistance of resistor 1407 may be selectable
according to digital temperature sensitivity control signal
D.sub.temp. Selectively controlling current and temperature
sensitivity may be used to reduce or eliminate gain errors of the
digital-to-time converter as a function of temperature alone or in
conjunction with other gain calibration techniques.
[0067] The techniques described above may result in a residual
phase error primarily due to the quantization error resulting from
the digital-to-time converter and the noise of the system. The
quantization error may be due to data converter non-idealities such
as offset, gain error, and integral nonlinearity. While offset is
not detrimental to clock synthesizer applications, addressing gain
error and integral nonlinearity are critical to spurious
performance. Background calibration of the digital-to-time
converter, described below, addresses gain error with the
assumption that the native integral nonlinearity of the converter
is acceptable.
[0068] Techniques for background calibration of the digital-to-time
converter gain error may be used. Note that, while the calibration
may be performed digitally, hardware requirements and associated
power consumption may be impracticable for low cost and/or low
power applications. As described above, the digital-to-time
converter and dithering modulo divider form a true fractional
divider. In typical usage, the fractional divider is always driving
edges into the phase detector of the PLL. However, since signal
edges only occur every PLL reference clock period (e.g. 20 ns for a
50 MHz clock), calibration circuitry may perform operations between
edges. Therefore, by monitoring the gain of the digital-to-time
converter of the phase interpolator in the background between PLL
reference clock edges, error detection and correction circuitry may
reduce or eliminate gain error using analog techniques.
[0069] In at least one embodiment, a gain calibration technique
exploits linearity of the digital-to-analog converter of the phase
interpolator described above. Systematic nonlinearity may be
reduced or eliminated with disciplined unit cell design. Use of
simple capacitor-based units have reduced random mismatch as
compared to units including transistors or other non-linear
devices. Use of active gain error calibration reduces overhead
hardware and design complexity. In addition, a target refresh rate
of the calibration is independent of a divide ratio. In at least
one embodiment, since the digital-to-analog converter is inactive
following phase interpolator edge transmission, phase interpolator
calibration is performed between edge transmissions. In at least
one embodiment, the calibration technique is addressed at the block
level, e.g., locally for each phase interpolator. Local calibration
facilitates system integration, duplication, and design reuse.
[0070] Referring to FIG. 17, a technique for compensating for a
gain error of a digital-to-time converter of a phase interpolator
generates a gain control signal G.sub.ref that is fed back to the
digital-to-time converter 1650. Digital-to-time converter 1650
generates output analog signal t'.sub.out based on a digital input
signal D'.sub.in. During evaluation intervals (i.e., when
calibration is not enabled, e.g., intervals during which cal=`0`),
selection module 1654 provides digital signal D.sub.in as digital
input signal D'.sub.in. During background calibration intervals
(e.g., intervals during which cal=`1`) selection module 1654
provides a calibration digital signal D.sub.cal as digital input
signal D'.sub.in. Referring to FIGS. 17 and 18, edge generator 1520
provides clock signal t.sub.ref and calibration clock signal
t.sub.cal, both generated with the same delay to reference clock
signal ck.sub.ref. Clock signal t.sub.ref is used by
digital-to-time converter 1650, e.g., as evaluate control signal
ck.sub.DMD of digital-to-time converter including unit cell 700 of
FIG. 8, digital-to-time converter 900 of FIG. 10, or
digital-to-time converter 1100 of FIG. 12. Referring back to FIGS.
17 and 18, calibration clock signal t.sub.cal vacillates between a
low value that corresponds to a minimum delay and a high value that
corresponds to a minimum delay plus one full reference clock signal
ck.sub.ref period delay (e.g., generated using delay element 1522,
which may be a flip-flop or other element providing a suitable
delay) according to the value of delay control signal
D.sub.delay
[0071] In at least one embodiment, edge generator 1520 provides
calibration clock signal t.sub.ref based on reference clock signal
ck.sub.ref and gating clock signal gate, which is a
frequency-divided version of reference clock signal ck.sub.ref
(e.g., frequency-divided by N). Accordingly, calibration clock
signal t.sub.cal includes a stream of pulses occurring when
calibration is enabled. Individual pulses of the stream alternate
between pulses having edges that nominally correspond to edges of
pulses of clock signal t.sub.ref and pulses having edges that
nominally correspond to edges of t.sub.ref delayed by an entire
period of reference clock signal ck.sub.ref, which will be
described further below with reference to FIGS. 20-24, where
t.sub.ref, t.sub.cal, and t'.sub.out of FIGS. 17 and 18 correspond
to clock signals ck.sub.DMD, ck.sub.D, and ck.sub.PI, respectively,
of FIGS. 21-25.
[0072] Referring back to FIGS. 17 and 18, gain adjustment generator
1652 may provide output clock signal t'.sub.out as output clock
signal t.sub.out during evaluation intervals. When performing
background calibration, gain adjustment generator 1652 generates an
analog gain adjustment that is fed back to digital-to-time
converter 1650 to compensate for gain error of digital-to-time
converter 1650.
[0073] Referring to FIG. 19, the gain calibration techniques
described herein with regard to digital-to-time converters may be
applied to time-to-digital converters that include a
digital-to-time converter. For example, the techniques may be
adapted to generate an analog gain adjustment G.sub.ref that is fed
back to the time-to-digital converter 1750 to compensate for gain
error of time-to-digital converter 1750. Time-to-digital converter
1650 generates output digital signal D'.sub.out based on an analog
input signal t'.sub.in. During evaluation intervals (i.e., when
calibration is not enabled, e.g., intervals during which cal=`0`),
selection module 1754 provides analog signal t.sub.in as t'.sub.in.
During background calibration intervals (e.g., intervals during
which cal=`1`), selection module 1754 provides a calibration analog
signal t.sub.cal. In at least one embodiment of the gain
calibration technique, gain adjustment generator 1752 generates a
digital gain adjustment that is internally applied to the output
digital signal D'.sub.out to generate adjusted output digital
signal D.sub.out (FIG. 20).
[0074] In at least one embodiment of the calibration technique, the
digital-to-time converter is a phase interpolator configured to
generate phase interpolator output ck.sub.PI, based on clock signal
ck.sub.DMD, which is the output of a fractional divider (e.g., the
output of feedback clock signal ck.sub.fb or output clock signal
ck.sub.out output by respective phase interpolators 204 responsive
to respective fractional dividers 108 of corresponding
interpolative dividers 202 of FIGS. 2 and 3). Referring to FIG. 21,
error detection and correction module 1508 generates gain control
signal g.sub.ctrl based on phase interpolator output ck.sub.PI and
feeds back gain control signal g.sub.ctrl to phase interpolator
1506 to compensate for gain error of phase interpolator 1506. Delay
module 1504 is a delay matching module that matches the delay of
the phase interpolator 1506 such that delayed reference signal
ck.sub.D is delayed by the same amount as phase interpolator output
ck.sub.PI (e.g., delay introduced by comparator 508 of
digital-to-time converter 1100 of FIG. 12) in the minimum delay
condition (e.g., delay control signal D.sub.PI equals zero).
[0075] Referring back to FIG. 21, error detection and correction
module 1508 compares edges of the output of phase interpolator 1506
(i.e., phase interpolator output ck.sub.PI generated during
calibration intervals), and the output of delay module 1504,
delayed reference signal ck.sub.D, generated during calibration
intervals to determine the gain error. Delay module 1504 receives
pulses for error detection as calibration timing reference signal
ck.sub.CDTC. During evaluation intervals (e.g., intervals during
which cal=`0`) during which phase interpolator 1506 transmits
delayed edges, calibration timing reference signal ck.sub.CDTC may
be static and does not transition. Calibration digital-to-time
converter 1502 generates the calibration timing reference signal
ck.sub.CDTC based on a reference clock signal ck.sub.ref and a
delay control signal D.sub.delay. When in calibration intervals
(e.g., intervals during which cal=`1`), calibration digital-to-time
converter 1502 delays the same, or related, gate signal as is used
to derive clock signal ck.sub.DMD based on delay control signal
D.sub.delay to generate timing reference signal ck.sub.CDTC.
[0076] In at least one embodiment of phase interpolator 204, delay
control signal D.sub.delay vacillates between a low value that
corresponds to a minimum delay and a high value that corresponds to
a minimum delay plus one full ck.sub.ref period delay (e.g., a
delay generated using delay element 1612 for a delay equivalent to
D.sub.PI=2.sup.NPI) or an entire least-significant bit of FDIV.
Accordingly, the output of calibration digital-to-time converter
1502 is a timing reference signal ck.sub.CDTC that is a stream of
pulses occurring when calibration is enabled. Individual pulses of
the stream alternate between pulses having edges that nominally
correspond to edges of pulses of clock signal ck.sub.DMD, and
pulses having edges that nominally correspond to edges of
ck.sub.DMD delayed by an entire period of ck.sub.ref. Although
illustrated using rising edges of ck.sub.ref, other embodiments
generate calibration timing reference signal ck.sub.CDTC based on
falling edges of ck.sub.ref.
[0077] Referring to FIGS. 21 and 22, divider 110 generates a clock
signal ck.sub.DMD, having pulses with periods that vacillate
between different clock periods to generate the reference timing
signal for both calibration and evaluation intervals having a
period based on the integer value D.sub.N. For example, during the
interval between time t.sub.1 and time t.sub.2, clock signal
ck.sub.DMD has a period according to integer value D.sub.N in an
evaluation mode (i.e., a transmit mode) corresponding to a clock
signal being generated by the target application (e.g., the value
of D.sub.N corresponds to three periods of ck.sub.ref). During a
calibration interval, e.g., the interval between time t.sub.2 and
time t.sub.3, clock signal ck.sub.DMD includes a pulse (e.g.,
rising edge) with a period according to integer value D.sub.N
corresponding to a clock signal being generated for use during the
calibration interval (e.g., integer value D.sub.N corresponds to
four periods of ck.sub.ref). In at least one embodiment of phase
interpolator 204, multiplexer 1503 spreads a binary or otherwise
coded delay control signal D.sub.delay to a number of bits
corresponding to the number of unit delay cells included in phase
interpolator 1506. For example, when D.sub.delay=`0,` and NPI=2,
then phase interpolator 1506 has four unit cells (one of which is
in addition to unit cells corresponding to bits output by
multiplexer 1503 and which is driven by the output of a logical AND
of D.sub.delay and cal), then D.sub.PI=`0000,` and when delay
control signal D.sub.delay=`1,` then D.sub.PI=2.sup.NPI=`1111,`
which corresponds to delaying by an entire period of
ck.sub.ref.
[0078] FIGS. 22 and 23, illustrate at least one embodiment of
timing reference signal generation. In at least one embodiment,
calibration digital-to-time converter 1502 is a single bit
digital-to-time converter with a least-significant bit of
T.sub.ref. When delay control signal D.sub.delay=0, ck.sub.CDTC is
delayed from ck.sub.DMD by T.sub.CDTC(0), which is ideally zero.
When delay control signal D.sub.delay=1, ck.sub.CDTC is delayed
from ck.sub.DMD by T.sub.CDTC(l), which is ideally T.sub.ref. The
calibration codes are time interleaved with the phase interpolator
evaluation values as signal D.sub.N. Note that in at least one
embodiment, corresponding pulse edges of the timing reference
signal ck.sub.D are generated with a fixed delay amount T.sub.D
that matches the minimum delay (e.g., D.sub.PI=0) of phase
interpolator 1506.
[0079] In at least one embodiment of a gain calibration technique,
a first phase of the gain calibration, delay control signal
D.sub.delay=`0,` and error detection and correction module 1508
generates an indication of a time difference between an edge of
fixed delay signal ck.sub.D and a corresponding edge of phase
interpolator output ck.sub.PI:
.DELTA.T.sub.cal(0)=T.sub.PI(0)-[T.sub.CDTC(0)+T.sub.D].
In a second phase of the gain calibration, D.sub.delay=`1,` and
error detection and correction module 1508 generates an indication
of a time difference between an edge of delay signal ck.sub.D and
an edge of phase interpolator output ck.sub.PI:
.DELTA.T.sub.cal(1)=T.sub.PI(2.sup.NPI)-[T.sub.CDTC(1)+T.sub.D].
[0080] Error detection and correction module 1508 determines the
difference between the two measurements to generate indicator of
linear gain error T.sub..gamma.:
T .gamma. = .DELTA. T cal ( 1 ) - .DELTA. T cal ( 0 ) = [ T PI ( 2
NPI ) - T PI ( 0 ) ] - [ T CDTC ( 1 ) - T CDTC ( 0 ) ] = T PI , FS
- T ref . ##EQU00011##
where T.sub.PI,FS [T.sub.PI(2.sup.NPI)-T.sub.PI (0)], and
T.sub.ref=[T.sub.CDTC(1)-T.sub.CDTC(0)].
[0081] Error detection and correction module 1508 generates gain
control signal g.sub.ctrl based on gain error T.sub..gamma..
Compensating for linear gain error T.sub..gamma., matches the gain
of phase interpolator 1506, which is a subrange data converter, to
the gain of the fractional divider 108, to obtain a linear transfer
function.
[0082] Referring to FIGS. 24 and 25, in each calibration phase,
phase interpolator 1506 introduces a different delay into clock
signal ck.sub.DMD to generate phase interpolator output ck.sub.PI.
When D.sub.delay=0, clock signal ck.sub.DMD is delayed relative to
ck.sub.CDTC by T.sub.PI(0)-T.sub.D, which is ideally zero. When
D.sub.delay=1, ck.sub.DMD is delayed relative to ck.sub.CDTC by
T.sub.PI(2.sup.NPI)-T.sub.D, which is ideally T.sub.ref. The
logical AND of D.sub.delay and cal control signal introduce an
extra least-significant bit to D.sub.PI so that the full-scale
range may be generated between the two calibration measurements
(without this extra bit, the maximum code is 2.sup.NPI-1). Note
that T.sub.skew=T.sub.CDTC(0)+T.sub.D-T.sub.PI(0). The gain error
and correction signal generation of error detection and correction
module 1508 may be implemented using digital circuits, analog
circuits, or a combination thereof. In at least one embodiment, an
analog implementation includes phase detector 1802 and a loop
filter 1804, which are configured to generate phase interpolator
gain control signal g.sub.ctrl. In at least one embodiment, digital
control within error detection and correction module 1508 includes
a time-to-digital converter coupled to a digital loop filter and a
gain control signal provided to an auxiliary digital-to-analog
converter. In at least one embodiment, an analog phase detector
provides signals to an analog loop filter that generates signals
provided to phase interpolator auxiliary digital-to-analog
converter. Note that during calibration phases, gating circuit 1806
may block propagation of ck.sub.PI to ck.sub.out.
[0083] Rather than delaying both ck.sub.D and ck.sub.PI in the
calibration mode, by applying a delay that vacillates between a low
value that corresponds to a minimum delay and a high value that
corresponds to a minimum delay plus one full ck.sub.ref period
delay in parallel, in separate paths as described above with
reference to FIGS. 21-25, other embodiments of the calibration
technique apply the two vacillating delays in series, in the same
path, but out of phase with each other. For example, referring to
FIG. 26, an embodiment of the calibration technique generates
timing reference signal ck'.sub.D having a fixed delay. Delay
element 1509 and logic gate 1511 generate timing reference signal
ck'.sub.D. Timing reference signal ck'.sub.D lags clock signal
ck.sub.DMD by one period of reference clock signal ck.sub.ref. In
calibration mode, the technique applies a first vacillating delay
to clock signal ck'D.sub.DMD to generate an input to the phase
interpolator. In calibration mode, the phase interpolator applies a
second vacillating delay serially to generate the output signal
ck.sub.PI. The first vacillating delay vacillates between the low
value that corresponds to the minimum delay and the high value that
corresponds to the minimum delay plus one full period of reference
clock signal ck.sub.ref, and the second vacillating delay
vacillates between the high value that corresponds to the minimum
delay plus one full period of reference clock signal ck.sub.ref,
and the low value that corresponds to the minimum delay.
Accordingly, the first and second vacillating delays introduce a
net delay of one full period of reference clock signal ck.sub.ref.
Error detection and correction circuit 1508 generates an indication
of a time difference between an edge of fixed delay signal ck.sub.D
and a corresponding edge of phase interpolator output
ck.sub.PI:
.DELTA.T.sub.cal(0)=[T.sub.CDTC(1)+T.sub.PI(0)]-[T.sub.ref+T.sub.D].
In a second phase of the gain calibration, D.sub.delay=`1,` and
error detection and correction module 1508 generates an indication
of a time difference between an edge of delay signal ck.sub.D, and
an edge of phase interpolator output ck.sub.PI:
.DELTA.T.sub.cal(i)=[T.sub.CDTC(0)+T.sub.PI(2.sup.NPI)]-[T.sub.ref+T.sub-
.D].
Error detection and correction module 1508 determines the
difference between the two measurements to generate indicator of
linear gain error T.sub..gamma.:
T .gamma. = .DELTA. T cal ( 1 ) - .DELTA. T cal ( 0 ) = [ T CDTC (
0 ) + T PI ( 2 NPI ) ] - [ T CDTC ( 1 ) + T PI ( 0 ) ] = T PI , FS
- T ref . ##EQU00012##
where T.sub.PI,FS[T.sub.PI(2.sup.NPI)-T.sub.PI(0)], and
T.sub.ref=[T.sub.CDTC(0)-T.sub.CDTC(1)].
When phase interpolator 1506 has the proper gain,
T.sub.PI,FS=T.sub.ref and no additional gain adjustment is needed.
Although the fixed delay of T.sub.ref introduced into ck'.sub.D is
not necessary, it may reduce the systematic phase error between
fixed delay signal ck.sub.D and phase interpolator output ck.sub.PI
in the calibration mode, which reduces the dynamic range
requirements of error detection and correction module 1508.
[0084] Referring to FIG. 27, analog error detection and correction
module 1508 generates a gain control compensation signal
.DELTA.I.sub.s,.gamma. that is provided to the current source of
the digital-to-time converter of the phase interpolator. During a
first calibration interval, delay control signal D.sub.delay has a
first value. Phase detector 2002 generates up and down signals
based on a first time difference in phases of reference signal
ck.sub.D and phase interpolator output ck.sub.PI. Charge pump 2004
converts the first time difference into differential charge that is
stored on integrating capacitors 2012 and 2014, each having
capacitance C.sub.int. The charge pump output is based on the
difference between the digital-to-time converter delay at a minimum
delay (i.e., D.sub.Q=0) and the delay through calibration
digital-to-time converter 1502 and delay module 1504. During a
second calibration interval, delay control signal D.sub.delay has a
second value. The charge pump output is based on the difference
between the digital-to-time converter delay at a maximum delay
(i.e., D.sub.Q=2.sup.NPI) and the delay through calibration
digital-to-time converter 1502 and delay module 1504. Phase
detector 2002 generates up and down signals based on a second time
difference in phases of reference signal ck.sub.D and phase
interpolator output ck.sub.PI. Charge pump 2004 converts the second
time difference into a second differential charge, switch 2006
inverts the second differential charge, and stores that inverted
difference in charge on integrating capacitors 2012 and 2014. When
in the second calibration interval, the track signal causes charge
transfer to hold capacitors 2016 and 2018, which updates
V.sub.hold. Transconductance amplifier 2008 generates the gain
control signal .DELTA.I.sub.s,.gamma., that is used to adjust the
slew current to correct for the gain error. Note that switch 2006
facilitates a subtraction function to isolate gain error
T.sub..gamma. from the two measurements. In addition, note that the
critical paths are identical between the two measurements. However,
note that charge-sharing due to T.sub.skew may cause systematic
gain error.
[0085] Referring to FIG. 28, in at least one embodiment, in
addition to generating gain control signal .DELTA.I.sub.s,.gamma.,
analog error detection and correction module 1508 also generates a
differential skew correction signal, .DELTA.I.sub.s,skew, which may
be combined with a current source control signal to compensate for
the skew between outputs of those two modules. One of the
complementary signals (e.g., -.DELTA.I.sub.s,skew) of the
differential signal is combined with a current source control
signal of the phase interpolator 1506 and the other of the
complementary signals (e.g., .DELTA.I.sub.s,skew) is combined with
a current source control signal of delay module 1504. In operation,
during a first calibration interval, D.sub.delay has a first value.
Phase detector 2002 generates up and down signals based on a first
time difference in phases of reference signal ck.sub.D and phase
interpolator output ck.sub.PI. Charge pump 2004 converts the first
time difference into a first differential charge, the track.sub.0
signal causes charge transfer of that charge to integrating
capacitor 2106. During a second calibration interval, D.sub.delay
has a second value. Phase detector 2002 generates up and down
signals based on a second time difference in phases of ck.sub.D and
ck.sub.PI. Charge pump 2004 converts the second time difference
into a second differential charge, and the track.sub.1 signal
causes charge transfer of that charge to integrating capacitor
2108. Differential-to-common mode transconductance amplifier 2008
applies gain control signal .DELTA.I.sub.s,.gamma. to adjust the
slew current of the phase interpolator. A
common-mode-to-differential-mode transconductance amplifier 2014
applies skew correction by differentially applying slew currents of
phase interpolator 1506 and delay module 1504 although in other
embodiments, all of the skew correction may be applied to the phase
interpolator 1506 delay elements or all of the skew correction may
be applied to the delay elements of delay module 1504. Note that
charge-sharing due to T.sub..gamma. may cause systematic gain
error, charge pump 2004 has a finite output resistance, and
supporting a differential voltage, V.sub.int1-V.sub.int0 may cause
gain errors. In addition, note that controlling slew current
I.sub.s affects the control loop for both calibration and
evaluation:
T PI ( D Q ) = C S I S ( V t - V rst ) + T comp + C S I S V ref 2 N
frac D Q , ##EQU00013##
Changing the slew current I.sub.s controls the gain of the phase
interpolator, which is desired, but also affects the skew
measurement in a calibration phase (e.g., calibration phase zero,
T.sub.skew+T.sub.PI (0), which is undesirable.
[0086] Referring to FIG. 29, in at least one embodiment, an analog
implementation of error detection and correction module 1508
decouples the gain and skew control loops. The gain is corrected by
controlling a voltage reference in digital-to-analog converter 2204
of phase interpolator 1506. Error detection and correction module
1508 senses skew only from V.sub.int0. The two integrator loop
forces V.sub.int1-V.sub.int0 to within a transconductor offset
voltage, which reduces charge sharing error. The charge-sharing
error may be further reduced by auto-zeroing the gain control
transconductor. In other embodiments, correction of the delay
module 1504 may also be implemented using voltage control of a
reference voltage. Note that V.sub.gctrlV.sub.ref for trim at
production test and upon startup.
[0087] Referring to FIG. 30, in at least one embodiment, error
detection and correction module 1508 includes bang-bang phase
detector 2302 coupled to digital accumulator 2308, and current
digital-to-analog converter 2310, which reduces or eliminates
T.sub.skew and issues associated with an analog control loop
implementation (e.g., charge sharing). Charge pump 2304 and
capacitor 2305 are configured as an integrating switched current
digital-to-analog converter. The charge pump output may include
small up/down charge packets to reduce V.sub.gctrl ripple. However,
note that this configuration dithers around on average, causing
ripple in the control signal and resulting in quantization noise.
In other embodiments, correction of the delay module 1504 may be
implemented using a charge pump and integrating switched-current
digital-to-analog converter control.
[0088] Referring back to FIG. 28, charge-sharing at the output of
charge pump 2004 behaves like a switched-capacitor resistor between
nodes V.sub.int0 and V.sub.int1, which results in a reduction in DC
charge pump gain. Sustaining a differential voltage across nodes
V.sub.int0 and V.sub.int1 may cause a substantial gain error. A
technique for reducing or eliminating that contribution to gain
error is illustrated in FIG. 31. Error detection and correction
module 1508 includes pre-charge voltage buffer 2406 and pre-charge
voltage buffer 2408 for each of capacitor nodes C.sub.int0 and
C.sub.int1. Pre-charge voltage buffer 2406 and pre-charge voltage
buffer 2408 are configured to force the respective nodes coupled to
the output of the charge pump 2004 to V.sub.int0 and V.sub.int1,
respectively, prior to connecting those nodes to C.sub.int0 and
C.sub.int1, respectively. Accordingly, the charge-sharing is
reduced to the buffer offset voltage. In other embodiments, the
switched-capacitor buffers 2406 and 2408 of error are modified to
be an integrator with noise cancellation, as illustrated in FIG. 32
for one calibration phase (i.e., for the D.sub.delay=0 calibration
phase). Although not shown, the integrator with noise cancellation
circuitry is replicated for the other calibration phase (i.e., for
the D.sub.delay=1 calibration phase). Such technique substantially
reduces charge-sharing in analog error detection and correction
module 1508.
[0089] Interpolative divider techniques that interleave evaluate or
transmit operations with calibration operations, as described
above, use a reference clock signal that is at least twice the
frequency of the transmit operation. Referring to FIG. 33, by
interleaving multiple interpolative dividers, an output clock
signal with approximately 50% duty cycle may be achieved. The
interleaved interpolative divider implementation may double the
output clock frequency or relax calibration timing requirements.
Dithering-modulo-divider and controller 2602 alternates between
phase interpolator 2604 and phase interpolator 2606. While phase
interpolator 2604 transmits a rising edge, which causes a rising
edge on ck.sub.out, phase interpolator 2606 makes a calibration
measurement. Phase interpolator 2606 transmits a rising edge, which
causes a falling edge on ck.sub.out, while phase interpolator 2604
performs a calibration measurement. Flip-flop 2608 latches the
rising edge ck.sub.PIr from phase interpolator 2604 and the falling
edge ck.sub.PIf from phase interpolator 2606 and generates output
clock ck.sub.out having approximately 50% duty cycle. Note that
more interleaving can support higher frequency operation at e.g.,
radio frequencies.
[0090] The gain calibration interleaving with digital-to-time
signal evaluation techniques described herein may be applied to
time-to-digital signal conversion applications. For example,
referring to FIG. 34, a gain measurement is interleaved between
edges of clock ck.sub.in. Use of the calibration digital-to-time
converter facilitates a two-point measurement with a precise time
base having reference period T.sub.ref. Similar to the
digital-to-time calibrations discussed above, the control loop may
change reference voltage V.sub.ref to force accurate
time-to-digital gain. A difference between code D.sub.T generated
by analog-to-digital converter 2704 determines a gain of the
time-to-digital converter. Skew between the calibration mode and
the input path introduces a fixed offset between time stamps. As a
result, additional range greater than reference period T.sub.ref
(as defined by the period of clock signal ck.sub.ref) may be
required for the analog-to-digital conversion in order to reduce or
eliminate over-ranging (i.e., saturation of the analog-to-digital
converter).
[0091] Referring to FIG. 35, exemplary time-to-digital converter
3200 includes capacitance C.sub.S distributed across capacitors
3208 and 3210 of feedback digital-to-analog converter units (e.g.,
digital-to-analog converter units 3214 and 3216 similar to
digital-to-analog converter 1102 of digital-to-time converter 1100
of FIGS. 12-14) of a digital-to-analog converter configured to
sample-and-hold input signal ck.sub.in. Comparator 3212 uses the
comparator threshold voltage V.sub.T to compare against the stored
input time signal V.sub.S generated by sample-and-hold of input
signal ck.sub.in. Comparator 3212 provides the results of the
comparison to successive approximation register 3202. Successive
approximation register 3202 provides a digital approximation code
to the internal capacitor-based digital-to-analog converter that
supplies comparators 3212 with an analog voltage representation of
the digital approximation code. Thus, analog-to-digital converter
3200 generates output digital bits b.sub.0, and b.sub.1, which
collectively form an output digital signal D.sub.out and are based
on input analog signal V.sub.S, originally derived from an input
time interval. The time domain information may be mapped into
voltages and digital-signal processing techniques may be used to
determine distances, velocities, etc. based on that time domain
information in radar or other applications.
[0092] An embodiment of the digital-to-time converter and
calibration technique described above may be included as a feedback
digital-to-analog converter in a high resolution time-to-digital
converter application. Referring to FIG. 36, an exemplary
high-resolution time-to-digital converter receives input signal
ck.sub.in, and digital control words D.sub.f,int and D.sub.f,frac
which correspond to coarse and fine frequency divider control
codes, respectively. Accumulator 3612 integrates the fine frequency
divider control code to generate a fine delay control code (i.e.,
fine phase domain control code D.sub..phi.,frac) and summing node
3618 combines any carry from the integration with the coarse
frequency divider control code and provides the sum to
digital-to-frequency converter 3616. Phase detector 3602 generates
analog phase error signal .phi..sub..epsilon. indicative of the
phase difference between input signal ck.sub.in and feedback signal
ck.sub.fb. Loop filter 3604 integrates .phi..sub..epsilon. and
quantizer 3606 generates digital phase output D.sub..phi.out based
on the loop filter output.
[0093] Summing node 3610 combines digital phase output
D.sub..phi.out with fine phase domain control code D.sub..phi.,frac
to generate digital phase control code D.sub..phi.DTC for
conversion to an analog signal by digital-to-time converter and
calibration module 3608, which generates feedback signal ck.sub.fb.
Feedback signal ck.sub.fb is an analog representation of the
digital output D.sub..phi.out Digital-to-frequency converter 3616
and edge gating circuit 3614 form a digitally controlled integer
divider and generate clock signal ck.sub.DMD based on reference
clock signal ck.sub.ref and digital control word D.sub.f, which
indicates a coarse (or integer portion) of a frequency divider
value. Since the gain of the digital-to-time conversion performed
by digital-to-time converter and calibration module 3608 is
calibrated consistent with techniques described above, feedback
clock signal ck.sub.fb has reduced deterministic jitter, which
allows for digital output D.sub..phi.out to provide a higher
resolution digital representation of the time information of input
signal ck.sub.in than other time-to-digital converters. Note that
in other high-resolution time-to-digital converters consistent with
the teachings herein, phase-detector 3602, loop filter 3604, and
quantizer 3608 may be replaced with a bang-bang phase detector or
other suitable implementations.
[0094] Thus, improved techniques for digital-to-time conversion and
phase interpolation for clock synthesis have been disclosed.
Systematic nonlinearities in digital-to-analog conversion are
reduced by using capacitor-based unit delay cells and ratio-metric
design techniques. In addition, an active gain error calibration
technique for block level implementation is disclosed for
high-performance applications. Techniques described herein reduce
or eliminate gain error of a digital-to-time converter. In
applications such as fractional clock synthesis, the reduction or
elimination of that gain error reduces spurious outputs due to
phase wrapping errors caused by the gain error of the
digital-to-time converter. Accordingly, fractional clock
synthesizers using those techniques may produce clocks with
spurious performance similar to integer clock synthesizer
counterparts but with increased power efficiency due to increased
bandwidth (e.g. suppressed VCO noise) of the fractional
synthesizer. In addition, the digital-to-time conversion techniques
described herein may have reduced area and power consumption as
compared to other techniques.
[0095] While circuits and physical structures have been generally
presumed in describing embodiments of the invention, it is well
recognized that in modern semiconductor design and fabrication,
physical structures and circuits may be embodied in
computer-readable descriptive form suitable for use in subsequent
design, simulation, test or fabrication stages. Structures and
functionality presented as discrete components in the exemplary
configurations may be implemented as a combined structure or
component. Various embodiments of the invention are contemplated to
include circuits, systems of circuits, related methods, and
tangible computer-readable medium having encodings thereon (e.g.,
VHSIC Hardware Description Language (VHDL), Verilog, GDSII data,
Electronic Design Interchange Format (EDIF), and/or Gerber file) of
such circuits, systems, and methods, all as described herein, and
as defined in the appended claims. In addition, the
computer-readable media may store instructions as well as data that
can be used to implement the invention. The instructions/data may
be related to hardware, software, firmware or combinations
thereof.
[0096] The description of the invention set forth herein is
illustrative, and is not intended to limit the scope of the
invention as set forth in the following claims. For example, while
the invention has been described in an embodiment in which a
digital-to-time converter of a phase interpolator of a clock
synthesizer is compensated, one of skill in the art will appreciate
that the teachings herein can be utilized with other
digital-to-time and time-to-digital converter applications.
Variations and modifications of the embodiments disclosed herein,
may be made based on the description set forth herein, without
departing from the scope and spirit of the invention as set forth
in the following claims.
* * * * *