U.S. patent application number 14/771502 was filed with the patent office on 2016-12-15 for method for manufacturing ltps tft substrate and ltps tft substrate.
The applicant listed for this patent is Shenzhen China Star Optoelectronics Technology Co. Ltd.. Invention is credited to Songshan Li.
Application Number | 20160365372 14/771502 |
Document ID | / |
Family ID | 57484002 |
Filed Date | 2016-12-15 |
United States Patent
Application |
20160365372 |
Kind Code |
A1 |
Li; Songshan |
December 15, 2016 |
METHOD FOR MANUFACTURING LTPS TFT SUBSTRATE AND LTPS TFT
SUBSTRATE
Abstract
The present invention provides a method for manufacturing a LTPS
TFT substrate and a LTPS TFT substrate. The method for
manufacturing the LTPS TFT substrate of the present invention forms
a thermally conductive electrical insulation layer having excellent
properties of electrical insulation and thermal conductivity on a
buffer layer to quickly absorb a great amount of heat during a RTA
process to be transferred to an amorphous silicon layer in contact
therewith so that the portion of the amorphous silicon at this site
shows an increased efficiency of crystallization, whereby
polycrystalline silicon has an increased grain size and reduced
gain boundaries and thus the mobility of charge carriers of a
corresponding TFT device is increased and the influence of the
leakage current caused by grain boundary is reduced. The LTPS TFT
substrate of the present invention includes a thermally conductive
electrical insulation layer formed on a buffer layer at a location
exactly under a polycrystalline silicon semiconductor layer and the
grain size of the crystallization of the polycrystalline silicon is
relatively large, the grain boundaries are reduced in number, the
mobility of charge carriers of a TFT device is increased, and the
electrical property of the TFT is improved.
Inventors: |
Li; Songshan; (Shenzhen
City, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Shenzhen China Star Optoelectronics Technology Co. Ltd. |
Shenzhen City |
|
CN |
|
|
Family ID: |
57484002 |
Appl. No.: |
14/771502 |
Filed: |
June 29, 2015 |
PCT Filed: |
June 29, 2015 |
PCT NO: |
PCT/CN2015/082667 |
371 Date: |
August 31, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/1262 20130101;
H01L 29/78603 20130101; H01L 27/1281 20130101; H01L 21/02422
20130101; H01L 21/02502 20130101; H01L 21/02488 20130101; H01L
29/66757 20130101; H01L 29/78618 20130101; H01L 21/02672 20130101;
H01L 29/78675 20130101; H01L 21/02532 20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12; H01L 29/66 20060101 H01L029/66; H01L 21/265 20060101
H01L021/265; H01L 21/02 20060101 H01L021/02 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 15, 2015 |
CN |
201510331333.7 |
Claims
1. A method for manufacturing a low-temperature polycrystalline
silicon (LTPS) thin-film transistor (TFT) substrate, comprising the
following steps: (1) providing a substrate and depositing a buffer
layer on the substrate; (2) depositing a thermally conductive
electrical insulation film on the buffer layer and patterning the
thermally conductive electrical insulation film to form a thermally
conductive electrical insulation layer; (3) depositing an amorphous
silicon layer on the buffer layer in such a way that the amorphous
silicon layer completely covers the thermally conductive electrical
insulation layer; (4) implanting boron ions in the amorphous
silicon layer through ion implantation; subjecting the amorphous
silicon layer to rapid thermal annealing to have the amorphous
silicon crystallized into polycrystalline silicon, and then
applying an etching operation to remove an electrically conductive
layer precipitating on a surface of the polycrystalline silicon
during crystallization to form a polycrystalline silicon layer; (5)
patterning the polycrystalline silicon layer to form a
polycrystalline silicon semiconductor layer; (6) coating
photoresist on the polycrystalline silicon semiconductor layer and
conducting exposure and development on the photoresist to form a
photoresist layer on the polycrystalline silicon semiconductor
layer in such a way that two end portions of the polycrystalline
silicon semiconductor layer are exposed; implanting boron ions into
the two end portions of the polycrystalline silicon semiconductor
layer through ion implantation with the photoresist layer serving
as a shielding layer so as to form source/drain contact zones; and
(7) peeling off the photoresist layer and forming, in sequence, a
gate insulation layer, a gate terminal, an interlayer insulation
layer, and source/drain terminals on the polycrystalline silicon
semiconductor layer, wherein the source/drain terminals are
respectively connected to the source/drain contact zones at the two
end portions of the polycrystalline silicon semiconductor
layer.
2. The method for manufacturing the LTPS TFT substrate as claimed
in claim 1, wherein in step (1), the buffer layer is formed of a
material of SiNx, SiOx, or a combination thereof.
3. The method for manufacturing the LTPS TFT substrate as claimed
in claim 1, wherein in step (2), photolithographic and etching
operations are applied to pattern the thermally conductive
electrical insulation layer; the thermally conductive electrical
insulation layer is formed of a material of Al.sub.2O.sub.3; and
the thermally conductive electrical insulation layer has a
thickness of 30-50 nm.
4. The method for manufacturing the LTPS TFT substrate as claimed
in claim 1, wherein in step (3), the amorphous silicon layer has a
thickness of 200-300 nm.
5. The method for manufacturing the LTPS TFT substrate as claimed
in claim 1, wherein in step (4), the rapid thermal annealing is
conducted at a temperature of 650.degree. C.-700.degree. C. for a
time period of 15-25 minutes; and the electrically conductive layer
that precipitates on the surface of the polycrystalline silicon is
removed through etching by a thickness of 100-150 nm.
6. The method for manufacturing the LTPS TFT substrate as claimed
in claim 1, wherein in step (5), photolithographic and etching
operations are applied to pattern the polycrystalline silicon
layer; and the pattern of the thermally conductive electrical
insulation layer corresponds to the pattern of the polycrystalline
silicon semiconductor layer.
7. The method for manufacturing the LTPS TFT substrate as claimed
in claim 1, wherein in step (7), the gate insulation layer is
formed of a material of SiOx.
8. A method for manufacturing a low-temperature polycrystalline
silicon (LTPS) thin-film transistor (TFT) substrate, comprising the
following steps: (1) providing a substrate and depositing a buffer
layer on the substrate; (2) depositing a thermally conductive
electrical insulation film on the buffer layer and patterning the
thermally conductive electrical insulation film to form a thermally
conductive electrical insulation layer; (3) depositing an amorphous
silicon layer on the buffer layer in such a way that the amorphous
silicon layer completely covers the thermally conductive electrical
insulation layer; (4) implanting boron ions in the amorphous
silicon layer through ion implantation; subjecting the amorphous
silicon layer to rapid thermal annealing to have the amorphous
silicon crystallized into polycrystalline silicon, and then
applying an etching operation to remove an electrically conductive
layer precipitating on a surface of the polycrystalline silicon
during crystallization to form a polycrystalline silicon layer; (5)
patterning the polycrystalline silicon layer to form a
polycrystalline silicon semiconductor layer; (6) coating
photoresist on the polycrystalline silicon semiconductor layer and
conducting exposure and development on the photoresist to form a
photoresist layer on the polycrystalline silicon semiconductor
layer in such a way that two end portions of the polycrystalline
silicon semiconductor layer are exposed; implanting boron ions into
the two end portions of the polycrystalline silicon semiconductor
layer through ion implantation with the photoresist layer serving
as a shielding layer so as to form source/drain contact zones; and
(7) peeling off the photoresist layer and forming, in sequence, a
gate insulation layer, a gate terminal, an interlayer insulation
layer, and source/drain terminals on the polycrystalline silicon
semiconductor layer, wherein the source/drain terminals are
respectively connected to the source/drain contact zones at the two
end portions of the polycrystalline silicon semiconductor layer;
wherein in step (1), the buffer layer is formed of a material of
SiNx, SiOx, or a combination thereof; wherein in step (2),
photolithographic and etching operations are applied to pattern the
thermally conductive electrical insulation layer; the thermally
conductive electrical insulation layer is formed of a material of
Al.sub.2O.sub.3; and the thermally conductive electrical insulation
layer has a thickness of 30-50 nm; wherein in step (3), the
amorphous silicon layer has a thickness of 200-300 nm.
9. The method for manufacturing the LTPS TFT substrate as claimed
in claim 8, wherein in step (4), the rapid thermal annealing is
conducted at a temperature of 650.degree. C.-700.degree. C. for a
time period of 15-25 minutes; and the electrically conductive layer
that precipitates on the surface of the polycrystalline silicon is
removed through etching by a thickness of 100-150 nm.
10. The method for manufacturing the LTPS TFT substrate as claimed
in claim 8, wherein in step (5), photolithographic and etching
operations are applied to pattern the polycrystalline silicon
layer; and the pattern of the thermally conductive electrical
insulation layer corresponds to the pattern of the polycrystalline
silicon semiconductor layer.
11. The method for manufacturing the LTPS TFT substrate as claimed
in claim 8, wherein in step (7), the gate insulation layer is
formed of a material of SiOx.
12. A low-temperature polycrystalline silicon (LTPS) thin-film
transistor (TFT) substrate, comprising a substrate, a buffer layer
arranged on the substrate, a thermally conductive electrical
insulation layer arranged on the buffer layer, a polycrystalline
silicon semiconductor layer arranged on the thermally conductive
electrical insulation layer, a gate insulation layer arranged on
the buffer layer and covering the thermally conductive electrical
insulation layer and the polycrystalline silicon semiconductor
layer, a gate terminal arranged on the gate insulation layer, an
interlayer insulation layer arranged on the gate insulation layer
and covering the gate terminal, and source/drain terminals arranged
on the interlayer insulation layer; wherein the polycrystalline
silicon semiconductor layer has two opposite end portions that are
source/drain contact zones implanted with boron ions; the gate
insulation layer and the interlayer insulation layer both have
portions corresponding to the source/drain contact zones and formed
with vias; and the source/drain terminals are respectively
connected through the vias to the source/drain contact zones.
13. The LTPS TFT substrate as claimed in claim 12, wherein the
buffer layer is formed of a material of SiNx, SiOx, or a
combination thereof; the thermally conductive electrical insulation
layer is formed of a material of Al.sub.2O.sub.3; and the gate
insulation layer is formed of a material of SiOx.
14. The LTPS TFT substrate as claimed in claim 12, wherein the
thermally conductive electrical insulation layer has a thickness of
30-50 nm; the thermally conductive electrical insulation layer has
a pattern corresponding to a pattern of the polycrystalline silicon
semiconductor layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to the field of display
technology, and in particular to a method for manufacturing a
low-temperature polycrystalline silicon (LTPS) thin-film-transistor
(TFT) substrate and a LTPS TFT substrate.
[0003] 2. The Related Arts
[0004] The development of flat-panel displays brings successive
demands for high-definition and low-power-consumption panels.
Low-temperature polycrystalline silicon (LTPS), which has a
relatively high mobility, has gained much attention from the
industry of liquid crystal displays (LCDs) and organic light
emitting diodes (OLEDs) and is considered an important material for
achieving low-cost full-color flat-panel displays. For a flat-panel
display, adopting a material of LTPS may possess various advantages
including high definition, fast response speed, high brightness,
high aperture rate, and low power consumption. In addition, LTPS
can be used in manufacture in a low temperature and is applicable
to the manufacture of C-MOS circuits, making it widely used to meet
the needs of high definition and low power consumption for
panels.
[0005] LTPS is a branch of the polycrystalline silicon (poly-Si)
technology. The molecular structure of polycrystalline silicon
shows an ordered and directional arrangement in a crystal grain. As
such, the mobility thereof is faster than that of amorphous silicon
(a-Si) that is generally randomly arranged by 200-300 times, making
it possible to significantly increase the response speed of a
flat-panel display. Various crystallization processes are available
for manufacturing LTPS, among which primary ones are chemical vapor
deposition (CVD), solid phase crystallization (SPC), metal-induced
crystallization (MIC), metal-induced lateral crystallization
(MILC), and excimer laser annealing (ELA).
[0006] Referring to FIGS. 1-6, a known method for manufacturing a
LTPS TFT substrate generally comprises the following steps: Step 1:
providing a substrate 100 and depositing a buffer layer 200 on the
glass substrate 100; Step 2: depositing an amorphous silicon (a-Si)
layer 300 on the buffer layer 200; Step 3: applying ion
implantation to implant a predetermined dosage of boron into the
amorphous silicon layer 300 and then applying rapid thermal anneal
(RTA) to heat for 20-30 minutes to have the amorphous silicon
crystallized into polycrystalline silicon (poly-Si), and then
etching and removing an electrically conductive layer that
precipitates on a surface of the polycrystalline silicon during the
crystallization process and has a low electrical resistance with
only a desired polycrystalline silicon layer 400 left; Step 4:
patterning the polycrystalline silicon layer 400 through
photolithographic and etching operations to form a polycrystalline
silicon semiconductor layer 450; Step 5: coating photoresist on the
polycrystalline silicon semiconductor layer 450 and conducting
exposure and development on the photoresist to form a photoresist
layer 550 on the polycrystalline silicon semiconductor layer 450 in
such a way that two end portions of the polycrystalline silicon
semiconductor layer 450 are exposed; implanting boron ions into the
two end portions of the polycrystalline silicon semiconductor layer
450 through ion implantation with the photoresist layer 550 serving
as a shielding layer so as to form source/drain contact zones 451;
Step 6: peeling off the photoresist layer 550 and forming, in
sequence, a gate insulation layer 500, a gate terminal 600, an
interlayer insulation layer 700, and source/drain terminals 800 on
the polycrystalline silicon semiconductor layer 450.
[0007] In the above-described method for manufacturing a LTPS TFT
substrate, the formation of low-temperature polycrystalline silicon
is achieved with a conventional SPC crystallization process. Such a
SPC crystallization process, although forming grain sizes showing
excellent consistency, the grain sizes are small and the grain
boundaries are numerous, imposing influences on the mobility of
charge carriers and the leakage current of a TFT device.
SUMMARY OF THE INVENTION
[0008] An object of the present invention is to provide a method
for manufacturing a low-temperature polycrystalline silicon (LTPS)
thin-film transistor (TFT) substrate, which effectively improves
crystallization efficiency of a crystallization process, increases
the grain sizes, reduces the number of grain boundaries, and thus
improving the mobility of charge carriers of a TFT device, reducing
the influence of the leakage current caused by the grain
boundaries, and improving the electrical property of the TFT
device.
[0009] Another object of the present invention is to provide a LTPS
TFT substrate, of which the grain size of polycrystalline silicon
is relatively large, the number of grain boundaries is reduced, the
mobility of charge carriers of a TFT device is increased, and the
electrical property of the TFT device is improved.
[0010] To achieve the above objects, the present invention provides
a method for manufacturing a LTPS TFT substrate, which comprises
the following steps:
[0011] (1) providing a substrate and depositing a buffer layer on
the substrate;
[0012] (2) depositing a thermally conductive electrical insulation
film on the buffer layer and patterning the thermally conductive
electrical insulation film to form a thermally conductive
electrical insulation layer;
[0013] (3) depositing an amorphous silicon layer on the buffer
layer in such a way that the amorphous silicon layer completely
covers the thermally conductive electrical insulation layer;
[0014] (4) implanting boron ions in the amorphous silicon layer
through ion implantation; subjecting the amorphous silicon layer to
rapid thermal annealing to have the amorphous silicon crystallized
into polycrystalline silicon, and then applying an etching
operation to remove an electrically conductive layer precipitating
on a surface of the polycrystalline silicon during crystallization
to form a polycrystalline silicon layer;
[0015] (5) patterning the polycrystalline silicon layer to form a
polycrystalline silicon semiconductor layer;
[0016] (6) coating photoresist on the polycrystalline silicon
semiconductor layer and conducting exposure and development on the
photoresist to form a photoresist layer on the polycrystalline
silicon semiconductor layer in such a way that two end portions of
the polycrystalline silicon semiconductor layer are exposed;
implanting boron ions into the two end portions of the
polycrystalline silicon semiconductor layer through ion
implantation with the photoresist layer serving as a shielding
layer so as to form source/drain contact zones; and
[0017] (7) peeling off the photoresist layer and forming, in
sequence, a gate insulation layer, a gate terminal, an interlayer
insulation layer, and source/drain terminals on the polycrystalline
silicon semiconductor layer, wherein the source/drain terminals are
respectively connected to the source/drain contact zones at the two
end portions of the polycrystalline silicon semiconductor
layer.
[0018] In step (1), the buffer layer is formed of a material of
SiNx, SiOx, or a combination thereof.
[0019] In step (2), photolithographic and etching operations are
applied to pattern the thermally conductive electrical insulation
layer; the thermally conductive electrical insulation layer is
formed of a material of Al.sub.2O.sub.3; and the thermally
conductive electrical insulation layer has a thickness of 30-50
nm.
[0020] In step (3), the amorphous silicon layer has a thickness of
200-300 nm.
[0021] In step (4), the rapid thermal annealing is conducted at a
temperature of 650.degree. C.-700.degree. C. for a time period of
15-25 minutes; and the electrically conductive layer that
precipitates on the surface of the polycrystalline silicon is
removed through etching by a thickness of 100-150 nm.
[0022] In step (5), photolithographic and etching operations are
applied to pattern the polycrystalline silicon layer; and the
pattern of the thermally conductive electrical insulation layer
corresponds to the pattern of the polycrystalline silicon
semiconductor layer.
[0023] In step (7), the gate insulation layer is formed of a
material of SiOx.
[0024] The present invention also provides a method for
manufacturing a LTPS TFT substrate, which comprises the following
steps:
[0025] (1) providing a substrate and depositing a buffer layer on
the substrate;
[0026] (2) depositing a thermally conductive electrical insulation
film on the buffer layer and patterning the thermally conductive
electrical insulation film to form a thermally conductive
electrical insulation layer;
[0027] (3) depositing an amorphous silicon layer on the buffer
layer in such a way that the amorphous silicon layer completely
covers the thermally conductive electrical insulation layer;
[0028] (4) implanting boron ions in the amorphous silicon layer
through ion implantation; subjecting the amorphous silicon layer to
rapid thermal annealing to have the amorphous silicon crystallized
into polycrystalline silicon, and then applying an etching
operation to remove an electrically conductive layer precipitating
on a surface of the polycrystalline silicon during crystallization
to form a polycrystalline silicon layer;
[0029] (5) patterning the polycrystalline silicon layer to form a
polycrystalline silicon semiconductor layer;
[0030] (6) coating photoresist on the polycrystalline silicon
semiconductor layer and conducting exposure and development on the
photoresist to form a photoresist layer on the polycrystalline
silicon semiconductor layer in such a way that two end portions of
the polycrystalline silicon semiconductor layer are exposed;
implanting boron ions into the two end portions of the
polycrystalline silicon semiconductor layer through ion
implantation with the photoresist layer serving as a shielding
layer so as to form source/drain contact zones; and
[0031] (7) peeling off the photoresist layer and forming, in
sequence, a gate insulation layer, a gate terminal, an interlayer
insulation layer, and source/drain terminals on the polycrystalline
silicon semiconductor layer, wherein the source/drain terminals are
respectively connected to the source/drain contact zones at the two
end portions of the polycrystalline silicon semiconductor
layer;
[0032] wherein in step (1), the buffer layer is formed of a
material of SiNx, SiOx, or a combination thereof;
[0033] wherein in step (2), photolithographic and etching
operations are applied to pattern the thermally conductive
electrical insulation layer; the thermally conductive electrical
insulation layer is formed of a material of Al.sub.2O.sub.3; and
the thermally conductive electrical insulation layer has a
thickness of 30-50 nm;
[0034] wherein in step (3), the amorphous silicon layer has a
thickness of 200-300 nm.
[0035] The present invention further provides a LTPS TFT substrate,
which comprises a substrate, a buffer layer arranged on the
substrate, a thermally conductive electrical insulation layer
arranged on the buffer layer, a polycrystalline silicon
semiconductor layer arranged on the thermally conductive electrical
insulation layer, a gate insulation layer arranged on the buffer
layer and covering the thermally conductive electrical insulation
layer and the polycrystalline silicon semiconductor layer, a gate
terminal arranged on the gate insulation layer, an interlayer
insulation layer arranged on the gate insulation layer and covering
the gate terminal, and source/drain terminals arranged on the
interlayer insulation layer;
[0036] wherein the polycrystalline silicon semiconductor layer has
two opposite end portions that are source/drain contact zones
implanted with boron ions; the gate insulation layer and the
interlayer insulation layer both have portions corresponding to the
source/drain contact zones and formed with vias; and the
source/drain terminals are respectively connected through the vias
to the source/drain contact zones.
[0037] The buffer layer is formed of a material of SiNx, SiOx, or a
combination thereof; the thermally conductive electrical insulation
layer is formed of a material of Al.sub.2O.sub.3; and the gate
insulation layer is formed of a material of SiOx.
[0038] The thermally conductive electrical insulation layer has a
thickness of 30-50 nm; the thermally conductive electrical
insulation layer has a pattern corresponding to a pattern of the
polycrystalline silicon semiconductor layer.
[0039] The efficacy of the present invention is that the present
invention provides a method for manufacturing a LTPS TFT substrate,
in which a thermally conductive electrical insulation layer having
excellent properties of electrical insulation and thermal
conductivity is formed on the buffer layer to quickly absorb a
great amount of heat during a RTA process to be transferred to an
amorphous silicon layer in contact therewith so that the portion of
the amorphous silicon at this site shows an increased efficiency of
crystallization, whereby polycrystalline silicon has an increased
grain size and reduced gain boundaries and thus the mobility of
charge carriers of a corresponding TFT device is increased and the
influence of the leakage current caused by grain boundary is
reduced. The present invention also provides an LTPS TFT substrate,
in which a thermally conductive electrical insulation layer is
formed on a buffer layer at a location exactly under the
polycrystalline silicon semiconductor layer and the grain size of
the crystallization of the polycrystalline silicon is relatively
large, the grain boundaries are reduced in number, the mobility of
charge carriers of a TFT device is increased, and the electrical
property of the TFT is improved.
BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The features and technical contents of the present invention
will be apparent from the following detailed description of the
present invention and the attached drawing; however, these drawings
are provided for reference and illustration and are not intended to
limit the scope of the present invention. In the drawing:
[0041] FIG. 1 is a schematic view illustrating a first step of a
known method for manufacturing a low-temperature polycrystalline
silicon (LTPS) thin-film transistor (TFT) substrate;
[0042] FIG. 2 is a schematic view illustrating a second step of the
known method for manufacturing the LTPS TFT substrate;
[0043] FIG. 3 is a schematic view illustrating a third step of the
known method for manufacturing the LTPS TFT substrate;
[0044] FIG. 4 is a schematic view illustrating a fourth step of the
known method for manufacturing the LTPS TFT substrate;
[0045] FIG. 5 is a schematic view illustrating a fifth step of the
known method for manufacturing the LTPS TFT substrate;
[0046] FIG. 6 is a schematic view illustrating a sixth step of the
known method for manufacturing the LTPS TFT substrate;
[0047] FIG. 7 is a flow chart illustrating a method for
manufacturing a LTPS TFT substrate according to the present
invention;
[0048] FIG. 8 is a schematic view illustrating a first step of the
method for manufacturing the LTPS TFT substrate according to the
present invention;
[0049] FIG. 9 is a schematic view illustrating a second step of the
method for manufacturing the LTPS TFT substrate according to the
present invention;
[0050] FIG. 10 is a schematic view illustrating a third step of the
method for manufacturing the LTPS TFT substrate according to the
present invention;
[0051] FIG. 11 is a schematic view illustrating implanting a
predetermined amount of boron in an amorphous silicon layer in a
fourth step of the method for manufacturing the LTPS TFT substrate
according to the present invention;
[0052] FIG. 12 is a schematic view illustrating the structure after
the fourth step of the method for manufacturing the LTPS TFT
substrate according to the present invention;
[0053] FIG. 13 is a schematic view illustrating a fifth step of the
method for manufacturing the LTPS TFT substrate according to the
present invention;
[0054] FIG. 14 is a schematic view illustrating a sixth step of the
method for manufacturing the LTPS TFT substrate according to the
present invention; and
[0055] FIG. 15 is a schematic view illustrating a seventh step of
the method for manufacturing the LTPS TFT substrate structure
according to the present invention and is also a schematic
cross-sectional view of the LTPS TFT substrate according to the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0056] To further expound the technical solution adopted in the
present invention and the advantages thereof, a detailed
description is given to a preferred embodiment of the present
invention and the attached drawings.
[0057] Referring to FIGS. 7-15, firstly, the present invention
provides a method for manufacturing a low-temperature
polycrystalline (LTPS) thin-film transistor (TFT) substrate, which
comprises the following steps:
[0058] Step 1: as shown in FIG. 8, providing a substrate 1 and
depositing a buffer layer 2 on the substrate 1.
[0059] The substrate 1 can be a regular transparent substrate and,
preferably, the substrate 1 is a glass substrate.
[0060] Specifically, the buffer layer 2 is formed of a material of
SiNx, SiOx, or a combination thereof.
[0061] Step 2: as shown in FIG. 9, depositing a thermally
conductive electrical insulation film on the buffer layer 2 and
patterning the thermally conductive electrical insulation film to
form a thermally conductive electrical insulation layer 3.
[0062] Specifically, the thermally conductive electrical insulation
layer 3 is formed of a material of Al.sub.2O.sub.3.
[0063] Preferably, the thermally conductive electrical insulation
layer 3 has a thickness of 30-50 nm.
[0064] Specifically, photolithographic and etching operations are
applied to pattern the thermally conductive electrical insulation
layer 3 in such a way that the thermally conductive electrical
insulation layer 3 has a size that corresponds to a size of a
polycrystalline silicon semiconductor layer 5 to be formed
later.
[0065] Step 3: as shown in FIG. 10, depositing an amorphous silicon
layer 4 on the buffer layer 2 in such a way that the amorphous
silicon layer 4 completely covers the thermally conductive
electrical insulation layer 3.
[0066] Preferably, the amorphous silicon layer 4 has a thickness of
200-300 nm.
[0067] Step 4: as shown in FIGS. 11 and 12, implanting a
predetermined amount of boron ions in the amorphous silicon layer 4
through ion implantation; subjecting the amorphous silicon layer 4
to rapid thermal annealing (RTA) to have the amorphous silicon
crystallized into polycrystalline silicon, and then applying an
etching operation to remove an electrically conductive layer
precipitating on a surface of the polycrystalline silicon during
crystallization to form a polycrystalline silicon layer 5.
[0068] Specifically, the RTA is conducted at a temperature of
650.degree. C.-700.degree. C. for a time period of 15-25
minutes.
[0069] Preferably, the electrically conductive layer that
precipitates on the surface of the polycrystalline silicon is
removed through etching by a thickness of 100-150 nm in order to
completely remove the electrically conductive layer with only the
structure of the polycrystalline silicon left.
[0070] Step 5: as shown in FIG. 13, patterning the polycrystalline
silicon layer 5 through photolithographic and etching operations to
form a polycrystalline silicon semiconductor layer 50.
[0071] Specifically, the pattern of the polycrystalline silicon
semiconductor layer 50 corresponds to the pattern of the thermally
conductive electrical insulation layer 3.
[0072] Step 6: as shown in FIG. 14, coating photoresist on the
polycrystalline silicon semiconductor layer 50 and conducting
exposure and development on the photoresist to form a photoresist
layer 55 on the polycrystalline silicon semiconductor layer 50 in
such a way that two end portions of the polycrystalline silicon
semiconductor layer 50 are exposed; implanting boron ions into the
two end portions of the polycrystalline silicon semiconductor layer
50 through ion implantation with the photoresist layer 55 serving
as a shielding layer so as to form source/drain contact zones
51.
[0073] Step 7: as shown in FIG. 15, peeling off the photoresist
layer 55 and forming, in sequence, a gate insulation layer 6, a
gate terminal 7, an interlayer insulation layer 8, and source/drain
terminals 9 on the polycrystalline silicon semiconductor layer 50,
wherein the source/drain terminals 9 are respectively connected to
the source/drain contact zones 51 at the two end portions of the
polycrystalline silicon semiconductor layer 50.
[0074] To this point, the manufacturing of the LTPS TFT substrate
is completed. Since the thermally conductive electrical insulation
layer 3 provides excellent properties of electrical insulation and
thermal conduction, during RTA, the thermally conductive electrical
insulation layer 3 quickly absorbs a great amount of heat that is
transferred to the amorphous silicon layer 4 in contact therewith
so that the portion of the amorphous silicon at this site shows an
increased efficiency of crystallization, whereby the grain size of
polycrystalline silicon of the polycrystalline silicon layer 5
formed in Step 4 is increased and grain boundaries are reduced and
thus the polycrystalline silicon semiconductor layer 50 formed in
Step 5 possesses bettered electrical property, helping improve the
mobility of charge carriers of a corresponding TFT device, reducing
the influence of leakage current by the gain boundaries, and
improving the electrical property of the TFT.
[0075] Referring to FIG. 15, the present invention also provides a
LTPS TFT substrate, which comprises a substrate 1, a buffer layer 2
arranged on the substrate 1, a thermally conductive electrical
insulation layer 3 arranged on the buffer layer 2, a
polycrystalline silicon semiconductor layer 50 arranged on the
thermally conductive electrical insulation layer 3, a gate
insulation layer 6 arranged on the buffer layer 2 and covering the
thermally conductive electrical insulation layer 3 and the
polycrystalline silicon semiconductor layer 50, a gate terminal 7
arranged on the gate insulation layer 6, an interlayer insulation
layer 8 arranged on the gate insulation layer 6 and covering the
gate terminal 7, and source/drain terminals 9 arranged on the
interlayer insulation layer 8.
[0076] The polycrystalline silicon semiconductor layer 50 has two
opposite end portions that are source/drain contact zones 51
implanted with boron ions; the gate insulation layer 6 and the
interlayer insulation layer 8 both have portions corresponding to
the source/drain contact zones 51 and formed with vias 91; and the
source/drain terminals 9 are respectively connected through the
vias 91 to the source/drain contact zones 51.
[0077] Specifically, the buffer layer 2 is formed of a material of
SiNx, SiOx, or a combination thereof.
[0078] Preferably, the thermally conductive electrical insulation
layer 3 is formed of a material of Al.sub.2O.sub.3. Specifically,
the gate insulation layer 6 is formed of a material of SiOx.
[0079] Preferably, the thermally conductive electrical insulation
layer 3 has a thickness of 30-50 nm.
[0080] Specifically, the thermally conductive electrical insulation
layer 3 has a pattern that corresponds to a pattern of the
polycrystalline silicon semiconductor layer 50.
[0081] In the above-described LTPS TFT substrate, the buffer layer
is provided thereon with the thermally conductive electrical
insulation layer at a location exactly under the polycrystalline
silicon semiconductor layer and the grain size of the
crystallization of the polycrystalline silicon is relatively large,
the grain boundaries are reduced in number, the mobility of charge
carriers of a TFT device is increased, and the electrical property
of the TFT is improved.
[0082] In summary, the present invention provides a method for
manufacturing a LTPS TFT substrate, in which a thermally conductive
electrical insulation layer having excellent properties of
electrical insulation and thermal conductivity is formed on the
buffer layer to quickly absorb a great amount of heat during a RTA
process to be transferred to an amorphous silicon layer in contact
therewith so that the portion of the amorphous silicon at this site
shows an increased efficiency of crystallization, whereby
polycrystalline silicon has an increased grain size and reduced
gain boundaries and thus the mobility of charge carriers of a
corresponding TFT device is increased and the influence of the
leakage current caused by grain boundary is reduced. The present
invention also provides an LTPS TFT substrate, in which a thermally
conductive electrical insulation layer is formed on a buffer layer
at a location exactly under the polycrystalline silicon
semiconductor layer and the grain size of the crystallization of
the polycrystalline silicon is relatively large, the grain
boundaries are reduced in number, the mobility of charge carriers
of a TFT device is increased, and the electrical property of the
TFT is improved.
[0083] Based on the description given above, those having ordinary
skills of the art may easily contemplate various changes and
modifications of the technical solution and technical ideas of the
present invention and all these changes and modifications are
considered within the protection scope of right for the present
invention.
* * * * *