U.S. patent application number 14/792591 was filed with the patent office on 2016-12-15 for semiconductor structure and manufacturing method thereof.
The applicant listed for this patent is United Microelectronics Corp.. Invention is credited to Li-Wei Feng, Nan-Yuan Huang, Jyh-Shyang Jenq, Chao-Hung Lin, Hon-Huei Liu, Shih-Hung Tsai.
Application Number | 20160365344 14/792591 |
Document ID | / |
Family ID | 57287849 |
Filed Date | 2016-12-15 |
United States Patent
Application |
20160365344 |
Kind Code |
A1 |
Feng; Li-Wei ; et
al. |
December 15, 2016 |
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
Abstract
The present invention provides a semiconductor structure,
including a substrate having a first fin structure and a second fin
structure disposed thereon, a first isolation region located
between the first fin structure and the second fin structure, a
second isolation region located opposite the first fin structure
from the first isolation region, and at least an epitaxial layer
disposed on the side of the first fin structure and the second fin
structure. The epitaxial layer has a bottom surface, the bottom
surface extending from the first fin structure to the second fin
structure, and the bottom surface is lower than a bottom surface of
the first isolation region and a top surface of the second
isolation region.
Inventors: |
Feng; Li-Wei; (Kaohsiung
City, TW) ; Tsai; Shih-Hung; (Tainan City, TW)
; Liu; Hon-Huei; (Kaohsiung City, TW) ; Lin;
Chao-Hung; (Changhua County, TW) ; Huang;
Nan-Yuan; (Tainan City, TW) ; Jenq; Jyh-Shyang;
(Pingtung County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
United Microelectronics Corp. |
Hsin-Chu City |
|
TW |
|
|
Family ID: |
57287849 |
Appl. No.: |
14/792591 |
Filed: |
July 6, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/42372 20130101;
H01L 29/7842 20130101; H01L 27/088 20130101; H01L 21/76224
20130101; H01L 21/823431 20130101; H01L 27/0886 20130101; H01L
29/0649 20130101; H01L 29/165 20130101; H01L 21/823481 20130101;
H01L 29/785 20130101; H01L 21/308 20130101; H01L 27/1211 20130101;
H01L 21/845 20130101; H01L 27/092 20130101 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 21/306 20060101 H01L021/306; H01L 21/762 20060101
H01L021/762; H01L 29/06 20060101 H01L029/06; H01L 21/8234 20060101
H01L021/8234 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 9, 2015 |
CN |
201510311627.3 |
Claims
1. A semiconductor structure, comprising: a substrate having a
first fin structure and a second fin structure disposed thereon; a
first isolation region located between the first fin structure and
the second fin structure; a second isolation region located
opposite the first fin structure from the first isolation region;
and at least an epitaxial layer disposed on the side of the first
fin structure and the second fin structure, wherein the epitaxial
layer has a bottom surface, the bottom surface extending from the
first fin structure to the second fin structure, and the bottom
surface is lower than a bottom surface of the first isolation
region and a top surface of the second isolation region, in
addition, the epitaxial layer has a stepped-shaped sidewall
profile.
2. The semiconductor structure of claim 1, further comprising at
least one gate structure crossing over the first fin structure and
the second fin structure.
3. The semiconductor structure of claim 2, wherein the gate
structure covers the first fin structure asymmetrically.
4. The semiconductor structure of claim 2, wherein at least one
gate structure comprises two epitaxial layers disposed on two sides
of the gate structure respectively, wherein the two epitaxial
layers have different volumes.
5. The semiconductor structure of claim 1, wherein the depth of the
second isolation region is larger than the depth of the first
isolation region.
6. The semiconductor structure of claim 1, wherein the bottom
surface of the epitaxial layer is a flat surface, and the epitaxial
layer further comprises two sidewalls.
7. The semiconductor structure of claim 6, wherein the angle
between the flat surface and one of the sidewall is larger than 90
degrees.
8. The semiconductor structure of claim 1, wherein the bottom
surface of the epitaxial layer has an angle.
9. A method for forming a semiconductor structure, comprising:
providing a substrate having a first fin structure and a second fin
structure disposed thereon; forming a first isolation region
located between the first fin structure and the second fin
structure; forming a second isolation region located opposite the
first fin structure from the first isolation region; and forming at
least an epitaxial layer disposed on the side of the first fin
structure and the second fin structure, wherein the epitaxial layer
has a bottom surface, the bottom surface extending from the first
fin structure to the second fin structure, and the bottom surface
is lower than a bottom surface of the first isolation region and a
top surface of the second isolation region, in addition, the
epitaxial layer has a stepped-shaped sidewall profile.
10. The method of claim 9, wherein the step for forming the first
fin structure and the second fin structure on the substrate
comprising: forming a plurality of third fins on the substrate;
forming a patterned hard mask on the substrate and covering parts
of each third fin; and performing an etching process to remove
parts of each third fin, after the etching process is performed,
the rest of the third fins being defined as the first fin structure
and the second fin structure.
11. The method of claim 10, further comprising forming at least one
gate structure crossing over the first fin structure and the second
fin structure.
12. The method of claim 11, wherein the step for forming the first
fin structure and the second fin structure is performed before the
step for forming the gate structure.
13. The method of claim 9, wherein after the first fin structure
and the second fin structure are formed on the substrate, the first
isolation region and the second isolation region are then formed in
the substrate.
14. The method of claim 9, wherein the depth of the second
isolation region is larger than the depth of the first isolation
region.
15. The method of claim 9, wherein the bottom surface of the
epitaxial layer is a flat surface, and the epitaxial layer further
comprises two sidewalls.
16. The method of claim 15, wherein the angle between the flat
surface and one of the sidewall is larger than 90 degrees.
17. The method of claim 9, wherein the bottom surface of the
epitaxial layer has an angle.
18. The method of claim 11, wherein the gate structure covers the
first fin structure asymmetrically.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a semiconductor structure and
fabrication method thereof, and more particularly, to a
semiconductor structure with better quality epitaxial layer.
[0003] 2. Description of the Prior Art
[0004] With the trend in the industry being towards scaling down
the size of the metal oxide semiconductor transistors (MOS),
three-dimensional or non-planar transistor technology, such as fin
field effect transistor technology (FinFET) has been developed to
replace planar MOS transistors. Since the three-dimensional
structure of a FinFET increases the overlapping area between the
gate and the fin-shaped structure of the silicon substrate, the
channel region can therefore be more effectively controlled. This
way, the drain-induced barrier lowering (DIBL) effect and the short
channel effect are reduced. The channel region is also longer for
an equivalent gate length, thus the current between the source and
the drain is increased. In addition, the threshold voltage of the
fin FET can be controlled by adjusting the work function of the
gate.
[0005] Nevertheless, conventional FinFET fabrication of forming
recesses after removing part of fin-shaped structures to
accommodate the growth of epitaxial layer typically causes the
fin-shaped structures to be lower than the surrounding shallow
trench isolation (STI) as a result of over-etching, thereby
influencing the formation of epitaxial layer afterwards. Hence, how
to improve the current FinFET fabrication process for resolving
this issue has become an important task in this field.
SUMMARY OF THE INVENTION
[0006] The present invention provides a semiconductor structure,
comprising a substrate having a first fin structure and a second
fin structure disposed thereon, a first isolation region located
between the first fin structure and the second fin structure, a
second isolation region located opposite the first fin structure
from the first isolation region, and at least an epitaxial layer
disposed on the side of the first fin structure and the second fin
structure, wherein the epitaxial layer has a bottom surface, the
bottom surface extending from the first fin structure to the second
fin structure, and the bottom surface is lower than a bottom
surface of the first isolation region and a top surface of the
second isolation region.
[0007] The present invention further provides a method for forming
a semiconductor structure, comprising: firstly, a substrate having
a first fin structure and a second fin structure disposed thereon
is provided, afterwards, a first isolation region located between
the first fin structure and the second fin structure is formed, a
second isolation region located opposite the first fin structure
from the first isolation region is also formed, and at least an
epitaxial layer disposed on the side of the first fin structure and
the second fin structure is then formed, wherein the epitaxial
layer has a bottom surface, the bottom surface extending from the
first fin structure to the second fin structure, and the bottom
surface is lower than a bottom surface of the first isolation
region and a top surface of the second isolation region.
[0008] The feature of the present invention is each fin structure
is partially removed during the process for forming the fin
structure, and the removed region is used for growing the epitaxial
layer. In this way, the quality of the epitaxial layer can be
increased, thereby improving the semiconductor device performance.
Besides, the epitaxial layer of the present invention contacts more
than one fin structure. In other words, the source/drain regions of
a plurality of transistors can be formed simultaneously, and
further improves the convenience of the process.
[0009] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1 to FIG. 8 are schematic diagrams showing a method for
fabricating a semiconductor structure according to a first
preferred embodiment of the present invention, wherein:
[0011] FIG. 1 to FIG. 5 are 3D schematic diagrams showing the
semiconductor structure according to a first preferred embodiment
of the present invention, and
[0012] FIG. 6 to FIG. 8 are cross section schematic diagrams
showing the semiconductor structure according to a first preferred
embodiment of the present invention.
[0013] FIG. 9 shows the cross section diagram of the semiconductor
structure according to another embodiment of the present
invention.
[0014] FIG. 10 shows the cross section diagram of the semiconductor
structure according to another embodiment of the present
invention.
DETAILED DESCRIPTION
[0015] To provide a better understanding of the present invention
to users skilled in the technology of the present invention,
preferred embodiments are detailed as follows. The preferred
embodiments of the present invention are illustrated in the
accompanying drawings with numbered elements to clarify the
contents and the effects to be achieved.
[0016] Please note that the figures are only for illustration and
the figures may not be to scale. The scale may be further modified
according to different design considerations. When referring to the
words "up" or "down" that describe the relationship between
components in the text, it is well known in the art and should be
clearly understood that these words refer to relative positions
that can be inverted to obtain a similar structure, and these
structures should therefore not be precluded from the scope of the
claims in the present invention.
[0017] FIG. 1 to FIG. 8 are schematic diagrams showing a method for
fabricating a semiconductor structure according to a first
preferred embodiment of the present invention. Please refer to FIG.
1. FIG. 1 is a schematic diagram showing a semiconductor structure
at the beginning of the fabrication process. As this stage, a
semiconductor structure having a substrate 100 and a plurality of
fin structures 112 disposed thereon is provided. In addition, the
substrate 100 may be chosen from semiconductor substrate such as a
bulk silicon substrate, a silicon containing substrate, a III-V
semiconductor-on-silicon (such as GaAs-on-silicon) substrate, a
graphene-on-silicon substrate, a silicon-on-insulator (SOI)
substrate, a silicon dioxide substrate, an aluminum oxide
substrate, a sapphire substrate, a germanium containing substrate
or an alloy of silicon and germanium substrate.
[0018] More precisely, the method for fabricating the fin-shaped
structures 112 may include the following processes, but not limited
thereto. First, a bulk substrate (not shown) is provided and a hard
mask layer (not shown) is formed thereon. The hard mask layer is
then patterned through a photolithographic and an etching process
(photo-etching process), so as to define the location for forming
fin structures 112 in the bulk substrate. Afterwards, an etching
process is performed to form fin structures 112 in the bulk
substrate. After the above processes, the fabrication method for
the fin structures 112 is complete. In this case, the fin
structures 112 may be regarded as protruding from the surface of
the substrate 100 and the compositions of the fin structures 112
and the substrate 100 may be the same, such as monocrystalline
silicon. In another case, when the substrate is chosen from a III-V
semiconductor-on-silicon substrate rather than the above-mentioned
bulk silicon substrate, the main compositions of the fin-shaped
structures may be the same as that of the III-V semiconductor and
differ from that of the underlying substrate.
[0019] As shown in FIG. 2, a photo-etching process P2 is then
performed, to remove parts of the fin structure 112, and so as to
form a plurality of fin structures 114 which are separated from
each other. More precisely, another hard mask (not shown) can be
formed on the substrate, and the hard mask preferably consists of a
plurality of strip-shaped photoresist patterns arranged parallel to
each other, wherein the extending direction of each strip-shaped
photoresist pattern is preferably perpendicular to the extending
direction of each fin structure 112. Therefore, after the etching
process is performed, each fin structure 112 will be segmented into
a plurality of fin structures 114 which are separated from each
other. It is noteworthy that in this step, the removing region of
the fin structure 112 is the region that an epitaxial layer will be
formed in the following steps. It will be described again in the
following paragraphs. In addition, in this step, parts of the fin
structure may be regarded as the dummy fin structure (such as the
dummy fin structure 112a shown in FIG. 2), and the dummy fin
structure 112a will not be etched.
[0020] Besides, in the method mentioned above, after the fin
structures 112 are formed, another photo-etching process P2 is then
formed to remove parts of the fin structures 112, so as to form the
fin structures 114. However, in another embodiment, after the
strip-shaped photoresist patterns are formed, an etching process
can be performed to remove parts of the photoresist patterns,
thereby forming a plurality of hard masks separated from each
other. Afterwards, another etching process is then performed, so as
to transfer the patterns of the rest of the hard masks to the
substrate 100, and the fin structure 114 shown in FIG. 2 can be
formed. This should also be within the scope of the present
invention. In addition, the hard masks mentioned above can be
formed on the substrate through a sidewalls image transfer (SIT)
process. It is a well-known technology and will not be redundantly
described here.
[0021] Next, a photoresist layer (not shown) is used as the hard
mask to perform a fin-cut process. As shown in FIG. 3, after the
fin-cut process P3 is performed, parts of the fin structure 112 and
parts of the substrate are removed, and the recess 116 is therefore
formed. Generally, the recess 116 will be filled in the isolation
layer in the following steps, so as to form shallow trench
isolation (STI). The region A1 which surrounded by the recess 116
can be defined as the active area of the semiconductor device,
namely the region comprising the semiconductor device such as
transistors disposed therein.
[0022] As shown in FIG. 4, a flat isolation layer 120 is entirely
formed on the substrate 110, covering each fin structure 114 and
also filling in the recess 116. The isolation layer 120 comprises
isolating materials such as silicon oxide or silicon nitride. It is
noteworthy that the thickness of the isolation layer 120 within the
active area A1 is smaller than the thickness of each fin structure
114. More precisely, in the present invention, the isolation layer
120 disposed between each of the fin structures 114 can be defined
as a first isolation region 122, and the isolation layer 120
disposed in the recess 116 can be defined as a second isolation
region 124, the depth D2 of the second isolation region 124 being
larger than the depth D1 of the first isolation region 122. In
addition, before the isolation layer 120 is formed, a liner can be
selectively formed between the substrate and the isolation layer
120, and it should also be within the scope of the present
invention.
[0023] As shown in FIG. 5, a plurality of gate structures 130 are
formed on the isolation layer 120 and cross over each fin structure
114. Each gate structure 130 includes a gate dielectric layer 132,
a gate conductive layer 134 and a cap layer 136. The material of
the gate dielectric layer 132 may include silicon oxide (SiO),
silicon nitride (SiN), silicon oxynitride (SiON), or a high-k
dielectric material having a dielectric constant (k value) larger
than 4 such as metallic oxide, such as hafnium oxide (HfO.sub.2),
hafnium silicon oxide (HfSiO.sub.4), hafnium silicon oxynitride
(HfSiON), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide
(La.sub.2O.sub.3), tantalum oxide (Ta.sub.2O.sub.5), yttrium oxide
(Y.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), strontium titanate
oxide (SrTiO.sub.3), zirconium silicon oxide (ZrSiO.sub.4), hafnium
zirconium oxide (HfZrO.sub.4), strontium bismuth tantalate
(SrBi.sub.2Ta2O.sub.9, SBT), lead zirconate titanate
(PbZrxTi.sub.1-xO.sub.3, PZT), barium strontium titanate
(BaxSr.sub.1-xTiO.sub.3, BST) or a combination thereof. The
material of the gate conductive layer 134 may include undoped
polysilicon, heavily doped polysilicon, or one or a plurality of
metal layers such as a work function metal layer, a barrier layer
and a low-resistance metal layer, etc. The cap layer 136 may
include a single-layer structure or multi-layer structure made of
dielectric materials such as silicon oxide (SiO), silicon nitride
(SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon
oxynitride (SiON) or a combination thereof. Besides, spacers should
also be comprised and disposed on two sides of the gate structure
130, but in order to simplify the figure, spacers are not shown in
FIG. 5, but it will be described in the following paragraphs and
shown in FIG. 6.
[0024] FIG. 6 show the cross section diagrams along the cross
section line A-A' and along the cross section line B-B' of FIG. 5
respectively. Please also refer to FIG. 5, the cross section
diagrams along the cross section line A-A' is the X-direction cross
section diagram, and the cross section diagrams along the cross
section line B-B' is the Y-direction cross section diagram. In
order to simplify the description, the following figures are shown
in cross section views, the relative position of each element can
be known by referring the FIGS. 5-6. In addition, the spacers 138
are shown in the Y-direction cross section diagram of FIG. 6.
[0025] FIG. 7 shows the cross section diagram of the present
invention after performing an epitaxial recess etching process. As
shown in FIG. 7, a patterned photoresist layer (not shown) is
formed on the isolation layer 120. The patterned photoresist layer
includes a plurality of openings, each opening disposed between two
adjacent gate structures 130, and afterwards, an etching process P4
is then performed, to form the recesses 140 on two sides of each
gate structure 130. During the process for etching the recess 140,
not only is the isolation layer 120 partially etched, but the fin
structure 114 and the substrate 110 may also be etched
simultaneously, or they will be etched in the following etching
processes, so the bottom surface 142 of the recess 140 may lower
than the top surface of the substrate 110 within the active area
A1. When viewed in Y-direction cross section diagram (along the
cross section line B-B'), the bottom surface 142 of the recess 140
is lower than the bottom surface of the fin structure 114. Besides,
when viewed in X-direction cross section diagram (along the cross
section line A-A'), the recess 140 has two sidewalls 144, the angle
t1 between the bottom surface 142 and the sidewall 144 is
preferably larger than 90 degrees, but not limited thereto. The
shapes of the recess can be adjusted according to actual
requirements.
[0026] Finally, FIG. 8 shows the cross section diagram of the
present invention after performing a selective epitaxy growing
process. As shown in FIG. 8, after the patterned photoresist layer
is removed, a selective epitaxy growing (SEG) process P5 is
performed to form an epitaxial layer 150 in the recess 140, and the
epitaxial layer 150 fills up the recess 140. It is well-known to
those skilled in the art that in the SEG process P5, the epitaxial
layer 150 is to grow along each surface of the recess 140.
Therefore, the epitaxial layer 150 has a bottom surface 152, and
the bottom surface 152 is lower than the top surface 120a of the
isolation layer 120 (it is also the top surface of the second
isolation region 124). Furthermore, the bottom surface 152 is also
lower than the bottom surface of the isolation layer 122 (please
also refer to FIG. 6). In addition, the angle between the flat
bottom surface 152 of the epitaxial layer 150 and the sidewall 154
is preferably larger than 90 degrees. It is noteworthy that the
epitaxial layer 150 disposed on sidewalls of each fin structure
114, and the bottom surface 152 at least extends through more than
two fin structures 114. In other words, the bottom surface 152 of
the epitaxial layer 150 disposed in the substrate 110, and the
epitaxial layer 150 directly contacts more than two fin structures
114.
[0027] In the embodiment mentioned above, the epitaxial layer 150
has a flat bottom surface 152. But in another embodiment of the
present invention, as shown in FIG. 9, which shows the cross
section diagram of the semiconductor structure according to another
embodiment of the present invention. In this embodiment, the bottom
surface 152a of the epitaxial layer 150a it is not a flat surface
and has an angle t2. It should also be within the scope of the
present invention.
[0028] In another embodiment, the epitaxial layer 150, 150a may
include a silicon-germanium epitaxial layer suited for a PMOS
transistor, or a silicon-carbide epitaxial layer suited for an NMOS
transistor, depending upon the electrical properties of the
Multi-gate MOSFET. The epitaxial layer 150,150a is formed in the
recess R, and grows conformally along the shape of the recess R,
therefore having a hexagon-shaped profile structure. Thereafter, an
ion implantation process may be performed to dope impurities, or
impurities may be doped while performing the SEG process P5, so
that the epitaxial layer 150 can be used as a source/drain region.
After the epitaxial layer 150 is formed, a silicide process (or a
salicide process, not shown) may be performed to form silicide in
the source/drain region, wherein the silicide process may include a
post clean process, a metal depositing process, an annealing
process, a selective etching process, or a test process, etc.
Thereafter, other processes may be performed after the silicide
process is performed.
[0029] FIG. 10 shows the cross section diagram of the semiconductor
structure according to another embodiment of the present invention.
In this embodiment, the substrate 210 comprises a plurality of fin
structures 214 and a plurality of gate structures 230 disposed
thereon, each gate structure 230 includes the cap layer 236
disposed on the top of the gate structure 230, and the spacers 238
disposed on two sidewalls of the gate structure 230. In addition,
the epitaxial layers 250 are disposed on two sides of every gate
structure 230. The differences between FIG. 10 and the Y-axis
direction cross section of FIG. 8 is that in this embodiment, since
some overlay errors may occur during the process, a misalignment
will exist between the gate structure 230 and the fin structure
214, and the gate structure 230 will be shifted towards a specific
direction. In this case, the middle line M of one fin structure 214
is regarded as the symmetry axis, and each fin structure 214 is
covered by the gate structure 230 asymmetrically. In other words,
the distances between the central point of the gate structure 230
and two ends of the fin structure 214 are labeled as "a" and "b"
respectively, and the value a and value b are different. Therefore,
the two epitaxial layers 250 disposed on two sides of the gate
structure 230 (especially the gate structure disposed near the
edges of the active area) may have different volumes.
[0030] Besides, after the gate structure 230 are completed, and
during the process for forming the epitaxial recess through an
etching process, a photoresist layer (not shown) will firstly
formed, the opening of the photoresist layer may be larger than the
gap between every two adjacent gate structure 230, so as to perform
a self-aligned etching by using the spacer 238 of the gate
structure 230 and/or the cap layer 236. Therefore during the
process mentioned above, partial sidewall of the fin structure 214
may also be removed, and the fin structure 214 will have a
stepped-shaped sidewall profile, since the epitaxial layer 250
grows along each surface of the recess, so the epitaxial layer 250
will also have a stepped-shaped sidewall profile (such as the angle
t3 shown in FIG. 10). Besides, the first embodiment of the present
invention mentioned above may also include the stepped-shaped
sidewall profile of this embodiment, and will not be described
again.
[0031] The feature of the present invention is each fin structure
is partially removed during the process for forming the fin
structure, and the removed region is used for growing the epitaxial
layer. In this way, the quality of the epitaxial layer can be
increased, thereby improving the semiconductor device performance.
Besides, the epitaxial layer of the present invention contacts more
than one fin structure. In other words, the source/drain regions of
a plurality of transistors can be formed simultaneously, and
further improves the convenience of the process.
[0032] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *