U.S. patent application number 15/226931 was filed with the patent office on 2016-11-24 for pixel array.
This patent application is currently assigned to E Ink Holdings Inc.. The applicant listed for this patent is E Ink Holdings Inc.. Invention is credited to Chi-Ming Wu, Shu-Ping Yan.
Application Number | 20160342059 15/226931 |
Document ID | / |
Family ID | 50824594 |
Filed Date | 2016-11-24 |
United States Patent
Application |
20160342059 |
Kind Code |
A1 |
Wu; Chi-Ming ; et
al. |
November 24, 2016 |
PIXEL ARRAY
Abstract
A pixel array includes multiple scan lines, multiple gate lines,
multiple data lines and multiple pixel structures. The scan lines
are disposed on a substrate. The gate lines intersect with the scan
lines to demarcate multiple first unit regions and multiple second
unit regions. Each gate line electrically connects to one of the
scan lines. The data lines intersect with the scan lines and pass
through the first unit regions. Each data line is located between
two adjacent gate lines. The pixel structures are disposed on the
first unit regions. Each pixel structure includes an active device
and a pixel electrode. The active device is driven by one
corresponding scan line and connects with one corresponding data
line. An orthographic projection of each pixel electrode on the
substrate is non-overlapped with or incompletely overlapped with an
orthographic projection of the corresponding gate lines on the
substrate.
Inventors: |
Wu; Chi-Ming; (Hsinchu,
TW) ; Yan; Shu-Ping; (Hsinchu, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
E Ink Holdings Inc. |
Hsinchu |
|
TW |
|
|
Assignee: |
E Ink Holdings Inc.
Hsinchu
TW
|
Family ID: |
50824594 |
Appl. No.: |
15/226931 |
Filed: |
August 3, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14071662 |
Nov 5, 2013 |
9436046 |
|
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15226931 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G02F 2201/123 20130101;
G02F 1/13306 20130101; G02F 1/136213 20130101; G02F 1/136286
20130101; G02F 1/134336 20130101; G02F 1/134309 20130101; H01L
27/124 20130101 |
International
Class: |
G02F 1/1362 20060101
G02F001/1362; G02F 1/133 20060101 G02F001/133; H01L 27/12 20060101
H01L027/12; G02F 1/1343 20060101 G02F001/1343 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 5, 2012 |
TW |
101145706 |
Claims
1. A pixel array, disposed on a substrate, the pixel array
comprising: a plurality of first signal lines arranged in parallel;
a plurality of second signal lines arranged in parallel and
intersecting with the first signal lines to demarcate a plurality
of first unit regions and a plurality of second unit regions,
wherein each of the second signal lines electrically connects to
one of the first signal lines, the second signal lines are arranged
in different pitches, and an area of each of the second unit
regions is smaller than an area of each of the first unit regions,
and the first unit regions and the second unit regions are
alternately arranged; a plurality of third signal lines
intersecting with the first signal lines and passing through the
first unit regions, wherein each of the third signal lines is
located between two of the adjacent second signal lines; and a
plurality of pixel structures disposed on the first unit regions,
each of the pixel structures comprising an active device and a
pixel electrode connecting with the active device, the active
device being driven by a corresponding third signal line and
connecting with a corresponding first signal line, wherein an
orthographic projection of each of the pixel electrodes on the
substrate is non-overlapped with or incompletely overlapped with an
orthographic projection of the corresponding second signal lines on
the substrate.
2. The pixel array as recited in claim 1, wherein an extending
direction of the plurality of second signal lines is parallel to an
extending direction of the plurality of third signal lines.
3. The pixel array as recited in claim 1, wherein the second signal
lines and the first signal lines are composed of different film
layers, and the second signal lines and the third signal lines are
composed of a same film layer.
4. The pixel array as recited in claim 1, further comprising a
contact hole, electrically connecting to each of the second signal
lines and one of a corresponding first signal lines.
5. The pixel array as recited in claim 1, wherein the pixel
electrodes extend to the second unit regions and the two adjacent
pixel electrodes in the longitudinal direction are in an interlaced
arrangement.
6. The pixel array as recited in claim 5, wherein an area of each
of the pixel electrodes is greater than an area of each of the
first unit regions.
7. The pixel array as recited in claim 1, wherein an area of each
of the pixel electrodes is smaller than the area of each of the
first unit regions.
8. The pixel array as recited in claim 1, wherein each of the pixel
electrodes comprises a first pixel electrode portion, a second
pixel electrode portion, a third pixel electrode portion, a first
pixel electrode connecting portion and a second pixel electrode
connecting portion, the first pixel electrode portion is located
between the second electrode portion and the third pixel electrode
portion, the first pixel electrode portion is located in the first
unit region, and the second pixel electrode portion and the third
pixel electrode portion are respectively located in the plurality
of second unit regions adjacent to two sides of the first unit
region, the first pixel electrode connecting portion connects the
first pixel electrode portion and the second pixel electrode
portion, and the second pixel electrode connecting portion connects
the first pixel electrode portion and the third pixel electrode
portion.
9. A pixel array, disposed on a substrate, the pixel array
comprising: a plurality of first signal lines arranged in parallel;
a plurality of second signal lines arranged in parallel and
intersecting with the first signal lines to demarcate a plurality
of first unit regions and a plurality of second unit regions,
wherein each of the second signal lines electrically connects to
one of the first signal lines, the second signal lines are arranged
in different pitches, and an area of each of the second unit
regions is smaller than an area of each of the first unit regions,
and the first unit regions and the second unit regions are
alternately arranged; a plurality of third signal lines
intersecting with the first signal lines and passing through the
first unit regions, wherein each of the third signal lines is
located between two of the adjacent second signal lines; and a
plurality of pixel structures disposed on the first unit regions,
each of the pixel structures comprising an active device and a
pixel electrode connecting with the active device, wherein an
orthographic projection of each of the pixel electrodes on the
substrate is non-overlapped with or incompletely overlapped with an
orthographic projection of the corresponding second signal lines on
the substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation application of and claims
the priority benefit of a prior application Ser. No. 14/071,662,
filed on Nov. 5, 2013, now allowed. The prior application Ser. No.
14/071,662 claims the priority benefit of Taiwan application serial
no. 101145706, filed on Dec. 5, 2012. The entirety of each of the
above-mentioned patent applications is hereby incorporated by
reference herein and made a part of this specification.
BACKGROUND
[0002] 1. Field of the Invention
[0003] The invention relates to a display array. More particularly,
the invention relates to a pixel array.
[0004] 2. Description of Related Art
[0005] Generally speaking, a liquid crystal display panel is mainly
composed of an active device matrix substrate, an opposite
substrate and a liquid crystal layer sandwiched between the active
device matrix substrate and the opposite substrate. The active
device matrix substrate can be divided into a display region and a
non-display region. A plurality of pixel units arranged as a matrix
is disposed on the display region, and each of the pixel units
includes a thin film transistor (TFT) and a pixel electrode
connecting to the TFT. Additionally, a plurality of scan lines and
a plurality of data lines are disposed in the display region, and
the TFT of each of the pixel units is electrically connected to the
corresponding scan lines and data lines. The signal lines, the
source drivers and the gate drivers are disposed in the non-display
region.
[0006] When the liquid crystal display panel is about to display
image frames, the liquid crystal display panel has to turn on the
pixels of each row in a display panel sequentially through the gate
drivers, and the pixels of each row correspondingly receive data
voltage provided by the source drivers within a turn-on time.
Accordingly, the liquid crystal molecules of pixels of each row
will be properly arranged based on the received data voltage.
However, with enhanced resolution of the liquid crystal display
panel, the liquid crystal display apparatus has to increase numbers
of the gate drivers and the source drivers so as to match the
enhancement of resolution, and an area of an non-display region (or
border lines) is getting greater due to increased numbers of the
gate drivers and the source drivers. Based on the above reasons,
production costs of the liquid crystal display apparatus increase
when numbers of the gate drivers and the source drivers increase,
and in the meantime, border lines also gets wider and wider. If
numbers of the gate drivers and/or the source drivers can be
reduced, an issue that costs cannot be reduced can be easily solved
and border lines will be narrower, which means a product with a
smaller area of a non-display region can be manufactured.
SUMMARY OF THE INVENTION
[0007] The invention provides a pixel array to mitigate the mura
phenomenon of a display panel.
[0008] The invention provides a pixel array adapted to be disposed
on a substrate. The pixel array includes a plurality of scan lines,
a plurality of gate lines, a plurality of data lines and a
plurality of pixel structures. The scan lines are disposed on the
substrate and arranged in parallel. The gate lines are arranged in
parallel and intersect with the scan lines to demarcate a plurality
of first unit regions and a plurality of second unit regions. Each
gate line electrically connects to one of the scan lines, and an
area of each second unit region is smaller than an area of each
first unit region, and the first unit region and the second unit
region are alternately arranged in a longitudinal direction. The
data lines intersect with the scan lines and pass through the first
unit regions, wherein each data line is located between two of the
adjacent gate lines. The pixel structures are disposed on the first
unit regions. Each pixel structure includes an active device and a
pixel electrode connecting with the active device. The active
device is driven by one corresponding scan line and connects with
one corresponding data line. An orthographic projection of each
pixel electrode on the substrate is non-overlapped with or
incompletely overlapped with an orthographic projection of the
corresponding gate lines on the substrate.
[0009] In an embodiment of the invention, an extending direction of
the gate lines is parallel to an extending direction of the data
lines.
[0010] In an embodiment of the invention, the gate lines and the
scan lines are composed of different film layers, and the gate
lines and the data lines are composed of a same film layer.
[0011] In an embodiment of the invention, the pixel array further
includes a contact hole that electrically connects each gate line
and one of the corresponding scan lines.
[0012] In an embodiment of the invention, each of the pixel
electrodes extends and covers another corresponding scan line to
form a storage capacitor.
[0013] In an embodiment of the invention, the pixel electrodes
extend to the second unit regions and two adjacent pixel electrodes
in a longitudinal direction are in an interlaced arrangement.
[0014] In an embodiment of the invention, an area of each of the
pixel electrodes is greater than an area of each of the first unit
regions.
[0015] In an embodiment of the invention, an area of each of the
pixel electrodes is smaller than an area of each of the first unit
regions.
[0016] In an embodiment of the invention, each of the pixel
electrodes includes a first pixel electrode portion, a second pixel
electrode portion, a third pixel electrode portion, a first pixel
electrode connecting portion and a second pixel electrode
connecting portion. The first pixel electrode portion is located
between the second pixel electrode portion and the third pixel
electrode portion. The first pixel electrode portion is located in
the first unit region, and the second pixel electrode portion and
the third pixel electrode portion are located in the second unit
regions that are adjacent to two sides of the first unit regions,
respectively. The first pixel electrode connecting portion connects
the first pixel electrode portion and the second pixel electrode
portion, and the second pixel electrode connecting portion connects
the first pixel electrode portion and the third pixel electrode
portion.
[0017] In an embodiment of the invention, an area of the first
pixel electrode portion is greater than an area of the second pixel
electrode portion and an area of the third pixel electrode portion.
Orthographic projections of the first pixel electrode connecting
portion and the second pixel electrode connecting portion on the
substrate are partially overlapped with orthographic projections of
the corresponding gate lines on the substrate.
[0018] Accordingly, since the orthographic projections of pixel
electrodes on the substrate in the embodiments of the invention are
non-overlapped with or incompletely overlapped with the
orthographic projections of the corresponding gate lines on the
substrate, a coupling effect can be reduced between the gate lines
and the pixel electrodes with a design of the pixel array of the
embodiments of the invention. Additionally, when the pixel array is
further applied to a display panel, the mura phenomenon on the
display panel can be substantially reduced and the display panel
may have better display quality.
[0019] In order to make the aforementioned features and advantages
of the invention more comprehensible, embodiments accompanied with
figures are described in details below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings are included to provide a further
understanding of the disclosure, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the disclosure and, together with the description,
serve to explain the principles of the invention.
[0021] FIG. 1 illustrates a schematic view of a pixel array
according to an embodiment of the invention.
[0022] FIG. 2 illustrates a schematic view of a pixel array
according to another embodiment of the invention.
[0023] FIG. 3 illustrates a schematic view of a pixel array
according to yet another embodiment of the invention.
DESCRIPTION OF EMBODIMENTS
[0024] FIG. 1 illustrates a schematic view of a pixel array
according to an embodiment of the invention. Referring to FIG. 1,
in the present embodiment, a pixel array 100a is adapted to be
disposed on a substrate 10. The pixel array 100a includes a
plurality of scan lines 110a, 110b and 110c, a plurality of gate
lines 120a and 120b, a plurality of data lines 130a and 130b, and a
plurality of pixel structures 140a and 140b.
[0025] Specifically, the scan lines 110a, 110b and 110c are
disposed on the substrate 10 and are arranged in parallel. The gate
lines 120a and 120b are arranged in parallel and intersect with the
scan lines 110a, 110b and 110c to demarcate a plurality of first
unit regions D1 and a plurality of second unit regions D2. Each of
the gate lines 120a and 120b electrically connects to one of the
scan lines 110a, 110b and 110c, and an area of each of the second
unit regions D2 is smaller than an area of each of the first unit
regions D1, and the first unit regions D1 and the second unit
regions D2 are alternately arranged in a longitudinal direction P.
The data lines 130a and 130b intersect with the scan lines 110a,
110b and 110c and pass through the first unit regions D1, wherein
each of the data lines 130a and 130b is located between two
adjacent gate lines 120a and 120b. The pixel structures 140a and
140b are disposed on the first unit regions D1, and each pixel
structure 140a (or 140b) includes an active device 142a (or 142b)
and a pixel electrode 144a (or 144b) connecting with the active
device 142a (or 142b). The active device 142a (or 142b) is driven
by one corresponding scan line 110b (or 110c) and connects with one
corresponding data line 130a. An orthographic projection of each
pixel electrode 144a (or 144b) on the substrate 10 is incompletely
overlapped with an orthographic projection of the corresponding
gate lines 120a and 120b on the substrate 10.
[0026] More specifically, in the present embodiment, an extending
direction of the gate lines 120a and 120b is substantially parallel
to an extending direction of the data lines 130a and 130b. The gate
lines 120a and 120b and the scan lines 110a, 110b and 110c are
composed of different film layers, and the gate lines 120a and 120b
and the data lines 130a and 130b are composed of a same layer.
Herein, the gate lines 120a and 120b are arranged in different
pitches G1, G2. As shown in FIG. 1, the gate line 120b and the two
adjacent gate lines 120a have different pitches G1, G2. Therefore,
the first unit regions D1 and the second unit regions D2 defined by
the gate lines 120a and 120b and the scan lines 110a, 110b and 110c
have different areas.
[0027] Moreover, in the present embodiment, the pixel array 100a
further includes a contact hole C, wherein the contact hole C
electrically connects each gate line 120b and one of the
corresponding scan lines 110b. In other words, the gate line 120b
drives the scan line 110b through the contact hole C for the
corresponding data line 130a to write a data signal into the pixel
structure 140a. Additionally, in the present embodiment, each pixel
electrode 144a (or 144b) further extends and covers another
corresponding scan line 110a (or 110b) to form a storage capacitor
Cst1 (or Cst2). When the pixel array 100a of the present embodiment
is further applied to a display panel (not illustrated here), the
display panel can maintain excellent display quality.
[0028] Specifically, the pixel electrodes 144a and 144b extends to
the second unit regions D2, and the two adjacent pixel electrodes
144a and 144b in the longitudinal direction P are in an interlaced
arrangement. An area of each pixel electrode 144a and 144b is
substantially greater than an area of each first unit region D1. As
shown in FIG. 1, the pixel electrode 144a overlaps with the gate
line 120a, but does not overlap with the gate line 120b.
Consequently, when the gate line 120b drives the scan line 110b
through the contact hole C, the gate line 120b and the pixel
electrode 144a do not have a coupling effect. For this reason, when
the pixel array 100a of the present embodiment is further applied
to a display panel (not illustrated here), the display panel may
have better display quality, rather than having the mura phenomenon
on the display panel caused by pressure difference generated
between pixel electrodes due to the conventional coupling
effect.
[0029] It should be noted that the reference numerals and a part of
the contents in the aforementioned embodiment are used in the
following embodiments, in which identical reference numerals are
adopted to represent identical or similar components, and repeated
descriptions of the same technical contents are omitted. For
detailed descriptions of the omitted parts, a reference can be
found in the aforementioned embodiment, and repeated descriptions
thereof are omitted in the following embodiments.
[0030] FIG. 2 illustrates a schematic view of a pixel array
according to another embodiment of the present invention. Referring
to FIG. 1 and FIG. 2 together, a pixel array 100b of FIG. 2 is
similar to the pixel array 100a of FIG. 1, while the main
difference therebetween lies in that an area of each pixel
electrode 144c of the pixel array 100b in the present embodiment is
smaller than an area of each first unit region D1, and two adjacent
pixel electrodes 140c in a longitudinal direction P are arranged in
a straight line.
[0031] Since the area of each pixel electrode 144c of the present
embodiment is smaller than the area of each first unit region D,
that means the pixel electrode 144c of the present embodiment is
exclusively disposed inside the first unit regions D1. In other
words, an orthographic projection of each pixel electrode 144c on
the substrate 10 is not overlapped with orthographic projections of
the corresponding gate lines 120a and 120b on the substrate 10.
Therefore, when the gate line 120b drives the scan line 110b
through the contact hole C, the gate line 120b and the pixel
electrode 144c therebetween do not have a coupling effect. For this
reason, when the pixel array 100b of the present embodiment is
further applied to a display panel (not illustrated here), the
display panel may have better display quality, rather than having
mura phenomenon on the display panel caused by pressure difference
generated between pixel electrodes due to the conventional coupling
effect.
[0032] FIG. 3 illustrates a schematic view of a pixel array
according to yet another embodiment of the invention. First,
referring to FIG. 1 and FIG. 3 together, a pixel array 100c of FIG.
3 is similar to the pixel array 100a of FIG. 1, while the main
difference therebetween lies in that each pixel electrode 140d of
the pixel array 100c in the present embodiment includes a first
pixel electrode portion 145d, a second pixel electrode portion
146d, a third pixel electrode portion 147d, a first pixel electrode
connecting portion 148d and a second pixel electrode connecting
portion 149d. The first pixel electrode portion 145d is disposed
between the second pixel electrode portion 146d and the third pixel
electrode portion 147d. The first pixel electrode portion 145d is
disposed inside the first unit region D1, and the second pixel
electrode portion 146d and the third pixel electrode portion 147d
are disposed inside the second unit region D2 adjacent to two sides
of the first unit region D1, respectively. The first pixel
electrode connecting portion 148d connects the first pixel
electrode portion 145d and the second pixel electrode portion 146d,
and the second pixel electrode connecting portion 149d connects the
first pixel electrode portion 145d and the third pixel electrode
147d.
[0033] Furthermore, an area of the first pixel electrode portion
145d of the present embodiment is greater than an area of the
second pixel electrode portion 146d and an area of the third pixel
electrode portion 147d. An area of each pixel electrode 140d is
substantially greater than an area of each first unit region D1.
Orthographic projections of the first pixel electrode connecting
portion 148d and the second pixel electrode connecting portion 149d
on the substrate 10 is partially overlapped with orthographic
projections of the corresponding gate lines 120a and 120b on the
substrate 10. Since the orthographic projections of the first pixel
electrode connecting portion 148d and the second pixel electrode
connecting portion 149d of the pixel electrode 140d of the present
embodiment on the substrate 10 is overlapped only in a small part
with the orthographic projections of the corresponding gate lines
120a and 120b on the substrate 10, when the gate line 120b drives
the scan line 110b through the contact hole C, a design of the
pixel array 100c of the present embodiment can reduce a coupling
effect between the gate line 120a and the pixel electrode 140d. For
this reason, when the pixel array 100c of the present embodiment is
further applied to a display panel (not illustrated here), the mura
phenomenon on the display panel caused by pressure difference
generated between pixel electrodes due to the conventional coupling
effect can be substantially reduced and the display panel may have
better display quality.
[0034] Accordingly, since the orthographic projections of the pixel
electrodes on the substrate in the embodiments of the invention are
non-overlapped with or incompletely overlapped with the
orthographic projections of the corresponding gate lines on the
substrate, a coupling effect can be reduced between the gate lines
and the pixel electrodes with a design of the pixel array of the
embodiments of the invention. Additionally, when the pixel array is
further applied to a display panel, the mura phenomenon on the
display panel caused by pressure difference generated between the
pixel electrodes due to the conventional coupling effect can be
substantially reduced and the display panel may have better display
quality.
[0035] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
disclosed embodiments without departing from the scope or spirit of
the invention. In view of the foregoing, it is intended that the
disclosure cover modifications and variations of this specification
provided they fall within the scope of the following claims and
their equivalents.
* * * * *