U.S. patent application number 15/204084 was filed with the patent office on 2016-10-27 for display device and electronic device.
The applicant listed for this patent is Semiconductor Energy Laboratory Co., Ltd.. Invention is credited to Jun KOYAMA, Toru TANABE.
Application Number | 20160315202 15/204084 |
Document ID | / |
Family ID | 47141291 |
Filed Date | 2016-10-27 |
United States Patent
Application |
20160315202 |
Kind Code |
A1 |
KOYAMA; Jun ; et
al. |
October 27, 2016 |
DISPLAY DEVICE AND ELECTRONIC DEVICE
Abstract
An object is, in a structure where switch circuits in a signal
line driver circuit is placed over the same substrate as a pixel
portion, to reduce the size of transistors in the switch circuits
and to reduce load in the circuits during charging and discharging
of signal lines due to the supply of data. A display device is
provided which includes a pixel portion receiving a video signal,
and a signal line driver circuit including a switch circuit portion
configured to control output of the video signal to the pixel
portion. The switch circuit portion includes a transistor over an
insulating substrate. The transistor has a field-effect mobility of
at least 80 cm.sup.2/Vs or more. The transistor includes an oxide
semiconductor layer.
Inventors: |
KOYAMA; Jun; (Sagamihara,
JP) ; TANABE; Toru; (Atsugi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Semiconductor Energy Laboratory Co., Ltd. |
Atsugi-shi |
|
JP |
|
|
Family ID: |
47141291 |
Appl. No.: |
15/204084 |
Filed: |
July 7, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13466635 |
May 8, 2012 |
9397222 |
|
|
15204084 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/1225 20130101;
H01L 27/1244 20130101; H01L 27/127 20130101; H01L 29/78696
20130101; H01L 29/24 20130101; H01L 29/7869 20130101 |
International
Class: |
H01L 29/786 20060101
H01L029/786; H01L 27/12 20060101 H01L027/12; H01L 29/24 20060101
H01L029/24 |
Foreign Application Data
Date |
Code |
Application Number |
May 13, 2011 |
JP |
2011-108664 |
Claims
1. (canceled)
2. A display device comprising: a pixel portion; and a signal line
driver circuit configured to drive the pixel portion, the signal
line driver circuit comprising a switch circuit portion, wherein
the switch circuit portion comprises a transistor, wherein the
transistor has a field-effect mobility of 80 cm.sup.2/Vs or more,
and wherein the transistor comprises an oxide semiconductor layer
comprising In, Sn, and Zn.
3. The display device according to claim 2, wherein the transistor
has the field-effect mobility of 120 cm.sup.2/Vs or more.
4. The display device according to claim 2, wherein the transistor
further comprises: a source electrode and a drain electrode which
are electrically connected to the oxide semiconductor layer; a gate
electrode; and a gate insulating film between the oxide
semiconductor layer and the gate electrode.
5. The display device according to claim 2, wherein a concentration
of hydrogen in the oxide semiconductor layer is lower than
5.times.10.sup.19 cm.sup.-3.
6. The display device according to claim 2, wherein a concentration
of sodium in the oxide semiconductor layer is lower than
5.times.10.sup.16 cm.sup.-3, wherein a concentration of lithium in
the oxide semiconductor layer is lower than 5.times.10.sup.15
cm.sup.-3, and wherein a concentration of potassium in the oxide
semiconductor layer is lower than 5.times.10.sup.15 cm.sup.-3.
7. A display device comprising: a pixel portion; and a signal line
driver circuit configured to drive the pixel portion, the signal
line driver circuit comprising a switch circuit portion, wherein
the switch circuit portion comprises at least a first transistor, a
second transistor, and a third transistor, wherein each of the
first transistor, the second transistor, and the third transistor
has a field-effect mobility of 80 cm.sup.2/Vs or more, wherein each
of the first transistor, the second transistor, and the third
transistor comprises an oxide semiconductor layer comprising In,
Sn, and Zn, wherein a gate of the first transistor is electrically
connected to a sampling signal output circuit through a first
wiring, wherein a gate of the second transistor is electrically
connected to the sampling signal output circuit through a second
wiring, wherein a gate of the third transistor is electrically
connected to the sampling signal output circuit through a third
wiring, wherein one of a source and a drain of the first transistor
is electrically connected to a first pixel through a fourth wiring,
wherein one of a source and a drain of the second transistor is
electrically connected to a second pixel through a fifth wiring,
wherein one of a source and a drain of the third transistor is
electrically connected to a third pixel through a sixth wiring, and
wherein the other of the source and the drain of the first
transistor, the other of the source and the drain of the second
transistor, and the other of the source and the drain of the third
transistor are electrically connected to a video signal output
circuit through a seventh wiring.
8. The display device according to claim 7, wherein each of the
first transistor, the second transistor, and the third transistor
has the field-effect mobility of 120 cm.sup.2/Vs or more.
9. The display device according to claim 7, wherein each of the
first transistor, the second transistor, and the third transistor
further comprises: a source electrode and a drain electrode which
are electrically connected to the oxide semiconductor layer; a gate
electrode; and a gate insulating film between the oxide
semiconductor layer and the gate electrode.
10. The display device according to claim 7, wherein a
concentration of hydrogen in the oxide semiconductor layer is lower
than 5.times.10.sup.19 cm.sup.-3.
11. The display device according to claim 7, wherein a
concentration of sodium in the oxide semiconductor layer is lower
than 5.times.10.sup.16 cm.sup.-3, wherein a concentration of
lithium in the oxide semiconductor layer is lower than
5.times.10.sup.15 cm.sup.-3, and wherein a concentration of
potassium in the oxide semiconductor layer is lower than
5.times.10.sup.15 cm.sup.-3.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a display device and an
electronic device including the display device.
[0003] 2. Description of the Related Art
[0004] With the widespread use of large display devices such as
liquid crystal televisions, display devices are required to be
higher-value-added and thus are under development. Particularly, a
technique to form a driver circuit or part of a driver circuit over
a substrate, where a pixel portion is formed, using thin film
transistors (TFTs) whose channel region is formed using an
amorphous semiconductor or a microcrystalline semiconductor is
actively developed because the technique greatly helps a reduction
in cost and improvement in reliability.
[0005] Instead of forming a signal line driver circuit (a source
driver) over a substrate where a pixel portion is formed, in a
display device using transistors whose channel regions are formed
using an amorphous semiconductor or a microcrystalline
semiconductor, by using a technique called COG (chip on glass) or
COF (chip on film), a video signal is input from a driving IC
through connection terminals which are provided as many as signal
lines. The number of the connection terminals which are provided as
many as the signal lines is increased as the number of the signal
lines is increased, which causes a rise of cost. Patent Document 1
discloses a structure in which three analog switches are provided
for signal lines in a signal line driver circuit and are provided
over the same substrate as a pixel portion and one horizontal
scanning period has three writing periods.
[0006] In recent years, display devices in which light emitting
elements such as EL elements are driven (EL display devices) have
been actively developed. Patent Document 2 discloses a structure of
a pixel circuit in which the number of transistors provided in a
pixel is reduced and variations in threshold voltage and
field-effect mobility between the transistors can be
compensated.
REFERENCE
Patent Document
[Patent Document 1] Japanese Published Patent Application No.
2004-309949
[Patent Document 2] Japanese Published Patent Application No.
2007-310311
SUMMARY OF THE INVENTION
[0007] Like liquid crystal displays the size of which has been
already increased, EL display devices will probably be put under
development aimed at increasing panel size. With an increase in
panel size, the number of pieces of data input to signal lines is
increased. Possible solutions to this problem include a structure
in which the number of pieces of data sampled during one horizontal
scan period is increased by providing analog switches, which are
switch circuits, in a signal line driver circuit as described in
Patent Document 1.
[0008] However, in the case where the analog switch is placed over
the same substrate as the pixel portion, if a transistor used as
the analog switch has a channel region of an amorphous
semiconductor or a microcrystalline semiconductor, the transistor
has insufficient field-effect mobility. Therefore, the channel
width of the transistor is necessarily increased in order to
increase the amount of the current flowing through the transistor.
This increases the area of the transistor and the percentage of the
load due to the transistor in the circuit.
[0009] An object of one embodiment of the present invention is, in
a structure where switch circuits in a signal line driver circuit
is placed over the same substrate as a pixel portion, to reduce the
size of transistors in the switch circuits and to reduce load in
the circuits during charging and discharging of signal lines due to
the supply of data.
[0010] One embodiment of the present invention is a display device
including a pixel portion receiving a video signal, and a signal
line driver circuit including a switch circuit portion configured
to control output of the video signal to the pixel portion. The
switch circuit portion includes a transistor over an insulating
substrate. The transistor has a field-effect mobility of at least
80 cm.sup.2/Vs or more. The transistor includes an oxide
semiconductor layer.
[0011] In a display device according to one embodiment of the
present invention, the transistor preferably has a field-effect
mobility of 120 cm.sup.2/Vs or more.
[0012] In a display device according to one embodiment of the
present invention, the pixel portion preferably includes a pixel
provided with a transistor including an oxide semiconductor
layer.
[0013] In a display device according to one embodiment of the
present invention, the oxide semiconductor layer preferably
includes at least a channel formation region overlapping with a
gate electrode layer with a gate insulating layer therebetween.
[0014] In a display device according to one embodiment of the
present invention, the oxide semiconductor layer is preferably a
highly-purified oxide semiconductor layer.
[0015] In a display device according to one embodiment of the
present invention, the highly-purified oxide semiconductor layer is
preferably made of an oxide semiconductor containing at least one
element selected from the group consisting of In, Sn, and Zn.
[0016] In one embodiment of the present invention, a way to improve
the field-effect mobility is supplying oxygen to an oxide
semiconductor in the transistor with an insulating film in the
vicinity of the oxide semiconductor or/and supplying oxygen to an
oxide semiconductor in the transistor through ion implantation to
reduce oxygen deficiency part of which generates a carrier. Another
way to improve the field-effect mobility is highly purifying the
oxide semiconductor in a process for manufacturing the transistor
to reduce the concentration of hydrogen, part of which generates a
carrier, to an extremely low level.
[0017] A detail description is given below of a process for
manufacturing a transistor formed using an oxide semiconductor
according to one embodiment of the present invention with reference
to cross-sectional views of FIGS. 1A to 1D.
[0018] First, a base insulating film 10 that releases oxygen when
undergoing heat treatment is formed, and an oxide semiconductor
film 11 is stacked over the base insulating film 10 (FIG. 1A).
Then, a stack of the base insulating film 10 and the oxide
semiconductor film 11 is subjected to a first heat treatment (FIG.
1B).
[0019] When an insulating film from which oxygen is released by
heat treatment is provided as the base insulating film 10 serving
as a gate insulating film and the like, oxygen deficiency caused in
the oxide semiconductor film 11 can be repaired by heat treatment
in a later step. Oxygen deficiency in the oxide semiconductor film
11 partly generates a carrier, which can cause a variation in the
threshold voltage of the obtained transistor.
[0020] In addition, when the base insulating film 10 from which
oxygen is released by heat treatment is provided, interface state
between the base insulating film 10 and the oxide semiconductor
film 11 can be reduced. An interface state traps an electric charge
generated as a result of operation of the obtained transistor in
some cases and thus can be a factor that causes a reduction in
reliability of the transistor.
[0021] Note that the base insulating film 10 is preferably flat.
Specifically, the base insulating film 10 has an average surface
roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, further
preferably 0.1 nm or less. The base insulating film 10 may be
subjected to planarization treatment such as chemical mechanical
polishing (CMP) treatment. When the base insulating film 10 is
flat, the state of an interface between the base insulating film 10
and the oxide semiconductor film 11 is favorable, whereby
field-effect mobility can be increased and a variation in the
threshold voltage can be reduced in the obtained transistor.
[0022] It is particularly preferable that the oxide semiconductor
film 11 be formed using an In--Sn--Zn-based oxide because it
increases the field-effect mobility and reliability of the
transistor. Examples of other oxides producing similar effects
include a four-component metal oxide such as an
In--Sn--Ga--Zn-based oxide; a three-component metal oxide such as
an In--Ga--Zn-based oxide (also referred to as IGZO), an
In--Al--Zn-based oxide, a Sn--Ga--Zn-based oxide, an
Al--Ga--Zn-based oxide, a Sn--Al--Zn-based oxide, an
In--Hf--Zn-based oxide, an In--La--Zn-based oxide, an
In--Ce--Zn-based oxide, an In--Pr--Zn-based oxide, an
In--Nd--Zn-based oxide, an In--Pm--Zn-based oxide, an
In--Sm--Zn-based oxide, an In--Eu--Zn-based oxide, an
In--Gd--Zn-based oxide, an In--Tb--Zn-based oxide, an
In--Dy--Zn-based oxide, an In--Ho--Zn-based oxide, an
In--Er--Zn-based oxide, an In--Tm--Zn-based oxide, an
In--Yb--Zn-based oxide, or an In--Lu--Zn-based oxide; a
two-component metal oxide such as an In--Zn-based oxide, a
Sn--Zn-based oxide, an Al--Zn-based oxide, a Zn--Mg-based oxide, a
Sn--Mg-based oxide, an In--Mg-based oxide, or an In--Ga-based
oxide; and a one-component metal oxide such as In-based oxide,
Sn-based oxide, Zn-based oxide.
[0023] Note that the oxide semiconductor film 11 is preferably
formed while the substrate is heated because in that case, the
obtained transistor can have increased field-effect mobility.
Substrate heating temperature at the time of formation of the oxide
semiconductor film 11 is higher than or equal to 100.degree. C. and
lower than or equal to 600.degree. C., preferably higher than or
equal to 150.degree. C. and lower than or equal to 550.degree. C.,
further preferably higher than or equal to 200.degree. C. and lower
than or equal to 500.degree. C. The oxide semiconductor film 11 is
preferably formed by a sputtering method.
[0024] Note that the band gap of the oxide semiconductor film 11 is
2.5 eV or more, preferably 2.8 eV or more, further preferably 3.0
eV or more. When the band gap of the oxide semiconductor film 11 is
in the above range, the transistor can have extremely low off-state
current.
[0025] Note that the oxide semiconductor film 11 is in a single
crystal state, a polycrystalline (also referred to as polycrystal)
state, an amorphous state, or the like. Preferably, a c-axis
aligned crystalline oxide semiconductor (CAAC-OS) film can be used
as the oxide semiconductor film 11.
[0026] The CAAC-OS film is not completely single crystal nor
completely amorphous. The CAAC-OS film is an oxide semiconductor
film with a crystal-amorphous mixed phase structure where crystal
parts and amorphous parts are included in an amorphous phase. Note
that in most cases, the crystal part fits inside a cube whose one
side is less than 100 nm. From an observation image obtained with a
transmission electron microscope (TEM), a boundary between the
amorphous part and a crystal part in the CAAC-OS film is not clear.
Further, with the TEM, a grain boundary in the CAAC-OS film is not
found. Thus, in the CAAC-OS film, a reduction in electron mobility,
due to the grain boundary, is suppressed.
[0027] The first heat treatment is performed in a reduced-pressure
atmosphere (10 Pa or lower), an inert atmosphere (an atmosphere of
an inert gas such as nitrogen or a rare gas), or an oxidizing
atmosphere (an atmosphere containing an oxidizing gas such as
oxygen, ozone, or nitrous oxide at 10 ppm or more) at a temperature
higher than or equal to 250.degree. C. and lower than or equal to
650.degree. C., preferably higher than or equal to 300.degree. C.
and lower than or equal to 600.degree. C.
[0028] By the first heat treatment, the concentration of impurities
such as hydrogen in the oxide semiconductor film 11 can be reduced.
Alternatively, the state of the interface between the base
insulating film 10 and the oxide semiconductor film 11 can be made
favorable. Since the first heat treatment is performed after the
oxide semiconductor film 11 is formed, outward diffusion of oxygen
that is released from the base insulating film 10 can be prevented.
Note that it is alternatively possible that heat treatment is
performed in an inert atmosphere or a reduced-pressure atmosphere,
the atmosphere is then changed to an oxidizing atmosphere without
changing the temperature, and heat treatment is performed in the
oxidizing atmosphere. When the first heat treatment is performed in
this manner, impurities in the oxide semiconductor film 11 can be
reduced in the inert atmosphere or the reduced-pressure atmosphere
and then oxygen deficiency caused at the time of removal of
impurities can be reduced in the oxidizing atmosphere.
[0029] Note that a gas containing fewer impurities is used for the
heat treatment and film formation. Specifically, a gas whose dew
point is -70.degree. C. or lower can be used.
[0030] After the first heat treatment, the oxide semiconductor film
11 is processed into an island-shaped oxide semiconductor film 12.
Processing of the oxide semiconductor film 12 can be performed in
such a manner that a resist mask is formed with the use of a
photomask and a part in which the resist mask is not formed is
etched by a dry etching method or a wet etching method. Such a
process is called photolithography process.
[0031] Then, a conductive film is formed and processed by a
photolithography process, so that a source electrode 13A and a
drain electrode 13B which are at least partly in contact with the
oxide semiconductor film are formed.
[0032] Next, an upper insulating film 14 serving as an interlayer
insulating film is formed (FIG. 1C). It is preferable that an
insulating film from which oxygen is released by heat treatment be
used as the upper insulating film 14.
[0033] Next, second heat treatment is performed (FIG. 1D). The
second heat treatment can be performed under a condition similar to
that of the first heat treatment. By the second heat treatment,
oxygen is released from the base insulating film 10 and the upper
insulating film 14, so that oxygen deficiency in the island-shaped
oxide semiconductor film 12 can be reduced. Moreover, interface
state between the base insulating film 10 and the island-shaped
oxide semiconductor film 12 and interface state between the
island-shaped oxide semiconductor film 12 and the upper insulating
film 14 can be reduced, whereby in the obtained transistor,
field-effect mobility can be increased, a variation in threshold
voltage can be reduced and the reliability can be improved.
[0034] In the above-described manner, a highly reliable transistor
can be manufactured which includes an oxide semiconductor and has
high field-effect mobility and in which a variation in threshold
voltage is small.
[0035] Note that it is preferable that an interlayer insulating
film be additionally formed to cover the transistor. By the
interlayer insulating film, outward diffusion of oxygen that is
released from the base insulating film 10 and the upper insulating
film 14 from the transistor can be prevented. In the case where the
interlayer insulating film is provided, the second heat treatment
may be performed after formation of the interlayer insulating
film.
[0036] A transistor which is obtained in the above manner has high
field-effect mobility (e.g., a field-effect mobility of 31
cm.sup.2/Vs or more), a small variation in threshold voltage, high
reliability (e.g., a fluctuation range of threshold voltage by a
negative BT test is 1 V or less), and extremely low off-state
current.
[0037] A description will be given of the reason that highly
purifying an oxide semiconductor increases the field-effect
mobility of an insulated gate transistor.
[0038] The actually measured field-effect mobility of an insulated
gate transistor can be lower than its original mobility because of
a variety of reasons; this phenomenon occurs not only in the case
of using an oxide semiconductor. One of the reasons that reduce the
mobility is a defect inside a semiconductor or a defect at the
interface between the semiconductor and an insulating film. When a
Levinson model is used, the field-effect mobility that is based on
the assumption that no defect exists inside the semiconductor can
be calculated theoretically.
[0039] Assuming that the original mobility and the measured
field-effect mobility of a semiconductor are .mu..sub.0 and .mu.,
respectively, and a potential barrier (such as a grain boundary)
exists in the semiconductor, the measured field-effect mobility
.mu. can be expressed as Formula 1.
.mu. = .mu. 0 exp ( - E kT ) [ Formula 1 ] ##EQU00001##
[0040] Here, E represents the height of the potential barrier, k
represents the Boltzmann constant, and T represents the absolute
temperature. When the potential barrier is assumed to be attributed
to a defect, the height E of the potential barrier can be expressed
as Formula 2 according to the Levinson model.
E = 2 N 2 8 n = 3 N 2 t 8 C ox V g [ Formula 2 ] ##EQU00002##
[0041] Here, e represents the elementary charge, N represents the
average defect density per unit area in a channel, s represents the
permittivity of the semiconductor, n represents the number of
carriers per unit area in the channel, C.sub.ox represents the
capacitance per unit area, V.sub.g represents the gate voltage, and
t represents the thickness of the channel. Note that in the case
where the thickness of the semiconductor layer is less than or
equal to 30 nm, the thickness of the channel may be regarded as
being the same as the thickness of the semiconductor layer.
[0042] The drain current I.sub.d in a linear region can be
expressed as Formula 3.
I d = W .mu. V g V d C ox L exp ( - E kT ) [ Formula 3 ]
##EQU00003##
[0043] Here, L represents the channel length and W represents the
channel width, and L and W are each 10 .mu.m. Further, V.sub.d
represents the drain voltage.
[0044] When dividing both sides of the above equation by V.sub.g
and then taking logarithms of both sides, Formula 4 can be
obtained.
ln ( I d V g ) = ln ( W .mu. V d C ox L ) - E kT = ln ( W .mu. V d
C ox L ) - 3 N 2 t 8 kT C ox V g [ Formula 4 ] ##EQU00004##
[0045] The right side of Formula 4 is a function of V.sub.g. From
the formula, it is found that the defect density N can be obtained
from the slope of a line in a graph which plots actual measured
values and where the ordinate represents ln(I.sub.d/V.sub.g) and
the abscissa represents 1/V.sub.g. That is, the defect density can
be evaluated from the I.sub.d-V.sub.g characteristics of the
transistor. The defect density N of an oxide semiconductor in which
the ratio of indium (In), tin (Sn), and zinc (Zn) is 1:1:1 is
approximately 1.times.10.sup.12/cm.sup.2.
[0046] On the basis of the defect density obtained in this manner,
to can be calculated to be 120 cm.sup.2/Vs from Formula 1 and
Formula 2. The measured mobility of an In--Sn--Zn oxide including a
defect is approximately 40 cm.sup.2/Vs. However, assuming that no
defect exists inside the semiconductor and at the interface between
the semiconductor and an insulating film, the mobility .mu..sub.0
of the oxide semiconductor is expected to be 120 cm.sup.2/Vs.
[0047] Note that even when no defect exists inside a semiconductor,
scattering at the interface between a channel and a gate insulating
film adversely affects the transport property of the transistor. In
other words, the mobility .mu..sub.1 at a position that is distance
x away from the interface between the channel formation region and
the gate insulating film can be expressed as Formula 5.
1 .mu. 1 = 1 .mu. 0 + D B exp ( - x l ) [ Formula 5 ]
##EQU00005##
[0048] Here, D represents the electric field in the gate direction,
and B and I are constants. Note that B and I can be obtained from
actual measurement results; according to the above measurement
results, B is 4.75.times.10.sup.7 cm/s and I is 10 nm (the depth to
which the influence of interface scattering reaches). When D is
increased (i.e., when the gate voltage is increased), the second
term of Formula 5 is increased and accordingly the mobility
.mu..sub.1 is decreased.
[0049] FIG. 2 shows calculation results of the mobility .mu..sub.2
of a transistor whose channel is formed using an ideal oxide
semiconductor without a defect inside the semiconductor. For the
calculation, device simulation software Sentaurus Device
manufactured by Synopsys, Inc. was used, and the band gap, the
electron affinity, the relative permittivity, and the thickness of
the oxide semiconductor were assumed to be 2.8 eV, 4.7 eV, 15, and
15 nm, respectively. These values were obtained by measurement of a
thin film that was formed by a sputtering method.
[0050] Further, the work functions of a gate, a source, and a drain
were assumed to be 5.5 eV, 4.6 eV, and 4.6 eV, respectively. The
thickness of a gate insulating film was assumed to be 100 nm, and
the relative permittivity thereof was assumed to be 4.1. The
channel length and the channel width were each assumed to be 10
.mu.m, and the drain voltage V.sub.d was assumed to be 0.1 V.
[0051] As shown in FIG. 2, the mobility has a peak of 100
cm.sup.2/Vs or more at a gate voltage that is a little over 1 V,
and is decreased as the gate voltage becomes higher because the
influence of interface scattering is increased. Note that in order
to reduce interface scattering, it is desirable that a surface of
the semiconductor layer be flat at the atomic level (atomic layer
flatness).
[0052] Calculation results of characteristics of minute transistors
formed using an oxide semiconductor having such a mobility are
shown in FIGS. 3A to 3C, FIGS. 4A to 4C, and FIGS. 5A to 5C. FIGS.
6A and 6B illustrate cross-sectional structures of the transistors
used for the calculation. The transistors illustrated in FIGS. 6A
and 6B each include a semiconductor region 103a and a semiconductor
region 103c that have n.sup.+-type conductivity in an oxide
semiconductor layer. The resistivity of the semiconductor regions
103a and 103c is 2.times.10.sup.-3 .OMEGA.cm.
[0053] The transistor in FIG. 6A is formed over a base insulating
layer 101 and an embedded insulating layer 102 that is embedded in
the base insulating layer 101 and formed of aluminum oxide. The
transistor includes the semiconductor region 103a, the
semiconductor region 103c, an intrinsic semiconductor region 103b
that is placed between the semiconductor regions 103a and 103c and
serves as a channel formation region, and a gate 105. The width of
the gate 105 is 33 nm.
[0054] A gate insulating film 104 is formed between the gate 105
and the semiconductor region 103b. A sidewall insulating layer 106a
and a sidewall insulating layer 106b are formed on both side
surfaces of the gate 105, and an insulating layer 107 is formed
over the gate 105 so as to prevent a short circuit between the gate
105 and another wiring. The sidewall insulating layer has a width
of 5 nm. A source 108a and a drain 108b are provided in contact
with the semiconductor region 103a and the semiconductor region
103c, respectively. Note that the channel width of this transistor
is 40 nm.
[0055] The transistor in FIG. 6B is the same as the transistor in
FIG. 6A in that it is formed over the base insulating layer 101 and
the embedded insulating layer 102 formed of aluminum oxide and that
it includes the semiconductor region 103a, the semiconductor region
103c, the intrinsic semiconductor region 103b provided
therebetween, the gate 105 having a width of 33 nm, the gate
insulating film 104, the sidewall insulating layer 106a, the
sidewall insulating layer 106b, the insulating layer 107, the
source 108a, and the drain 108b.
[0056] The difference between the transistor in FIG. 6A and the
transistor in FIG. 6B is the conductivity type of semiconductor
regions under the sidewall insulating layers 106a and 106b. In the
transistor in FIG. 6A, the semiconductor regions under the sidewall
insulating layer 106a and the sidewall insulating layer 106b are
part of the semiconductor region 103a having n.sup.+-type
conductivity and part of the semiconductor region 103c having
n.sup.+-type conductivity, whereas in the transistor in FIG. 6B,
the semiconductor regions under the sidewall insulating layer 106a
and the sidewall insulating layer 106b are part of the intrinsic
semiconductor region 103b. In other words, a region having a width
of L.sub.off which overlaps with neither the semiconductor region
103a (the semiconductor region 103c) nor the gate 105 is provided.
This region is called an offset region, and the width L.sub.off is
called an offset length. As is seen from the drawing, the offset
length is equal to the width of the sidewall insulating layer 106a
(the sidewall insulating layer 106b).
[0057] The other parameters used in calculation are as described
above. For the calculation, device simulation software Sentaurus
Device manufactured by Synopsys, Inc. was used. FIGS. 3A to 3C show
the gate voltage (V.sub.g: a potential difference between the gate
and the source) dependence of the drain current (I.sub.d, a solid
line) and the mobility (.mu., a dotted line) of the transistor
having the structure illustrated in FIG. 6A. The drain current
I.sub.d is obtained by calculation under the assumption that the
drain voltage (a potential difference between the drain and the
source) is +1 V, and the mobility .mu. is obtained by calculation
under the assumption that the drain voltage is +0.1 V.
[0058] FIG. 3A shows the gate voltage dependence of the transistor
in the case where the thickness of the gate insulating layer is 15
nm, FIG. 3B shows that of the transistor in the case where the
thickness of the gate insulating layer is 10 nm, and FIG. 3C shows
that of the transistor in the case where the thickness of the gate
insulating layer is 5 nm. As the gate insulating layer becomes
thinner, the drain current I.sub.d in the off state (off-state
current) in particular is significantly decreased. In contrast,
there is no noticeable change in the peak value of the mobility
.mu. and the drain current I.sub.d in an on state (on-state
current). The graphs show that the drain current exceeds 10 .mu.A
at a gate voltage of around 1 V.
[0059] FIGS. 4A to 4C show the gate voltage V.sub.g dependence of
the drain current I.sub.d (a solid line) and the mobility .mu. (a
dotted line) of the transistor having the structure in FIG. 6B and
an offset length L.sub.off of 5 nm. The drain current I.sub.d is
obtained by calculation under the assumption that the drain voltage
V.sub.d is +1 V and the mobility .mu. is obtained by calculation
under the assumption that the drain voltage is +0.1 V. FIG. 4A
shows the gate voltage dependence of the transistor in the case
where the thickness of the gate insulating layer is 15 nm, FIG. 4B
shows that of the transistor in the case where the thickness of the
gate insulating layer is 10 nm, and FIG. 4C shows that of the
transistor in the case where the thickness of the gate insulating
layer is 5 nm.
[0060] FIGS. 5A to 5C show the gate voltage dependence of the drain
current I.sub.d (a solid line) and the mobility .mu. (a dotted
line) of the transistor having the structure in FIG. 6B and an
offset length L.sub.off of 15 nm. The drain current I.sub.d is
obtained by calculation under the assumption that the drain voltage
V.sub.d is +1 V and the mobility .mu. is obtained by calculation
under the assumption that the drain voltage is +0.1 V. FIG. 5A
shows the gate voltage dependence of the transistor in the case
where the thickness of the gate insulating layer is 15 nm, FIG. 5B
shows that of the transistor in the case where the thickness of the
gate insulating layer is 10 nm, and FIG. 5C shows that of the
transistor in the case where the thickness of the gate insulating
layer is 5 nm.
[0061] In both of the structures, as the gate insulating layer
becomes thinner, the off-state current is significantly decreased,
whereas no noticeable change arises in the peak value of the
mobility .mu. and the on-state current.
[0062] Note that the peak of the mobility .mu. is approximately 80
cm.sup.2/Vs in FIGS. 3A to 3C, approximately 60 cm.sup.2/Vs in
FIGS. 4A to 4C, and approximately 40 cm.sup.2/Vs in FIGS. 5A to 5C;
thus, the peak of the mobility .mu. is decreased as the offset
length L.sub.off is increased. Further, the same applies to the
off-state current. The on-state current is also decreased as the
offset length L.sub.off is increased; however, the decrease in the
on-state current is much more gradual than the decrease in the
off-state current.
[0063] The above-described transistor including a highly purified
oxide semiconductor in a channel formation region has a
field-effect mobility of as high as 80 cm.sup.2/Vs or more or 120
cm.sup.2/Vs, so that the transistor can have a high current supply
capability even when formed over the same insulated substrate as
the pixel portion.
[0064] According to one embodiment of the present invention,
transistors in switch circuit portions in a signal line driver
circuit can be reduced in size and adequate charging and
discharging of a signal line can be achieved.
BRIEF DESCRIPTION OF THE DRAWINGS
[0065] FIGS. 1A to 1D are cross-sectional views illustrating one
embodiment of the present invention.
[0066] FIG. 2 is a graph showing gate voltage dependence of
mobility obtained by calculation.
[0067] FIGS. 3A to 3C are graphs each showing gate voltage
dependence of drain current and mobility obtained by
calculation.
[0068] FIGS. 4A to 4C are graphs each showing gate voltage
dependence of drain current and mobility obtained by
calculation.
[0069] FIGS. 5A to 5C are graphs each showing gate voltage
dependence of drain current and mobility obtained by
calculation.
[0070] FIGS. 6A and 6B illustrate cross-sectional structures of
transistors used for calculation.
[0071] FIG. 7 illustrates one embodiment of a display device
according to one embodiment of the present invention.
[0072] FIG. 8 illustrates one embodiment of a display device
according to one embodiment of the present invention.
[0073] FIG. 9 illustrates an example of an electronic device.
[0074] FIG. 10 shows XRD spectra of In--Sn--Zn-based oxide
films.
[0075] FIGS. 11A to 11D are cross-sectional views illustrating a
method for manufacturing a transistor according to one embodiment
of the present invention.
[0076] FIGS. 12A to 12D are cross-sectional views illustrating a
method for manufacturing a transistor according to one embodiment
of the present invention.
[0077] FIGS. 13A and 13B are a top view and a cross-sectional view
of a transistor according to one embodiment of the present
invention.
[0078] FIGS. 14A and 14B are a top view and a cross-sectional view
of a transistor according to one embodiment of the present
invention.
[0079] FIGS. 15A to 15E are diagrams each illustrating a crystal
structure of an oxide material.
[0080] FIGS. 16A to 16C are diagrams illustrating a crystal
structure of an oxide material.
[0081] FIGS. 17A to 17C are diagrams illustrating a crystal
structure of an oxide material.
[0082] FIG. 18 is a cross-sectional TEM image of an
In--Sn--Zn-based oxide film.
[0083] FIG. 19 is a cross-sectional TEM image of an
In--Sn--Zn-based oxide film.
DETAILED DESCRIPTION OF THE INVENTION
[0084] Hereinafter, embodiments will be described with reference to
drawings. However, the embodiments can be implemented with
different modes. It will be readily appreciated by those skilled in
the art that modes and details can be changed in various ways
without departing from the spirit and scope of the present
invention. Therefore, the present invention is not interpreted as
being limited to the description of the embodiments below. Note
that in structures described below, the same portions or portions
having similar functions are denoted by the same reference numerals
in different drawings, and description thereof is not repeated.
[0085] Note that the size, the thickness of a layer, distortion of
the waveform of a signal, and a region of each structure
illustrated in the drawings and the like in the embodiments are
exaggerated for simplicity in some cases. Therefore, embodiments of
the present invention are not limited to such scales.
[0086] Note that terms such as "first", "second", and "third" in
this specification are used in order to avoid confusion among
components, and the terms do not limit the components
numerically.
Embodiment 1
[0087] This embodiment describes a configuration of a display
device having a signal line driver circuit including switch circuit
portions.
[0088] A structural example of a display device is described with
reference to FIG. 7. The display device includes a pixel portion
701, a scan line driver circuit portion 702, and a signal line
driver circuit portion 703 over a substrate 700.
[0089] Note that as the substrate 700, in addition to a glass
substrate and a ceramic substrate, a plastic substrate or the like
with heat resistance can be used.
[0090] In the pixel portion 701, a plurality of pixels is provided
for intersection portions of scan lines and signal lines. Since the
video signal is supplied to respective pixels 704 through the
signal lines in the pixel portion 701, an image with desired
grayscale is displayed. In addition, a pixel electrode which is
connected to a transistor and a display element is provided for
each pixel. A gate electrode of the transistor is connected to a
scan line; one of electrodes serving as a source electrode and a
drain electrode (a first terminal) of the thin film transistor is
connected to a signal line; and the other of the electrodes serving
as the source electrode and the drain electrode (a second terminal)
of the thin film transistor is connected to any other element in
the pixel. Note that the display element connected to the pixel
electrode may be any display element that is driven with an
electric signal, e.g., a liquid crystal display element or a light
emitting element.
[0091] The scan line driver circuit portion 702 outputs scan
signals to a plurality of scan lines which extends to the pixel
portion. In FIG. 7, although the scan line driver circuit portion
702 is provided over the substrate 700, part or all of functions of
the scan line driver circuit may be provided outside the substrate
700. In addition, although not shown, signals for driving the scan
line driver circuit, such as a clock signal (GCK) and a start pulse
(GSP), are input to the scan line driver circuit portion 702
through an external connection terminal 705.
[0092] The signal line driver circuit portion 703 includes a
plurality of switch circuit portions 706_1 to 706_N (N is a natural
number). The switch circuit portions 706_1 to 706_N each include a
plurality of transistors 707_1 to 707_k (k is a natural number).
The transistors 707_1 to 707_k have the same conductivity type as a
transistor in the pixel 704 and a transistor in the scan line
driver circuit portion 702.
[0093] Connections in the signal line driver circuit portion 703
are described taking the switch circuit portion 706_1 as an
example. First terminals of the transistors 707_1 to 707_k in the
switch circuit portion 706_1 are connected to a wiring 708_1.
Second terminals of the transistors 707_1 to 707_k in the switch
circuit portion 706_1 are connected to wirings S.sub.1 to S.sub.k,
respectively. Gates of the transistors 707_1 to 707_k in the switch
circuit portion 706_1 are connected to wirings 709_1 to 709_k,
respectively.
[0094] A sampling signal output circuit 709 has a function of
supplying sampling signals to the switch circuit portions 706_1 to
706_N through the external connection terminal 705 via the wirings
709_1 to 709_k.
[0095] A video signal output circuit 708 has a function of
outputting the video signal to the switch circuit portions 706_1 to
706_N through the external connection terminal 705. For example,
the video signal output circuit 708 supplies the video signal to
the switch circuit portion 706_1 through the external connection
terminal 705 and the wiring 708_1. The video signal is an analog
signal in many cases.
[0096] Note that in the case where the sampling signal output
circuit 709 and the video signal output circuit 708 are formed
outside the substrate 700, the sampling signal output circuit 709
and the video signal output circuit 708 can be mounted on an FPC
(flexible printed circuit) which is connected to the external
connection terminal 705 by TAB (tape automated bonding).
Alternatively, the sampling signal output circuit 709 and the video
signal output circuit 708 can be mounted on the substrate 700 by
COG (chip on glass).
[0097] The switch circuit portions 706_1 to 706_N have a function
of selecting, with the transistors 707_1 to 707_k, to which wiring
the video signal from the video signal output circuit 708 is
output. For example, the switch circuit portion 706_1 has a
function of selecting, with sampling signals supplied via the
wirings 709_1 to 709_k, to which wiring between the wirings S.sub.1
to S.sub.k the video signal output from the video signal output
circuit 708 via the wiring 708_1 is output.
[0098] The transistors 707_1 to 707_k in the switch circuit portion
706_1 have functions of controlling conduction or nonconduction
between the wiring 708_1 and the wirings S.sub.1 to S.sub.k, in
accordance with the sampling signals from the sampling signal
output circuit 709.
[0099] Next, the operation of the signal line driver circuit in
FIG. 7 is described with reference to a timing chart of FIG. 8.
FIG. 8 illustrates examples of sampling signals supplied via the
wirings 709_1 to 709_k (in FIGS. 8, 709_1, 709_2, and 709_k) and
signals supplied via the wirings 708_1 to 708_N (in FIGS. 8, 708_1,
708_2, and 708_N). Note that one operation period for the signal
line driver circuit corresponds to one gate selection period for a
display device. Note that one gate selection period is divided into
periods T1 to Tk, for example. In the periods T1 to Tk, the pixels
in a selected row are supplied with the video signal (Data
(D)).
[0100] In the periods T1 to Tk, the sampling signal output circuit
709 outputs a high level signal in sequence to the wirings 709_1 to
709_k. For example, in the period T1, the sampling signal output
circuit 709 outputs a high level signal to the wiring 709_1. Then,
the transistors 707_1 in the switch circuit portions 706_1 to 706_N
are turned on. Consequently, for example, electrical continuity
between each of the wirings 708_1 to 708_N and a corresponding one
of the signal lines S.sub.1, S.sub.k+1, S.sub.(N-1)k+1 is
established. At this time, the wiring 708_1, the wiring 708_2, and
the wiring 708_N receive D (S.sub.1), D (S.sub.k+1), and D
(S.sub.(N-1)k+1), respectively. Thus, in the periods T1 to Tk, the
pixels in a selected row are supplied (N columns of pixels at a
time) with a video signal.
[0101] By supplying the video signal to a plurality of columns of
pixels at a time as described above, the number of the wirings
which select the video signal can be reduced. This results in a
reduction in the number of connections between the display device
and the sampling signal output circuit 709. Moreover, by supplying
the video signal to a plurality of columns of pixels at a time,
write time can be increased, which prevents insufficient supply of
a write signal.
[0102] In the case where the transistors 707_1 to 707_k in the
switch circuit portions 706_1 to 706_N include an In--Ga--Zn-based
oxide film that is a film of an oxide semiconductor not highly
purified, assumed conditions for these transistors are as follows.
The case of the transistor 707_1 is described as an example.
[0103] On resistance Ron can be represented by Formula 6 assuming
that the transistor 707_1 has a 300-nm-thick gate insulating layer,
a dielectric constant of 3.8, a gate-source voltage Vgs of 5 V, a
threshold voltage Vth of 2 V, a field-effect mobility .mu. of 10
cm.sup.2/Vs, and a gate length L of 3 .mu.m.
Ron=Vds/Id [Formula 6]
[0104] Drain current Id in Formula 6 is represented by Formula
7.
Id=.mu.CoW/L(Vgs-Vth)ds [Formula 7]
[0105] Co is an electrostatic capacitance per unit area of the gate
insulating layer, W is a gate width, L is a gate length, and Vds is
a voltage between the drain and the source.
[0106] Formula 6 and Formula 7 indicate that W needs to be 9 cm in
order that the on resistance can be 110.OMEGA. or less. However,
although the display device is required to have a small frame size,
the transistors in the switch circuit portions occupy a very large
area if W is 9 cm. In other words, the display device has a very
large frame size when using an In--Ga--Zn-based oxide film that is
a film of an oxide semiconductor not highly purified and that
results in a field-effect mobility .mu. of 10 cm.sup.2/Vs. Use of
amorphous silicon leads to a lower mobility than use of such an
oxide semiconductor and therefore results in a larger frame size
than use of such an oxide semiconductor.
[0107] In contrast, an In--Sn--Zn-based oxide film that is a
highly-purified oxide semiconductor film can lead to a field-effect
mobility .mu. of 80 cm.sup.2/Vs or more or 120 cm.sup.2/Vs or more.
In this case, under the above-described conditions, W can be
reduced to 11.3 mm or 7.5 mm, thereby reducing the area of the
transistors in the switch circuit portions. Consequently, the frame
size of the display device can be reduced.
[0108] Thus, use of a highly-purified oxide semiconductor film as
active layers of the transistors in the switch circuit portions
results in a reduction in frame size and allows these transistors
to be formed over the same insulating substrate as circuits such as
pixels. Moreover, use of a highly-purified oxide semiconductor film
as active layers of the transistors in the switch circuit portions
prevents variations between the transistors in characteristics such
as threshold voltage and enables adequate charging and discharging
of the signal lines.
[0109] As described above, a transistor having a highly-purified
oxide semiconductor in a channel formation region may be used as
the transistors in the switch circuit portions in the signal line
driver circuit in this embodiment. A transistor having a
highly-purified oxide semiconductor in a channel formation region
has a high field-effect mobility. Thus, use of this transistor
reduces the size of the transistors in the switch circuit portions
in the signal line driver circuit and enables adequate charging and
discharging of the signal lines.
[0110] This embodiment can be implemented in appropriate
combination with any of the structures described in the other
embodiments.
Embodiment 2
[0111] This embodiment describes an example of a method for
manufacturing the transistors in the switch circuit portions
described in Embodiment 1 with reference to FIGS. 11A to 11D and
FIGS. 12A to 12D. FIGS. 13A and 13B and FIGS. 14A and 14B are
examples of top views and cross-sectional views (taken along lines
in the top views) of a transistor in each pixel in the pixel
portion that can be formed over the same substrate as the
transistors in the switch circuit portions.
[0112] This embodiment describes an example of a method for
manufacturing a transistor with a bottom-gate structure, but the
transistors in the switch circuit portions and the transistors in
the pixels may have a top-gate structure. In addition, this
embodiment describes an example of a method for manufacturing a
staggered transistor, but a coplanar transistor can also be
manufactured.
[0113] This embodiment describes an example of a method for
manufacturing the transistors in the switch circuit portions, but
the transistors in the signal line driver circuit and/or the scan
line driver circuit can also be manufactured by this method.
[0114] A description is given of an example of a method for
manufacturing a transistor with a channel-etch and bottom-gate
structure with reference to FIGS. 11A to 11D.
[0115] First, a conductive film is formed over a substrate 400
which is a substrate having an insulating surface, and then, a gate
electrode layer 401 is provided using a photolithography process
with the use of a photomask.
[0116] As the substrate 400, a glass substrate which enables mass
production is preferably used. As a glass substrate used for the
substrate 400, a glass substrate whose strain point is higher than
or equal to 730.degree. C. may be used when the temperature of heat
treatment to be performed in a later step is high. For the
substrate 400, for example, a glass material such as
aluminosilicate glass, aluminoborosilicate glass, or barium
borosilicate glass is used.
[0117] An insulating layer serving as a base layer may be provided
between the substrate 400 and the gate electrode layer 401. The
base layer has a function of preventing diffusion of an impurity
element from the substrate 400, and can be formed with a
single-layer or stacked-layer structure using one or more of
silicon nitride, silicon oxide, silicon nitride oxide, and silicon
oxynitride.
[0118] Silicon oxynitride refers to a substance that contains a
larger amount of oxygen than that of nitrogen. For example, silicon
oxynitride contains oxygen, nitrogen, silicon, and hydrogen at
concentrations of higher than or equal to 50 at. % and lower than
or equal to 70 at. %, higher than or equal to 0.5 at. % and lower
than or equal to 15 at. %, higher than or equal to 25 at. % and
lower than or equal to 35 at. %, and higher than or equal to 0 at.
% and lower than or equal to 10 at. %, respectively. In addition,
silicon nitride oxide refers to a substance that contains a larger
amount of nitrogen than that of oxygen. For example, silicon
nitride oxide contains oxygen, nitrogen, silicon, and hydrogen at
concentrations of higher than or equal to 5 at. % and lower than or
equal to 30 at. %, higher than or equal to 20 at. % and lower than
or equal to 55 at. %, higher than or equal 25 at. % and lower than
or equal to 35 at. %, and higher than or equal to 10 at. % and
lower than or equal to 25 at. %, respectively. Note that the above
ranges are obtained in the case where measurement is performed
using Rutherford backscattering spectrometry (RBS) and hydrogen
forward scattering spectrometry (HFS). Moreover, the total of the
percentages of the constituent elements does not exceed 100 at.
%.
[0119] The gate electrode layer 401 may be formed to have a
single-layer or stacked-layer structure using one or more of the
following materials: Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and
W, a nitride of any of these elements, an oxide of any of these
elements, and an alloy of any of these elements. Alternatively, an
oxide or an oxynitride which contains at least In and Zn may be
used. For example, an In--Ga--Zn--O--N-based oxide or the like can
be used.
[0120] Next, a gate insulating layer 402 is formed over the gate
electrode layer 401. The gate insulating layer 402 is formed by a
sputtering method, an evaporation method, a plasma-enhanced
chemical vapor deposition (PCVD) method, a pulsed laser deposition
(PLD) method, an atomic layer deposition (ALD) method, a molecular
beam epitaxy (MBE) method, or the like without exposure to the air
after the gate electrode layer 401 is formed.
[0121] It is preferable that an insulating film from which oxygen
is released by heat treatment be used as the gate insulating layer
402.
[0122] To release oxygen by heat treatment means that the released
amount of oxygen which is converted into oxygen atoms is greater
than or equal to 1.0.times.10.sup.18 atoms/cm.sup.3, preferably
greater than or equal to 3.0.times.10.sup.20 atoms/cm.sup.3 in
thermal desorption spectroscopy (TDS) analysis.
[0123] Here, a method in which the amount of released oxygen is
measured by conversion into oxygen atoms using TDS analysis will be
described.
[0124] The amount of released gas in TDS analysis is proportional
to the integral value of a spectrum. Therefore, the amount of
released gas can be calculated from the ratio between the integral
value of a measured spectrum and the reference value of a standard
sample. The reference value of a standard sample refers to the
ratio of the density of a predetermined atom contained in a sample
to the integral value of a spectrum.
[0125] For example, the amount of the released oxygen molecules
(No2) from an insulating film can be obtained according to Formula
8 with the TDS analysis results of a silicon wafer containing
hydrogen at a predetermined density which is the standard sample
and the TDS analysis results of the insulating film. Here, all
spectra having a mass number of 32 which are obtained by the TDS
analysis are assumed to originate from an oxygen molecule.
CH.sub.3OH, which is given as a gas having a mass number of 32, is
not taken into consideration on the assumption that it is unlikely
to be present. Further, an oxygen molecule including an oxygen atom
having a mass number of 17 or 18 which is an isotope of an oxygen
atom is not taken into consideration either because the proportion
of such a molecule in the natural world is minimal.
N O 2 = N H 2 S H 2 .times. S O 2 .times. .alpha. [ Formula 8 ]
##EQU00006##
[0126] In Formula 8, N.sub.H2 is the value obtained by conversion
of the amount of hydrogen molecules released from the standard
sample into density. S.sub.H2 is the integral value of a spectrum
when the standard sample is subjected to TDS analysis. Here, the
reference value of the standard sample is set to N.sub.H2/S.sub.H2.
S.sub.O2 is the integral value of a spectrum when the insulating
film is subjected to TDS analysis. .alpha. is a coefficient
affecting the intensity of the spectrum in the TDS analysis. Refer
to Japanese Published Patent Application No. H6-275697 for details
of the Formula 8. Note that the amount of released oxygen from the
above insulating film is measured with a thermal desorption
spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W, using
a silicon wafer containing hydrogen atoms at 1.times.10.sup.16
atoms/cm.sup.3 as the standard sample.
[0127] Further, in the TDS analysis, oxygen is partly detected as
an oxygen atom. The ratio between oxygen molecules and oxygen atoms
can be calculated from the ionization rate of the oxygen molecules.
Note that, since the above .alpha. includes the ionization rate of
the oxygen molecules, the amount of the released oxygen atoms can
also be estimated through the evaluation of the amount of the
released oxygen molecules.
[0128] Note that N.sub.O2 is the amount of the released oxygen
molecules. The amount of released oxygen when converted into oxygen
atoms is twice the amount of the released oxygen molecules.
[0129] In the above structure, the film from which oxygen is
released by heat treatment may be oxygen-excess silicon oxide
(SiO.sub.X (X>2)). In the oxygen-excess silicon oxide (SiO.sub.X
(X>2)), the number of oxygen atoms per unit volume is more than
twice the number of silicon atoms per unit volume. The number of
silicon atoms and the number of oxygen atoms per unit volume are
measured by Rutherford backscattering spectrometry.
[0130] Oxygen is supplied from the gate insulating layer 402 to an
oxide semiconductor film in contact with the gate insulating layer
402, whereby interface states between the oxide semiconductor film
and the gate insulating layer 402 which are in contact with each
other can be reduced. As a result, carrier trapping, occurring due
to an operation of the transistor or the like, at the interface
between the oxide semiconductor film and the gate insulating layer
402 which are in contact with each other can be suppressed, and
thus, a transistor with less deterioration in electric
characteristics can be obtained.
[0131] Further, in some cases, electric charge is generated owing
to an oxygen vacancy in the oxide semiconductor film in contact
with the gate insulating layer. In general, part of oxygen
vacancies in an oxide semiconductor film serves as a donor and
causes release of an electron which is a carrier. As a result, the
threshold voltage of a transistor shifts in the negative direction.
In view of this, when oxygen is sufficiently supplied from the gate
insulating layer 402 to the oxide semiconductor film provided in
contact with the gate insulating layer 402 and the oxide
semiconductor film provided in contact with the gate insulating
layer 402 preferably contains excess oxygen, oxygen vacancies in
the oxide semiconductor film which cause the negative shift of the
threshold voltage can be reduced.
[0132] For easier crystal growth in the oxide semiconductor film in
contact with the gate insulating layer 402, it is preferable that
the gate insulating layer 402 be sufficiently flat.
[0133] The gate insulating layer 402 may be formed to have a
single-layer or stacked-layer structure, using one or more of
silicon oxide, silicon oxynitride, silicon nitride oxide, silicon
nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium
oxide, yttrium oxide, lanthanum oxide, cesium oxide, tantalum
oxide, and magnesium oxide.
[0134] The gate insulating layer 402 is formed preferably by a
sputtering method in an oxygen gas atmosphere at a substrate
heating temperature of higher than or equal to room temperature and
lower than or equal to 200.degree. C., preferably higher than or
equal to 50.degree. C. and lower than or equal to 150.degree. C.
Note that an oxygen gas to which a rare gas is added may be used.
In that case, the percentage of the oxygen gas is higher than or
equal to 30 vol. %, preferably higher than or equal to 50 vol. %,
more preferably higher than or equal to 80 vol. %. The thickness of
the gate insulating layer 402 is greater than or equal to 100 nm
and less than or equal to 1000 nm, preferably greater than or equal
to 200 nm and less than or equal to 700 nm. Lower substrate heating
temperature at the time of film formation, higher percentage of an
oxygen gas in a film formation atmosphere, or a larger thickness of
the gate insulating layer 402 leads to a larger amount of oxygen
that is released at the time of performing heat treatment on the
gate insulating layer 402. The concentration of hydrogen in the
film can be more reduced by a sputtering method than a PCVD method.
Note that the thickness of the gate insulating layer 402 is set
such that the productivity is not reduced, although can be greater
than 1000 nm.
[0135] Then, an oxide semiconductor film 403 is formed by a
sputtering method, an evaporation method, a PCVD method, a PLD
method, an ALD method, an MBE method, or the like over the gate
insulating layer 402. The above steps correspond to the
cross-sectional view illustrated in FIG. 11A.
[0136] The thickness of the oxide semiconductor film 403 is greater
than or equal to 1 nm and less than or equal to 40 nm, preferably
greater than or equal to 3 nm and less than or equal to 20 nm. In
particular, in the case where the transistor has a channel length
of less than or equal to 30 nm and the oxide semiconductor film 403
has a thickness of around 5 nm, a short channel effect can be
suppressed and stable electric characteristics can be obtained.
[0137] In particular, when the oxide semiconductor film 403 is
formed using an In--Sn--Zn-based oxide material, a transistor
having high field-effect mobility can be obtained.
[0138] As for the oxide semiconductor film 403, a material which
has a band gap of greater than or equal to 2.5 eV, preferably
greater than or equal to 2.8 eV, more preferably greater than or
equal to 3.0 eV is selected in order to reduce the off-state
current of the transistor. With the use of the oxide semiconductor
film 403 with a band gap in the above range, the off-state current
of the transistor can be reduced.
[0139] In the oxide semiconductor film 403, preferably, hydrogen,
an alkali metal, an alkaline earth metal, and the like are reduced
and the concentration of impurities is very low. When the oxide
semiconductor film 403 contains any of the above impurities,
recombination in a band gap occurs owing to a level formed by the
impurity, so that the transistor has increased off-state
current.
[0140] Specifically, the concentration of hydrogen in the oxide
semiconductor film 403, which is measured by secondary ion mass
spectrometry (SIMS), is lower than 5.times.10.sup.19 cm.sup.-3,
preferably lower than or equal to 5.times.10.sup.18 cm.sup.-3, more
preferably lower than or equal to 1.times.10.sup.18 cm.sup.-3,
still more preferably lower than or equal to 5.times.10.sup.17
cm.sup.-3.
[0141] Further, as for alkali metal concentration in the oxide
semiconductor film 403, which is measured by SIMS, the
concentration of sodium is lower than or equal to 5.times.10.sup.16
cm.sup.-3, preferably lower than or equal to 1.times.10.sup.16
cm.sup.-3, more preferably lower than or equal to 1.times.10.sup.15
cm.sup.-3. The concentration of lithium is lower than or equal to
5.times.10.sup.15 cm.sup.-3, preferably lower than or equal to
1.times.10.sup.15 cm.sup.-3. The concentration of potassium is
lower than or equal to 5.times.10.sup.15 cm.sup.-3, preferably
lower than or equal to 1.times.10.sup.15 cm.sup.-3.
[0142] The oxide semiconductor film 403 is preferably formed by a
sputtering method in an oxygen gas atmosphere at a substrate
heating temperature of higher than or equal to 100.degree. C. and
lower than or equal to 600.degree. C., preferably higher than or
equal to 150.degree. C. and lower than or equal to 550.degree. C.,
more preferably higher than or equal to 200.degree. C. and lower
than or equal to 500.degree. C. The thickness of the oxide
semiconductor film 403 is greater than or equal to 1 nm and less
than or equal to 40 nm, preferably greater than or equal to 3 nm
and less than or equal to 20 nm. As the substrate heating
temperature at the time of film formation is higher, the impurity
concentration in the obtained oxide semiconductor film 403 is
lower. In addition, an atomic arrangement in the oxide
semiconductor film 403 is ordered, and the density thereof is
increased, so that a polycrystalline oxide semiconductor film or a
CAAC-OS film can easily be formed. Furthermore, when an oxygen gas
atmosphere is employed for the deposition, an unnecessary atom such
as a rare gas atom is not contained in the oxide semiconductor film
403, so that a polycrystalline oxide semiconductor film or a
CAAC-OS film is likely to be formed. A mixed gas atmosphere
including an oxygen gas and a rare gas may be used. In that case,
the percentage of an oxygen gas is higher than or equal to 30 vol.
%, preferably higher than or equal to 50 vol. %, more preferably
higher than or equal to 80 vol. %. As the oxide semiconductor film
403 is thinner, the short-channel effect of the transistor can be
reduced. However, when the oxide semiconductor film 403 is too
thin, the oxide semiconductor film 403 is significantly influenced
by interface scattering; thus, the field-effect mobility might be
decreased.
[0143] In the case of forming a film of an In--Sn--Zn-based oxide
as the oxide semiconductor film 403 by a sputtering method, it is
preferable to use an In--Sn--Zn--O target having an atomic ratio of
In:Sn:Zn=2:1:3, 1:2:2, 1:1:1, or 20:45:35. When the oxide
semiconductor film 403 is formed using an In--Sn--Zn--O target
having the aforementioned composition ratio, a polycrystalline
oxide semiconductor film or CAAC-OS film is easily formed.
[0144] Next, first heat treatment is performed. The first heat
treatment is performed in a reduced pressure atmosphere, an inert
atmosphere, or an oxidizing atmosphere. By the first heat
treatment, the impurity concentration in the oxide semiconductor
film 403 can be reduced. The above steps correspond to the
cross-sectional view illustrated in FIG. 11B.
[0145] The first heat treatment is preferably performed in such a
manner that heat treatment in a reduced pressure atmosphere or an
inert gas atmosphere is completed and then, the atmosphere is
changed to an oxidizing atmosphere while the temperature is kept,
and heat treatment is further performed. When the heat treatment is
performed in a reduced pressure atmosphere or an inert atmosphere,
the impurity concentration in the oxide semiconductor film 403 can
be effectively reduced; however, oxygen vacancies are caused at the
same time. By the heat treatment in the oxidizing atmosphere, the
caused oxygen vacancies can be reduced.
[0146] By performing the first heat treatment on the oxide
semiconductor film 403 in addition to the substrate heating in
deposition, the impurity levels in the film can be significantly
reduced. Accordingly, the field-effect mobility of the transistor
can be increased so as to be close to ideal field-effect mobility
to be described later.
[0147] The oxide semiconductor film 403 may be crystallized in the
following manner: oxygen ions are implanted into the oxide
semiconductor film 403, impurities such as hydrogen included in the
oxide semiconductor film 403 are released by heat treatment, and
the oxide semiconductor film 403 is crystallized through the heat
treatment or by another heat treatment performed later.
[0148] Further, the oxide semiconductor film 403 may be selectively
crystallized not by the first heat treatment but by irradiation
with a laser beam. Alternatively, it is also possible that the
oxide semiconductor film 403 is selectively crystallized by
irradiation with a laser beam while the first heat treatment is
performed. Laser beam irradiation is performed in an inert
atmosphere, an oxidizing atmosphere, or a reduced-pressure
atmosphere. When laser beam irradiation is performed, a continuous
wave (CW) laser beam or a pulsed laser beam can be used. For
example, it is possible to use a gas laser beam such as an Ar laser
beam, a Kr laser beam, or an excimer laser beam; a laser beam
using, as a medium, single crystal or polycrystalline YAG,
YVO.sub.4, forsterite (Mg.sub.2SiO.sub.4), YAlO.sub.3, or
GdVO.sub.4 doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm,
and Ta as a dopant; a solid-state laser beam such as a glass laser
beam, a ruby laser beam, an alexandrite laser beam, or a
Ti:sapphire laser beam; or a vapor laser beam emitted using one or
both of a copper vapor laser and a gold vapor laser. By irradiation
with the fundamental harmonic of such a laser beam or any of the
second harmonic to the fifth harmonic of the fundamental harmonic
of the laser beam, the oxide semiconductor film 403 can be
crystallized. Note that it is preferable to use a laser beam having
larger energy than a band gap of the oxide semiconductor film 403.
For example, a laser beam emitted from a KrF, ArF, XeCl, or XeF
excimer laser may be used. Note that the shape of the laser beam
may be linear.
[0149] Note that laser beam irradiation may be performed plural
times under different conditions. For example, it is preferable
that first laser beam irradiation is performed in a rare gas
atmosphere or a reduced-pressure atmosphere, and second laser beam
irradiation is performed in an oxidizing atmosphere because in that
case, high crystallinity can be obtained while oxygen vacancies in
the oxide semiconductor film 403 are reduced.
[0150] Then, the oxide semiconductor film 403 is processed into an
island shape by a photolithography process or the like, so that an
oxide semiconductor film 404 is formed.
[0151] Then, after a conductive film is formed over the gate
insulating layer 402 and the oxide semiconductor film 404, a source
electrode 405A and a drain electrode 405B are formed through a
photolithography process or the like. The conductive film may be
formed by a sputtering method, an evaporation method, a PCVD
method, a PLD method, an ALD method, an MBE method, or the like.
The source electrode 405A and the drain electrode 405B may be
formed as in the case of the gate electrode layer 401 to have a
single-layer structure or a stacked-layer structure using one or
more of the following materials: Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo,
Ag, Ta, and W, a nitride of any of these elements, an oxide of any
of these elements, and an alloy of any of these elements.
[0152] Then, an insulating film 406 to be an upper insulating film
is formed by a sputtering method, an evaporation method, a PCVD
method, a PLD method, an ALD method, an MBE method, or the like.
The above steps correspond to the cross-sectional view illustrated
in FIG. 11C. The insulating film 406 may be formed by a method
similar to that of the gate insulating layer 402.
[0153] A protective insulating film may be formed to be stacked
over the insulating film 406 (not illustrated). It is preferable
that the protective insulating film be a film through which oxygen
does not pass even when heat treatment at a temperature of higher
than or equal to 250.degree. C. and lower than or equal to
450.degree. C., preferably higher than or equal to 150.degree. C.
and lower than or equal to 800.degree. C. is performed for one
hour, for example.
[0154] In the case where the protective insulating film with such a
property is provided in the periphery of the insulating film 406,
oxygen released from the insulating film 406 by heat treatment can
be inhibited from diffusing toward the outside of the transistor.
Since oxygen is held in the insulating film 406 in this manner, the
field-effect mobility of the transistor can be prevented from
decreasing, variation in the threshold voltage can be reduced, and
the reliability can be improved.
[0155] The protective insulating film may be formed to have a
single-layer structure or a stacked-layer structure including at
least one of silicon nitride oxide, silicon nitride, aluminum
oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium
oxide, lanthanum oxide, cesium oxide, tantalum oxide, and magnesium
oxide.
[0156] After the insulating film 406 is formed, second heat
treatment is performed. The above steps correspond to the
cross-sectional view illustrated in FIG. 11D. The second heat
treatment is performed at a temperature of higher than or equal to
150.degree. C. and lower than or equal to 550.degree. C.,
preferably higher than or equal to 250.degree. C. and lower than or
equal to 400.degree. C. in a reduced pressure atmosphere, an inert
atmosphere, or an oxidation atmosphere. By the second heat
treatment, oxygen is released from the gate insulating layer 402
and the insulating film 406, so that oxygen vacancies in the oxide
semiconductor film 404 can be reduced. In addition, interface
states between the gate insulating layer 402 and the oxide
semiconductor film 404 and interface states between the oxide
semiconductor film 404 and the insulating film 406 can be reduced,
so that variation in threshold voltage of the transistor can be
reduced, and the reliability thereof can be improved.
[0157] Although the transistor illustrated in FIG. 11D has a bottom
gate structure, it has a structure equivalent to the structures of
the transistors illustrated in FIGS. 6A and 6B. That is, the
semiconductor region 103b overlapping with the gate 105 in FIGS. 6A
and 6B corresponds to the oxide semiconductor film 404 in FIG. 11D.
In addition, the semiconductor region 103a and the semiconductor
region 103c having n.sup.+-type conductivity in FIGS. 6A and 6B
corresponds to a contact region of the source electrode 405A and
the oxide semiconductor film 404 and a contact region of the drain
electrode 405B and the oxide semiconductor film 404 in FIG. 11D.
Thus, when interface states between the gate insulating layer 402
and the oxide semiconductor film 404 and interface states between
the oxide semiconductor film 404 and the insulating film 406 are
reduced, high field-effect mobility as in the result of the
calculation can be obtained.
[0158] The transistor including the oxide semiconductor film 404
subjected to the first heat treatment and the second heat treatment
has high field-effect mobility and a small off-state current.
Specifically, the field-effect mobility of the transistor can be
higher than or equal to 80 cm.sup.2/Vs, preferably higher than or
equal to 120 cm.sup.2/Vs, and the off-state current per micrometer
of the channel width can be lower than or equal to
1.times.10.sup.-18 A, lower than or equal to 1.times.10.sup.-21 A,
or lower than or equal to 1.times.10.sup.-24 A.
[0159] The oxide semiconductor film 404 is preferably
non-single-crystal. If operation of the transistor or light or heat
from the outside causes oxygen vacancies in the oxide semiconductor
film 404 which is completely single crystal, a carrier due to the
oxygen vacancy is generated in the oxide semiconductor film 404
owing to the absence of oxygen between lattices which compensate
the oxygen vacancy; as a result, the threshold voltage of the
transistor shifts in the negative direction in some cases.
[0160] The oxide semiconductor film 404 preferably has
crystallinity. For example, a polycrystalline oxide semiconductor
or a CAAC-OS in the oxide semiconductor film 403 is used.
[0161] Through the above-described steps, the transistor 407
illustrated in FIG. 11D can be manufactured.
[0162] As another structural example, an example in which a
channel-stop bottom gate transistor is manufactured is described
with reference to FIGS. 12A to 12D.
[0163] The transistor illustrated in FIGS. 12A to 12D is different
from the transistor in FIGS. 11A to 11D in that it includes an
insulating film 408 serving as a channel-stop film. In the
description of FIGS. 12A to 12D, description of part in common to
FIGS. 11A to 11D is omitted and for the common part, the
description of FIGS. 11A to 11D may be referred to.
[0164] Description about FIGS. 12A and 12B is similar to that about
FIGS. 11A and 11B. The insulating film 408 illustrated in FIG. 12C
can be formed in a manner similar to that of the gate insulating
layer 402 and the insulating film 406. That is, the insulating film
408 is preferably formed using an insulating film from which oxygen
is released by heat treatment.
[0165] By providing the insulating film 408 serving as a
channel-stop film, the oxide semiconductor film 404 can be
prevented from being etched when the source electrode 405A and the
drain electrode 405B are formed by a photolithography process or
the like.
[0166] Like the insulating film 406, oxygen is released from the
insulating film 408 by the second heat treatment which is performed
after the insulating film 406 illustrated in FIG. 12D is formed.
Therefore, an effect of reducing oxygen vacancies in the oxide
semiconductor film 404 can be improved. In addition, interface
states between the gate insulating layer 402 and the oxide
semiconductor film 404 and interface states between the oxide
semiconductor film 404 and the insulating film 408 can be reduced,
so that variation in threshold voltage of the transistor can be
reduced, and the reliability thereof can be improved.
[0167] Through the above-described steps, a transistor 409
illustrated in FIG. 12D can be manufactured.
[0168] FIG. 13A is a top view of the case where a channel-etched
bottom gate transistor is applied to a transistor of a pixel. FIG.
13B is a cross-sectional view taken along chain line C1-C2 in the
top view of FIG. 13A.
[0169] The cross-sectional view of FIG. 13B can be described as in
the case of the channel-etched bottom gate transistor illustrated
in FIGS. 11A to 11D. The top view of the transistor of the pixel
illustrated in FIG. 13A can also be similarly described. For
example, in a pixel portion, a signal line corresponds to the
source electrode 405A and a scan line corresponds to the gate
electrode layer 401, and a channel formation region corresponds to
the oxide semiconductor film 404. An electrode extending from the
transistor to another element corresponds to the drain electrode
405B.
[0170] As described above, the channel-etched bottom gate
transistor 407 can be applied to the transistor of the pixel.
[0171] FIG. 14A is a top view of the case where a channel-stop
bottom gate transistor is applied to a transistor of a pixel. FIG.
14B is a cross-sectional view taken along chain line C1-C2 in the
top view of FIG. 14A.
[0172] The cross-sectional view of FIG. 14B is described as in the
case of the channel-stop bottom gate transistor illustrated in
FIGS. 12A to 12D. The top view of the transistor of the pixel
illustrated in FIG. 14A can also be similarly described. For
example, in a pixel portion, a signal line corresponds to the
source electrode 405A and a scan line corresponds to the gate
electrode layer 401, and a channel formation region corresponds to
the oxide semiconductor film 404. An electrode extending from the
transistor to another element corresponds to the drain electrode
405B, and a channel-stop film corresponds to the insulating film
408.
[0173] As described above, the channel-stop bottom gate transistor
409 can be applied to the transistor of the pixel.
[0174] According to this embodiment, it is possible to provide a
highly reliable transistor having high field-effect mobility and
extremely small off-state current which includes an oxide
semiconductor and in which variation in threshold voltage is
small.
Embodiment 3
[0175] In this embodiment, a c-axis aligned crystalline oxide
semiconductor (CAAC-OS) film will be described.
[0176] The CAAC-OS film is not completely single crystal nor
completely amorphous. The CAAC-OS film is an oxide semiconductor
film with a crystal-amorphous mixed phase structure where crystal
parts and amorphous parts are included in an amorphous phase. Note
that in most cases, the crystal part fits inside a cube whose one
side is less than 100 nm. From an observation image obtained with a
transmission electron microscope (TEM), a boundary between an
amorphous part and a crystal part in the CAAC-OS film is not clear.
Further, with the TEM, a grain boundary in the CAAC-OS film is not
found. Thus, in the CAAC-OS film, a reduction in electron mobility,
due to the grain boundary, is suppressed.
[0177] In each of the crystal parts included in the CAAC-OS film, a
c-axis is aligned in a direction parallel to a normal vector of a
surface where the CAAC-OS film is formed or a normal vector of a
surface of the CAAC-OS film, atoms are arranged in a triangular or
hexagonal pattern when seen from a direction perpendicular to an
a-b plane, and metal atoms are arranged in a layered manner or
metal atoms and oxygen atoms are arranged in a layered manner when
seen from the direction perpendicular to the c-axis. Note that,
among crystal parts, the directions of the a-axis and the b-axis of
one crystal part may be different from those of another crystal
part. In this specification, a simple term "perpendicular" includes
a range from 85.degree. to 95.degree.. In addition, a simple term
"parallel" includes a range from -5.degree. to 5.degree..
[0178] In the CAAC-OS film, distribution of crystal parts is not
necessarily uniform. For example, in the formation process of the
CAAC-OS film, in the case where crystal growth occurs from a
surface side of the oxide semiconductor film, the proportion of
crystal parts in the vicinity of the surface of the oxide
semiconductor film is higher than that in the vicinity of the
surface where the oxide semiconductor film is formed in some cases.
Further, when an impurity is added to the CAAC-OS film, the crystal
part in a region to which the impurity is added becomes amorphous
in some cases.
[0179] Since the c-axes of the crystal parts included in the
CAAC-OS film are aligned in the direction parallel to a normal
vector of a surface where the CAAC-OS film is formed or a normal
vector of a surface of the CAAC-OS film, the directions of the
c-axes may be different from each other depending on the shape of
the CAAC-OS film (the cross-sectional shape of the surface where
the CAAC-OS film is formed or the cross-sectional shape of the
surface of the CAAC-OS film). Note that when the CAAC-OS film is
formed, the direction of the c-axis of the crystal part is the
direction parallel to a normal vector of the surface where the
CAAC-OS film is formed or a normal vector of the surface of the
CAAC-OS film. The crystal part is formed by deposition or by
performing treatment for crystallization such as heat treatment
after deposition.
[0180] With the use of the CAAC-OS film in a transistor, change in
electric characteristics of the transistor due to irradiation with
visible light or ultraviolet light can be reduced. Thus, the
transistor has high reliability.
[0181] The CAAC-OS film will be described in detail with reference
to FIGS. 15A to 15E, FIGS. 16A to 16C, and FIGS. 17A to 17C. In
FIGS. 15A to 15E, FIGS. 16A to 16C, and FIGS. 17A to 17C, the
vertical direction corresponds to the c-axis direction and a plane
perpendicular to the c-axis direction corresponds to the a-b plane,
unless otherwise specified. When the expressions "an upper half"
and "a lower half" are simply used, they refer to an upper half
above the a-b plane and a lower half below the a-b plane (an upper
half and a lower half with respect to the a-b plane). Furthermore,
in FIGS. 15A to 15E, O surrounded by a circle represents
tetracoordinate O and O surrounded by a double circle represents
tricoordinate O.
[0182] FIG. 15A illustrates a structure including one
hexacoordinate In atom and six tetracoordinate oxygen (hereinafter
referred to as tetracoordinate O) atoms proximate to the In atom.
Here, a structure including one metal atom and oxygen atoms
proximate thereto is referred to as a small group. The structure in
FIG. 15A is actually an octahedral structure, but is illustrated as
a planar structure for simplicity. Note that three tetracoordinate
O atoms exist in each of an upper half and a lower half in FIG.
15A. In the small group illustrated in FIG. 15A, electric charge is
0.
[0183] FIG. 15B illustrates a structure including one
pentacoordinate Ga atom, three tricoordinate oxygen (hereinafter
referred to as tricoordinate O) atoms proximate to the Ga atom, and
two tetracoordinate O atoms proximate to the Ga atom. All the
tricoordinate O atoms exist on the a-b plane. One tetracoordinate O
atom exists in each of an upper half and a lower half in FIG. 15B.
An In atom can also have the structure illustrated in FIG. 15B
because an In atom can have five ligands. In the small group
illustrated in FIG. 15B, electric charge is 0.
[0184] FIG. 15C illustrates a structure including one
tetracoordinate Zn atom and four tetracoordinate O atoms proximate
to the Zn atom. In FIG. 15C, one tetracoordinate O atom exists in
an upper half and three tetracoordinate O atoms exist in a lower
half. Alternatively, three tetracoordinate O atoms may exist in the
upper half and one tetracoordinate O atom may exist in the lower
half in FIG. 15C. In the small group illustrated in FIG. 15C,
electric charge is 0.
[0185] FIG. 15D illustrates a structure including one
hexacoordinate Sn atom and six tetracoordinate O atoms proximate to
the Sn atom. In FIG. 15D, three tetracoordinate O atoms exist in
each of an upper half and a lower half. In the small group
illustrated in FIG. 15D, electric charge is +1.
[0186] FIG. 15E illustrates a small group including two Zn atoms.
In FIG. 15E, one tetracoordinate O atom exists in each of an upper
half and a lower half. In the small group illustrated in FIG. 15E,
electric charge is -1.
[0187] Here, a plurality of small groups form a medium group, and a
plurality of medium groups form a large group (also referred to as
a unit cell).
[0188] Now, a rule of bonding between the small groups will be
described. The three O atoms in the upper half with respect to the
hexacoordinate In atom in FIG. 15A each have three proximate In
atoms in the downward direction, and the three O atoms in the lower
half each have three proximate In atoms in the upward direction.
The one O atom in the upper half with respect to the
pentacoordinate Ga atom in FIG. 15B has one proximate Ga atom in
the downward direction, and the one O atom in the lower half has
one proximate Ga atom in the upward direction. The one O atom in
the upper half with respect to the tetracoordinate Zn atom in FIG.
15C has one proximate Zn atom in the downward direction, and the
three O atoms in the lower half each have three proximate Zn atoms
in the upward direction. In this manner, the number of
tetracoordinate O atoms above a metal atom is equal to the number
of metal atoms proximate to and below the tetracoordinate O atoms;
similarly, the number of tetracoordinate O atoms below a metal atom
is equal to the number of metal atoms proximate to and above the
tetracoordinate O atoms. Since the coordination number of the
tetracoordinate O atom is 4, the sum of the number of the metal
atoms proximate to and below the O atom and the number of the metal
atoms proximate to and above the O atom is 4. Accordingly, when the
sum of the number of tetracoordinate O atoms above a metal atom and
the number of tetracoordinate O atoms below another metal atom is
4, the two kinds of small groups including the metal atoms can be
bonded. The reason will be described hereinafter. For example, in
the case where the hexacoordinate metal (In or Sn) atom is bonded
through three tetracoordinate O atoms in the lower half, it is
bonded to the pentacoordinate metal (Ga or In) atom or the
tetracoordinate metal (Zn) atom.
[0189] A metal atom whose coordination number is 4, 5, or 6 is
bonded to another metal atom through a tetracoordinate O atom in
the c-axis direction. In addition to the above, a medium group can
be formed in a different manner by combining a plurality of small
groups so that the total electric charge of the layered structure
is 0.
[0190] FIG. 16A illustrates a model of a medium group included in a
layered structure of an In--Sn--Zn-based oxide. FIG. 16B
illustrates a large group including three medium groups. Note that
FIG. 16C illustrates an atomic arrangement in the case where the
layered structure in FIG. 16B is observed from the c-axis
direction.
[0191] In FIG. 16A, a tricoordinate O atom is omitted for
simplicity, and a tetracoordinate O atom is illustrated by a
circle; the number in the circle shows the number of
tetracoordinate O atoms. For example, three tetracoordinate O atoms
existing in each of an upper half and a lower half with respect to
a Sn atom are denoted by circled 3. Similarly, in FIG. 16A, one
tetracoordinate O atom existing in each of an upper half and a
lower half with respect to an In atom is denoted by circled 1. FIG.
16A also illustrates a Zn atom proximate to one tetracoordinate O
atom in a lower half and three tetracoordinate O atoms in an upper
half, and a Zn atom proximate to one tetracoordinate O atom in an
upper half and three tetracoordinate O atoms in a lower half.
[0192] In the medium group included in the layered structure of the
In--Sn--Zn-based oxide in FIG. 16A, in the order starting from the
top, a Sn atom proximate to three tetracoordinate O atoms in each
of an upper half and a lower half is bonded to an In atom proximate
to one tetracoordinate O atom in each of an upper half and a lower
half, the In atom is bonded to a Zn atom proximate to three
tetracoordinate O atoms in an upper half, the Zn atom is bonded to
an In atom proximate to three tetracoordinate O atoms in each of an
upper half and a lower half through one tetracoordinate O atom in a
lower half with respect to the Zn atom, the In atom is bonded to a
small group that includes two Zn atoms and is proximate to one
tetracoordinate O atom in an upper half, and the small group is
bonded to a Sn atom proximate to three tetracoordinate O atoms in
each of an upper half and a lower half through one tetracoordinate
O atom in a lower half with respect to the small group. A plurality
of such medium groups are bonded, so that a large group is
formed.
[0193] Here, electric charge for one bond of a tricoordinate O atom
and electric charge for one bond of a tetracoordinate O atom can be
assumed to be -0.667 and -0.5, respectively. For example, electric
charge of a (hexacoordinate or pentacoordinate) In atom, electric
charge of a (tetracoordinate) Zn atom, and electric charge of a
(pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4,
respectively. Accordingly, electric charge of a small group
including a Sn atom is +1. Therefore, electric charge of -1, which
cancels +1, is needed to form a layered structure including a Sn
atom. As a structure having electric charge of -1, the small group
including two Zn atoms as illustrated in FIG. 15E can be given. For
example, with one small group including two Zn atoms, electric
charge of one small group including a Sn atom can be cancelled, so
that the total electric charge of the layered structure can be
0.
[0194] When the large group illustrated in FIG. 16B is repeated,
crystal of an In--Sn--Zn-based oxide (In.sub.2SnZn.sub.3O.sub.8)
can be obtained. Note that a layered structure of the obtained
crystal of an In--Sn--Zn-based oxide can be expressed as a
composition formula, In.sub.2SnZn.sub.2O.sub.7(ZnO).sub.m (m is 0
or a natural number).
[0195] The above-described rule also applies to the following
oxides: a four-component metal oxide such as an
In--Sn--Ga--Zn-based oxide; a three-component metal oxide such as
an In--Ga--Zn-based oxide (also referred to as IGZO), an
In--Al--Zn-based oxide, a Sn--Ga--Zn-based oxide, an
Al--Ga--Zn-based oxide, a Sn--Al--Zn-based oxide, an
In--Hf--Zn-based oxide, an In--La--Zn-based oxide, an
In--Ce--Zn-based oxide, an In--Pr--Zn-based oxide, an
In--Nd--Zn-based oxide, an In--Pm--Zn-based oxide, an
In--Sm--Zn-based oxide, an In--Eu--Zn-based oxide, an
In--Gd--Zn-based oxide, an In--Tb--Zn-based oxide, an
In--Dy--Zn-based oxide, an In--Ho--Zn-based oxide, an
In--Er--Zn-based oxide, an In--Tm--Zn-based oxide, an
In--Yb--Zn-based oxide, or an In--Lu--Zn-based oxide; a
two-component metal oxide such as an In--Zn-based oxide, a
Sn--Zn-based oxide, an Al--Zn-based oxide, a Zn--Mg-based oxide, a
Sn--Mg-based oxide, an In--Mg-based oxide, or an In--Ga-based
oxide; a one-component metal oxide such as an In-based oxide, a
Sn-based oxide, or a Zn-based oxide; and the like.
[0196] For example, FIG. 17A illustrates a model of a medium group
included in a layered structure of an In--Ga--Zn-based oxide
material.
[0197] In the medium group included in the layered structure of the
In--Ga--Zn-based oxide material in FIG. 17A, in the order starting
from the top, an In atom proximate to three tetracoordinate O atoms
in each of an upper half and a lower half is bonded to a Zn atom
proximate to one tetracoordinate O atom in an upper half, the Zn
atom is bonded to a Ga atom proximate to one tetracoordinate O atom
in each of an upper half and a lower half through three
tetracoordinate O atoms in a lower half with respect to the Zn
atom, and the Ga atom is bonded to an In atom proximate to three
tetracoordinate O atoms in each of an upper half and a lower half
through one tetracoordinate O atom in a lower half with respect to
the Ga atom. A plurality of such medium groups are bonded, so that
a large group is formed.
[0198] FIG. 17B illustrates a large group including three medium
groups. Note that FIG. 17C illustrates an atomic arrangement in the
case where the layered structure in FIG. 17B is observed from the
c-axis direction.
[0199] Here, since electric charge of a (hexacoordinate or
pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn
atom, and electric charge of a (pentacoordinate) Ga atom are +3,
+2, and +3, respectively, electric charge of a small group
including any of an In atom, a Zn atom, and a Ga atom is 0. As a
result, the total electric charge of a medium group having a
combination of such small groups is always 0.
[0200] In order to form the layered structure of the
In--Ga--Zn-based oxide material, a large group can be formed using
not only the medium group illustrated in FIG. 17A but also a medium
group in which the arrangement of the In atom, the Ga atom, and the
Zn atom is different from that in FIG. 17A.
[0201] This embodiment can be implemented in appropriate
combination with any of the structures described in the other
embodiments.
Embodiment 4
[0202] A display device disclosed in this specification can be
applied to a variety of electronic devices (including game
machines). Examples of electronic devices are a television set
(also referred to as a television or a television receiver), a
monitor of a computer or the like, a camera such as a digital
camera or a digital video camera, a digital photo frame, a mobile
phone handset (also referred to as a mobile phone or a mobile phone
device), a portable game console, a portable information terminal,
an audio reproducing device, a large-sized game machine such as a
pachinko machine, and the like.
[0203] FIG. 9 illustrates a television set 9600 as one example of
such electronic devices. In the television set 9600, a display
portion 9603 is incorporated in a housing 9601. The display portion
9603 can display images. Here, the housing 9601 is supported by a
stand 9605.
[0204] The television set 9600 can be operated with an operation
switch of the housing 9601 or a separate remote controller 9610.
Channels and volume can be controlled with an operation key 9609 of
the remote controller 9610 so that an image displayed on the
display portion 9603 can be controlled. Furthermore, the remote
controller 9610 may be provided with a display portion 9607 for
displaying data output from the remote controller 9610.
[0205] In the display portion 9603, a plurality of transistors
described in Embodiment 2 are provided as switching elements of
pixels, and a transistor described in Embodiment 2 is provided in a
switch circuit portion formed over the same insulating substrate as
the display portion 9603. Accordingly, the television set with a
narrow frame can be manufactured.
[0206] This embodiment can be implemented in appropriate
combination with any of the structures described in the other
embodiments.
Example 1
[0207] In this example, a crystal state of an In--Sn--Zn-based
oxide film is described.
[0208] First, X-ray diffraction (XRD) analysis of an
In--Sn--Zn-based oxide film was conducted. The XRD analysis was
conducted using an X-ray diffractometer D8 ADVANCE manufactured by
Bruker AXS, and measurement was performed by an out-of-plane
method.
[0209] Sample A and Sample B were prepared and the XRD analysis was
performed thereon. A method for manufacturing Sample A and Sample B
will be described below.
[0210] First, a quartz substrate which had been subjected to
dehydrogenation treatment was prepared.
[0211] Next, an In--Sn--Zn-based oxide film with a thickness of 100
nm was formed over the quartz substrate.
[0212] The In--Sn--Zn-based oxide film was formed with a sputtering
apparatus with a power of 100 W (DC) in an oxygen atmosphere. An
In--Sn--Zn--O target of In:Sn:Zn=1:1:1 [atomic ratio] was used as a
target. Note that the substrate heating temperature in film
formation was set at room temperature or 200.degree. C. A sample
manufactured in this manner was used as Sample A.
[0213] Next, a sample manufactured by a method similar to that of
Sample A was subjected to heat treatment at 650.degree. C. As the
heat treatment, heat treatment in a nitrogen atmosphere was first
performed for one hour and heat treatment in an oxygen atmosphere
was further performed for one hour without lowering the
temperature. A sample manufactured in this manner was used as
Sample B.
[0214] FIG. 10 shows XRD spectra of Sample A and Sample B. No peak
derived from crystal was observed in Sample A, whereas peaks
derived from crystal were observed when 20 was around 35 deg. and
at 37 deg. to 38 deg. in Sample B.
[0215] FIG. 18 and FIG. 19 are cross-sectional images of Sample B
which were obtained with a transmission electron microscope
(TEM).
[0216] FIG. 18 is a cross-sectional TEM image at a magnification of
0.5 million times, and FIG. 19 is a cross-sectional TEM image at a
magnification of 4 million times. Note that H-9000NAR manufactured
by Hitachi, Ltd was used as the TEM, and the acceleration voltage
was 300 kV.
[0217] As can be seen in FIG. 18 and FIG. 19, the In--Sn--Zn-based
oxide film of Sample B is polycrystalline, where crystals are
oriented in various directions.
[0218] This application is based on Japanese Patent Application
serial no. 2011-108664 filed with Japan Patent Office on May 13,
2011, the entire contents of which are hereby incorporated by
reference.
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