U.S. patent application number 15/201211 was filed with the patent office on 2016-10-27 for semiconductor device and method of manufacturing semiconductor device.
This patent application is currently assigned to FUJI ELECTRIC CO., LTD.. The applicant listed for this patent is FUJI ELECTRIC CO., LTD.. Invention is credited to Yuichi HARADA, Yasuyuki HOSHI, Masanobu IWAYA, Akimasa KINOSHITA, Mina RYO, Yoshiyuki SAKAI.
Application Number | 20160315186 15/201211 |
Document ID | / |
Family ID | 55162997 |
Filed Date | 2016-10-27 |
United States Patent
Application |
20160315186 |
Kind Code |
A1 |
KINOSHITA; Akimasa ; et
al. |
October 27, 2016 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR
DEVICE
Abstract
A semiconductor device includes on an n-type semiconductor
substrate of silicon carbide, an n-type semiconductor layer, a
p-type base region, an n-type source region, a p-type contact
region, a gate insulating film, a gate electrode, and a source
electrode. The semiconductor device has a drain electrode on a back
surface of the semiconductor substrate. On a surface of the gate
electrode, an interlayer insulating film is disposed. The
interlayer insulating film has plural layers among which, one layer
is formed by a silicon nitride film. With such a structure,
degradation of semiconductor device properties are suppressed.
Further, increases in the number of processes at the time of
manufacturing are suppressed.
Inventors: |
KINOSHITA; Akimasa;
(Matsumoto-city, JP) ; HOSHI; Yasuyuki;
(Matsumoto-city, JP) ; HARADA; Yuichi;
(Matsumoto-city, JP) ; SAKAI; Yoshiyuki;
(Matsumoto-city, JP) ; IWAYA; Masanobu;
(Matsumoto-city, JP) ; RYO; Mina; (Tsukuba-city,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
FUJI ELECTRIC CO., LTD. |
Kawasaki-shi |
|
JP |
|
|
Assignee: |
FUJI ELECTRIC CO., LTD.
Kawasaki-shi
JP
|
Family ID: |
55162997 |
Appl. No.: |
15/201211 |
Filed: |
July 1, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
PCT/JP2015/070336 |
Jul 15, 2015 |
|
|
|
15201211 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/0615 20130101;
H01L 29/41775 20130101; H01L 29/66068 20130101; H01L 29/7811
20130101; H01L 29/1608 20130101; H01L 29/0661 20130101; H01L 29/045
20130101; H01L 29/408 20130101; H01L 29/7815 20130101; H01L 29/1095
20130101; H01L 29/41741 20130101; H01L 29/0878 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/04 20060101 H01L029/04; H01L 29/40 20060101
H01L029/40; H01L 29/16 20060101 H01L029/16; H01L 29/66 20060101
H01L029/66; H01L 29/417 20060101 H01L029/417 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 23, 2014 |
JP |
2014-150256 |
Claims
1. A semiconductor device comprising: a semiconductor substrate of
a first conductivity type formed of silicon carbide; a
semiconductor layer of the first conductivity type, disposed on a
first principal surface of the semiconductor substrate, and having
an impurity concentration that is lower than that of the
semiconductor substrate; a base region of a second conductivity
type, disposed on a surface of the semiconductor layer; a source
region of the first conductivity type, disposed in a surface region
of the base region; a contact region of the second conductivity
type, disposed in a surface region of the base region, and having
an impurity concentration that is higher than that of the base
region; a source electrode contacting the source region and the
contact region; a gate insulating film disposed on a surface of the
base region between the semiconductor layer and the source region;
a gate electrode disposed on a surface of the gate insulating film;
an interlayer insulating film disposed on a surface of the gate
electrode and including a plurality of layers, the plurality of
layers including a silicon nitride layer; and a drain electrode
disposed on a second principal surface of the semiconductor
substrate.
2. The semiconductor device according to claim 1, wherein the
plurality of layers includes silicon oxide layers sandwiching the
silicon nitride layer.
3. The semiconductor device according to claim 2, wherein the
silicon nitride layer has a thickness equal to or greater than 0.2
.mu.m.
4. The semiconductor device according to claim 3, wherein the
silicon oxide layers that are formed on the silicon nitride layer
are formed from a silicon oxide glass containing boron and
phosphorus.
5. The semiconductor device according to claim 1, wherein the first
principal surface of the semiconductor substrate is in a plane
parallel to or tilted within 10 degrees of a plane whose a
crystallographic plane index is (000-1).
6. The semiconductor device according to claim 1, wherein the first
principal surface of the semiconductor substrate is in a plane
parallel to or tilted within 10 degrees of a plane whose
crystallographic plane index is (0001).
7. The semiconductor device according to claim 1, wherein the
silicon nitride layer is an uppermost layer of the plurality of
layers.
8. The semiconductor device according to claim 7, wherein the
silicon nitride layer has a thickness equal to or greater than 0.5
.mu.m.
9. A semiconductor device comprising: a semiconductor substrate of
a first conductivity type formed of silicon carbide; a
semiconductor layer of the first conductivity type, disposed on a
first principal surface of the semiconductor substrate, and having
an impurity concentration that is lower than that of the
semiconductor substrate; a semiconductor region of a second
conductivity type, disposed in a portion of a surface region of the
semiconductor layer; a base region disposed on a surface of the
semiconductor region and having an impurity concentration that is
lower than that of the semiconductor region; a well region of the
first conductivity type formed of a silicon carbide, disposed on
the surface of the semiconductor layer, contacting the base region,
and having an impurity concentration that is lower than that of the
semiconductor substrate; a source region of the first conductivity
type, disposed in a surface region of the base region and away from
the well region, and having an impurity concentration that is
higher than that of the well region; a contact region of the second
conductivity type, disposed in a surface of the base region and
contacting the source region, and having an impurity concentration
that is higher than that of the base region; a source electrode
contacting the source region and the contact region; a gate
insulating film disposed on a surface of the base region between
the well region and the source region; a gate electrode disposed on
a surface of the gate insulating film; an interlayer insulating
film disposed on a surface of the gate electrode and including a
plurality of layers, the plurality of layers including a silicon
nitride layer; and a drain electrode disposed on a second principal
surface of the semiconductor substrate.
10. The semiconductor device according to claim 9, wherein the
plurality of layers includes silicon oxide layers sandwiching the
silicon nitride layer.
11. The semiconductor device according to claim 10, wherein the
silicon nitride layer has a thickness equal to or greater than 0.2
.mu.m.
12. The semiconductor device according to claim 11, wherein the
silicon oxide layers that are on the silicon nitride layer are
formed from a silicon oxide glass containing boron and
phosphorus.
13. The semiconductor device according to claim 9, wherein the
first principal surface of the semiconductor substrate is in a
plane parallel to or tilted within 10 degrees of a plane whose
crystallographic plane index is (000-1).
14. The semiconductor device according to claim 9, wherein the
first principal surface of the semiconductor substrate is in a
plane parallel to or tilted within 10 degrees of a plane whose
crystallographic plane index is (0001).
15. The semiconductor device according to claim 9, wherein the
silicon nitride layer is an uppermost layer of the plurality of
layers.
16. The semiconductor device according to claim 15, wherein the
silicon nitride layer has a thickness equal to or greater than 0.5
.mu.m.
17. A method of manufacturing a semiconductor device, the method
comprising forming of silicon carbide a semiconductor substrate a
first conductivity type; forming a semiconductor layer of the first
conductivity type on a first principal surface of the semiconductor
substrate, to have an impurity concentration lower than that of the
semiconductor substrate; forming a base region of a second
conductivity type on a surface of the semiconductor layer; forming
a source region of the first conductivity type in a surface region
of the base region; forming a contact region of the second
conductivity type on a surface region of the base region, to have
an impurity concentration greater than that of the base region;
forming a source electrode contacting the source region and the
contact region; forming a gate insulating film on a surface of the
base region between the semiconductor layer and the source region;
forming a gate electrode on a surface of the gate insulating film;
forming an interlayer insulating film on a surface of the gate
electrode, including forming the interlayer insulating film to
include a plurality of layers, and forming at least one of the
plurality of layers as a silicon nitride layer; and forming a drain
electrode on a second principal surface of the semiconductor
substrate.
18. A method of manufacturing a semiconductor device, the method
comprising forming of silicon carbide a semiconductor substrate of
a first conductivity type; forming a semiconductor layer of the
first conductivity type on a first principal surface of the
semiconductor substrate, to have an impurity concentration lower
than that of the semiconductor substrate; forming a semiconductor
region of a second conductivity type in a portion of a surface
region of the semiconductor layer; forming a base region on a
surface of the semiconductor region, to have an impurity
concentration lower than that of the semiconductor region; forming
of a silicon carbide a well region of the first conductivity type,
on the surface of the semiconductor layer and contacting the base
region, to have an impurity concentration lower than that of the
semiconductor substrate; forming a source region of the first
conductivity type, in a surface region of the base region and away
from the well region, to have an impurity concentration greater
than that of the well region; forming a contact region of the
second conductivity type, in a surface of the base region and
contacting the source region, to have an impurity concentration
greater than that of the base region; forming a source electrode
contacting the source region and the contact region; forming a gate
insulating film on a surface of the base region between the well
region and the source region; forming a gate electrode formed on a
surface of the gate insulating film; forming a interlayer
insulating film on a surface of the gate electrode, including
forming the interlayer insulating film to include a plurality of
layers, and forming at least one of the plurality of layers as a
silicon nitride layer; and forming a drain electrode on a second
principal surface of the semiconductor substrate.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation application of International
Application PCT/JP2015/070336 filed on Jul. 15, 2015 which claims
priority from a Japanese Patent Application No. 2014-150256 filed
on Jul. 23, 2014, the contents of which are incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device and
a method of manufacturing a semiconductor device.
[0004] 2. Description of the Related Art
[0005] High temperature gate bias (HTGB) tests are conducted with
respect to metal oxide semiconductor field-effect transistors
(MOSFET) that use silicon carbide (SiC). In a HTGB test, voltage is
applied between a gate and a source for a long period of time in a
high temperature environment. During the HTGB test, a threshold
voltage (Vth) between the gate and source is known to decrease.
[0006] The threshold voltage decreases consequent to the diffusion
of an impurity from an external source. A method of forming, for
example, a titanium (Ti) alloy that prevents the diffusion of
impurities into the surface of the MOSFET has been disclosed to
suppress decreases in the threshold voltage (for example, refer to
Japanese Laid-Open Patent Publication No. 2012-129503). The
diffusion coefficient of a silicon nitride film is smaller than
that of a silicon oxide (SiO.sub.2) film, thus use of a silicon
nitride (SiN) film is also conceivable to prevent the diffusion of
impurities (for example, refer to Perkins, W. G., et al, "Diffusion
and Permeation of He, Ne, Ar, Kr, and D2 through Silicon Oxide Thin
Films", J. Chem. Phys., Vol. 54, No. 4, pp. 1683-1694, (1971); and
Arnoldbik, W. M., et al, "Dynamic behavior of hydrogen in silicon
nitride and oxynitride films made by low-pressure chemical vapor
deposition", Phys. Rev. B, Vol. 48, No. 8, pp. 5444-5456,
(1993)).
SUMMARY OF THE INVENTION
[0007] Nonetheless, since MOS surface structures are complicated,
when a barrier metal of a titanium alloy is formed on a MOS
structure, a portion of the barrier metal may be deficient, whereby
the threshold voltage may decrease. Further, when an electrode pad
is formed using aluminum (Al), a problem arises in that the number
of processes at the time of manufacture increases since the etching
methods differ for a titanium alloy, which forms the barrier metal,
and aluminum. Further, when a silicon nitride film is used, the
degree of hardness of the silicon nitride film is high, making the
silicon nitride film unsuitable in forming complicated surface
structures such as that of a MOS.
[0008] According to one aspect of the present invention, a
semiconductor device includes a semiconductor substrate formed of
silicon carbide of a first conductivity type; and a semiconductor
layer of the first conductivity type and having an impurity
concentration that is lower than that of the semiconductor
substrate is disposed on a first principal surface of the
semiconductor substrate. A base region of a second conductivity
type is disposed on a surface of the semiconductor layer; and a
source region of the first conductivity type is disposed in a
surface region of the base region. A contact region of the second
conductivity type and having an impurity concentration that is
higher than that of the base region is disposed in a surface region
of the base region; and a source electrode that contacts the source
region and the contact region is disposed. A gate insulating film
is disposed on a surface of the base region between the
semiconductor layer and the source region; and a gate electrode is
disposed on a surface of the gate insulating film. An interlayer
insulating film is disposed on a surface of the gate electrode; and
a drain electrode is disposed on a second principal surface of the
semiconductor substrate. The interlayer insulating film includes
plural layers and among the plural layers at least one layer that
is a first layer is formed from a silicon nitride film.
[0009] According to another aspect of the invention, a
semiconductor device includes a semiconductor substrate formed of
silicon carbide of a first conductivity type; and a semiconductor
layer of the first conductivity type is disposed on a first
principal surface of the semiconductor substrate and has an
impurity concentration that is lower than that of the semiconductor
substrate. A semiconductor region of a second conductivity type is
disposed in a portion of a surface region of the semiconductor
layer; and a base region is disposed on a surface of the
semiconductor region and has an impurity concentration that is
lower than that of the semiconductor region. A well region formed
of a silicon carbide of the first conductivity type is disposed on
the surface of the semiconductor layer, contacts the base region,
and has an impurity concentration that is lower than that of the
semiconductor substrate. A source region of the first conductivity
type is disposed in a surface region of the base region and away
from the well region, and has an impurity concentration that is
higher than that of the well region. A contact region of the second
conductivity type is disposed in a surface of the base region and
contacts the source region, and has an impurity concentration that
is higher than that of the base region. A source electrode
contacting the source region and the contact region is disposed. A
gate insulating film is disposed on a surface of the base region
between the well region and the source region; and a gate electrode
is disposed on a surface of the gate insulating film. An interlayer
insulating film is disposed on a surface of the gate electrode; and
a drain electrode is disposed on a second principal surface of the
semiconductor substrate. The interlayer insulating film includes
plural layers and among the plural layers, at least one layer that
is a first layer formed from a silicon nitride film.
[0010] Further, in the interlayer insulating film, the first layer
is sandwiched by a second layer formed from a silicon oxide
film.
[0011] Further, in the interlayer insulating film, the first layer
has a thickness of at least 0.2 .mu.m.
[0012] Further, in the interlayer insulating film, the second layer
that is on the first layer is formed from a glass in which boron
and phosphorus are added to silicon oxide.
[0013] Further, in the interlayer insulating film, the first layer
is an uppermost layer of the interlayer insulating film.
[0014] Further, in the interlayer insulating film, the first layer
has a thickness of at least 0.5 .mu.m.
[0015] Further, a crystallographic plane index (Miller index) of
the first principal surface of the semiconductor substrate is a
plane parallel to or a plane tilted within 10 degrees with respect
to a (000-1) plane.
[0016] Further, a crystallographic plane index of the first
principal surface of the semiconductor substrate is a plane
parallel to or a plane tilted within 10 degrees with respect to a
(0001) plane.
[0017] A method of manufacturing a semiconductor device according
to the present invention includes forming an interlayer insulating
film to include plural layers and among the plural layers, at least
one layer is formed from a silicon nitride film. The semiconductor
device includes a semiconductor substrate formed of silicon carbide
of a first conductivity type; a semiconductor layer of the first
conductivity type, formed on a first principal surface of the
semiconductor substrate, and having an impurity concentration that
is lower than that of the semiconductor substrate; a base region of
a second conductivity type and formed on a surface of the
semiconductor layer; a source region of the first conductivity type
and formed in a surface region of the base region; a contact region
of the second conductivity type, formed in a surface region of the
base region, and having an impurity concentration that is higher
than that of the base region; a source electrode contacting the
source region and the contact region; a gate insulating film formed
on a surface of the base region between the semiconductor layer and
the source region; a gate electrode formed on a surface of the gate
insulating film; the interlayer insulating film formed on a surface
of the gate electrode; and a drain electrode formed on a second
principal surface of the semiconductor substrate.
[0018] A method of manufacturing a semiconductor device according
to the present invention includes forming an interlayer insulating
film to include plural layers and among the plural layers, at least
one layer is formed from a silicon nitride film. The semiconductor
device includes a semiconductor substrate formed of silicon carbide
of a first conductivity type; a semiconductor layer of the first
conductivity type, formed on a first principal surface of the
semiconductor substrate, and having an impurity concentration that
is lower than that of the semiconductor substrate; a semiconductor
region of a second conductivity type and formed in a portion of a
surface region of the semiconductor layer; a base region formed on
a surface of the semiconductor region and having an impurity
concentration that is lower than that of the semiconductor region;
a well region formed of a silicon carbide of the first conductivity
type, on the surface of the semiconductor layer and contacting the
base region, and having an impurity concentration that is lower
than that of the semiconductor substrate; a source region of the
first conductivity type, formed in a surface region of the base
region and away from the well region, and having an impurity
concentration that is higher than that of the well region; a
contact region of the second conductivity type, formed in a surface
of the base region and contacting the source region, and having an
impurity concentration that is higher than that of the base region;
a source electrode contacting the source region and the contact
region; a gate insulating film formed on a surface of the base
region between the well region and the source region; a gate
electrode formed on a surface of the gate insulating film; the
interlayer insulating film formed on a surface of the gate
electrode; and a drain electrode formed on a second principal
surface of the semiconductor substrate.
[0019] The other objects, features, and advantages of the present
invention are specifically set forth in or will become apparent
from the following detailed description of the invention when read
in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a cross-sectional view of an example of a
semiconductor device according to a first embodiment of the present
invention;
[0021] FIG. 2 is a cross-sectional view of a state during
manufacture in an example of a method of manufacturing a
semiconductor device according to the first embodiment;
[0022] FIG. 3 is a cross-sectional view of a state subsequent to
the state depicted in FIG. 2;
[0023] FIG. 4 is a cross-sectional view of a state subsequent to
the state depicted in FIG. 3;
[0024] FIG. 5 is a cross-sectional view of a state subsequent to
the state depicted in FIG. 4;
[0025] FIG. 6 is a cross-sectional view of a state subsequent to
the state depicted in FIG. 5;
[0026] FIG. 7 is a property diagram of one example of threshold
voltage change characteristics for a comparative example and a
first example and a second example of the semiconductor device
according to the first embodiment and a second embodiment of the
present invention; and
[0027] FIG. 8 is a cross-sectional view of an example of a
semiconductor device according to the second embodiment of the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0028] Embodiments of a semiconductor device and a method of
manufacturing a semiconductor device according to the present
invention will be described in detail with reference to the
accompanying drawings. In the present description and accompanying
drawings, layers and regions prefixed with n or p mean that
majority carriers are electrons or holes. Additionally, + or -
appended to n or p means that the impurity concentration is higher
or lower, respectively, than layers and regions without + or -. In
the description of the embodiments below and the accompanying
drawings, identical constituent elements will be given the same
reference numerals and will not be repeatedly described. Further,
-- appended to p means that the impurity concentration is lower
than that of p-type layers and regions appended with -. Further, in
the present description, when Miller indices are described, "-"
means a bar added to an index immediately after the "-", and a
negative index is expressed by prefixing "-" to the index.
[0029] Here, although description will be given taking a 1200V
rated MOSFET as an example of the semiconductor device, the
semiconductor device according to the present invention is not
limited to a 1200V rated MOSFET. In the description and
accompanying drawings, identical components will be given the same
reference numerals and will not be redundantly described.
[0030] FIG. 1 is a cross-sectional view of an example of the
semiconductor device according to a first embodiment of the present
invention. As depicted in FIG. 1, a semiconductor device 100
according to the first embodiment has an active region 101 and an
edge termination structure 102. The edge termination structure 102
may be disposed to encompass the active region 101. The
semiconductor device 100 has an n.sup.+ semiconductor substrate 1
of silicon carbide and an n semiconductor layer 2.
[0031] The n.sup.+ semiconductor substrate 1, for example, may be a
single crystal silicon carbide substrate in which silicon carbide
is doped with nitrogen atoms (N) of an impurity concentration of
about 2.times.10.sup.18/cm.sup.3. The n.sup.+ semiconductor
substrate 1, for example, forms a drain region. A crystallographic
plane index (Miller index) of a first principal surface of the
n.sup.+ semiconductor substrate 1 may be, for example, a (000-1)
plane. The first principal surface of the n.sup.+ semiconductor
substrate 1, for example, may be a plane parallel to the (000-1)
plane, or a plane tilted 10 degrees or less. The first principal
surface of the n.sup.+ semiconductor substrate 1, for example, may
be a (000-1) plane having an OFF angle of about 4 degrees in a
<11-20> direction. In the description of the present
embodiment, a front surface of the n.sup.+ semiconductor substrate
1 is assumed as the first principal surface and a back surface is
assumed as a second principal surface.
[0032] The n semiconductor layer 2 is disposed on the first
principal surface of the n.sup.+ semiconductor substrate 1. The
impurity concentration of the n semiconductor layer 2 is lower than
that of the n.sup.+ semiconductor substrate 1. The n semiconductor
layer 2 may be, for example, a semiconductor layer in which silicon
carbide is doped with nitrogen atoms of an impurity concentration
of about 1.times.10.sup.16/cm.sup.3. The n semiconductor layer 2,
for example, forms an n-type drift layer. The thickness of the n
semiconductor layer 2 may be about 10 .mu.m, for example. The n
semiconductor layer 2 may be stacked on the n.sup.+ semiconductor
substrate 1 by an epitaxial growth method.
[0033] A structure of the active region 101 will be described. In
the active region 101, on a first principal surface side of the
n.sup.+ semiconductor substrate 1, MOS structures of the
semiconductor device 100, i.e., device structures are formed. In
the example depicted in FIG. 1, although one MOS structure is
depicted in the active region 101, multiple MOS structures may be
disposed in parallel.
[0034] The semiconductor device 100 has, for example, p.sup.+
semiconductor regions 3, p base regions 4, n.sup.+ source regions
6, p.sup.+ contact regions 7, source electrodes 13, a gate
insulating film 9, and a gate electrode 10, as MOS structures. In
the active region 101, on the second principal surface side of the
n.sup.+ semiconductor substrate 1, for example, a back surface
electrode forming a drain electrode 12 and a back surface electrode
pad forming a drain electrode pad 16 are disposed.
[0035] The p.sup.+ semiconductor regions 3 are disposed on a
portion of a surface region of the n semiconductor layer 2. The
p.sup.+ semiconductor regions 3 may be disposed, for example, to
sandwich another portion of the surface region of the n
semiconductor layer 2. The p.sup.+ semiconductor regions 3 may be,
for example, a semiconductor region where the silicon carbide is
doped with aluminum atoms of a concentration of about
3.times.10.sup.18/cm.sup.3. The width of the p.sup.+ semiconductor
regions 3 may be, for example, about 13 .mu.m. The depth of the
p.sup.+ semiconductor regions 3 may be, for example, about 0.5
.mu.m. A region between adjacent p.sup.+ semiconductor regions 3 is
a region of the n semiconductor layer 2. A distance between
adjacent p.sup.+ semiconductor regions 3 may be, for example, about
2 .mu.m.
[0036] The p base regions 4 are disposed on a surface of the
p.sup.+ semiconductor regions 3. The impurity concentration of the
p base regions 4 is lower than that of the p.sup.+ semiconductor
regions 3. The p base regions 4 may be, for example, a
semiconductor region where silicon carbide is doped with aluminum
atoms of a concentration of about 8.times.10.sup.15/cm.sup.3. The
thickness of the p base regions 4 may be, for example, about 0.5
.mu.m. The p base regions 4 may be formed by patterning a p
semiconductor layer stacked on the n semiconductor layer 2 by an
epitaxial growth method.
[0037] An n well region 8 is disposed on the surface of the n
semiconductor layer 2, at the region that is between adjacent
p.sup.+ semiconductor regions 3. The n well region 8 is disposed
contacting the p base regions 4. The impurity concentration of the
n well region 8 is lower than that of the n.sup.+ semiconductor
substrate 1. The impurity concentration of the n well region 8 may
be, for example, about 2.times.10.sup.16/cm.sup.3. The n well
region 8, for example, as described above, may be a region in which
the conductivity of a portion of the p semiconductor layer stacked
on the n semiconductor layer 2 by an epitaxial growth method is
reversed by ion implantation of phosphorus atoms and heat
treatment. Silicon atoms (Si) of a portion of the n well region 8
are replaced by the ion implanted phosphorus atoms. The n well
region 8, for example, forms the n semiconductor layer 2 and an
n-type drift region. The depth of the n well region 8 may be, for
example, about 0.6 .mu.m. The width of the n well region 8 may be,
for example, about 2 .mu.m.
[0038] The n.sup.+ source regions 6 are disposed on a surface
region of the p base regions 4 on the p.sup.+ semiconductor regions
3. The n.sup.+ source regions 6 are disposed away from the n well
region 8. The impurity concentration of the n.sup.+ source regions
6 is higher than that of the n well region 8.
[0039] The p.sup.+ contact regions 7 are disposed opposing the n
well region 8 with the p base regions 4 therebetween, i.e., is
disposed away from the n well region 8, toward the edge termination
structure 102. The p.sup.+ contact regions 7 contact the n.sup.+
source regions 6. The p.sup.+ contact regions 7, for example, as
described, penetrate the p semiconductor layer that forms the p
base regions 4 on the n semiconductor layer 2 and contacts the
p.sup.+ semiconductor regions 3. The impurity concentration of the
p.sup.+ contact regions 7 is higher than that of the p base regions
4.
[0040] The gate insulating film 9 is disposed on a surface of the p
base regions 4, at a region between the n well region 8 and the
n.sup.+ source regions 6. The gate insulating film 9, for example,
may extend from the surface of a first p base region 4 adjacent to
the n well region 8, across a surface of the n well region 8, to
the surface of a second p base region 4 adjacent to the n well
region 8 and opposing the first p base region 4 via the n well
region 8. The gate insulating film 9, for example, may extend to
the edge termination structure 102. The gate insulating film 9 may
be, for example, an oxide film. The thickness of the gate
insulating film 9 may be, for example, about 100 nm.
[0041] The gate electrode 10 is disposed on a surface of the gate
insulating film 9. The gate electrode 10, for example, may extend
from a position above the first p base region 4 and pass over the n
well region 8 to a position above the second p base region 4. The
gate electrode 10 may be formed using a conductive material. The
gate electrode 10 may be formed using, for example, polycrystalline
silicon doped with phosphorus atoms. The gate electrode 10, for
example, may be electrically connected to a gate pad in a region
not appearing in FIG. 1.
[0042] The gate electrode 10 is covered by an interlayer insulating
film 11. The interlayer insulating film 11 extends to the edge
termination structure 102 and is disposed on an entire side where
the gate electrode 10 is disposed. The interlayer insulating film
11 has a multi-layer structure and, for example, may have a silicon
oxide film 11a at a lower layer and a silicon nitride film 11b at
an upper layer. The silicon oxide film 11a, for example, may be
formed using a nondoped silicate glass (NSG) or may be formed using
a phosphor silicate glass (PSG). The thickness of the silicon oxide
film 11a may be, for example, about 0.5 .mu.m. The thickness of the
silicon nitride film 11b may be, for example, 3 .mu.m or less. The
thickness of the silicon nitride film 11b may be, for example,
about 0.5 .mu.m.
[0043] The source electrodes 13, for example, are disposed in
contact holes that penetrate the interlayer insulating film 11
disposed in the active region 101 and the edge termination
structure 102, and the gate insulating film 9 disposed in the
active region 101 and the edge termination structure 102. The
source electrodes 13 contact the n.sup.+ source regions 6 and the
p.sup.+ contact regions 7. The source electrodes 13 are
electrically connected to the n.sup.+ source regions 6 and the
p.sup.+ contact regions 7. The source electrodes 13 are insulated
from the gate electrode 10 by the interlayer insulating film
11.
[0044] The semiconductor device 100 may have a source electrode pad
14. The source electrode pad 14 is disposed so as to cover the
source electrodes 13 and the interlayer insulating film 11 in the
active region 101. The source electrode pad 14 contacts the source
electrodes 13. The source electrode pad 14 is electrically
connected to the source electrodes 13. The thickness of the source
electrode pad 14 at a portion on the interlayer insulating film 11
may be, for example, 5 .mu.m. The source electrode pad 14 may be
formed using, for example, aluminum (Al).
[0045] The drain electrode 12 is disposed on the second principal
surface of the n.sup.+ semiconductor substrate 1. The drain
electrode 12 may be formed using a conductive film, for example, a
metal film. The drain electrode 12 may be formed using, for
example, nickel (Ni). The drain electrode 12 forms an ohmic contact
with the n.sup.+ semiconductor substrate 1.
[0046] The drain electrode pad 16 is disposed on a surface of the
drain electrode 12. The drain electrode pad 16 may be formed using
a conductive film, for example, a metal film. The drain electrode
pad 16 may be formed by, for example, titanium (Ti), nickel, and
gold (Au) sequentially stacked from the drain electrode 12. The
drain electrode pad 16 is electrically connected to the drain
electrode 12.
[0047] A structure of the edge termination structure 102 will be
described. The semiconductor device 100 may have a p.sup.-
semiconductor region 5a, a p.sup.- semiconductor region 5b, and a
protective film 15 in the edge termination structure 102.
[0048] The p.sup.- semiconductor region 5a is disposed on a portion
of the surface region of the n semiconductor layer 2 in the edge
termination structure 102. The p.sup.- semiconductor region 5a
contacts, for example, the p.sup.+ semiconductor region 3. The
p.sup.- semiconductor region 5a may be disposed so as to surround
the p.sup.+ semiconductor regions 3. The p.sup.- semiconductor
region 5a may be, for example, a semiconductor region where the
silicon carbide is doped with aluminum atoms. The impurity
concentration of the p.sup.- semiconductor region 5a is lower than
that of the p+ semiconductor regions 3.
[0049] The p.sup.- semiconductor region 5b is disposed in a portion
of the surface region of the n semiconductor layer 2 in the edge
termination structure 102. The p.sup.- semiconductor region 5b
contacts, for example, the p.sup.- semiconductor region 5a. The
p.sup.- semiconductor region 5b may be disposed so as to surround
the p.sup.- semiconductor region 5a. The p.sup.- semiconductor
region 5b may be, for example, a semiconductor region in which
silicon carbide is doped with aluminum atoms. The impurity
concentration of the p.sup.- semiconductor region 5b is lower than
that of the p.sup.- semiconductor region 5a.
[0050] In this manner, by the first p.sup.- type region 5a and the
second p.sup.--type region 5b, the semiconductor device 100 may
have a double-zone junction termination extension (JTE) structure
in which two p-type regions of differing impurity concentrations
are parallel so as to contact each other. Without limitation to a
double-zone JTE structure, the semiconductor device 100 may have a
multi-zone JTE structure in which 3 or more p-type regions of
differing impurity concentrations are parallel so as to contact
each other. Further, the semiconductor device 100 may have, for
example, a termination structure in which multiple p-type regions
are disposed a predetermined interval so as to form a field
limiting ring structure.
[0051] The protective film 15 may be disposed so as to cover an
edge termination structure 102 side of the source electrode pad 14.
The protective film 15 forms a passivation film. The protective
film 15 has a function of preventing discharge. The protective film
15 may be formed of, for example, polyimide.
[0052] FIG. 2 is a cross-sectional view of a state during
manufacture in an example of the method of manufacturing a
semiconductor device according to the first embodiment. FIG. 3 is a
cross-sectional view of a state subsequent to the state depicted in
FIG. 2. FIG. 4 is a cross-sectional view of a state subsequent to
the state depicted in FIG. 3. FIG. 5 is a cross-sectional view of a
state subsequent to the state depicted in FIG. 4. FIG. 6 is a
cross-sectional view of a state subsequent to the state depicted in
FIG. 5.
[0053] As depicted in FIG. 2, the n.sup.+ semiconductor substrate 1
formed of an n-type silicon carbide is prepared. On the first
principal surface of the n.sup.+ semiconductor substrate 1, an
n-type impurity, for example, nitrogen atoms are doped while the n
semiconductor layer 2 formed of silicon carbide, for example, is
epitaxially grown to a thickness of about 10 The state up to this
point is depicted in FIG. 2.
[0054] As depicted in FIG. 3, on the surface of the n semiconductor
layer 2, a mask (not depicted) that has a predetermined opening is
formed by a photolithographic technique. A p-type impurity, e.g.,
aluminum atoms, is ion implanted, whereby as depicted by dotted
lines in FIG. 3, in a portion of a surface region of the n
semiconductor layer 2, for example, first ion implanted regions 21
having a width of about 13 .mu.m and a depth of about 0.5 .mu.m are
disposed so that, for example, a distance between adjacent first
ion implanted regions 21 is about 2 .mu.m. The first ion implanted
regions 21, for example, become the p.sup.+ semiconductor regions 3
through heat treatment described hereinafter. A dosing amount in
the ion implantation to dispose the first ion implanted regions 21,
for example, may be set so that the impurity concentration of the
p.sup.+ semiconductor regions 3 becomes about
3.times.10.sup.18/cm.sup.3.
[0055] The mask used in the ion implantation to dispose the first
ion implanted regions 21 is removed. On the surface of the n
semiconductor layer 2, a p-type impurity, for example, aluminum
atoms are doped while a second semiconductor layer 22 formed of
silicon carbide, for example, is epitaxially grown to a thickness
of about 0.5 .mu.m. The second semiconductor layer 22, for example,
becomes the p base regions 4 through a photolithographic technique
and an etching process described hereinafter. A dosing amount in
the ion implantation to dispose the second semiconductor layer 22,
for example, may be set so that the impurity concentration of the p
base regions 4 becomes about 8.times.10.sup.15/cm.sup.3. The state
up to this point is depicted in FIG. 3.
[0056] As depicted in FIG. 4, on the surface of the second
semiconductor layer 22, a mask (not depicted) that has a
predetermined opening is formed by a photolithographic technique.
An etching process is performed to pattern the second semiconductor
layer 22, whereby the p base regions 4 are formed and at a region
becoming the edge termination structure 102, the second
semiconductor layer 22, for example, is removed to a depth of about
0.7 .mu.m, exposing the n semiconductor layer 2. The mask used in
the etching process for patterning the second semiconductor layer
22 is removed.
[0057] On the exposed surface of the n semiconductor layer 2 and on
the surface of the p base regions 4, a mask (not depicted) that has
a predetermined opening is formed by a photolithographic technique.
A p-type impurity, e.g., aluminum atoms, is ion implanted, whereby
as depicted by dotted lines in FIG. 4, in a portion of the surface
region of the n semiconductor layer 2, a second ion implanted
region 23 is disposed in a region becoming the edge termination
structure 102, for example, so as to be adjacent to the first ion
implanted regions 21. The second ion implanted region 23, for
example, becomes the p.sup.- semiconductor region 5a in the
described double-zone JTE structure through the heat treatment
described hereinafter. A dosing amount in the ion implantation to
dispose the second ion implanted region 23, for example, may be set
to about 2.times.10.sup.13/cm.sup.2. The mask used in the ion
implantation to dispose the second ion implanted region 23 is
removed.
[0058] On the exposed surface of the n semiconductor layer 2 and
the surface of the p base regions 4, a mask (not depicted) that has
a predetermined opening is formed by a photolithographic technique.
A p-type impurity, e.g., aluminum atoms, is ion implanted, whereby
as depicted by dotted lines in FIG. 4, in a surface region of the n
semiconductor layer 2, a third ion implanted region 24 is disposed
in the region the edge termination structure 102, for example, so
as to contact the second ion implanted region 23. The third ion
implanted region 24, for example, becomes the p.sup.- semiconductor
region 5b in the described double-zone JTE structure through the
heat treatment described hereinafter. A dosing amount in the ion
implantation to dispose the third ion implanted region 24, for
example, may be set to about 1.times.10.sup.13/cm.sup.2. The mask
used in the ion implantation to dispose the third ion implanted
region 24 is removed. The state up to this point is depicted in
FIG. 4.
[0059] As depicted in FIG. 5, on the exposed surface of the n
semiconductor layer 2 and on the surface of the p base regions 4, a
mask (not depicted) that has a predetermined opening is formed by a
photolithographic technique. An n-type impurity, e.g., phosphorus
atoms, is ion implanted, whereby as depicted by dotted lines in
FIG. 5, in the second semiconductor layer 22, a fourth ion
implanted region 25 of, for example, a width of about 2 .mu.m and a
depth of about 0.6 .mu.m is disposed at a region above a region of
the n semiconductor layer 2 between adjacent first ion implanted
regions 21. The fourth ion implanted region 25, for example,
becomes the n well region 8 through the heat treatment described
hereinafter. A dosing amount in the ion implantation to dispose the
fourth ion implanted region 25, for example, may be set so that the
impurity concentration of the n well region 8 becomes about
2.times.10.sup.16/cm.sup.3. The mask used in the ion implantation
to dispose the fourth ion implanted region 25 is removed.
[0060] On the exposed surface of the n semiconductor layer 2 and on
the surface of the p base regions 4, a mask (not depicted) that has
a predetermined opening is formed by a photolithographic technique.
An n-type impurity is ion implanted, whereby as depicted by dotted
lines in FIG. 5, in a surface region of the second semiconductor
layer 22, fifth ion implanted regions 26 are disposed at a region
away from the fourth ion implanted region 25. The fifth ion
implanted regions 26, for example, become the n.sup.+ source
regions 6 through the heat treatment described hereinafter. A
dosing amount in the ion implantation to dispose the fifth ion
implanted regions 26 may be set so that the impurity concentration
becomes higher than that of the fourth ion implanted region 25. The
mask used in the ion implantation to dispose the fifth ion
implanted regions 26 is removed.
[0061] On the exposed surface of the n semiconductor layer 2 and on
the surface of the p base regions 4, a mask (not depicted) that has
a predetermined opening is formed by a photolithographic technique.
A p-type impurity is ion implanted, whereby as depicted by dotted
lines in FIG. 5, in the second semiconductor layer 22, a sixth ion
implanted region 27 is disposed in each region above a first ion
implanted region 21 and contacting a p base region 4 and a fifth
ion implanted region 26. The sixth ion implanted regions 27, for
example, become the p.sup.+ contact regions 7 through the heat
treatment described hereinafter. A dosing amount in the ion
implantation to dispose the sixth ion implanted regions 27 may be
set so that the impurity concentration becomes higher than that of
the p base regions 4. The mask used in the ion implantation to
dispose the sixth ion implanted regions 27 is removed.
[0062] The sequence of the ion implantations to dispose the second
ion implanted region 23, the third ion implanted region 24, the
fourth ion implanted region 25, the fifth ion implanted regions 26,
and the sixth ion implanted regions 27 is not limited hereto and
may be modified. The state up to this point is depicted in FIG.
5.
[0063] As depicted in FIG. 6, heat treatment (annealing) is
performed to activate, for example, the first ion implanted regions
21, the second ion implanted region 23, the third ion implanted
region 24, the fourth ion implanted region 25, the fifth ion
implanted regions 26, and the sixth ion implanted regions 27. As a
result, the first ion implanted regions 21 become the p.sup.+
semiconductor regions 3. Ion implanted phosphorus atoms replace
silicon atoms to reverse the conductivity type whereby the fourth
ion implanted region 25 becomes the n well region 8. The fifth ion
implanted regions 26 become the n.sup.+ source regions 6. The sixth
ion implanted regions 27 become the p.sup.+ contact regions 7. The
second ion implanted region 23 becomes the p.sup.- semiconductor
region 5a. The third ion implanted region 24 becomes the p.sup.-
semiconductor region 5b. The temperature of the heat treatment, for
example, may be about 1620 degrees C. The period of the heat
treatment, for example, may be about 2 minutes. As described, the
ion implanted regions may be collectively activated by performing
heat treatment once or heat treatment may be performed each time
ion implantation is performed.
[0064] The surface of the side on which the p base regions 4, the
n.sup.+ source regions 6, the p.sup.+ contact regions 7, the n well
region 8, the p.sup.- semiconductor region 5a, and the p.sup.-
semiconductor region 5b are disposed is thermally oxidized, for
example, to dispose on the entire surface, for example, the gate
insulating film 9 having a thickness of about 100 nm. This thermal
oxidation process, for example, may be implemented by heat
treatment performed in an oxygen atmosphere, for example, at about
1000 degrees C.
[0065] On the gate insulating film 9, for example, a polysilicon
layer doped with phosphorus atoms is disposed. The polysilicon
layer is patterned so that a portion remains on the gate insulating
film 9, where the gate insulating film 9 is above a portion of a p
base region 4, between an n.sup.+ source region 6 and the n well
region 8, whereby the gate electrode 10 is disposed.
[0066] For example, nondoped silicate glass (NSG) or phosphor
silicate glass (PSG) is deposited so as to cover the gate
insulating film 9 and the gate electrode 10 and have a thickness
of, for example, about 0.5 .mu.m, whereby the silicon oxide film
11a forming the lower layer of the interlayer insulating film 11 is
disposed. Silicon nitride is deposited so as to cover the silicon
oxide film 11a and have a thickness of, for example, about 0.5
.mu.m, whereby the silicon nitride film 11b forming the upper layer
of the interlayer insulating film 11 is disposed. The interlayer
insulating film 11 is formed by the silicon oxide film 11a and the
silicon nitride film 11b. For example, the silicon nitride film 11b
may be deposited by a plasma chemical vapor deposition (CVD)
method. The state up to this point is depicted in FIG. 6.
[0067] As depicted in FIG. 1, the silicon nitride film 11b, the
silicon oxide film 11a, and the gate insulating film 9 are
patterned and selectively removed, whereby a contact hole is
formed, exposing the n.sup.+ source regions 6 and the p.sup.+
contact regions 7. Thereafter, heat treatment (reflow) is performed
and the interlayer insulating film 11 is planarized.
[0068] Inside the contact hole and on the interlayer insulating
film 11, a conductive film to become the source electrodes 13 is
disposed. The conductive film is selectively removed so that, for
example, only the source electrodes 13 inside the contact hole
remains.
[0069] On the second principal surface of the n.sup.+ semiconductor
substrate 1, for example, the drain electrode 12 formed by a nickel
film is disposed. Thereafter, for example, heat treatment is
performed at about 970 degrees C. to ohmically bond the n.sup.+
semiconductor substrate 1 and the drain electrode 12.
[0070] Subsequently, for example, an aluminum (Al) film is disposed
by a sputtering method so as to cover the source electrodes 13 and
the interlayer insulating film 11 and at a portion above the
interlayer insulating film 11, have a thickness of, for example,
about 5 .mu.m. Thereafter, the Al film is selectively removed so
that a portion remains covering the interlayer insulating film 11
at the source electrodes 13 and the active region 101, to form the
source electrode pad 14.
[0071] In the region becoming the edge termination structure 102,
the protective film 15 formed of, for example, polyimide is
disposed so as to cover an end of the source electrode pad 14, on
the edge termination structure 102 side.
[0072] On the surface of the drain electrode 12, for example,
titanium, nickel, and gold are sequentially stacked, whereby the
drain electrode pad 16 is disposed. Thus, as described, the
semiconductor device 100 depicted in FIG. 1 is completed.
[0073] The semiconductor device 100 in which the interlayer
insulating film 11 is formed by the lower-layer silicon oxide film
11a and the upper-layer silicon nitride film 11b is assumed as a
first example. A semiconductor device where in the semiconductor
device 100, the interlayer insulating film 11 is formed by only a
silicon oxide film is assumed as a comparative example.
[0074] Threshold voltage (Vth) change (.DELTA.Vth) was evaluated
for the first example and the comparative example. In the
evaluation, .DELTA.Vth was defined as the difference of the initial
threshold voltage value and the threshold voltage value after -20V
was applied between the gate and the source for 10 minutes at 200
degrees C. Results of the .DELTA.Vth evaluation are discussed. FIG.
7 is a property diagram of one example of threshold voltage change
characteristics for the comparative example and the first example
and a second example of the semiconductor device according to the
first embodiment and a second embodiment of the present invention.
In FIG. 7, the vertical axis represents changes .DELTA.Vth in the
threshold voltage Vth (V) and the horizontal axis represents the
thickness of the silicon nitride film (.mu.m). In the comparative
example, the thickness of the silicon nitride film is zero. As
depicted in FIG. 7, although the evaluation results indicate
.DELTA.Vth to be at least -11V for the comparative example, it was
confirmed that in the first example, .DELTA.Vth improved to a
greater extent than in the comparative example. Further, it was
confirmed that when the thickness of the silicon nitride film 11b
was 0.5 .mu.m or greater, .DELTA.Vth was improved to -0.1V or
less.
[0075] According to the first embodiment, disposal of the silicon
nitride film 11b in the interlayer insulating film 11 prevents
element diffusion into the interface of the silicon oxide film and
semiconductor, a cause of the threshold voltage decreases, and
consequently, threshold voltage decreases are suppressed. As a
result, property degradation of the semiconductor device 100 can be
suppressed. Further, according to the first embodiment, for
example, drops in reliability according to reliability tests such
as high temperature gate bias (HTGB) tests can be avoided.
According to the first embodiment, since the silicon oxide film
11a, which provides better coverage than the silicon nitride film
11b, is the layer below the silicon nitride film 11b, the coverage
of the interlayer insulating film 11 is improved, enabling problems
such as cracking to be avoided. Therefore, a function as an
interlayer insulating film of a MOS structure is achieved and
threshold voltage variation can be improved. Further, according to
the first embodiment, since a titanium alloy barrier metal is
unnecessary, apart from etching for the source electrode pad 14,
additional etching for a titanium alloy need not be performed,
enabling an increase in the number of processes at the time of
manufacture to be suppressed.
[0076] FIG. 8 is a cross-sectional view of an example of a
semiconductor device according to the second embodiment of the
present invention. As depicted in FIG. 8, a semiconductor device
200 according to the second embodiment has as the interlayer
insulating film 11, the silicon oxide film 11a as a lower layer,
the silicon nitride film 11b as an intermediate layer, and a second
silicon oxide film 11c as an uppermost layer. Although the
interlayer insulating film 11 may have a structure of 4 or more
layers, in the second embodiment, description will be given for a
3-layer structure.
[0077] The second silicon oxide film 11c may be formed from, for
example, nondoped silicate glass (NSG), or phosphor silicate glass
(PSG). The second silicon oxide film 11c may be formed from, for
example, boron and phosphorous in a silicon oxide (Boro-Phospho
Silicate Glass (BPSG)). When the second silicon oxide film 11c is
formed from BPSG, an effect may be achieved in that optimal
planarization is realized by reflow.
[0078] In the semiconductor device 200 according to the second
embodiment, components identical to those of the semiconductor
device 100 described in the first embodiment are given the same
reference numeral used in the first embodiment and will not be
redundantly described.
[0079] Similar to the method of manufacturing the semiconductor
device 100 according to the first embodiment, according to the
second embodiment, the gate electrode 10 is disposed and after the
silicon oxide film 11a forming the lower layer and the silicon
nitride film 11b forming the intermediate layer in the interlayer
insulating film 11 are disposed, the second silicon oxide film 11c
forming the uppermost layer is formed. Thus, the interlayer
insulating film 11 formed by the silicon oxide film 11a, the
silicon nitride film 11b, and the second silicon oxide film 11c is
formed.
[0080] The second silicon oxide film 11c, the silicon nitride film
11b, the silicon oxide film 11a, and the gate insulating film 9 are
patterned and selectively removed, whereby a contact hole is
formed, exposing the n.sup.+ source regions 6 and the p.sup.+
contact regions 7. Thereafter, heat treatment (reflow) is performed
and the interlayer insulating film 11 is planarized. The method
hereafter is identical to the method of manufacturing the
semiconductor device 100 according to the first embodiment and
therefore, redundant description is omitted herein.
[0081] The semiconductor device 200 in which the interlayer
insulating film 11 is formed by the lower-layer silicon oxide film
11a, the intermediate-layer silicon nitride film 11b, and the
uppermost-layer second silicon oxide film 11c is assumed as the
second example. A semiconductor device where in the semiconductor
device 200, the interlayer insulating film 11 is formed by only a
silicon oxide film is assumed as a comparative example. The
comparative example in the second embodiment is identical to the
comparative example in the first embodiment.
[0082] Threshold voltage (Vth) change (.DELTA.Vth) was evaluated
for the second example and the comparative example. In the
evaluation, .DELTA.Vth was defined as the difference of the initial
threshold voltage and the threshold voltage value after -20V was
applied between the gate and the source for 10 minutes at 200
degrees C. As depicted in FIG. 7, the evaluation results confirm
that in the second example, .DELTA.Vth improved to a greater extent
that in the comparative example. Further, it was confirmed that
when the thickness of the silicon nitride film 11b was 0.2 .mu.m or
greater, .DELTA.Vth was improved to -0.1V or less.
[0083] According to the second embodiment, similar to the first
embodiment, disposal of the silicon nitride film 11b in the
interlayer insulating film 11 suppressed threshold voltage
decreases, enabling property degradation of the semiconductor
device 200 to be suppressed. Further, according to the second
embodiment, similar to the first embodiment, drops in reliability
according to reliability tests can be avoided. According to the
second embodiment, similar to the first embodiment, disposal of the
silicon oxide film 11a in the interlayer insulating film 11 enables
a function as an interlayer insulating film of a MOS structure to
be achieved and threshold voltage variation to be improved.
Further, according to the second embodiment, similar to the first
embodiment, since a titanium alloy barrier metal is unnecessary, an
increase in the number of processes at the time of manufacture may
be suppressed.
[0084] The present invention is not limited to the embodiments
above and various modifications are possible. For example, the
plane orientation of the first principal surface of the n.sup.+
semiconductor substrate 1 and the like may be changed. For example,
the first principal surface of the n.sup.+ semiconductor substrate
1 may be a plane that is parallel to a (0001) plane or a plane that
is within 10 degrees with respect to a (0001) plane, for example, a
(0001) plane having an off angle of 4 degrees in a <11-20>
direction. For example, dimensions, concentrations, and the like
described in the embodiments are examples and the present invention
is not limited to these values. Further, in the embodiments,
although a first conductivity is assumed as an n-type and a second
conductivity type is assumed as a p-type, the present invention is
applicable when the first conductivity is a p-type and the second
conductivity is an n-type.
[0085] According to the present invention, in the interlayer
insulating film, the layer formed of a silicon nitride film
prevents element diffusion, which causes the threshold voltage at
the interface of the silicon oxide film and the semiconductor to
decrease. Thus, drops in the threshold voltage are suppressed.
[0086] Although a silicon nitride film has a high degree of
hardness, making coverage thereof poorer than that of a silicon
oxide film and making the silicon nitride film susceptible to
cracking, as described, a silicon oxide film is disposed in a layer
beneath the silicon nitride film, whereby the coverage is improved
and problems such as cracking are avoided. Further, variation of
the threshold voltage is reduced as compared to a case where in the
interlayer insulating film, the layer formed by the silicon nitride
film has a thickness that is less than 0.2 .mu.m.
[0087] According to the present invention, threshold voltage
decreases and degradation of semiconductor device properties can be
suppressed. Further, increases in the number of processes at the
time of manufacturing can be suppressed.
[0088] As described, a semiconductor device according to the
present invention, for example, is useful in high-voltage
semiconductor devices and is particularly suitable, for example, in
high-voltage semiconductor devices used in power source devices
such as power converters and various industrial machinery.
[0089] Although the invention has been described with respect to a
specific embodiment for a complete and clear disclosure, the
appended claims are not to be thus limited but are to be construed
as embodying all modifications and alternative constructions that
may occur to one skilled in the art which fairly fall within the
basic teaching herein set forth.
* * * * *