U.S. patent application number 14/675100 was filed with the patent office on 2016-10-06 for multichannel receiver.
The applicant listed for this patent is Alcatel-Lucent USA Inc.. Invention is credited to Walter Honcharenko, Boris A. Kurchuk.
Application Number | 20160294591 14/675100 |
Document ID | / |
Family ID | 57015447 |
Filed Date | 2016-10-06 |
United States Patent
Application |
20160294591 |
Kind Code |
A1 |
Kurchuk; Boris A. ; et
al. |
October 6, 2016 |
MULTICHANNEL RECEIVER
Abstract
An embodiment of the disclosed multichannel receiver may use a
single master clock to generate (i) the sampling-clock signal that
sets the sampling rate of the receiver's ADC and (ii) multiple
electrical local-oscillator signals that are used in various
channels of the receiver's analog down-converter to translate to
intermediate frequency the RF signals received on the receiver's
array of antennas. The multichannel receiver may employ a plurality
of interconnected frequency dividers configured to variously divide
the master-clock frequency to generate the sampling-clock signal
and the multiple local-oscillator signals in a manner that causes
these signals to have different respective frequencies.
Inventors: |
Kurchuk; Boris A.;
(Bridgewater, NJ) ; Honcharenko; Walter; (Monmouth
Junction, NJ) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Alcatel-Lucent USA Inc. |
Murray Hill |
NJ |
US |
|
|
Family ID: |
57015447 |
Appl. No.: |
14/675100 |
Filed: |
March 31, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H04L 7/0008 20130101;
H03M 1/124 20130101; H04B 1/1036 20130101; H04B 1/10 20130101; H04B
1/06 20130101 |
International
Class: |
H04L 27/22 20060101
H04L027/22; H03M 1/12 20060101 H03M001/12 |
Claims
1. An apparatus comprising: a plurality of mixers, each one of the
plurality of mixers being configured to mix a respective one of a
plurality of electrical radio-frequency (RF) signals and a
respective one of a plurality of electrical local-oscillator (LO)
signals to generate a respective one of a plurality of electrical
intermediate-frequency (IF) signals, each electrical LO signal of
the plurality of LO signals having a different frequency; an
analog-to-digital converter (ADC) configured to convert the
electrical IF signals into a corresponding digital IF signal
carrying a sequence of discrete digital samples generated by the
ADC at a sampling rate determined by a sampling-clock signal; and a
plurality of frequency dividers configured to frequency divide a
master-clock signal to generate the sampling-clock signal and the
plurality of electrical LO signals of different frequencies.
2. The apparatus of claim 1, further comprising a first clock
generator configured to generate the master-clock signal.
3. The apparatus of claim 2, further comprising: a second clock
generator configured to generate a digital reference-clock signal;
and a digital down-converter configured to digitally translate the
digital IF signal to baseband using the digital reference-clock
signal; and wherein the first clock generator is configured to
generate the master-clock signal in response to receiving the
digital reference-clock signal.
4. The apparatus of claim 3, wherein the digital down-converter is
a part of a digital signal processor configured to process the
digital IF signal to recover data encoded in the plurality of
electrical RF signals.
5. The apparatus of claim 3, wherein the digital down-converter
comprises: a plurality of numerically controlled oscillators
configured to generate a plurality of digital LO signals in
response to receiving the digital reference-clock signal; and a
plurality of digital mixers, each configured to mix a respective
portion of the digital IF signal and a respective one of the
plurality of digital LO signals to generate a respective one of a
plurality of digital baseband signals.
6. The apparatus of claim 1, wherein the plurality of frequency
dividers comprises two or more frequency dividers, with each of
said two or more frequency dividers being configured to receive a
respective copy of the master-clock signal and further configured
to frequency divide the master-clock signal using a respective
division factor.
7. The apparatus of claim 1, wherein the plurality of frequency
dividers comprises two or more frequency dividers that are serially
connected to one another in a manner that causes a following one of
the two or more frequency dividers to divide a frequency generated
by a preceding one of the two or more frequency dividers.
8. The apparatus of claim 1, wherein the apparatus is configured to
combine said plurality of electrical IF signals to generate a
combined electrical IF signal; and wherein the ADC is configured to
convert the combined electrical IF signal into said corresponding
digital IF signal carrying said sequence of discrete digital
samples generated by the ADC at the sampling rate determined by the
sampling-clock signal.
9. The apparatus of claim 8, wherein the plurality of frequency
dividers are further configured to divide the frequency of the
master-clock signal in a manner that causes the sampling-clock
signal to have a frequency that is different from any LO frequency
in the plurality of electrical LO signals.
10. The apparatus of claim 1, wherein the plurality of frequency
dividers are configured to frequency divide the master-clock signal
in a manner that causes the sampling-clock signal to have a
frequency that is different from any LO frequency in the plurality
of electrical LO signals.
11. The apparatus of claim 1, wherein each frequency divider of the
plurality of frequency dividers is configured to produce a
respective one of the electrical LO signals with a respective LO
frequency such that a frequency of the master-clock signal is an
integer multiple of the respective LO frequency.
12. The apparatus of claim 11, wherein the frequency dividers are
configured to use integer frequency-division factors to frequency
divide the master-clock signal, wherein a set of the integer
frequency-division factors includes two or more consecutive
integers.
13. The apparatus of claim 1, wherein each frequency divider of the
plurality of frequency dividers is configured to produce a
respective one of the electrical LO signals with a respective LO
frequency such that a frequency of the master-clock signal is equal
to the respective LO frequency multiplied by a mixed fractional
value.
14. The apparatus of claim 1, further comprising a receiver having
an array of antennas; and wherein each of the antennas is
configured to generate the respective one of the plurality of
electrical RF signals based on an electrical input provided by a
corresponding antenna.
15. The apparatus of claim 1, wherein the multichannel
down-converter is an analog electrical circuit.
16. An apparatus comprising: a first mixer configured to mix a
first electrical radio-frequency (RF) signal and a first electrical
local-oscillator (LO) signal to generate a first electrical
intermediate-frequency (IF) signal; an analog-to-digital converter
(ADC) configured to convert the first electrical IF signal into a
corresponding digital IF signal carrying a sequence of discrete
digital samples generated by the ADC at a sampling rate determined
by a sampling-clock signal; a first clock generator configured to
generate a master-clock signal; a first frequency divider
configured to frequency divide the master-clock signal to generate
the first electrical LO signal; and a second frequency divider
configured to frequency divide the master-clock signal to generate
the sampling-clock signal.
17. The apparatus of claim 16, wherein the first electrical LO
signal and the sampling-clock signal have different respective
frequencies.
18. The apparatus of claim 16, further comprising: a second mixer
configured to mix a second electrical RF signal and a second
electrical LO signal to generate a second electrical IF signal,
wherein the ADC is further configured to convert the second
electrical IF signal into a corresponding portion of the digital IF
signal; and the apparatus further comprises a third frequency
divider configured to frequency divide the master-clock signal to
generate the second electrical LO signal.
19. The apparatus of claim 18, wherein the first electrical LO
signal and the second electrical LO signal have different
respective frequencies.
20. The apparatus of claim 16, further comprising: a second clock
generator configured to generate a digital reference-clock signal;
and a digital down-converter configured to digitally translate the
digital IF signal to baseband using the digital reference-clock
signal; and wherein the first clock generator is configured to
generate the master-clock signal in response to receiving the
digital reference-clock signal.
Description
BACKGROUND
[0001] 1. Field
[0002] The present disclosure relates to communication equipment
and, more specifically but not exclusively, to radio-frequency (RF)
receivers.
[0003] 2. Description of the Related Art
[0004] This section introduces aspects that may help facilitate a
better understanding of the disclosure. Accordingly, the statements
of this section are to be read in this light and are not to be
understood as admissions about what is in the prior art or what is
not in the prior art.
[0005] Recent development of very high-speed, high-resolution, and
high-dynamic-range linear analog-to-digital converters (ADCs)
enables implementation of certain RF-receiver functions using a
digital signal processor (DSP) instead of the analog RF hardware
conventionally used for these purposes in the previous generation
of RF receivers. However, the use of wider bandwidths, multiple
spectral bands, and/or spectrum sharing introduces new challenges
to the receiver design.
SUMMARY OF SOME SPECIFIC EMBODIMENTS
[0006] Whereas multichannel-receiver architectures often need local
oscillator (LO) signals in multiple spectral bands, a phase-lock
loop (PLL) for providing a LO signal is a relatively complex
circuit. Such a circuit can take up a relatively large chip area
and/or consume considerable power. In addition, a PLL may result in
an increased level of electromagnetic interference (EMI), ground
bouncing, frequency pulling, and other deleterious effects that
tend to degrade the overall receiver performance.
[0007] An embodiment of a disclosed multichannel receiver may use a
single master clock to generate (i) the sampling-clock signal that
sets the sampling rate of the receiver's ADC and (ii) multiple
electrical local-oscillator signals that are used in various
channels of the receiver's analog down-converter to translate to
intermediate frequency the RF signals received on the receiver's
array of antennas. The multichannel receiver may employ a plurality
of interconnected frequency dividers configured to variously divide
the master-clock frequency to generate the sampling-clock signal
and the multiple local-oscillator signals in a manner that causes
these signals to have different respective frequencies. The use of
a single master clock may advantageously enable the multichannel
receiver to have a smaller size, consume less power, and exhibit
lower levels of phase noise and EMI than conventional receivers
that rely on multiple PLLs to generate sampling-clock and
local-oscillator signals.
[0008] According to one embodiment, a multichannel receiver
comprises: a plurality of mixers, each one of the plurality of
mixers being configured to mix a respective one of a plurality of
electrical RF signals and a respective one of a plurality of
electrical LO signals to generate a respective one of a plurality
of electrical intermediate-frequency (IF) signals, each electrical
LO signal of the plurality of LO signals having a different
frequency; an ADC configured to convert the electrical IF signals
into a corresponding digital IF signal carrying a sequence of
discrete digital samples generated by the ADC at a sampling rate
determined by a sampling-clock signal; and a plurality of frequency
dividers configured to frequency divide a master-clock signal to
generate the sampling-clock signal and the plurality of electrical
LO signals of different frequencies.
[0009] According to another embodiment, a receiver comprises: a
first mixer configured to mix a first electrical RF signal and a
first electrical LO signal to generate a first electrical IF
signal; an ADC configured to convert the first electrical IF signal
into a corresponding digital IF signal carrying a sequence of
discrete digital samples generated by the ADC at a sampling rate
determined by a sampling-clock signal; a first clock generator
configured to generate a master-clock signal; a first frequency
divider configured to frequency divide the master-clock signal to
generate the first electrical LO signal; and a second frequency
divider configured to frequency divide the master-clock signal to
generate the sampling-clock signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Other aspects, features, and benefits of various disclosed
embodiments will become more fully apparent, by way of example,
from the following detailed description and the accompanying
drawings, in which:
[0011] FIG. 1 shows a block diagram of an RF receiver according to
one embodiment;
[0012] FIG. 2 shows a block diagram of a DSP that can be used in an
embodiment of the RF receiver shown in FIG. 1;
[0013] FIGS. 3A-3E graphically illustrate the operation of an
example embodiment of the RF receiver shown in FIG. 1 employing the
DSP shown in FIG. 2;
[0014] FIG. 4 shows a block diagram of a divider circuit that can
be used in an alternative embodiment of the RF receiver shown in
FIG. 1; and
[0015] FIG. 5 shows a block diagram of an RF receiver according to
an alternative embodiment.
DETAILED DESCRIPTION
[0016] FIG. 1 shows a block diagram of a radio-frequency (RF)
receiver 100 according to one embodiment. Receiver 100 is
illustratively shown in FIG. 1 as having n channels, where n is a
positive integer greater than or equal to two. A person of ordinary
skill in the art will understand that engineering constraints may
impose an upper limit on the maximum number of channels that an
embodiment of receiver 100 can have in practice. Various
embodiments of receiver 100 may be used in cellular base stations
and/or user equipment compatible with carrier-aggregation (CA) and
multiple-input/multiple-output (MIMO) signal-transmission
technologies.
[0017] Receiver 100 comprises an array of antennas
102.sub.1-102.sub.n, each coupled to a respective one of RF
front-end (FE) circuits 106.sub.1-106.sub.n. In operation, each
antenna 102.sub.i converts a received electromagnetic wave into a
corresponding electrical RF signal 104.sub.i, where i=1, 2, . . . ,
n. Each FE circuit 106.sub.i then transforms electrical signal
104.sub.i generated by antenna 102.sub.i into a corresponding
electrical RF signal 108.sub.i more suitable for down-conversion to
intermediate frequency (IF) in a multichannel down-converter 110.
In an example embodiment, the signal transformation performed in FE
circuit 106.sub.i may include, but is not limited to (i) signal
amplification to compensate for transmission losses and (ii)
rejection of possible out-of-band noise and interference. These
operations can be achieved, e.g., as known in the art, using one or
more low-noise amplifiers (LNAs) and one or more filter stages,
respectively (not explicitly shown in FIG. 1).
[0018] Multichannel down-converter 110 includes a plurality of
mixers 112.sub.1-112.sub.n, each configured to mix the
corresponding one of electrical signals 108.sub.1-108.sub.n with a
corresponding one of electrical local-oscillator (LO) signals
116.sub.1-116.sub.n. Each of the resulting translated electrical
signals 118.sub.1-118.sub.n may optionally be filtered in a
respective band-pass filter (not explicitly shown in FIG. 1) and
then combined, in a signal combiner 120, with the other translated
electrical signals 118 to generate a combined electrical signal
124. An anti-aliasing filter 130 then passes through a useful
portion of combined electrical signal 124 while rejecting the
unwanted signal components. A resulting filtered electrical signal
132 generated by filter 130 is applied to an analog-to-digital
converter (ADC) 140. The frequencies of LO signals
116.sub.1-116.sub.n and the characteristics of anti-aliasing filter
140 are selected such that electrical signal 132 is an IF signal
located within a designated IF band.
[0019] In an example embodiment, ADC 140 is an RF-sampling ADC
(RF-ADC) that has a relatively high resolution and a relatively
high dynamic range, and is capable of sampling IF signal 132 at a
sampling rate that is higher, by at least a factor of two, than the
bandwidth of this IF signal. RF-ADCs that can be used as ADC 140
are commercially available from several vendors. For example, Texas
Instruments Inc. and Analog Devices Inc. offer for sale two
families of direct RF-sampling ADCs under the product codes
ADC32RFXX and AD96XX, respectively. A person of ordinary skill in
the art will be able to select, from those two families, a suitable
ADC for use in an embodiment of receiver 100.
[0020] A digital electrical signal 142 generated by ADC 140 is
applied to a digital signal processor (DSP) 150 configured to
recover the data encoded in the electromagnetic wave received by
antennas 102.sub.1-102.sub.n. The digital signal processing
implemented in DSP 150 may include, but is not limited to (i)
digital down-conversion from the designated IF band to baseband,
(ii) digital filtering, and (iii) data decoding. The recovered data
are directed to external circuits via an electrical output signal
152.
[0021] LO signals 116.sub.1-116.sub.n and a sampling-clock signal
138 that clocks ADC 140 are generated using a master-clock
generator 160. More specifically, master-clock generator 160 is
configured to generate a master-clock signal 162 having a
relatively high frequency (see example values given in the text
below), sufficiently low jitter, and sufficiently fast slew rate.
In an example embodiment, master-clock generator 160 may be
implemented using a PLL. The output of the voltage-controlled
oscillator (VCO) in the PLL may be buffered, e.g., as known in the
art, to cause master-clock signal 162 to have the aforementioned
desired characteristics.
[0022] A plurality of frequency dividers 170.sub.0-170.sub.n are
configured to variously divide the frequency of master-clock signal
162 to generate divided-frequency signals 172.sub.0-172.sub.n,
respectively. Each of divided-frequency signals 172.sub.0-172.sub.n
typically has multiple frequency components that include a
respective main divided frequency and also higher harmonics and/or
sub-harmonics of the main divided frequency. The main divided
frequency in a divided-frequency signal 172.sub.k generated by
frequency divider 170.sub.k is lower than the frequency of
master-clock signal 162 by a fixed division factor M.sub.k (also
see FIG. 1), where k=0, 1, 2, . . . , n. In various embodiments,
the set of division factors M.sub.k may include integer values or
mixed fractional values, or some combination of both.
[0023] In some embodiments, frequency dividers 170.sub.0-170.sub.n
may benefit from or be implemented using circuits disclosed in the
following publications: (i) Benzad Razavi, "RF Microelectronics,"
Prentice Hall, 1998, pp. 290-297; (ii) Louis Fan Fei, "Frequency
Divider Design Strategies," Broadband Technology, March 2005; (iii)
Mohit Arora, Clock Dividers Made Easy, SNUG Boston, 2002; and (iv)
Myung-Woon Hwang, Jong-Tae Hwang, and Gyu-Hyeong Cho, "Design of
high-speed CMOS prescaler," IEEE APC on ASICs, 2000. These
publications are incorporated herein by reference in their
entirety.
[0024] A filter 174.sub.i located between frequency divider 170 and
mixer 112.sub.i is configured to generate LO signal 116.sub.i by
passing through the main divided frequency of signal 172.sub.i,
while stopping, attenuating, and/or rejecting the higher-order
harmonics and, in some embodiments, also the sub-harmonics thereof.
In an example embodiment, filters 174.sub.1-174.sub.n can be
implemented as low-pass filters. In an alternative embodiment,
filters 174.sub.1-174.sub.n can be implemented as band-pass
filters.
[0025] A filter 180 located between frequency divider 170.sub.0 and
ADC 140 generates sampling-clock signal 138 by passing through the
main divided frequency of signal 172.sub.0 and a predetermined
number of the odd higher harmonics thereof, while stopping or
rejecting the other harmonics and sub-harmonics of the main divided
frequency, and possibly noise that may be coupled to the
sampling-clock channel due to EMI, the presence of power-supply
noise, and/or via any other coupling mechanism. A representative
filter that can be used as filter 180, as well as representative
benefits of its use in generating the sampling-clock signal of an
ADC, such as ADC 140, are described in commonly owned U.S. Patent
Application Publication No. 2014/0210536, which is incorporated
herein by reference in its entirety.
[0026] An example embodiment of receiver 100 may be implemented as
an RF integrated circuit (IC) or chipset. For example, in one
embodiment, receiver 100 may be implemented using the following
three ICs: (i) an RF-ADC IC, e.g., containing ADC 140; (ii) a
multiband down-converter IC, e.g., containing down-converter 110
and, optionally, a circuit portion 190 indicated by the
corresponding dashed rectangle in FIG. 1; and (iii) a DSP IC, e.g.,
containing DSP 150. Alternatively, receiver 100 may be implemented
using the following two ICs: (i) an RF IC, e.g., containing ADC
140, down-converter 110, and circuit portion 190; and (ii) a DSP
IC, e.g., containing DSP 150. Other alternative breakdowns of the
receiver structure into discrete ICs are also possible. For
example, certain parts of FE circuits 106.sub.1-106.sub.n, such as
a variable-gain amplifier (or variable attenuator), may be included
into the IC containing down-converter 110 IC or into the RF IC
containing ADC 140, down-converter 110, and circuit portion 190. In
some embodiments, filters 174.sub.1-174.sub.n and 130, and possibly
the optional filters configured to filter translated electrical
signals 118.sub.1-118.sub.n can be tunable, e.g., to increase
flexibility of the IC usage and to accommodate different possible
operating-frequency bands of the corresponding multiband
receiver.
[0027] The architecture of receiver 100 may provide one or more of
the following benefits.
[0028] An example embodiment of receiver 100 uses a single common
PLL (e.g., located in 160, FIG. 1) to generate multiple LO signals
(e.g., 116.sub.1-116.sub.n, FIG. 1) and the sampling-clock signal
(e.g., 138, FIG. 1) for the RF-ADC. As a result, receiver 100 may
have a smaller size, lower cost, and/or lower power consumption
than comparably performing conventional receivers employing
multiple PLLs. In addition, phase coherence across the signal paths
in receiver 100 may be improved due to the substantial elimination
of a distributed, conventionally used PLL network. Furthermore,
receiver 100 may exhibit a reduced level of phase noise and/or EMI
due to the absence of inter-PLL crosstalk.
[0029] An example embodiment of receiver 100 may be used for
applications where low cost and enhanced performance are
simultaneously required.
[0030] The use of filter 180 positively contributes to the improved
signal-to-noise ratio (SNR), sensitivity, and blocking exhibited by
receiver 100.
[0031] The use of a chipset, e.g., as outlined above, in an
embodiment of receiver 100 may result in further size and/or cost
reduction. Reduced power consumption may also reduce the junction
temperature of one or more of the ICs in the chipset, which may
positively contribute to the overall reliability of the receiver
and of the corresponding wireless communication system.
[0032] FIG. 2 shows a block diagram of a DSP 200 that can be used
in an embodiment of DSP 150 (FIG. 1). For illustration purposes,
DSP 200 is shown in FIG. 2 as being configured to receive digital
electrical signal 142 and to generate electrical output signal 152.
A person of ordinary skill in the art will understand that
alternative configurations of DSP 200 are also possible.
[0033] DSP 200 comprises a digital down-converter 202 and a digital
demodulator 204. Digital down-converter 202 is configured to
translate digital signal 142 to one or more baseband channels for
demodulation and decoding in digital demodulator 204. Frequency
translation is achieved by digitally mixing, in digital mixers
220.sub.1-220.sub.n, (i) a plurality of portions
212.sub.1-212.sub.n of digital electrical signal 142 generated by a
digital signal splitter 210 and (ii) a plurality of digital LO
signals 216.sub.1-216.sub.n generated by numerically controlled
oscillators (NCOs) 214.sub.1-214.sub.n, respectively, as indicated
in FIG. 2. Each of the resulting mixed digital signals
222.sub.1-222.sub.n is filtered in a respective one of digital
filters 230.sub.1-230.sub.n to generate a respective one of digital
baseband signals 232.sub.1-232.sub.n. Digital filters
230.sub.1-230.sub.n typically operate to provide decimation and
baseband-channel selectivity. More specifically, the frequencies of
digital LO signals 216.sub.1-216.sub.n and the band-pass
characteristics of digital filters 230.sub.1-230.sub.n are
selected, e.g., according to a predefined frequency plan. Digital
demodulator 204 operates generate electrical output signal 152 by
demodulating and decoding digital baseband signals
232.sub.1-232.sub.n.
[0034] NCOs 214.sub.1-214.sub.n generate digital LO signals
216.sub.1-216.sub.n using a common (single) digital-reference-clock
signal 208 generated by a digital clock generator 206. In some
embodiments, digital-reference-clock signal 208 may optionally be
provided, as a reference input signal, to the PLL in master-clock
generator 160 (see FIG. 1). In such embodiments, all of LO signals
116.sub.1-116.sub.n, sampling-clock signal 138 (FIG. 1), and
digital LO signals 216.sub.1-216.sub.n (FIG. 2) are generated in
reference to a single common clock signal, i.e.,
digital-reference-clock signal 208. This configuration may be
beneficial, e.g., because it may improve synchronization between
ADC 140, down-converter 110, and DSP 150, reduce clock noise, and
improve the overall phase coherence across all carriers/signals
processed in the DSP.
[0035] In some embodiments, digital clock generator 206 may
generate digital-reference-clock signal 208 based on an external
clock reference signal 205.
[0036] FIGS. 3A-3E graphically illustrate the operation of an
example embodiment of receiver 100 (FIG. 1) employing DSP 200 (FIG.
2). More specifically, the graphs shown in FIGS. 3A-3E illustrate
an embodiment of receiver 100 having four channels (i.e., n=4)
corresponding to a 4-channel MIMO system. FIG. 3A graphically shows
the spectra of electrical signals 108.sub.1-108.sub.4 (FIG. 1).
FIG. 3B graphically shows the spectra of LO signals
116.sub.1-116.sub.4 (FIG. 1). FIG. 3C graphically shows the
spectrum of combined electrical signal 124 (FIG. 1). FIG. 3D
graphically shows the spectra of digital LO (DLO) signals
216.sub.1-216.sub.4 (FIG. 2). FIG. 3E graphically shows the spectra
of digital baseband signals 232.sub.1-232.sub.n (FIG. 2). Also note
that the abscissas in the graphs shown in FIGS. 3A-3E have
different scales, and the graph origins are not necessarily located
at the zero (dc) frequency.
[0037] Referring to FIG. 3A, the spectral bands representing
electrical signals 108.sub.1-108.sub.4 have different amplitudes
but are all centered on the same carrier frequency RF.sub.0.
[0038] Referring to FIG. 3B, LO signals 116.sub.1-116.sub.4 have
frequencies LO1-LO4, respectively. Each of frequencies LO1-LO4 is
generated by dividing the output frequency of the VCO (F.sub.VCO)
located in the PLL of master-clock generator 160 by a respective
one of division factors M.sub.1-M.sub.4.
[0039] Referring to FIG. 3C, combined electrical signal 124 has
four IF bands centered on frequencies IF1-IF4, respectively. The
relationship between IF1-IF4 and LO1-LO4 is indicated in FIG.
3C.
[0040] Referring to FIG. 3D, DLO signals 216.sub.1-216.sub.4 have
frequencies DLO1-DLO4, respectively.
[0041] Referring to FIG. 3E, digital baseband signals
232.sub.1-232.sub.n represent baseband channels BB1-BB4,
respectively. These baseband signals can be generated, e.g., as
indicated above in the description of digital down-converter 202
(FIG. 2), by translation to the baseband of the four IF bands shown
in FIG. 3C.
[0042] In one embodiment, receiver 100 may be designed using the
following frequency plan: [0043] F.sub.VCO=2457.6 MHz; [0044]
M.sub.0=2, for the ADC sampling rate of 1228.8 MHz; [0045]
M.sub.1=8, for LO1=307.2 MHz; [0046] M.sub.2=9, for LO2=273.07 MHz;
[0047] M.sub.3=10, for LO3=245.76 MHz; and [0048] M.sub.4=11, for
LO4=223.42 MHz.
[0049] In an alternative embodiment, receiver 100 may be designed
using the following frequency plan: [0050] F.sub.VCO=3072 MHz;
[0051] M.sub.0=2, for the ADC sampling rate of 1536 MHz; [0052]
M.sub.1=7, for LO1=438.85 MHz; [0053] M.sub.2=8, for LO2=384 MHz;
[0054] M.sub.3=9, for LO3=341.33 MHz; and [0055] M.sub.4=10, for
LO4=307.2 MHz.
[0056] In yet another alternative embodiment, receiver 100 may be
designed using the following frequency plan: [0057] F.sub.VCO=3072
MHz; [0058] M.sub.0=2, for the ADC sampling rate of 1536 MHz;
[0059] M.sub.1=7, for LO1=279.27 MHz; [0060] M.sub.2=8, for LO2=256
MHz; [0061] M.sub.3=9, for LO3=236.31 MHz; and [0062] M.sub.4=10,
for LO4=219.43 MHz.
[0063] Based on the above examples, a person of ordinary skill in
the art will understand how to make additional alternative
frequency plans for use in the corresponding alternative
embodiments of receiver 100.
[0064] FIG. 4 shows a block diagram of a divider circuit 400 that
can be used in an alternative embodiment of receiver 100 (FIG. 1).
More specifically, divider circuit 400 may be used to replace the
plurality of frequency dividers 170.sub.0-170.sub.n in receiver
100. The electrical connections of divider circuit 400 to the rest
of receiver 100 are indicated in FIG. 4 by signals 162 and
172.sub.0-172.sub.n, which are also shown in FIG. 1.
[0065] Circuit 400 comprises a plurality of frequency dividers
470.sub.0-470.sub.n that are generally analogous to frequency
dividers 170.sub.0-170.sub.n. However, unlike frequency dividers
170.sub.0-170.sub.n in receiver 100, which are connected in
parallel to one another, frequency dividers 470.sub.0-470.sub.n in
circuit 400 are serially connected to one another. As a result, the
main divided frequency of signal 172.sub.k in circuit 400 depends
on the division factors M.sub.0-M.sub.k of all preceding frequency
dividers 470 and can be expressed as
F.sub.VCO/(M.sub.0.times.M.sub.1.times. . . . .times.M.sub.k). In
contrast, the main divided frequency of signal 172.sub.k in the
embodiment of receiver 100 shown in FIG. 1 does not depend on
division factors M.sub.0-M.sub.k-1 and can be expressed as
F.sub.VCO/M.sub.k.
[0066] A person of ordinary skill in the art will understand that
various alternative connections of frequency dividers are also
possible in a divider circuit configured to generate signals
172.sub.0-172.sub.n. For example, in an alternative embodiment of
the divider circuit, some frequency dividers may be connected
serially with one another, while some other frequency dividers may
be connected in parallel to one another.
[0067] FIG. 5 shows a block diagram of an RF receiver 500 according
to an alternative embodiment. Receiver 500 can be built using some
of the same functional blocks as those used in receiver 100 (FIG.
1). These functional blocks are labeled in FIG. 5 using the same
numerals as in FIG. 1. The description of the reused functional
blocks is not repeated here. Instead, the description of receiver
500 that is given below focuses primarily on the differences
between receivers 100 and 500.
[0068] One difference between receivers 100 and 500 is that the
latter receiver has a "complex" IF-signal-processing chain, as
opposed to the "real" IF-signal-processing chain used in the former
receiver. Receiver 500 implements the complex IF-signal processing
using two parallel circuit planes, the elements of which are
labeled using subscripts I and Q, respectively, where the "I"
stands for "in-phase," and the "Q" stands for "quadrature."
Receiver 500 employs a plurality of complex mixers
512.sub.1-512.sub.n to generate appropriate input signals for the I
and Q circuit planes. More specifically, a complex mixer 512.sub.i
generates a respective input signal for the I circuit plane by
mixing, in its first mixer, a first copy of signal 108.sub.i and a
first copy of LO signal 116.sub.i. Complex mixer 512.sub.i also
generates a respective input signal for the Q circuit plane by
mixing, in its second mixer, a second copy of signal 108.sub.i and
a relatively phase-shifted copy of the same LO signal 116.sub.i
that is generated in the complex mixer by applying a relative phase
shift of approximately 90 degrees to a second copy of LO signal
116.sub.i.
[0069] A digital output signal 542.sub.I of the I circuit plane is
generated by ADC 140.sub.I. A digital output signal 542.sub.Q of
the Q circuit plane is similarly generated by ADC 140.sub.Q. Both
ADCs are clocked using sampling-clock signal 138. Digital signals
542.sub.I and 542.sub.Q are applied to a DSP 550 for appropriate
processing therein to recover the data encoded in the
electromagnetic wave received by antennas 102.sub.1-102.sub.n.
[0070] According to an example embodiment disclosed above in
reference to FIGS. 1-5, provided is an apparatus (e.g., 100, FIG.
1; 500, FIG. 5) comprising: a multichannel down-converter (e.g.,
110, FIG. 1) having a plurality of mixers (e.g.,
112.sub.1-112.sub.n, FIG. 1; 512.sub.1-512.sub.n, FIG. 5), each
configured to mix a respective one of a plurality of electrical RF
signals (e.g., 108.sub.1-108.sub.n, FIGS. 1, 5) and a respective
one of a plurality of electrical LO signals (e.g.,
116.sub.1-116.sub.n, FIG. 1) to generate a respective one of a
plurality of electrical IF signals (e.g., 118.sub.1-118.sub.n, FIG.
1), wherein the multichannel down-converter is configured to
combine said plurality of electrical IF signals to generate a
combined electrical IF signal (e.g., 132, FIG. 1); an ADC (e.g.,
140, FIG. 1) configured to sample the combined electrical IF signal
at a sampling rate determined by a sampling-clock signal (e.g.,
138, FIG. 1) to convert the combined electrical IF signal into a
corresponding digital IF signal (e.g., 142, FIG. 1) carrying a
sequence of discrete digital samples generated by the ADC at the
sampling rate; and a plurality of interconnected frequency dividers
(e.g., 170.sub.0-170.sub.n, FIG. 1; 470.sub.0-470.sub.n, FIG. 4)
configured to divide a frequency of a master-clock signal (e.g.,
162, FIG. 1) to generate the sampling-clock signal and the
plurality of electrical LO signals.
[0071] In some embodiments of the above apparatus, the apparatus
further comprises a first clock generator (e.g., 160, FIG. 1)
configured to generate the master-clock signal.
[0072] In some embodiments of any of the above apparatus, the
apparatus further comprises: a second clock generator (e.g., 206,
FIG. 2) configured to generate a digital reference-clock signal
(e.g., 208, FIG. 2); and a digital down-converter (e.g., 202, FIG.
2) configured to digitally translate the digital IF signal to
baseband (e.g., as indicated in FIGS. 3C-3E) using the digital
reference-clock signal. The first clock generator is configured to
generate the master-clock signal using the digital reference-clock
signal.
[0073] In some embodiments of any of the above apparatus, the
digital down-converter is a part of a digital signal processor
(e.g., 150, FIG. 1) configured to process the digital IF signal to
recover data encoded in the plurality of electrical RF signals.
[0074] In some embodiments of any of the above apparatus, the
digital down-converter comprises: a digital signal splitter (e.g.,
210, FIG. 2) configured to split the digital IF signal into a
plurality of digital portions (e.g., 212.sub.1-212.sub.n, FIG. 2);
a plurality of numerically controlled oscillators (e.g.,
214.sub.1-214.sub.n, FIG. 2) configured to generate a plurality of
digital LO signals (e.g., 216.sub.1-216.sub.n, FIG. 2) using the
digital reference-clock signal; and a plurality of digital mixers
(e.g., 220.sub.1-220.sub.n, FIG. 2), each configured to mix a
respective one of the plurality of digital portions and a
respective one of the plurality of digital LO signals to generate a
respective one of a plurality of digital baseband signals (e.g.,
232.sub.1-232.sub.n, FIG. 2), wherein the digital down-converter is
configured to combine said plurality of digital baseband signals to
generate a combined digital baseband signal (e.g., 242, FIG. 2)
representing the digital IF signal.
[0075] In some embodiments of any of the above apparatus, the
plurality of interconnected frequency dividers comprises two or
more frequency dividers (e.g., 170.sub.0-170.sub.n, FIG. 1), with
each of said two or more frequency dividers being configured to
receive a respective copy of the master-clock signal and further
configured to divide the frequency of the master-clock signal by a
respective division factor.
[0076] In some embodiments of any of the above apparatus, the
plurality of interconnected frequency dividers comprises two or
more frequency dividers (e.g., 470.sub.0-470.sub.n, FIG. 4) that
are serially connected to one another in a manner that causes a
following one of the two or more frequency dividers to divide a
frequency generated by a preceding one of the two or more frequency
dividers.
[0077] In some embodiments of any of the above apparatus, one or
more of the plurality of interconnected frequency dividers are
configured to divide the frequency of the master-clock signal in a
manner that causes different electrical LO signals of the plurality
of electrical LO signals to have different respective
frequencies.
[0078] In some embodiments of any of the above apparatus, some of
the plurality of interconnected frequency dividers are further
configured to divide the frequency of the master-clock signal in a
manner that causes the sampling-clock signal to have a frequency
that is different from any of the respective frequencies.
[0079] In some embodiments of any of the above apparatus, some of
the plurality of interconnected frequency dividers are configured
to divide the frequency of the master-clock signal in a manner that
causes the sampling-clock signal to have a frequency that is
different from a frequency of any other of the plurality of
electrical LO signals.
[0080] In some embodiments of any of the above apparatus, the
plurality of interconnected frequency dividers includes a set of
frequency dividers, with each frequency divider in said set being
configured to apply a respective integer frequency-division
factor.
[0081] In some embodiments of any of the above apparatus, the set
of frequency dividers is configured such that a set of integer
values that consists of the respective integer frequency-division
factors includes two or more consecutive integers (e.g., M.sub.1=8,
M.sub.2=9, M.sub.3=10, M.sub.4=11).
[0082] In some embodiments of any of the above apparatus, the
plurality of interconnected frequency dividers includes a set of
frequency dividers, with each frequency divider in said set being
configured to apply a respective fractional frequency-division
factor.
[0083] In some embodiments of any of the above apparatus, the
apparatus further comprises an array of antennas (e.g.,
102.sub.1-102.sub.n, FIG. 1). Each of the antennas is coupled to a
respective one of RF front-end circuits (e.g., 106.sub.1-106.sub.n,
FIG. 1) configured to generate the respective one of the plurality
of electrical RF signals based on an electrical input provided by a
corresponding antenna.
[0084] In some embodiments of any of the above apparatus, the ADC
(e.g., 140, FIG. 1; 140.sub.1, 140.sub.Q, FIG. 5) is configured to
operate in a single selected Nyquist zone (e.g., in the first or
second Nyquist zone) or in more than one Nyquist zone (e.g., both
in the first Nyquist zone and in the second Nyquist zone).
[0085] In some embodiments of any of the above apparatus, the
multichannel down-converter is an analog electrical circuit.
[0086] In some embodiments of any of the above apparatus, the
multichannel down-converter is a mixed-signal electrical circuit
that includes an analog circuit portion and a digital circuit
portion.
[0087] According to another example embodiment disclosed above in
reference to FIGS. 1-5, provided is an apparatus comprising: an
electrical analog down-converter (e.g., 110, FIG. 1) having a first
mixer (e.g., 112.sub.i, FIG. 1) configured to mix a first
electrical radio-frequency (RF) signal (e.g., 108.sub.i, FIG. 1)
and a first electrical local-oscillator (LO) signal (e.g.,
116.sub.i, FIG. 1) to generate a first electrical
intermediate-frequency (IF) signal (e.g., 118.sub.i, FIG. 1),
wherein the electrical analog down-converter is configured to
convert the first electrical IF signal into a second electrical IF
signal (e.g., 124 or filtered 118.sub.i, FIG. 1); an ADC (e.g.,
140, FIG. 1) configured to sample the second electrical IF signal
at a sampling rate determined by a sampling-clock signal (e.g.,
138, FIG. 1) to convert the second electrical IF signal into a
corresponding digital IF signal (e.g., 142, FIG. 1) carrying a
sequence of discrete digital samples generated by the ADC at the
sampling rate; a first clock generator (e.g., 160, FIG. 1)
configured to generate a master-clock signal (e.g., 162, FIG. 1); a
first frequency divider (e.g., 170.sub.i, FIG. 1) configured to
divide a frequency of the master-clock signal to generate the first
electrical LO signal; and a second frequency divider (e.g.,
170.sub.0, FIG. 1) configured to divide the frequency of the
master-clock signal to generate the sampling-clock signal.
[0088] In some embodiments of the above apparatus, the first
electrical LO signal and the sampling-clock signal have different
respective frequencies.
[0089] In some embodiments of any of the above apparatus, the
electrical analog down-converter includes a second mixer (e.g.,
112.sub.j, i.noteq.j, FIG. 1) configured to mix a second electrical
RF signal (e.g., 108.sub.j, FIG. 1) and a second electrical LO
signal (e.g., 116.sub.j, FIG. 1) to generate a third electrical IF
signal (e.g., 118.sub.j, FIG. 1), wherein the electrical analog
down-converter is configured to combine the first electrical IF
signal and the third electrical IF signal to generate the second
electrical IF signal. The apparatus further comprises a third
frequency divider (e.g., 170.sub.j, FIG. 1) configured to divide
the frequency of the master-clock signal to generate the second
electrical LO signal.
[0090] In some embodiments of any of the above apparatus, the first
electrical LO signal and the second electrical LO signal have
different respective frequencies.
[0091] In some embodiments of any of the above apparatus, the
apparatus further comprises a second clock generator (e.g., 206,
FIG. 2) configured to generate a digital reference-clock signal
(e.g., 208, FIG. 2); and a digital down-converter (e.g., 202, FIG.
2) configured to digitally translate the digital IF signal to
baseband (e.g., as indicated in FIGS. 3C-3E) using the digital
reference-clock signal. The first clock generator is configured to
generate the master-clock signal using the digital reference-clock
signal.
[0092] In some embodiments of any of the above apparatus, the
apparatus further comprises a filter (e.g., an optional filter
configured to filter 118.sub.i, not explicitly shown in FIG. 1)
configured to generate the second electrical IF signal by filtering
the first electrical IF signal.
[0093] While this disclosure includes references to illustrative
embodiments, this specification is not intended to be construed in
a limiting sense.
[0094] For example, in some embodiments, receiver 100 may be
modified to be a single-channel receiver. The corresponding
modification of receiver 100 may include removing or disabling all
but one channel of down-converter 110, thereby transforming that
down-converter into a single-channel down-converter.
[0095] Various modifications of the described embodiments, as well
as other embodiments within the scope of the disclosure, which are
apparent to persons skilled in the art to which the disclosure
pertains are deemed to lie within the principle and scope of the
disclosure, e.g., as expressed in the following claims.
[0096] Unless explicitly stated otherwise, each numerical value and
range should be interpreted as being approximate as if the word
"about" or "approximately" preceded the value or range.
[0097] It will be further understood that various changes in the
details, materials, and arrangements of the parts which have been
described and illustrated in order to explain the nature of this
disclosure may be made by those skilled in the art without
departing from the scope of the disclosure, e.g., as expressed in
the following claims.
[0098] Although the elements in the following method claims, if
any, are recited in a particular sequence with corresponding
labeling, unless the claim recitations otherwise imply a particular
sequence for implementing some or all of those elements, those
elements are not necessarily intended to be limited to being
implemented in that particular sequence.
[0099] Reference herein to "one embodiment" or "an embodiment"
means that a particular feature, structure, or characteristic
described in connection with the embodiment can be included in at
least one embodiment of the disclosure. The appearances of the
phrase "in one embodiment" in various places in the specification
are not necessarily all referring to the same embodiment, nor are
separate or alternative embodiments necessarily mutually exclusive
of other embodiments. The same applies to the term
"implementation."
[0100] Also for purposes of this description, the terms "couple,"
"coupling," "coupled," "connect," "connecting," or "connected"
refer to any manner known in the art or later developed in which
energy is allowed to be transferred between two or more elements,
and the interposition of one or more additional elements is
contemplated, although not required. Conversely, the terms
"directly coupled," "directly connected," etc., imply the absence
of such additional elements.
[0101] The described embodiments are to be considered in all
respects as only illustrative and not restrictive. In particular,
the scope of the disclosure is indicated by the appended claims
rather than by the description and figures herein. All changes that
come within the meaning and range of equivalency of the claims are
to be embraced within their scope.
[0102] The description and drawings merely illustrate the
principles of the disclosure. It will thus be appreciated that
those of ordinary skill in the art will be able to devise various
arrangements that, although not explicitly described or shown
herein, embody the principles of the disclosure and are included
within its spirit and scope. Furthermore, all examples recited
herein are principally intended expressly to be only for
pedagogical purposes to aid the reader in understanding the
principles of the disclosure and the concepts contributed by the
inventor(s) to furthering the art, and are to be construed as being
without limitation to such specifically recited examples and
conditions. Moreover, all statements herein reciting principles,
aspects, and embodiments of the disclosure, as well as specific
examples thereof, are intended to encompass equivalents
thereof.
[0103] The functions of the various elements shown in the figures,
including any functional blocks labeled as "processors," may be
provided through the use of dedicated hardware as well as hardware
capable of executing software in association with appropriate
software. When provided by a processor, the functions may be
provided by a single dedicated processor, by a single shared
processor, or by a plurality of individual processors, some of
which may be shared. Moreover, explicit use of the term "processor"
or "controller" should not be construed to refer exclusively to
hardware capable of executing software, and may implicitly include,
without limitation, digital signal processor (DSP) hardware,
network processor, application specific integrated circuit (ASIC),
field programmable gate array (FPGA), read only memory (ROM) for
storing software, random access memory (RAM), and non volatile
storage. Other hardware, conventional and/or custom, may also be
included.
[0104] It should be appreciated by those of ordinary skill in the
art that any block diagrams herein represent conceptual views of
illustrative circuitry embodying the principles of the
disclosure.
* * * * *