U.S. patent application number 15/185561 was filed with the patent office on 2016-10-06 for substrate for molecular beam epitaxy (mbe) hgcdte growth.
This patent application is currently assigned to Raytheon Company. The applicant listed for this patent is Raytheon Company. Invention is credited to Jeffrey M. Peterson.
Application Number | 20160293711 15/185561 |
Document ID | / |
Family ID | 54368548 |
Filed Date | 2016-10-06 |
United States Patent
Application |
20160293711 |
Kind Code |
A1 |
Peterson; Jeffrey M. |
October 6, 2016 |
Substrate For Molecular Beam Epitaxy (MBE) HGCDTE Growth
Abstract
A semiconductor structure having a first semiconductor body
having an upper surface with a non <211> crystallographic
orientation and a second semiconductor body having a surface with a
<211> crystallographic orientation, the surface of the second
semiconductor body being bonded to a bottom surface of the first
semiconductor body. A layer comprising CdTe is epitaxially disposed
on the upper surface of the second semiconductor body. The second
semiconductor body is CZ silicon, has a thickness less than 10
microns and has a diameter of at least eight inches. A getter
having micro-cavities has a bottom surface formed on an upper
surface of the first semiconductor body and has an upper surface
bonded to a bottom surface of the second semiconductor body.
Inventors: |
Peterson; Jeffrey M.; (Santa
Barbara, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Raytheon Company |
Waltham |
MA |
US |
|
|
Assignee: |
Raytheon Company
Waltham
MA
|
Family ID: |
54368548 |
Appl. No.: |
15/185561 |
Filed: |
June 17, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14271727 |
May 7, 2014 |
|
|
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15185561 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/02433 20130101;
H01L 21/02562 20130101; H01L 21/02381 20130101; H01L 21/3223
20130101; H01L 29/04 20130101; H01L 29/32 20130101; H01L 29/045
20130101; H01L 21/02631 20130101 |
International
Class: |
H01L 29/32 20060101
H01L029/32; H01L 21/02 20060101 H01L021/02; H01L 29/04 20060101
H01L029/04 |
Claims
1. A semiconductor structure, comprising: a first semiconductor
body; a getter layer; a second semiconductor body; wherein the
getter layer has a bottom surface formed on an upper surface of the
first semiconductor body and has an upper surface bonded to a
bottom surface of the second semiconductor body.
2. The semiconductor structure recited in claim 1 wherein the
second semiconductor body has a surface with a <211>.
3. The semiconductor structure recited in claim 2 including a layer
comprising CdTe epitaxially disposed on the upper surface of the
second semiconductor body.
4. The semiconductor structure recited in claim 3 wherein the
second semiconductor body has a thickness at least an order of
magnitude thinner than the thickness of the first semiconductor
body.
5. The semiconductor body recited in claim 1 wherein the second
semiconductor body is CZ silicon.
6. The semiconductor structure recited in claim 5 wherein the
second semiconductor body has a thickness less than 10 microns.
7. The semiconductor structure recited in claim 1 wherein the first
semiconductor body and the second semiconductor body are of the
same semiconductor material.
8. The semiconductor structure recited in claim 1 wherein the
getter layer has nanocavities.
9. The semiconductor structure recited in claim 8 wherein the
second semiconductor body has a surface with a <211>.
10. The semiconductor structure recited in claim 9 including a
layer comprising CdTe epitaxially disposed on the upper surface of
the second semiconductor body.
11. The semiconductor structure recited in claim 1 wherein the
first semiconductor body is FZ silicon.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This is a Divisional Application of application Ser. No.
14/271,727 filed May 7, 2014 which application is hereby
incorporated herein by reference in its entirety.
TECHNICAL FIELD
[0002] This disclosure relates generally to semiconductor
substrates and more particularly to semiconductor substrates for
MBE growth of mercury cadmium telluride (HgCdTe) devices.
BACKGROUND
[0003] As is known in the art, cryogenic infrared detectors are
typically made of small band gap (about 0.1-0.2 eV) semiconductors
such as HgCdTe (mercury cadmium telluride) grown on a semiconductor
substrate, such as a silicon substrate, using molecular beam
epitaxy (MBE). In order for proper crystallographic epitaxial
growth, the silicon surface upon which the HgCdTe is MBE grown
should have a<211> crystallographic orientation. Also, the
wafers should have sufficient support thicknesses, typically, at
least in the order of 100 microns.
[0004] As is also known in the art, many imaging application
require large arrays of the detectors on a single substrate, or
wafer; preferably at least eight inches in diameter. While, eight
inch diameter Float Zone (FZ) silicon wafers are readily available,
these wafers have surfaces with a <100> crystallographic
orientation and are therefore not suitable for MBE formation. of
the HgCdTe detectors. While silicon wafers produced by the
Czochralski (CZ) process produces silicon wafers (CZ silicon
wafers) having a surface with a <211> orientation, the CZ
silicon wafers having thickness in the order of 100 microns are
undesirable in many application because oxygen impurities therein
absorb light in many frequency bands where radiation detection is
required as in LWIR applications. Further, eight inch diameter CZ
silicon wafers with surfaces having a <211> orientation are
not readily available.
SUMMARY
[0005] In accordance with the present disclosure, a semiconductor
structure is provided, comprising: a first semiconductor body
having an upper surface with a non <211> crystallographic
orientation; a second semiconductor body having a surface with a
<211> crystallographic orientation, the surface of the second
semiconductor body being bonded to a bottom surface of the first
semiconductor body.
[0006] In one embodiment, the structure includes a layer comprising
CdTe epitaxially disposed on the upper surface of the second
semiconductor body.
[0007] In one embodiment, the second semiconductor body is CZ
silicon.
[0008] In one embodiment, the second semiconductor body has a
thickness less than 10 microns.
[0009] In one embodiment, the second semiconductor body has a
diameter of at least eight inches.
[0010] In one embodiment, the first semiconductor body and the
second semiconductor body are of the same semiconductor
material.
[0011] In one embodiment, the second semiconductor body has a
thickness at least an order of magnitude thinner than the thickness
of the first semiconductor body.
[0012] In one embodiment, a semiconductor structure is provided,
comprising; a first semiconductor body; a getter layer; and a
second semiconductor body. The getter layer has a bottom surface
formed on an upper surface of the first semiconductor body and has
an upper surface bonded to a bottom surface of the second
semiconductor body.
[0013] In one embodiment, the getter layer has nanocavities.
[0014] In one embodiment, the first semiconductor body is FZ
silicon.
[0015] With such an arrangement, wafer bonding is used to bond a
readily available <211> CZ wafer to an ordinary orientation
Float Zone silicon wafer. After wafer bonding, the <211> CZ
wafer is then thinned so that it does not appreciably absorb LWIR
radiation, and the FZ wafer serves only as an LWIR transparent
handle wafer. This arrangement: an LWIR compatible 8-in diameter
substrate for MBE growth and focal plane arrays is obtained without
having to obtain an 8-in diameter <211> FZ silicon wafer;
enables placing an impurity getter layer in the benign location
between the two substrates in close proximity to the HgCdTe; and
eases supply chain issues associated with <211> silicon (Si)
substrates. The use of wafer bonding of two more readily available
wafers to replace a difficult to obtain wafer will enable the
engineered silicon substrate to be a manufactured product with more
predictable lead times and better quality control.
DESCRIPTION OF DRAWINGS
[0016] FIGS. 1A-1E are diagrammatical cross sectional Sketches of a
process used to form an array of photo-detectors at various stages
in the fabrication thereof in accordance with the disclosure;
and,
[0017] FIGS. 2A-2E are diagrammatical cross sectional sketches of a
process used to form an array of photo-detectors at various stages
in the fabrication thereof in accordance with another embodiment of
the disclosure;
[0018] Like reference symbols in the various drawings indicate like
elements.
DETAILED DESCRIPTION
[0019] Referring now to FIG. 1A, a semiconductor wafer 10, here an
FZ silicon wafer, is shown. Here, the wafer 10 is an eight inch
diameter wafer have an upper surface with a <100>
crystallographic orientation, it should be understood that the
wafer 10 here has <100>crystallographic orientation, other
crystallographic orientations may be used. The thickness of the
wafer 10 is here, for example, 100 microns. Also shown in FIG. 1A
is a semiconductor wafer 12, here an eight inch diameter CZ silicon
wafer, disposed above the upper surface of wafer 10; the wafer 12
having a top and bottom surfaces each with a <211>
crystallographic orientation. The thickness of wafer 12 is here,
for example, 100 microns,
[0020] Referring now to FIG. 1B, the top surface of wafer 12 and
bottom surface of wafer 12 are cleaned and polished and then bonded
together in an oxide free environment to form an atomic bond
between the two wafers 10, 12, to form structure 14, as indicated.
Because the wafer bond interface will be silicon-to-silicon, the
bonding is likely to be a combination of atomic bonding and Van der
Waal's attraction.
[0021] Next, referring to FIG. 1C, the upper surface of the wafer
12 is polished, for example using standard silicon semiconductor
polishing methods to achieve a smooth, particle free surface, to
reduce the thickness of the wafer 12 to a wafer 12' having a
thickness thick enough for handling until it can he wafer bonded to
the handle wafer, for example, as thin as 100 .mu.m. After wafer
bonding is complete, the <211> wafer can be thinned to its
final thickness .about.5 .mu.m so as not to appreciably absorb MR
IR radiation. It is noted that the wafer 10 serves as a handle for
the thinned wafer 12' and that the upper surface of the thinned
wafer 12; has a <211> crystallographic orientation.
[0022] Next, referring to FIG. 1D, a layer 16 of HgCdTe is formed
using MBE on the upper surface of the thinned wafer 12'.
[0023] Here, referring to FIG. 1E, an array of HgCdTe detectors 18
is formed in the layer 16 using conventional
photolithographic--etching processing. Thus, an array of HgCdTe
photo-detectors has been formed on an eight inch diameter
substrate, here the structure 14, using MBE on a surface (the upper
surface of the thinned, and hence low oxygen impurity, CZ wafer
12') having a <211> crystallographic orientation.
[0024] Referring now to FIG. 2A, a semiconductor wafer 20, here an
FL silicon wafer, is shown. Here, the wafer 20 is an eight inch
diameter wafer have an upper surface with a <100>
crystallographic orientation. It should be understood that other
semiconductor materials may be used as well as other
crystallographic orientations for the surface. The thickness of the
wafer 20 is here, for example, 100 microns. Here, the upper surface
of wafer 20 has a getter layer 21, here a layer formed with
nanocavities by, for example, implanting ion of helium into the
surface of either wafer at the bonding interface between layers 12
and 20, as shown in FIG. 2A. In either case, the formation of the
gettering layer 21 must occur before wafer bonding (thereby putting
the gettering layer buried in the bondline between, protecting it
from both the MBE growth process and the wafer fabrication
process), followed by the application of heat to form bubbles in
the upper surface of wafer 20. The getter layer 21 to be used to
trap impurities in the environment, such as, for example, copper.
More particularly, the internal surfaces of the bubbles formed by
the nanocavities trap the impurities.
[0025] Referring now to FIG. 2B, the top surface of wafer 12 and
bottom surface of wafer 22 are cleaned and polished and cleaned to
form oxide free surfaces and then bonded together in a clean
environment to form an atomic bond between the two wafers 20, 12,
to form structure 14, as indicated. The gettering layer 21 will
attract undesired metallic impurities such as copper so that the
impurities will not affect the HgCdTe to be grown onto the
wafer.
[0026] Next, referring to FIG. 2C, the upper surface of the wafer
12 is polished, as described in connection with FIG. 1C to reduce
the thickness of the wafer 12 to the wafer 12' having a thickness
in the range between 540 .mu.m although it may be possible to be as
thin as 2 .mu.m if a high degree of polishing is provided. It is
noted that the wafer 20 serves as a handle for the thinned wafer
12' and that the upper surface of the thinned wafer 12; has a
<211> crystallographic orientation.
[0027] Next, referring to FIG. 2D, the layer 16 of HgCdTe is formed
using MBE on the upper surface of the thinned wafer 12,' as
described in connection with FIG. 1C.
[0028] Here, referring to FIG. 2E, an array of HgCdTe detectors is
formed in the layer 16 using conventional
photolithographic--etching processing as described in connection
with FIG. 1D. Thus, an array of HgCdTh photo-detectors 18 has been
formed on an eight inch diameter substrate, here the structure 14,
using MBE on a surface (the upper surface of the thinned, and hence
low oxygen impurity, CZ wafer 12') having a <211>
crystallographic orientation having an internal, buried, getter
layer 21.
[0029] A summary of the process is as follows: [0030] 1. Obtain a
growth wafer having <211> crystallographic orientation a
handle wafer having a Non <211> crystallographic orientation
[0031] 2. If not pre-thinned, then thin the <211>
crystallographic orientation growth wafer to .about.100 .mu.m.
[0032] 3. Create a gettering layer on either one or both wafers
[0033] 4. Bond the wafers together with gettering layer(s) at the
interface [0034] 5. If required, thermally activate gettering
layer. [0035] 6. Thin the <211> crystallographic orientation
wafer to .about.5 .mu.m or less to minimize LWIR loss. The surface
of the thinned <211> crystallographic orientation side needs
to be smooth and substantially particle free so that it is capable
of supporting the epitaxial growth of HgCdTe. The backside of the
handle wafer also needs to be polished to enable the transmission
of IR radiation through it.
[0036] A number of embodiments of the disclosure have been
described. Nevertheless, it will be understood that various
modifications may be made without departing from the spirit and
scope of the disclosure. For example, smaller wafer diameters,
variations in the growth to handle wafer such as CA to CZ or FZ to
FZ. Accordingly, other embodiments are within the scope of the
following claims.
* * * * *