U.S. patent application number 15/179049 was filed with the patent office on 2016-10-06 for semiconductor memory device.
The applicant listed for this patent is Semiconductor Energy Laboratory Co., Ltd.. Invention is credited to Jun KOYAMA, Shunpei YAMAZAKI.
Application Number | 20160293605 15/179049 |
Document ID | / |
Family ID | 48653676 |
Filed Date | 2016-10-06 |
United States Patent
Application |
20160293605 |
Kind Code |
A1 |
YAMAZAKI; Shunpei ; et
al. |
October 6, 2016 |
SEMICONDUCTOR MEMORY DEVICE
Abstract
A semiconductor memory device which includes a memory cell
including two or more sub memory cells is provided. The sub memory
cells each including a word line, a bit line, a first capacitor, a
second capacitor, and a transistor. In the semiconductor device,
the sub memory cells are stacked in the memory cell; a first gate
and a second gate are formed with a semiconductor film provided
therebetween in the transistor; the first gate and the second gate
are connected to the word line; one of a source and a drain of the
transistor is connected to the bit line; the other of the source
and the drain of the transistor is connected to the first capacitor
and the second capacitor; and the first gate and the second gate of
the transistor in each sub memory cell overlap with each other and
are connected to each other.
Inventors: |
YAMAZAKI; Shunpei; (Tokyo,
JP) ; KOYAMA; Jun; (Sagamihara, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Semiconductor Energy Laboratory Co., Ltd. |
Atsugi-shi |
|
JP |
|
|
Family ID: |
48653676 |
Appl. No.: |
15/179049 |
Filed: |
June 10, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14557506 |
Dec 2, 2014 |
9368501 |
|
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15179049 |
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13718426 |
Dec 18, 2012 |
8907392 |
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14557506 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/24 20130101;
H01L 27/10852 20130101; H01L 27/10858 20130101; H01L 27/108
20130101; H01L 27/10844 20130101; H01L 27/10873 20130101 |
International
Class: |
H01L 27/108 20060101
H01L027/108 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 22, 2011 |
JP |
2011-281599 |
Claims
1. (canceled)
2. A semiconductor device comprising: an oxide semiconductor layer
over a substrate; a first insulating layer over the oxide
semiconductor layer; and a first electrode over the oxide
semiconductor layer with the first insulating layer interposed
therebetween, wherein the oxide semiconductor layer comprises
indium, gallium and zinc, wherein the first electrode covers a side
surface and a top surface of the oxide semiconductor layer with the
first insulating layer interposed therebetween.
3. The semiconductor device according to claim 2, wherein the first
insulating layer comprises gallium.
4. The semiconductor device according to claim 2, further
comprising: a second electrode and a second insulating layer
between the substrate and the oxide semiconductor layer, wherein
the second electrode overlaps with the oxide semiconductor layer
with the second insulating layer interposed therebetween.
5. The semiconductor device according to claim 4, wherein the
second insulating layer comprises gallium.
6. The semiconductor device according to claim 2, further
comprising a capacitor, wherein the capacitor comprises the oxide
semiconductor layer.
7. The semiconductor device according to claim 6, wherein one of
electrodes of the capacitor is the oxide semiconductor layer.
8. A semiconductor device comprising: a transistor comprising: an
oxide semiconductor layer over a substrate; a first gate insulating
layer over the oxide semiconductor layer; and a first gate
electrode over the oxide semiconductor layer with the first gate
insulating layer interposed therebetween, wherein the oxide
semiconductor layer comprises indium, gallium and zinc, wherein the
transistor comprises a channel formation region in the oxide
semiconductor layer, and wherein in a cross-section in a channel
width direction, the first gate electrode covers a side surface and
a top surface of the oxide semiconductor layer with the first gate
insulating layer interposed therebetween.
9. The semiconductor device according to claim 8, further
comprising: a second gate electrode and a second gate insulating
layer between the substrate and the oxide semiconductor layer,
wherein the second gate electrode overlaps with the oxide
semiconductor layer with the second gate insulating layer
interposed therebetween.
10. The semiconductor device according to claim 9, wherein the
first gate electrode and the second gate electrode overlap with
each other and are electrically connected to each other.
11. The semiconductor device according to claim 8, wherein the
oxide semiconductor layer comprises impurity regions provided so as
to sandwich the channel formation region, and a source electrode
and a drain electrode are connected to the impurity regions.
12. The semiconductor device according to claim 8, further
comprising a capacitor, wherein the capacitor comprises the oxide
semiconductor layer.
13. The semiconductor device according to claim 12, wherein one of
electrodes of the capacitor is the oxide semiconductor layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser.
No. 14/557,506, filed Dec. 2, 2014, now allowed, which is a
divisional of U.S. application Ser. No. 13/718,426, filed Dec. 18,
2012, now U.S. Pat. No. 8,907,392, which claims the benefit of a
foreign priority application filed in Japan as Serial No.
2011-281599 on Dec. 22, 2011, all of which are incorporated by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor memory
device.
[0004] 2. Description of the Related Art
[0005] Examples of a semiconductor memory device (also referred to
as a memory device or a memory cell) include a dynamic random
access memory (DRAM), which is a volatile memory. The DRAM is a
semiconductor memory device which can store one-bit data using one
transistor and one capacitor. An area per unit memory cell of the
DRAM is small; the degree of integration thereof can be easily
increased at the time of making a module; and manufacturing cost
thereof is low.
[0006] When a transistor including an oxide semiconductor is used
for a DRAM, charge which is held in a capacitor in the DRAM can be
held for a long time owing to low off-state current characteristics
of the oxide semiconductor, which enables an interval between
refresh operations to be extended. As a result, it is possible to
reduce power consumption (see Patent Document 1).
[0007] In addition, in order to increase the operation speed and
storage capacity of a semiconductor memory device, an increase in
the degree of integration by a microfabrication technology is
required. However, as microfabrication of a semiconductor memory
device advances, a transistor having a channel with shorter channel
length and including various insulating films typified by a gate
insulating layer which have smaller thickness is used for a
semiconductor memory device. As a result, leakage current of the
transistor is increased, so that power consumption is
increased.
[0008] To reduce an area occupied by a semiconductor memory device,
an area occupied by a cell can be reduced by devising a layout of a
circuit (see Patent Document 2).
REFERENCE
Patent Document
[0009] [Patent Document 1] Japanese Published Patent Application
No. 2011-109084
[0010] [Patent Document 2] Japanese Published Patent Application
No. 2008-42050
SUMMARY OF THE INVENTION
[0011] Owing to the miniaturization of the semiconductor memory and
an increase in the degree of integration thereof, the operation
speed and storage capacity of the memory device can be increased.
However, for example, a DRAM includes a transistor and a capacitor,
and when the size of the DRAM is reduced and the degree of
integration thereof is increased, the area of the capacitor is
reduced, so that the capacitance of the capacitor is reduced.
Therefore, difference between the amount of charge in a writing
state and that in an erasing state becomes small in the memory
device, which results in difficulty in accurately holding stored
data.
[0012] The transistor including the oxide semiconductor enables
charge which is held in a capacitor in the DRAM to be held for a
long time, owing to low off-state current characteristics of the
transistor, and thus power consumption can be reduced. However, the
on-state current of the transistor is smaller than that of a
transistor including single crystal silicon or polycrystalline
silicon. Therefore, the on-state current characteristics of the
transistor including an oxide semiconductor are disadvantageous in
terms of operation speed in the memory device.
[0013] Thus, an object of one embodiment of the present invention
is to provide a semiconductor memory device which operates at high
speed and consumes low power.
[0014] Another object of one embodiment of the present invention is
to provide a semiconductor memory device whose storage capacity per
unit area is increased.
[0015] Another object of one embodiment of the present invention is
to increase the capacitance of the capacitor in a semiconductor
memory device.
[0016] One embodiment of the present invention is a semiconductor
memory device which includes a memory cell including a two or more
sub memory cells. The sub memory cells each including a word line,
a bit line, a first capacitor, a second capacitor, and a
transistor. In the semiconductor memory device, the sub memory
cells are stacked in the memory cell; a first gate and a second
gate are formed with a semiconductor film provided therebetween in
the transistor; the first gate and the second gate are electrically
connected to the word line; one of a source and a drain of the
transistor is electrically connected to the bit line; the other of
the source and the drain of the transistor is electrically
connected to the first capacitor and the second capacitor; and the
first gate and the second gate of the transistor overlap with each
other and are electrically connected to each other.
[0017] In one embodiment of the present invention, the first
capacitor and the second capacitor may be formed to overlap with
each other in each of the sub memory cells.
[0018] In one embodiment of the present invention, the memory cells
may be formed in matrix in a plane.
[0019] In one embodiment of the present invention, the transistor
includes an oxide semiconductor.
[0020] According to one embodiment of the present invention, the
sub memory cells overlap with each other to be stacked, whereby the
memory cell can be formed. This is because an oxide semiconductor
is used for an active layer of the transistor in the sub memory
cell and the oxide semiconductor can be formed by a deposition
method such as a sputtering method. The memory cell having a small
area can be manufactured using the sub memory cells which overlap
with each other to be stacked; accordingly, the storage capacity of
a memory module per unit area can be further increased.
[0021] In one embodiment of the present invention can include a
transistor including silicon which is stacked together with sub
memory cells. The transistor including silicon is preferably
provided in the lowest layer of the stacked-layer semiconductor
memory device, and can be formed using a silicon substrate, for
example. In addition, the number of layers including the transistor
including silicon is not limited to one and may be plural so that
the layers may be each provided between sub memory cells.
[0022] One embodiment of the present invention is a semiconductor
memory device in which a sub memory cell is a DRAM.
[0023] According to one embodiment of the present invention, with
the use of a transistor including an oxide semiconductor and having
high on-state characteristics and low off-state current
characteristics, it is possible to provide a semiconductor memory
device which operates at high speed and consumes low power.
[0024] According to one embodiment of the present invention, a
plurality of layers of the sub memory cells overlap with each other
to be stacked, whereby it is possible to provide a semiconductor
memory device whose memory capacity per unit area is increased.
[0025] According to one embodiment of the present invention, it is
possible to increase the capacitance of a capacitor in a
semiconductor memory device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] FIGS. 1A and 1B are a perspective view and a circuit diagram
illustrating one example of a semiconductor memory device according
to one embodiment of the present invention.
[0027] FIGS. 2A and 2B are a top view and a cross-sectional view
illustrating one example of a memory cell in a semiconductor memory
device according to one embodiment of the present invention.
[0028] FIGS. 3A and 3B are a top view and a cross-sectional view
illustrating the one example of a sub memory cell in the
semiconductor memory device according to one embodiment of the
present invention.
[0029] FIGS. 4A to 4C are cross-sectional views illustrating one
example of a manufacturing process of the memory cell according to
one embodiment of the present invention.
[0030] FIGS. 5A to 5C are cross-sectional views illustrating the
one example of the manufacturing process of the memory cell
according to one embodiment of the present invention.
[0031] FIGS. 6A to 6C are a top view and cross-sectional views
illustrating one example of a semiconductor memory device according
to one embodiment of the present invention.
[0032] FIG. 7A is a block diagram illustrating a specific example
of a CPU including a semiconductor memory device according to one
embodiment of the present invention and FIGS. 7B and 7C are each a
partial circuit diagram thereof.
[0033] FIGS. 8A to 8D are perspective views illustrating examples
of an electronic appliance including a semiconductor memory device
according to one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0034] Embodiments of the present invention will be described below
with reference to the accompanying drawings. Note that the present
invention is not limited to the description below, and it is easily
understood by those skilled in the art that various changes and
modifications can be made without departing from the spirit and
scope of the present invention. Therefore, the invention should not
be construed as being limited to the description in the following
embodiments. Note that the same portions or portions having the
same function in the structure of the present invention described
below are denoted by the same reference numerals in common among
different drawings and repetitive description thereof will be
omitted.
[0035] Note that in each drawing described in this specification,
the size, the film thickness, or the region of each component is
exaggerated for clarity in some cases. Therefore, embodiments of
the present invention are not limited to such scales.
[0036] Note that terms such as "first", "second", and "third" in
this specification are used in order to avoid confusion among
components, and the terms do not limit the components numerically.
Therefore, for example, the term "first" can be replaced with the
term "second", "third", or the like as appropriate.
[0037] In addition, in this specification, when one of a source and
a drain of a transistor is called a drain, the other is called a
source. That is, they are not distinguished depending on the
potential level. Therefore, a portion called a source in this
specification can be alternatively referred to as a drain.
[0038] In this specification, a gate of a transistor is referred to
as a "gate" or a "gate electrode", and these terms are not
distinguished from each other. In addition, a source and a drain of
a transistor are referred to as a "source" and a "drain", a "source
region" and a "drain region", or a "source electrode" and a "drain
electrode", respectively, and these terms are not distinguished
from each other.
[0039] Further, even when the expression "to be connected" is used
in this specification, there is a case in which no physical
connection is made and a wiring is just extended in an actual
circuit. For example, in the case of a circuit including an
insulated-gate field-effect transistor (MISFET), one wiring
functions as gates of a plurality of MISFETs in some cases. In that
case, one wiring which branches into gates may be illustrated in a
circuit diagram. Even in such a case, the expression "a wiring is
connected to a gate" may be used in this specification.
Embodiment 1
[0040] In this embodiment, an example of a structure of a memory
cell which is a semiconductor memory device and its operation
example will be described with reference to FIGS. 1A and 1B, FIGS.
2A and 2B, and the like.
[0041] In a semiconductor memory device 300 illustrated in FIG. 1A,
which is one embodiment of the present invention, a memory cell CL
is formed with a stack of sub memory cells SCL each including a
transistor, a first capacitor (also referred to as a front
capacitor (Cf)), and a second capacitor (also referred to as a back
capacitor (Cb)). The memory cells CL are arranged in matrix of a
(in the horizontal direction).times.b (in the vertical direction)
in a plane (a and b are natural numbers).
[0042] The sub memory cell SCL is a memory device including a
transistor, a front capacitor, and a back capacitor; that is, a
DRAM is formed therein.
[0043] The memory cell CL includes c sub memory cells SCL_1 to
SCL_c (c is a natural number) which are stacked. The sub memory
cell SCL_j (j is a natural number from 1 to c) includes a
transistor Tr_j (j is a natural number from 1 to c), a front
capacitor Cf_j (j is a natural number from 1 to c), and a back
capacitor Cb_j (j is a natural number from 1 to c). The transistor
Tr_j is what is called a dual-gate transistor which is controlled
by a gate of the transistor Tr_j (also referred to as a first gate
or a front gate) and a gate of a transistor Tr_(j-1) (also referred
to as a second gate or a back gate) which overlaps with the gate of
the transistor Tr_j with a semiconductor film positioned
therebetween. Note that in the case of a transistor Tr_1, a back
gate thereof is not a gate of the transistor Tr_(j-1) but a wiring
which overlaps with a gate of the transistor TO with a
semiconductor film of the transistor Tr_1 positioned therebetween.
Note that the front gate and the back gate of the transistor in
each sub memory cell are electrically connected to each other.
[0044] The front capacitor Cf_j is formed using a capacitance of a
gate insulating film between a capacitor electrode which is formed
using the same material and same layer as those of the front gate
and one of a source and a drain of the transistor Tr_j. The back
capacitor Cb_j is formed using a capacitance of an insulating film
between a capacitor electrode of a front capacitor Cf_(j-1) and the
one of the source and the drain of the transistor Tr_j.
[0045] Note that a back capacitor Cb_1 may be formed using a
capacitance of an insulating film between one of a source and a
drain of the transistor Tr_1 and a capacitor wiring which is
separately provided below a sub memory cell SCL_1.
[0046] A circuit connection of the memory cell CL including the sub
memory cells SCL_1 to SCL_c is as follows as illustrated in FIG.
1B: for example, in the case of the sub memory cell SCL_1, a front
gate and the back gate of the transistor Tr_1 are connected to a
word line WL, one of the source and the drain of the transistor
Tr_1 is connected to a bit line BL_1, the other of the source and
the drain of the transistor Tr_1 is connected to one end of a front
capacitor Cf_1 and one end of the back capacitor Cb_1, and the
other end of the front capacitor Cf_1 and the other end of the back
capacitor Cb_1 are grounded (connected to GND). In addition, the
other end of the front capacitor Cf_1 is connected to the other end
of a back capacitor Cb_2 in a sub memory cell SCL_2.
[0047] The gates of the transistors in the sub memory cells which
are stacked are connected to the word line. Therefore, when a
signal is input to the word line, the transistors in the stacked
sub memory cells can be operated at the same time.
[0048] As illustrated in FIG. 1B, the other end of the back
capacitor Cb_j is grounded in the case where j is 1, and is
connected to the other end of a front capacitor Cf_(j-1) in the
case where j is greater than 1.
[0049] As the transistor Tr_j, a transistor with small off-state
current is used. For example, with the use of a wide-gap
semiconductor having a band gap of 2.5 eV or higher, a transistor
with small off-current can be formed. In particular, an oxide
semiconductor is preferably used.
[0050] When the transistor with small off-state current is used in
the sub memory cell, charges held in the front capacitor and the
back capacitor can be prevented from leaking through the transistor
Tr_j. Accordingly, a holding time of a potential can be prolonged
and therefore the frequency of refresh in the DRAM can be reduced,
so that the power consumption can be reduced.
[0051] The transistor Tr_j described in this embodiment is what is
called a dual-gate transistor having a front gate and a back gate.
Thus, when a voltage which is higher than the threshold voltage is
applied to the front gate of the transistor, the transistor is
turned on. In addition, since the same voltage is applied to the
back gate at this time, the threshold voltage is shifted
negatively. Accordingly, on-state current in the case where a gate
voltage is higher than a certain threshold voltage is larger than
on-state current of a transistor having no back gate. In addition,
when a voltage which is lower than the threshold voltage is applied
to the front gate of the transistor, the transistor is turned off.
In addition, since the same voltage is applied to the back gate at
this time, the threshold voltage is shifted positively.
Accordingly, off-state current in the case where a gate voltage is
lower than a certain threshold voltage is smaller than off-state
current of a transistor having no back gate.
[0052] In other words, since the semiconductor memory device
described in this embodiment is formed so that both high on-state
current and low off-state current are obtained by using the
transistor including the oxide semiconductor, the semiconductor
memory device can operate at high speed and consume low power.
[0053] Furthermore, by adjusting the capacitance of the capacitor
in each sub memory cell, a plurality of potential levels can be
set. Thus, a multi-valued memory cell can be manufactured.
[0054] Next, methods for writing and reading data to/from the
memory cell are described below.
[0055] Writing of data to the memory cell can be performed in each
sub memory cell. Specifically, the potential of the word line is
set to VH (a potential which is higher than the sum of the
threshold voltage (Vth) of the transistor and VDD (power supply
potential)). Next, a potential of a bit line which is selected
arbitrarily is set to VDD, and the other bit lines are set to GND.
As a result, VDD is charged in a capacitor in a sub memory cell
which is connected to the selected bit line. Then, the potential of
the word line is set to GND, whereby data is held in the sub memory
cell. After that, data is sequentially written to other sub memory
cells. This is the method for wiring data to the memory cell.
[0056] Low off-state current of the transistor using an oxide
semiconductor film, which is one embodiment of the present
invention, enables data written to the memory cell array in this
manner to be stored for a long time.
[0057] Then, a method for reading data is described. Data reading
is performed in each sub memory cell. First, a potential of a bit
line which is selected arbitrarily is set to a predetermined
potential (fixed potential). Next, the potential of the word line
is set to VH, whereby a potential corresponding to data written to
the capacitor is applied to the bit line. After that, the applied
potential is read by a sense amplifier (not illustrated in
particular). Note that data is lost at the same time as the data
reading; however the data can be amplified by operation of the
sense amplifier and then can be rewritten in the sub memory cell.
After that, data is sequentially read from other sub memory cells.
This is the method for reading data from the memory cell.
[0058] The methods for writing and reading data to/from the memory
cell are not limited to the methods in which writing and reading
are performed on each sub memory cell. Alternatively, writing and
reading may be performed on all the sub memory cells at a time.
[0059] Next, a cross-sectional structure of the memory cell CL, in
which the sub memory cells SCL overlap with each other to be
stacked as illustrated in FIGS. 1A and 1B, is described using FIGS.
2A and 2B. The memory cell CL illustrated in FIGS. 2A and 2B
includes the c sub memory cells SCL_1 to SCL_c which overlap with
each other. Each sub memory cell includes the transistor Tr_j (j is
a natural number from 1 to c), the front capacitor Cf_j (j is a
natural number from 1 to c), and the back capacitor Cb_j (j is a
natural number from 1 to c). FIG. 2A is a top view of the sub
memory cell SCL_j and FIG. 2B is a cross-sectional view of the sub
memory cells SCL_1 to SCL_c.
[0060] In the top view of FIG. 2A, the transistor Tr_j and the
front capacitor Cf_j provided in the sub memory cell SCL_j are
illustrated. Note that the back capacitor Cb_j is not illustrated
to avoid complexity. Cross sections A-B, C-D, and E-F taken along
dashed dotted lines A-B, C-D, and E-F, respectively, in the top
view of the sub memory cell SCL_j in FIG. 2A are illustrated in
FIG. 2B.
[0061] As illustrated in FIG. 2B, the sub memory cells overlap with
each other to be stacked, and films in the transistors and the
capacitors included in the sub memory cells also overlap with each
other. All of the front gates (including the back gates) of the
transistors in the sub memory cells are electrically connected to
each other.
[0062] Next, a cross sectional structure of the transistor Tr_1,
the front capacitor Cf_1, and the back capacitor Cb_1 in the sub
memory cell SCL_1 is described in detail using FIGS. 3A and 3B.
[0063] FIG. 3A is a top view of the transistor Tr_1 and the front
capacitor Cf_1 in the sub memory cell SCL_1. Note that the back
capacitor Cb_1 is not illustrated to avoid complexity. Cross
sections A-B, C-D, and E-F taken along dashed dotted lines A-B,
C-D, and E-F, respectively, in the top view of the sub memory cell
SCL_1 in FIG. 3A are illustrated in FIG. 3B
[0064] The transistor Tr_1 illustrated in FIG. 3B includes a
substrate 100, a first wiring 101 and a third wiring 140 which are
provided over the substrate 100, a first interlayer insulating film
102 which is provided over the first wiring 101 and the third
wiring 140, a base insulating film 104 which is provided over the
first interlayer insulating film 102, an oxide semiconductor film
106 which is provided over the base insulating film 104 and
includes a channel formation region 106a and source and drain
regions 106b, a gate insulating film 108 over the oxide
semiconductor film 106, a gate electrode 110 and a capacitor
electrode 130 over the gate insulating film 108, a second
interlayer insulating film 112 over the gate electrode 110 and the
capacitor electrode 130, and a second wiring 114 which is connected
to the source or drain regions 106b in a contact hole which is
provided in the second interlayer insulating film 112.
[0065] The capacitor electrode 130 in the capacitor Cf_1 can be
formed using the same material and the same layer as those of the
gate electrode 110.
[0066] The third wiring 140 in the capacitor Cb_1 can be formed
using the same material and the same layer as those of the first
wiring 101.
[0067] The first wiring 101 functions as the back gate of the
transistor Tr_1.
[0068] Note that a structure may be employed in which the base
insulating film 104 is not particularly provided and the first
interlayer insulating film 102 also has a function as the base
insulating film 104.
[0069] The contact hole is not limited to the one described in this
embodiment. For example, the contact hole may be formed at a time
so as to penetrate a plurality of layers. Alternatively, the
contact hole may be formed separately in individual layers by
plural steps.
[0070] The oxide semiconductor film 106 in this embodiment includes
the channel formation region 106a and the source and drain regions
106b which have lower resistance than the channel formation region
106a. Contact resistance to the second wiring 114 can be reduced by
providing the source and drain regions 106b as described above, so
that the on-state characteristics of the transistor can be
improved. Note that the oxide semiconductor film 106 is not limited
to the one including the source and drain regions 106b as described
above, and the oxide semiconductor film may have no low resistance
region.
[0071] The source and drain regions 106b contain one or more kinds
of elements selected from phosphorus, boron, nitrogen, and
fluorine. When one or more of the above elements are added to the
oxide semiconductor film, the resistance value of the oxide
semiconductor film can be reduced.
[0072] There is no particular limitation on the substrate 100 as
long as it has heat resistance enough to withstand at least heat
treatment performed later. For example, a glass substrate, a
ceramic substrate, a quartz substrate, or a sapphire substrate may
be used as the substrate 100. Alternatively, a single crystal
semiconductor substrate or a polycrystalline semiconductor
substrate made of silicon, silicon carbide, or the like; a compound
semiconductor substrate made of GaN or the like; a
silicon-on-insulator (SOI) substrate; or the like may be used as
the substrate 100. Still alternatively, any of these substrates
further provided with a semiconductor element is preferably used as
the substrate 100.
[0073] Further alternatively, a flexible substrate may be used as
the substrate 100. Note that as a method for forming a transistor
over a flexible substrate, there is also a method in which, after a
transistor is formed over a non-flexible substrate, the transistor
is separated from the non-flexible substrate and transferred to the
substrate 100 which is a flexible substrate. In that case, a
separation layer is preferably provided between the non-flexible
substrate and the transistor.
[0074] As the substrate 100, a substrate which has been subjected
to heat treatment may be used. For example, the heat treatment
performed on the substrate may be performed with a gas rapid
thermal annealing (GRTA) apparatus, in which heat treatment is
performed using a high-temperature gas, at 650.degree. C. for 1
minute to 5 minutes. As the high-temperature gas for GRTA, an inert
gas which does not react with an object to be processed by heat
treatment, such as nitrogen or a rare gas like argon, is used.
Alternatively, the heat treatment may be performed with an electric
furnace at 500.degree. C. for 30 minutes to 1 hour.
[0075] The first wiring 101 and the third wiring 140 can be formed
using a metal material such as molybdenum, titanium, tantalum,
tungsten, aluminum, copper, chromium, neodymium, or scandium or an
alloy material which contains any of these materials as its main
component. Alternatively, a semiconductor film typified by a
polycrystalline silicon film doped with an impurity element such as
phosphorus, or a silicide film such as a nickel silicide film may
be used as the first wiring 101. Further, the first wiring 101 and
the third wiring 140 may have a single-layer structure or a
stacked-layer structure.
[0076] The first wiring 101 and the third wiring 140 can also be
formed using a conductive material such as indium oxide-tin oxide,
indium oxide containing tungsten oxide, indium zinc oxide
containing tungsten oxide, indium oxide containing titanium oxide,
indium tin oxide containing titanium oxide, indium oxide-zinc
oxide, or indium tin oxide to which silicon oxide is added.
[0077] The first interlayer insulating film 102 and the base
insulating film 104 may be formed to have a single-layer structure
or a stacked-layer structure including one or more of silicon
oxide, silicon oxynitride, silicon nitride oxide, silicon nitride,
aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide,
yttrium oxide, gallium oxide, lanthanum oxide, cesium oxide,
tantalum oxide, and magnesium oxide.
[0078] Heat treatment is preferably performed after the formation
of the base insulating film 104 to remove impurities such as
hydrogen and moisture which are contained in the first interlayer
insulating film 102 or the base insulating film 104. The heat
treatment is performed at a temperature higher than or equal to
350.degree. C. and lower than the strain point of the substrate,
preferably higher than or equal to 450.degree. C. and lower than or
equal to 650.degree. C. An atmosphere of the heat treatment may be
an inert atmosphere, an oxidizing atmosphere, or the like.
[0079] Further, it is preferable that the first interlayer
insulating film 102 and the base insulating film 104 have
sufficient planarity. Specifically, the films serving as a base are
provided so as to have an average surface roughness (Ra) of 1 nm or
less, preferably 0.3 nm or less, further preferably 0.1 nm or less.
When Ra is less than or equal to the above value, a crystal region
is easily formed in the oxide semiconductor film. Note that Ra is
obtained by expanding, into three dimensions, arithmetic mean
surface roughness that is defined by JIS B 0601: 2001
(ISO4287:1997) so as to be able to apply it to a curved surface. Ra
can be expressed as an "average value of the absolute values of
deviations from a reference surface to a designated surface" and is
defined by Formula 1.
Ra = 1 S 0 .intg. y 1 y 2 .intg. x 1 x 2 f ( x , y ) - Z 0 x y [
Formula 1 ] ##EQU00001##
[0080] Here, the specific surface is a surface which is a target of
roughness measurement, and is a quadrilateral region which is
specified by four points represented by the coordinates (x.sub.1,
y.sub.1, f(x.sub.1, y.sub.1)), (x.sub.1, y.sub.2, f(x.sub.1,
y.sub.2)), (x.sub.2, y.sub.1, f(x.sub.2, y.sub.1)), and (x.sub.2,
y.sub.2, f(x.sub.2, y.sub.2)). S.sub.0 represents the area of a
rectangle which is obtained by projecting the specific surface on
the xy plane, and Z.sub.0 represents the average height of the
specific surface. Ra can be measured using an atomic force
microscope (AFM).
[0081] In this specification, silicon oxynitride refers to a
substance that contains a larger amount of oxygen than that of
nitrogen. For example, silicon oxynitride contains oxygen,
nitrogen, silicon, and hydrogen at concentrations higher than or
equal to 50 at. % and lower than or equal to 70 at. %, higher than
or equal to 0.5 at. % and lower than or equal to 15 at. %, higher
than or equal to 25 at. % and lower than or equal to 35 at. %, and
higher than or equal to 0 at. % and lower than or equal to 10 at.
%, respectively. In addition, silicon nitride oxide refers to a
substance that contains a larger amount of nitrogen than that of
oxygen. For example, silicon nitride oxide contains oxygen,
nitrogen, silicon, and hydrogen at concentrations higher than or
equal to 5 at. % and lower than or equal to 30 a. %, higher than or
equal to 20 at. % and lower than or equal to 55 at. %, higher than
or equal to 25 at. % and lower than or equal to 35 at. %, and
higher than or equal to 10 at. % and lower than or equal to 25 at.
%, respectively. Note that the above ranges are ranges for cases
where measurement is performed using Rutherford backscattering
spectrometry (RBS) and hydrogen forward scattering spectrometry
(HFS). Moreover, the total of the percentages of the constituent
elements does not exceed 100 at. %.
[0082] It is preferable that an insulating film which releases
oxygen by heat treatment is used as the first interlayer insulating
film 102 and the base insulating film 104.
[0083] To release oxygen by heat treatment means that the released
amount of oxygen which is converted into oxygen atoms is greater
than or equal to 1.0.times.10.sup.18 atoms/cm.sup.3, preferably
greater than or equal to 3.0.times.10.sup.20 atoms/cm.sup.3 in a
thermal desorption spectroscopy (TDS) analysis.
[0084] Here, a method in which the amount of released oxygen is
measured by being converted into oxygen atoms using TDS analysis
will now be described.
[0085] The amount of released gas in TDS analysis is proportional
to the integral value of a spectrum. Therefore, the amount of
released gas can be calculated from the ratio between the integral
value of a measured spectrum and the reference value of a standard
sample. The reference value of a standard sample refers to the
ratio of the density of a predetermined atom contained in a sample
to the integral value of a spectrum.
[0086] For example, the number of the released oxygen molecules
(N.sub.O2) from an insulating film can be found according to a
numerical Formula 2 with the TDS analysis results of a silicon
wafer containing hydrogen at a predetermined density which is the
standard sample and the TDS analysis results of the insulating
film. Here, all spectra having a mass number of 32 which are
obtained by the TDS analysis are assumed to originate from an
oxygen molecule. CH.sub.3OH, which is given as a gas having a mass
number of 32, is not taken into consideration on the assumption
that it is unlikely to be present. Further, an oxygen molecule
including an oxygen atom having a mass number of 17 or 18 which is
an isotope of an oxygen atom is not taken into consideration either
because the proportion of such a molecule in the natural world is
minimal.
N O 2 = N H 2 S H 2 .times. S O 2 .times. .alpha. [ Formula 2 ]
##EQU00002##
[0087] N.sub.H2 is the value obtained by conversion of the number
of hydrogen molecules desorbed from the standard sample into
densities. S.sub.H2 is the integral value of a spectrum when the
standard sample is subjected to TDS analysis. Here, the reference
value of the standard sample is set to N.sub.H2/S.sub.H2. S.sub.O2
is the integral value of a spectrum when the insulating film is
subjected to TDS analysis. .alpha. is a coefficient affecting the
intensity of the spectrum in the TDS analysis. Refer to Japanese
Published Patent Application No. H6-275697 for details of the
Formula 2. Note that the amount of released oxygen from the above
insulating film is measured with a thermal desorption spectroscopy
apparatus produced by ESCO Ltd., EMD-WA1000S/W using a silicon
wafer containing a hydrogen atom at 1.times.10.sup.16
atoms/cm.sup.2 as the standard sample.
[0088] Further, in the TDS analysis, oxygen is partly detected as
an oxygen atom. The ratio between oxygen molecules and oxygen atoms
can be calculated from the ionization rate of the oxygen molecules.
Note that, since the above a is determined considering the
ionization rate of the oxygen molecules, the number of the released
oxygen atoms can also be estimated through the evaluation of the
number of the released oxygen molecules.
[0089] Note that N.sub.O2 is the number of the released oxygen
molecules. The amount of released oxygen when converted into oxygen
atoms is twice the number of the released oxygen molecules.
[0090] In the transistor including an oxide semiconductor film,
oxygen is supplied from the base insulating film to the oxide
semiconductor film, whereby an interface state density between the
oxide semiconductor film and the base insulating film can be
reduced. As a result, carrier trapping at the interface between the
oxide semiconductor film and the base insulating film due to the
operation of a transistor or the like can be suppressed, and thus,
the transistor can have high reliability.
[0091] Further, in some cases, charge is generated due to oxygen
vacancies in the oxide semiconductor film. In general, part of
oxygen vacancies in an oxide semiconductor film serves as a donor
and causes release of an electron which is a carrier. As a result,
the threshold voltage of a transistor shifts in the negative
direction. When oxygen is sufficiently supplied from the base
insulating film to the oxide semiconductor film and the oxide
semiconductor film preferably contains excessive oxygen, the
density of oxygen vacancies in the oxide semiconductor film, which
causes the negative shift of the threshold voltage, can be
reduced.
[0092] A material used for the oxide semiconductor film 106
preferably contains at least indium (In) or zinc (Zn). In
particular, In and Zn are preferably contained. As a stabilizer for
reducing variation in electrical characteristics of a transistor
including the oxide semiconductor film 106, gallium (Ga) is
preferably additionally contained. Tin (Sn), hafnium (Hf), aluminum
(Al), titanium (Ti), or zirconium (Zr) is preferably contained as a
stabilizer.
[0093] As another stabilizer, one or plural kinds of lanthanoid
such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium
(Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb),
dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium
(Yb), or lutetium (Lu) may be contained.
[0094] As the oxide semiconductor, for example, indium oxide, tin
oxide, zinc oxide, an In--Zn-based oxide, a Sn--Zn-based oxide, an
Al--Zn-based oxide, a Zn--Mg-based oxide, a Sn--Mg-based oxide, an
In--Mg-based oxide, an In--Ga-based oxide, an In--Ga--Zn-based
oxide (also referred to as IGZO), an In--Al--Zn-based oxide, an
In--Sn--Zn-based oxide, a Sn--Ga--Zn-based oxide, an
Al--Ga--Zn-based oxide, a Sn--Al--Zn-based oxide, an
In--Hf--Zn-based oxide, an In--La--Zn-based oxide, an
In--Ce--Zn-based oxide, an In--Pr--Zn-based oxide, an
In--Nd--Zn-based oxide, an In--Sm--Zn-based oxide, an
In--Eu--Zn-based oxide, an In--Gd--Zn-based oxide, an
In--Tb--Zn-based oxide, an In--Dy--Zn-based oxide, an
In--Ho--Zn-based oxide, an In--Er--Zn-based oxide, an
In--Tm--Zn-based oxide, an In--Yb--Zn-based oxide, an
In--Lu--Zn-based oxide, an In--Sn--Ga--Zn-based oxide, an
In--Hf--Ga--Zn-based oxide, an In--Al--Ga--Zn-based oxide, an
In--Sn--Al--Zn-based oxide, an In--Sn--Hf--Zn-based oxide, or an
In--Hf--Al--Zn-based oxide can be used.
[0095] The oxide semiconductor film 106 can be in a single crystal
state, a polycrystalline (also referred to as polycrystal) state,
an amorphous state, or the like.
[0096] The oxide semiconductor film 106 is preferably a c-axis
aligned crystalline oxide semiconductor (CAAC-OS) film.
[0097] The CAAC-OS film is not completely single crystal nor
completely amorphous. The CAAC-OS film is an oxide semiconductor
film with a crystal-amorphous mixed phase structure where crystal
parts are included in an amorphous phase. Note that in most cases,
the crystal part fits inside a cube whose one side is less than 100
nm. From an observation image obtained with a transmission electron
microscope (TEM), a boundary between an amorphous part and a
crystal part in the CAAC-OS film is not clear. Further, with the
TEM, a grain boundary in the CAAC-OS film is not found. Thus, in
the CAAC-OS film, a reduction in electron mobility, due to the
grain boundary, is suppressed.
[0098] In each of the crystal parts included in the CAAC-OS film, a
c-axis is aligned in a direction parallel to a normal vector of a
surface where the CAAC-OS film is formed or a normal vector of a
surface of the CAAC-OS film, triangular or hexagonal atomic
arrangement which is seen from the direction perpendicular to the
a-b plane is formed, and metal atoms are arranged in a layered
manner or metal atoms and oxygen atoms are arranged in a layered
manner when seen from the direction perpendicular to the c-axis.
Note that, among crystal parts, the directions of an a-axis and a
b-axis of one crystal part may be different from those of another
crystal part. In this specification, a simple term "perpendicular"
includes a range from 85.degree. to 95.degree.. In addition, a
simple term "parallel" includes a range from -5.degree. to
5.degree..
[0099] In the CAAC-OS film, distribution of crystal parts is not
necessarily uniform. For example, in the formation process of the
CAAC-OS film, in the case where crystal growth occurs from a
surface side of the oxide semiconductor film, the proportion of
crystal parts in the vicinity of the surface of the oxide
semiconductor film is higher than that in the vicinity of the
surface where the oxide semiconductor film is formed in some cases.
Further, when an impurity is added to the CAAC-OS film, the crystal
part in a region to which the impurity is added becomes amorphous
in some cases.
[0100] Since the c-axes of the crystal parts included in the
CAAC-OS film are aligned in the direction parallel to a normal
vector of a surface where the CAAC-OS film is formed or a normal
vector of a surface of the CAAC-OS film, the directions of the
c-axes may be different from each other depending on the shape of
the CAAC-OS film (the cross-sectional shape of the surface where
the CAAC-OS film is formed or the cross-sectional shape of the
surface of the CAAC-OS film). Note that the direction of c-axis of
the crystal part is the direction parallel to a normal vector of
the surface where the CAAC-OS film is formed or a normal vector of
the surface of the CAAC-OS film when the CAAC-OS film is formed.
The crystal part is formed by film formation or by performing
treatment for crystallization such as heat treatment after film
formation.
[0101] With the use of the CAAC-OS film in a transistor, change in
electric characteristics of the transistor due to irradiation with
visible light or ultraviolet light is small. Thus, the transistor
has high reliability.
[0102] Note that part of oxygen included in the oxide semiconductor
film may be substituted with nitrogen.
[0103] In addition, in an oxide semiconductor having a crystal
part, such as the CAAC-OS, defect in the bulk can be further
reduced. In addition, the oxide semiconductor can have higher
mobility than an amorphous oxide semiconductor by improvement in
surface planarity. To improve the surface flatness, the oxide
semiconductor is preferably formed over a flat surface.
Specifically, the oxide semiconductor may be formed over a surface
with the average surface roughness (Ra) of less than or equal to 1
nm, preferably less than or equal to 0.3 nm, more preferably less
than or equal to 0.1 nm.
[0104] The oxide semiconductor film can be formed by sputtering, a
molecular beam epitaxy (MBE) method, a CVD method, a pulse laser
deposition method, an atomic layer deposition (ALD) method, or the
like as appropriate. In addition, the oxide semiconductor film may
be deposited using a sputtering apparatus in which deposition is
performed in a state where surfaces of a plurality of substrates
are set substantially perpendicularly to a surface of a sputtering
target.
[0105] It is preferable that the oxide semiconductor film is highly
purified and hardly contains impurities such as copper, aluminum,
and chlorine. In the process for manufacturing the transistor,
steps in which these impurities are not mixed or attached to the
surface of the oxide semiconductor film are preferably selected as
appropriate. In the case where the impurities are attached to the
surface of the oxide semiconductor film, the impurities on the
surface of the oxide semiconductor film are preferably removed by
exposure to oxalic acid or dilute hydrofluoric acid or plasma
treatment (such as N.sub.2O plasma treatment). Specifically, the
copper concentration in the oxide semiconductor film is lower than
or equal to 1.times.10.sup.18 atoms/cm.sup.3, preferably lower than
or equal to 1.times.10.sup.17 atoms/cm.sup.3. The aluminum
concentration in the oxide semiconductor film is lower than or
equal to 1.times.10.sup.18 atoms/cm.sup.3. Further, the
concentration of chlorine in the oxide semiconductor film is lower
than or equal to 2.times.10.sup.18 atoms/cm.sup.3.
[0106] The gate insulating film 108 can be formed by a plasma CVD
method, a sputtering method, or the like. The gate insulating film
108 may be formed of a single layer or a stack of layers using one
or more kinds of materials selected from silicon oxide, silicon
oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide,
gallium oxide, magnesium oxide, tantalum oxide, yttrium oxide,
zirconium oxide, lanthanum oxide, and neodymium oxide.
[0107] The gate insulating film 108 can be formed using a high-k
material such as hafnium oxide, yttrium oxide, hafnium silicate
(HfSi.sub.xO.sub.y (x>0, y>0)), hafnium silicate to which
nitrogen is added (HfSiO.sub.xN.sub.y (x>0, y>0)), hafnium
aluminate (HfAl.sub.xO.sub.y (x>0, y>0)), or lanthanum oxide,
whereby gate leakage current can be reduced. The use of the gate
insulating film 108 for the capacitor is preferable because it
makes it possible to increase the capacitance of the capacitor.
Further, the gate insulating film 108 may have a single-layer
structure or a stacked-layer structure.
[0108] The gate electrode 110 and the capacitor electrode 130 can
be formed using a metal material such as molybdenum, titanium,
tantalum, tungsten, aluminum, copper, chromium, neodymium, or
scandium, or an alloy material which includes any of these
materials as a main component. Alternatively, a semiconductor film
typified by a polycrystalline silicon film doped with an impurity
element such as phosphorus, or a silicide film such as a nickel
silicide film may be used as the gate electrode 110. The gate
electrode 110 may be formed with either a single-layer structure or
a stacked-layer structure.
[0109] The gate electrode 110 and the capacitor electrode 130 can
also be formed using a conductive material such as indium oxide-tin
oxide, indium oxide containing tungsten oxide, indium zinc oxide
containing tungsten oxide, indium oxide containing titanium oxide,
indium tin oxide containing titanium oxide, indium oxide-zinc
oxide, or indium tin oxide to which silicon oxide is added.
[0110] As one layer of the gate electrode 110 which is in contact
with the gate insulating film 108, a metal oxide containing
nitrogen, specifically, an In--Ga--Zn--O film containing nitrogen,
an In--Sn--O film containing nitrogen, an In--Ga--O film containing
nitrogen, an In--Zn--O film containing nitrogen, a Sn--O film
containing nitrogen, an In--O film containing nitrogen, or a metal
nitride (e.g., InN or SnN) film can be used. These films each have
a work function of 5 eV (electron volts) or higher, preferably 5.5
eV or higher, which enables the threshold voltage, which is one of
electric characteristics of a transistor, to be positive when used
as the gate electrode layer.
[0111] The second interlayer insulating film 112 is formed using
the same material as that of the base insulating film 104.
[0112] It is preferable that the second interlayer insulating film
112 has low relative permittivity and a sufficient thickness. For
example, a silicon oxide film having a relative permittivity of
approximately 3.8 and a thickness of greater than or equal to 300
nm and less than or equal to 1000 nm may be used. A surface of the
interlayer insulating film 112 has a little fixed charge because of
influence of atmospheric components and the like, which might cause
the shift of the threshold voltage of the transistor. Therefore, it
is preferable that the interlayer insulating film 112 has relative
permittivity and a thickness such that the influence of the
electric charge at the surface is sufficiently reduced.
[0113] A metal film containing an element selected from aluminum
(Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti),
molybdenum (Mo), and tungsten (W), a metal nitride film containing
any of the above elements as its component (e.g., a titanium
nitride film, a molybdenum nitride film, or a tungsten nitride
film), or the like can be used to form the second wiring 114.
Alternatively, a film of a high-melting-point metal such as Ti, Mo,
or W or a metal nitride film thereof (e.g., a titanium nitride
film, a molybdenum nitride film, or a tungsten nitride film) may be
formed over or/and below a metal film such as an Al film or a Cu
film. Alternatively, the second wiring 114 may be formed using a
conductive metal oxide. As the electrically conductive metal oxide,
indium oxide (In.sub.2O.sub.3), tin oxide (SnO.sub.2), zinc oxide
(ZnO), indium oxide-tin oxide (In.sub.2O.sub.3--SnO.sub.2;
abbreviated to ITO), indium oxide-zinc oxide
(In.sub.2O.sub.3--ZnO), or any of these metal oxide materials in
which silicon oxide is contained can be used.
(Method for Manufacturing Transistor)
[0114] Next, a method for manufacturing the transistor Tr_1, the
front capacitor Cf_1, and the back capacitor Cb_1 in the cross
section taken along the line A-B in the sub memory cell SCL_1,
which is illustrated in FIG. 3B, is described using FIGS. 4A to 4C
and FIGS. 5A to 5C.
[0115] First, the first wiring 101 and the third wiring 140 are
formed over the substrate 100 (see FIG. 4A). The first wiring 101
and the third wiring 140 are formed in such a manner that a
conductive film is deposited over the substrate 100 and is
processed. Note that an insulating film may be additionally
provided between the substrate 100 and each of the first wiring 101
and the third wiring 140 depending on a material of the substrate
100. For example, a silicon nitride film or the like which has a
blocking property may be formed to prevent diffusion of impurities
from the substrate.
[0116] Note that "to process" means performing etching using a
resist mask formed by a photolithography method to obtain a film
having a desired shape, unless otherwise specified.
[0117] Note that the etching of the conductive film may be
performed by dry etching, wet etching, or both of them.
[0118] Next, the first interlayer insulating film 102 and the base
insulating film 104 are formed over the substrate 100, the first
wiring 101, and the third wiring 140 (see FIG. 4B). The first
interlayer insulating film 102 and the base insulating film 104 can
be formed by a chemical vapor deposition (CVD) method, a sputtering
method, a molecular beam epitaxy (MBE) method, or a pulsed laser
deposition (PLD) method and are preferably formed by a sputtering
method.
[0119] After the first interlayer insulating film 102 is formed
over the substrate 100, the first wiring 101, and the third wiring
140, a surface of the first interlayer insulating film 102 is
preferably subjected to planarization treatment. As the
planarization treatment, chemical mechanical polishing (CMP)
treatment or the like may be employed, for example. After the
surface of the first interlayer insulating film 102 is planarized,
the base insulating film 104 is formed. Such planarization of the
surface of the first interlayer insulating film 102 prevents a
breakage of a film to be formed in a later step, which can lead to
an improvement in accuracy of light exposure by a photolithography
method. Note that planarization treatment may be performed in each
of the timing after the formation of the first interlayer
insulating film 102 and the timing after the formation of the base
insulating film 104, or may be performed only after the formation
of the base insulating film 104.
[0120] Although there is no particular limitation on the
planarization treatment, CMP treatment, dry-etching treatment,
plasma treatment, or the like can be used as the planarization
treatment.
[0121] To remove impurities such as hydrogen and moisture contained
in the first interlayer insulating film 102 or the base insulating
film 104, heat treatment is preferably performed after the
deposition of the first interlayer insulating film 102 or the base
insulating film 104. The heat treatment is performed at a
temperature higher than or equal to 350.degree. C. and lower than
the strain point of the substrate, preferably higher than or equal
to 450.degree. C. and lower than or equal to 650.degree. C. The
heat treatment may be performed at an inert atmosphere or an
oxidizing atmosphere.
[0122] Next, an oxide semiconductor film is deposited over the base
insulating film 104. The oxide semiconductor film may be deposited
by a CVD method, a sputtering method, an MBE method, or a PLD
method and is preferably formed by a sputtering method.
[0123] In the deposition of the oxide semiconductor film, in order
that hydrogen and moisture are contained in the oxide semiconductor
film as little as possible, it is preferable that the substrate is
preheated in a treatment chamber of a sputtering apparatus as
pretreatment of the deposition of the oxide semiconductor film so
that impurities such as hydrogen and moisture adsorbed on the
substrate 100 and the base insulating film 104 are detached.
[0124] Further, before the oxide semiconductor film is deposited,
planarization treatment may be performed on a surface of the base
insulating film 104.
[0125] As the plasma treatment, reverse sputtering can be
performed. The reverse sputtering is a method in which voltage is
applied to a substrate side with use of an RF power source, for
example, in an argon atmosphere, and plasma is generated in the
vicinity of the substrate so that a surface to be processed is
modified. Note that instead of an argon atmosphere, a nitrogen
atmosphere, a helium atmosphere, an oxygen atmosphere, or the like
may be used.
[0126] Note that the oxide semiconductor film is preferably formed
in conditions such that a large amount of oxygen is contained in
the oxide semiconductor film at the time of the deposition (e.g.,
the deposition is performed in an atmosphere containing oxygen at
100% by a sputtering method).
[0127] After formation of the oxide semiconductor film, heat
treatment may be performed. By the heat treatment, the degree of
crystallinity of the oxide semiconductor film is increased. In
addition, the concentration of impurities (such as hydrogen and
moisture) in the oxide semiconductor film can be reduced, so that
the defect level in the oxide semiconductor film can be
reduced.
[0128] The heat treatment may be performed in an atmosphere
selected from an oxidizing atmosphere, an inert atmosphere, a
reduced-pressure atmosphere, and a dry-air atmosphere or in a
combined atmosphere of two or more of the aforementioned
atmospheres. Preferably, heat treatment is performed in an inert
atmosphere and then heat treatment is further performed in an
oxidizing atmosphere. The heat treatment may be performed at a
temperature higher than or equal to 150.degree. C. and lower than
or equal to 650.degree. C., preferably higher than or equal to
250.degree. C. and lower than or equal to 500.degree. C., and
further preferably higher than or equal to 300.degree. C. and lower
than or equal to 450.degree. C. A resistance heating method, a lamp
heating method, a method using a heated gas, or the like may be
used in the heat treatment.
[0129] Note that an oxidizing atmosphere refers to an atmosphere
containing an oxidizing gas. Oxidizing gas is oxygen, ozone,
nitrous oxide, or the like, and it is preferable that the oxidizing
gas does not contain water, hydrogen, and the like. For example,
the purity of oxygen, ozone, or nitrous oxide to be introduced to a
heat treatment apparatus is greater than or equal to 8N
(99.999999%), preferably greater than or equal to 9N (99.9999999%).
The oxidizing atmosphere may contain a mixed gas of an oxidizing
gas and an inert gas. In that case, the atmosphere contains an
oxidizing gas at a concentration of at least higher than or equal
to 10 ppm. By performing heat treatment in the oxidizing
atmosphere, the density of oxygen vacancies in the oxide
semiconductor film can be reduced.
[0130] The inert atmosphere contains an inert gas such as nitrogen
or a rare gas as its main component. Specifically, in an inert
atmosphere, the concentration of a reactive gas such as an
oxidizing gas is lower than 10 ppm. By performing heat treatment in
an inert atmosphere, the concentration of impurities included in
the oxide semiconductor film can be reduced.
[0131] In a reduced-pressure atmosphere, a pressure of a treatment
chamber is lower than or equal to 10 Pa. By performing heat
treatment in a reduced-pressure atmosphere, the concentration of
impurities included in the oxide semiconductor film can be reduced
as compared to the case of employing the inert atmosphere.
[0132] The dry-air atmosphere refers to an atmosphere with a dew
point of lower than or equal to -40.degree. C., preferably lower
than or equal to -50.degree. C. and with an oxygen content of
approximately 20% and a nitrogen content of approximately 80%. The
dry-air atmosphere is a kind of the oxidizing atmosphere. Since the
dry-air atmosphere is relatively low in cost, it is suitable for
mass production.
[0133] Next, the oxide semiconductor film is processed to form the
oxide semiconductor film 103 (see FIG. 4C).
[0134] Note that the etching of the oxide semiconductor film may be
dry etching, wet etching, or both dry etching and wet etching. As
an etchant used for wet etching of the oxide semiconductor film, a
mixed solution of phosphoric acid, acetic acid, and nitric acid, or
the like can be used. Alternatively, ITO-07N (produced by KANTO
CHEMICAL CO., INC.) may be used. Further, the oxide semiconductor
film may also be etched by dry etching using an inductively coupled
plasma (ICP) etching method.
[0135] Further alternatively, oxygen (which includes at least one
of an oxygen radical, an oxygen atom, and an oxygen ion) may be
introduced into the oxide semiconductor film to supply oxygen to
the oxide semiconductor film.
[0136] Oxygen is introduced to the oxide semiconductor film to
supply the oxygen to the film, whereby oxygen vacancies in the
oxide semiconductor film are compensated, which enables the oxide
semiconductor film to be close to an intrinsic semiconductor.
Accordingly, the threshold voltage of the transistor including the
oxide semiconductor film can be shifted in the positive direction,
so that the reliability of the transistor can be further
improved.
[0137] As a method for introducing the oxygen, an ion implantation
method, an ion doping method, plasma treatment, or the like can be
used.
[0138] Next, the gate insulating film 108 is formed over the oxide
semiconductor film 103. The gate insulating film 108 may be formed
by a CVD method, a sputtering method, an MBE method, or a PLD
method and is preferably formed by a sputtering method in
particular.
[0139] Next, a resist mask 107 is formed over the gate insulating
film 108. The resist mask 107 can be formed in such a manner that a
resist is applied to the gate insulating film 108 and then light
exposure and development are performed.
[0140] Then, a dopant is added to the oxide semiconductor film 103
using the resist mask 107 as a mask. The resistance of part of the
oxide semiconductor film 103, to which the dopant is added, is
reduced. By adding the dopant to the oxide semiconductor film 103
in the above manner, the oxide semiconductor film 106 which
includes the source and drain regions 106b resistance of which is
reduced by the addition of the dopant and the channel formation
region 106a to which the dopant is not added is formed (see FIG.
5A).
[0141] The dopant is an impurity which reduces the resistance of an
oxide semiconductor film. One or more of phosphorus (P), boron (B),
nitrogen (N), and fluorine (F) can be used as the dopant.
[0142] As a method for adding the dopant, an ion implantation
method, an ion doping method, or the like can be used. In addition,
the substrate 100 may be heated during the addition is
performed.
[0143] The addition of dopant may be performed plural times, and
the number of kinds of dopant may be plural.
[0144] Further, heat treatment may be performed thereon after the
dopant is added. As the preferable heating conditions, the heating
temperature is higher than or equal to 300.degree. C. and lower
than or equal to 700.degree. C., more preferably higher than or
equal to 300.degree. C. and lower than or equal to 450.degree. C.,
the heating time is one hour, and the heating atmosphere is an
oxygen atmosphere. The heat treatment may be performed in a
nitrogen atmosphere, reduced pressure, or the air (ultra-dry
air).
[0145] Next, the resist mask 107 is removed. Then, a conductive
film is deposited over the gate insulating film and processed by
etching to form the gate electrode 110 and the capacitor electrode
130 (see FIG. 5B).
[0146] Next, the second interlayer insulating film 112 is formed
over the gate insulating film 108, the gate electrode 110, and the
capacitor electrode 130. The second interlayer insulating film 112
may be formed by a CVD method, a sputtering method, an MBE method,
a PLD method, or a spin coating method using a material which is
similar to that of the base insulating film 104. Further, a contact
hole is formed in the second interlayer insulating film 112 to
expose part of one of the source and drain regions 106b, and then
the second wiring 114 which is connected to the one of the source
and drain regions 106b is formed (see FIG. 5C).
[0147] The transistor is a planar transistor in this embodiment but
is not limited thereto. Any of a top-gate top-contact transistor, a
top-gate bottom-contact transistor, a bottom-gate top-contact
transistor, a bottom-gate bottom-contact transistor, and the like
in each of which a source electrode and a drain electrode are
formed in contact with an oxide semiconductor film may be used.
Further, a top shape of the transistor is formed in square shape in
this embodiment but may be formed in a circle shape or the
like.
[0148] As described above, the dual-gate transistor Tr_1 in which
the gate electrode 110 (also referred to as the front gate) and the
first wiring 101 (also referred to as the back gate) overlap with
the channel formation region 106a can be formed. Further, the front
capacitor Cf_1, which is formed with the other of the source and
drain regions 106b and the capacitor electrode 130, and the back
capacitor Cb_1, which is formed with the other of the source and
drain regions 106b and the third wiring 140, can be formed.
[0149] According to this embodiment, a front gate and a back gate
are provided in a transistor in which a channel region is provided
in an oxide semiconductor film, whereby the transistor having high
on-state characteristics and low off-state current characteristics
can be provided. The use of the transistor makes is possible to
provide a semiconductor memory device which operates at high speed
and consumes low power.
[0150] According to one embodiment of the present invention, a
front capacitor and a back capacitor can be formed, whereby the
capacitance of a capacitor in a semiconductor memory device can be
increased.
[0151] A semiconductor memory device such as a DRAM can be formed
using the transistor and the capacitor of one embodiment of the
present invention. Further, a plurality of semiconductor memory
devices are provided so as to overlap with each other to be
stacked, whereby a semiconductor memory device whose storage
capacity per unit area can be increased can be provided.
[0152] This embodiment can be implemented in appropriate
combination with any of the other embodiments.
Embodiment 2
[0153] A semiconductor memory device which has a structure
different from that of the semiconductor memory device of
Embodiment 1 will be described in this embodiment with reference to
FIGS. 6A to 6C. This embodiment is different from Embodiment 1 in
that the semiconductor memory device includes a transistor
including silicon in addition to a memory cell which is formed
using a transistor including an oxide semiconductor.
[0154] The transistor including silicon has larger field-effect
mobility than the transistor including an oxide semiconductor and
thus is preferably used in a peripheral circuit of a memory cell or
the like. In addition, the transistor including silicon is
preferably provided below the memory cell which is formed with a
stack of sub memory cells; however the transistor including silicon
may be provided between sub memory cells which are stacked and the
number of layers including the transistor may be one or more.
[0155] In this embodiment, the semiconductor memory device in which
the transistor including silicon is formed in the lowest layer and
the memory cell of Embodiment 1 is stacked thereover is
described.
[0156] FIGS. 6A to 6C are a top view and cross-sectional views of
the semiconductor memory device of this embodiment. FIG. 6A is a
top view of the sub memory cell SCL_j and FIG. 6B is a
cross-sectional view of the sub memory cells SCL_1 to SCL_c. As
illustrated in FIG. 6B, a layer including a transistor 800
including silicon is formed below the memory cell CL in which sub
memory cells are stacked to overlap with each other.
[0157] In the top view of FIG. 6A, the transistor Tr_j and the
front capacitor Cf_j provided in the sub memory cell SCL_j are
illustrated. Note that the back capacitor Cb_j is not illustrated
to avoid complexity. Cross sections A-B, C-D, and E-F taken along
dashed dotted lines A-B, C-D, and E-F, respectively, in the top
view of the sub memory cell SCL_j in FIG. 6A are illustrated in
FIG. 6B.
[0158] FIG. 6C is a cross-sectional view of the transistor 800
including silicon.
[0159] The transistor 800 includes a channel formation region 201
provided in a silicon substrate 200, impurity regions 206 which are
provided so as to sandwich the channel formation region 201, a gate
insulating layer 208 which is provided over the channel formation
region 201, a gate electrode 210 which is provided over the gate
insulating layer 208, a first interlayer insulating film 212 over
the gate electrode 210 and the impurity regions, source and drain
electrodes 214 which are connected to the impurity regions 206
through contact holes provided in the first interlayer insulating
film 212, and a second interlayer insulating film 216 over the
first interlayer insulating film 212 and the source and drain
electrodes 214.
[0160] An element isolation insulating layer 203 is formed on the
silicon substrate 200 so as to surround the transistor 800.
[0161] A sidewall insulating film may be formed on the sidewall of
the gate electrode 210 to form an LDD region. Note that it is
preferable that the transistor 800 is not provided with a sidewall
insulating layer as illustrated in FIG. 6C to achieve higher
integration.
[0162] Next, components starting from the first wiring 101 and the
third wiring 140 are sequentially formed, as described in
Embodiment 1, over the second interlayer insulating film 216 of the
transistor 800.
[0163] In the above manner, the transistor 800 including silicon
can be formed and the dual-gate transistor Tr_j including an oxide
semiconductor, which is described in Embodiment 1, can be formed to
be stacked over the transistor 800. In addition, the front
capacitor Cf_j, which is formed with the other of the source and
drain regions 106b and the capacitor electrode 130, and the back
capacitor Cb_j, which is formed with the other of the source and
drain regions 106b and the third wiring 140, can be formed.
[0164] According to this embodiment, the transistor 800 including
silicon and the transistor including the oxide semiconductor film
can be formed. In addition, the transistor including the oxide
semiconductor film is provided with the front gate and the back
gate, whereby the transistor can have high on-state characteristics
and low off-state current characteristics. The use of the
transistor makes it possible to provide a semiconductor memory
device which operates at high speed and consumes low power.
[0165] According to one embodiment of the present invention, the
semiconductor memory device in which the front capacitor and the
back capacitor are provided in each sub memory cell can be formed.
When the two capacitors are provided in such a manner, the total
capacitance of all the capacitors in the semiconductor memory
device can be increased.
[0166] A semiconductor memory device such as a DRAM can be formed
using the transistor and the capacitor of one embodiment of the
present invention. In addition, the plurality of semiconductor
memory devices are provided so as to overlap with each other to be
stacked, whereby a semiconductor memory device whose storage
capacity per unit area can be increased can be provided.
[0167] Further, since the transistor including silicon has larger
field-effect mobility than the transistor including an oxide
semiconductor, the transistor including silicon can be used in a
peripheral circuit or the like of a memory cell, so that the memory
cell and the peripheral circuit can be formed over the same
substrate.
[0168] This embodiment can be implemented in appropriate
combination with any of the other embodiments.
Embodiment 3
[0169] A central processing unit (CPU) can be formed using the
semiconductor memory device described in Embodiment 1 or Embodiment
2 for at least part of the CPU.
[0170] FIG. 7A is a block diagram illustrating a specific structure
of a CPU. The CPU illustrated in FIG. 7A includes an arithmetic
logic unit (ALU) 1191, an ALU controller 1192, an instruction
decoder 1193, an interrupt controller 1194, a timing controller
1195, a register 1196, a register controller 1197, a bus interface
(Bus I/F) 1198, a rewritable ROM 1199, and an ROM interface (ROM
I/F) 1189 over a substrate 1190. A semiconductor substrate, an SOI
substrate, a glass substrate, or the like is used as the substrate
1190. The ROM 1199 and the ROM interface 1189 may each be provided
over a separate chip. Obviously, the CPU illustrated in FIG. 7A is
only an example in which the structure is simplified, and an actual
CPU has various structures depending on the application.
[0171] An instruction that is input to the CPU through the bus
interface 1198 is input to the instruction decoder 1193 and decoded
therein, and then, input to the ALU controller 1192, the interrupt
controller 1194, the register controller 1197, and the timing
controller 1195.
[0172] The ALU controller 1192, the interrupt controller 1194, the
register controller 1197, and the timing controller 1195 conduct
various controls in accordance with the decoded instruction.
Specifically, the ALU controller 1192 generates signals for
controlling the operation of the ALU 1191. While the CPU is
executing a program, the interrupt controller 1194 judges an
interrupt request from an external input/output device or a
peripheral circuit on the basis of its priority or a mask state,
and processes the request. The register controller 1197 generates
an address of the register 1196, and reads/writes data from/to the
register 1196 in accordance with the state of the CPU.
[0173] The timing controller 1195 generates signals for controlling
operation timings of the ALU 1191, the ALU controller 1192, the
instruction decoder 1193, the interrupt controller 1194, and the
register controller 1197. For example, the timing controller 1195
includes an internal clock generator for generating an internal
clock signal CLK2 based on a reference clock signal CLK1, and
supplies the internal clock signal CLK2 to the above circuits.
[0174] In the CPU illustrated in FIG. 7A, a memory element is
provided in the register 1196. As the memory element in the
register 1196, for example, the semiconductor memory device
described in Embodiment 1 or Embodiment 2 can be used.
[0175] In the CPU illustrated in FIG. 7A, the register controller
1197 selects operation of holding data in the register 1196 in
accordance with an instruction from the ALU 1191. That is, the
register controller 1197 selects whether data is held by a logic
element which inverts a logic (logic level) or a capacitor in the
memory element included in the register 1196. When data is held by
the logic element which inverts a logic (logic level), a power
supply voltage is supplied to the memory element in the register
1196. When data is held by the capacitor, the data in the capacitor
is rewritten, and supply of the power supply voltage to the memory
element in the register 1196 can be stopped.
[0176] The power supply can be stopped by providing a switching
element between a memory element group and a node to which a power
supply potential VDD or a power supply potential VSS is supplied,
as illustrated in FIG. 7B or FIG. 7C. Circuits illustrated in FIGS.
7B and 7C are described below.
[0177] FIGS. 7B and 7C each illustrate an example of a structure
including any of the transistors described in Embodiment 1 and
Embodiment 2 as a switching element for controlling supply of a
power supply potential to a memory element.
[0178] The memory device illustrated in FIG. 7B includes a
switching element 1141 and a memory element group 1143 including a
plurality of memory elements 1142. Specifically, as each of the
memory elements 1142, the memory element described in Embodiment 1
or Embodiment 2 can be used. Each of the memory elements 1142
included in the memory element group 1143 is supplied with the
high-level power supply potential VDD through the switching element
1141. Further, each of the memory elements 1142 included in the
memory element group 1143 is supplied with a potential of a signal
IN and a potential of the low-level power supply potential VSS.
[0179] In FIG. 7B, a transistor whose active layer includes a
semiconductor with a wide band gap, such as an oxide semiconductor,
is used as the switching element 1141, and the switching of the
transistor is controlled by a signal SigA supplied to a gate
thereof.
[0180] Note that FIG. 7B illustrates the structure in which the
switching element 1141 includes only one transistor; however,
without limitation thereto, the switching element 1141 may include
a plurality of transistors. In the case where the switching element
1141 includes a plurality of transistors which serves as switching
elements, the plurality of transistors may be connected to each
other in parallel, in series, or in combination of parallel
connection and series connection.
[0181] In FIG. 7C, an example of a memory device in which each of
the memory elements 1142 included in the memory element group 1143
is supplied with the low-level power supply potential VSS through
the switching element 1141 is illustrated. The supply of the
low-level power supply potential VSS to each of the memory elements
1142 included in the memory element group 1143 can be controlled by
the switching element 1141.
[0182] When a switching element is provided between a memory
element group and a node to which the power supply potential VDD or
the power supply potential VSS is supplied, data can be held even
in the case where an operation of a CPU is temporarily stopped and
the supply of the power supply voltage is stopped; accordingly,
power consumption can be reduced. For example, while a user of a
personal computer does not input data to an input device such as a
keyboard, the operation of the CPU can be stopped, so that the
power consumption can be reduced.
[0183] Although the CPU is given as an example, the transistor can
also be applied to an LSI such as a digital signal processor (DSP),
a custom LSI, or a field programmable gate array (FPGA).
[0184] This embodiment can be implemented in appropriate
combination with any of the other embodiments.
Embodiment 4
[0185] In this embodiment, examples of an electronic appliance
including at least one of the semiconductor memory devices
described in Embodiment 1 or 2 and the CPU described in Embodiment
3 will be described.
[0186] FIG. 8A illustrates a portable information terminal. The
portable information terminal illustrated in FIG. 8A includes a
housing 9300, a button 9301, a microphone 9302, a display portion
9303, a speaker 9304, and a camera 9305, and has a function as a
mobile phone.
[0187] FIG. 8B illustrates a display. The display illustrated in
FIG. 8B includes a housing 9310 and a display portion 9311.
[0188] FIG. 8C illustrates a digital still camera. The digital
still camera illustrated in FIG. 8C includes a housing 9320, a
button 9321, a microphone 9322, and a display portion 9323.
[0189] FIG. 8D illustrates a double-foldable portable information
terminal. The double-foldable portable information terminal
illustrated in FIG. 8D includes a housing 9630, a display portion
9631a, a display portion 9631b, a hinge 9633, and an operation
switch 9638.
[0190] Part or whole of the display portion 9631a and/or the
display portion 9631b can function as a touch panel. By touching an
operation key displayed on the touch panel, a user can input data,
for example.
[0191] By applying one embodiment of the present invention, the
performance of the electronic appliances can be improved.
[0192] This embodiment can be implemented in appropriate
combination with any of the other embodiments.
[0193] This application is based on Japanese Patent Application
serial no. 2011-281599 filed with Japan Patent Office on Dec. 22,
2011, the entire contents of which are hereby incorporated by
reference.
* * * * *