U.S. patent application number 14/867513 was filed with the patent office on 2016-10-06 for photonic integrated circuit chip packaging.
The applicant listed for this patent is Coriant Advanced Technology, LLC. Invention is credited to Michael J. Hochberg, Holger Klein, Nathan A. Nuttall.
Application Number | 20160291269 14/867513 |
Document ID | / |
Family ID | 57007696 |
Filed Date | 2016-10-06 |
United States Patent
Application |
20160291269 |
Kind Code |
A1 |
Klein; Holger ; et
al. |
October 6, 2016 |
PHOTONIC INTEGRATED CIRCUIT CHIP PACKAGING
Abstract
A localized hermetic sealing of a photonic integrated circuit
component chip mounted in a photonic integrated circuit device chip
to protect a chip-to-chip interface from contamination, thereby
enhancing functionality and reliability. A covering lid mounted on
or over the component chip is hermetically sealed to the device
chip surrounding the component chip forming a localized
hermetically sealed area.
Inventors: |
Klein; Holger; (Santa
Barbara, CA) ; Hochberg; Michael J.; (New York,
NY) ; Nuttall; Nathan A.; (Castaic, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Coriant Advanced Technology, LLC |
New York |
NY |
US |
|
|
Family ID: |
57007696 |
Appl. No.: |
14/867513 |
Filed: |
September 28, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62141650 |
Apr 1, 2015 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G02B 6/4238 20130101;
H01L 25/162 20130101; G02B 2006/12061 20130101; G02B 6/131
20130101; G02B 6/4251 20130101; H01L 25/50 20130101; H01L 31/125
20130101; H01L 31/18 20130101; G02B 2006/121 20130101; G02B 6/4232
20130101; H01L 25/16 20130101; G02B 6/423 20130101; G02B 6/4268
20130101; G02B 2006/12097 20130101; G02B 6/4274 20130101; H01L
25/167 20130101; G02B 6/136 20130101 |
International
Class: |
G02B 6/42 20060101
G02B006/42; H01L 25/16 20060101 H01L025/16; H01L 25/00 20060101
H01L025/00 |
Claims
1. A photonic integrated circuit (PIC) chip device comprising: a
component PIC chip including a component waveguide; a device PIC
chip for receiving the component PIC chip, and a device waveguide
optically coupled with the component waveguide; a covering lid, for
covering the component PIC chip; and a hermetic seal between the
covering lid and the device PIC chip forming a localized
hermetically sealed area around the component PIC chip.
2. The device according to claim 1, wherein the covering lid is
integral with the PIC component chip.
3. The device according to claim 2, wherein the covering lid
comprises a ledge extending from around an end of the component PIC
chip.
4. The device according to claim 3, wherein the device PIC chip
includes a pit; and wherein the component PIC chip is mounted in
the pit; and wherein the hermetic seal is provided between the
covering lid and an upper surface of the device PIC chip.
5. The device according to claim 1, wherein the covering lid is
separate from the PIC component chip.
6. The device according to claim 5, wherein the covering lid
includes a cavity for receiving an upper portion of the component
PIC chip.
7. The device according to claim 5, further comprising a
thermally-conductive heat spreader between the device PIC chip and
the covering lid for dissipating heat from the device PIC chip.
8. The device according to claim 1, further comprising a first
electrical connector on the component PIC chip, and a second
electrical connector on the device PIC chip; wherein the first and
second electrical connectors are connected within the localized
hermetically sealed area.
9. The device according to claim 8, wherein the first electrical
connector extends from one end of the component PIC chip; and
wherein the second electrical connector extends from a bottom of a
pit extending into the device PIC chip.
10. The device according to claim 9, further comprising an
electrically conductive bonding material between the first and
second electrical connectors bonding the component PIC chip in the
pit.
11. The device according to claim 1, wherein the hermetic seal
comprises a thermally conductive metal to dissipate heat from the
component PIC chip to the device PIC chip.
12. A method of assembling a photonic integrated circuit (PIC)
device comprising: mounting a component PIC chip onto a PIC device
chip; aligning waveguides on the component PIC chip with waveguides
on the device PIC chip; fixing the component PIC chip to the device
PIC chip; and hermetically sealing a covering lid to an upper
surface of the device PIC chip around the component PIC chip,
thereby providing a localized hermitically sealed area around the
component PIC chip.
13. The method according to claim 12, wherein the covering lid is
integral with the component PIC chip.
14. The method according to claim 13, wherein the covering lid
comprises a ledge extending from around an end of the component PIC
chip.
15. The method according to claim 14, wherein the device PIC chip
includes a pit for receiving the component PIC chip; and wherein
the hermetically sealing step includes hermetically sealing the
covering lid to an upper surface of the device PIC chip.
16. The method according to claim 13, wherein the component PIC
chip includes a substrate in or on which the waveguide is formed;
and wherein the method further comprises removing a portion of the
substrate to form the ledge.
17. The method according to claim 12, wherein the hermetically
sealing step includes mounting a separate covering lid over the
component PIC chip.
18. The method according to claim 17, wherein the covering lid
includes a cavity for receiving an upper portion of the component
PIC chip; and wherein a thermally conductive heat spreader is
mounted in the cavity for dissipating heat from the component PIC
chip.
19. The method according to claim 12, further comprising connecting
electrical connectors on the component PIC chip to electrical
connectors on the device PIC chip within the hermetically sealed
area.
20. The method according to claim 12, wherein the hermetically
sealing step is conducted under vacuum or any required inert gas
atmosphere.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional
Application No. 62/141,650, filed Apr. 1, 2015, which is hereby
incorporated by reference herein in its entirety.
TECHNICAL FIELD
[0002] The present disclosure relates to an opto-electronic device,
and in particular to an opto-electronic device with a localized
hermetically sealed photonic integrated circuit.
BACKGROUND
[0003] Opto-electronic chips requiring hermetic sealing may be
packaged along with the entire opto-electronic device in a hermetic
package, in which the package itself provides hermeticity for the
chip. However, hermetic packages are typically more expensive than
non-hermetic packages because all optical paths in and out of the
hermetic package require a hermetic optical window or a hermetic
fiber-feedthrough. Furthermore, all necessary electric connections
in and out of the package will also require a hermetic
feedthrough.
[0004] Telecom transceiver chips may be packaged in a gold box,
which provides hermetic sealing of any opto-electronic chips
inside. However, since hermetic electrical and optical feedthroughs
are more expensive than non-hermetic feedthroughs, the cost for the
gold boxes increases rapidly with increasing numbers of electrical
pins and optical feedthroughs.
[0005] The present invention may provide a solution to eliminate
the requirement for a hermetic gold box by providing a localized
hermetic sealing around individual components. The localized
hermetic seals, may not only eliminate the higher cost attributed
to a hermetic gold box, but may also enable the use of less
expensive packaging methods that are typically only used in
non-hermetic environments.
[0006] An object of the present invention is to overcome the
shortcomings of the prior art by providing a localized hermetic
sealing for photonic integrated circuits.
SUMMARY OF THE INVENTION
[0007] Accordingly, the present invention relates to a photonic
integrated circuit (PIC) chip device comprising: a component PIC
chip including a component waveguide; a device PIC chip for
receiving the component PIC chip, and a device waveguide optically
coupled with the component waveguide; a covering lid, for covering
the component PIC chip; and a hermetic seal between the covering
lid and the device PIC chip forming a localized hermetically sealed
area around the component PIC chip.
[0008] Another aspect of the present invention relates to a method
of assembling a photonic integrated circuit (PIC) device
comprising: mounting a component PIC chip onto a PIC device chip;
aligning waveguides on the component PIC chip with waveguides on
the device PIC chip; fixing the component PIC chip to the device
PIC chip; and hermetically sealing a covering lid to an upper
surface of the device PIC chip around the component PIC chip,
thereby providing a localized hermitically sealed area around the
component PIC chip.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The invention will be described in greater detail with
reference to the accompanying drawings which represent preferred
embodiments thereof, wherein:
[0010] FIG. 1 is an isometric view of a first opto-electronic
component of a first embodiment.
[0011] FIG. 2 is an isometric view of a second opto-electronic
component of the first embodiment.
[0012] FIG. 3 is a side view of first and second opto-electronic
components of a second embodiment.
[0013] FIG. 4 is an isometric view of first and second
opto-electronic components of a third embodiment.
[0014] FIG. 5 is a side view of first and second opto-electronic
components of a fourth embodiment with a hermetic covering lid.
[0015] FIG. 6 is a side view of first and second opto-electronic
components of the fifth embodiment with a hermetic covering
lid.
[0016] FIG. 7 is a top view of the first and second opto-electronic
components.
DETAILED DESCRIPTION
[0017] While the present teachings are described in conjunction
with various embodiments and examples, it is not intended that the
present teachings be limited to such embodiments. On the contrary,
the present teachings encompass various alternatives and
equivalents, as will be appreciated by those of skill in the
art.
[0018] With reference to FIGS. 1 and 2, a first exemplary
embodiment of the present disclosure includes a first component
integrated circuit (IC) chip 1, such as a photonic integrated
circuit (PIC), which includes an active or passive opto-electronic
component, such as a laser, a semiconductor optical amplifier (SOA)
or a photodetector, for integrating into a second device IC chip 2,
such as a PIC, which includes one or more passive and active
optical, opto-electronic or electronic components. The first
component IC chip 1 includes one or more optical component
waveguides 3a and 3b with a core surrounded by cladding and one or
more end facets 4a and 4b, respectively, to build a chip-to-chip
waveguide interface between the first component IC chip 1 and the
second device IC chip 2. The optical component waveguides 3a and 3b
on the first component IC chip 1 may be surface ridge type
waveguides mounted on a substrate 5, as in FIG. 1, or buried
waveguides mounted in the substrate 5, as hereinafter described
with reference to FIG. 3. The first component IC chip 1 may also
include first electrical contacts 6a and 6b mounted on the upper
surface of the substrate 5 adjacent to the component waveguides 3a
and 3b for electrically connecting with corresponding second
electrical contacts 7a and 7b on the second device IC chip 2. The
opto-electronic components on the first component IC chip 1 may
then be electrically connected to components on the second device
IC chip 2, e.g. for power, control or other forms of communication.
The first and second IC chips 1 and 2 may be comprised of any
material appropriate for IC's and PICs, such as but not limited to
Group III-V semiconductors, Silicon, polymers, and glasses.
Typically, the first component IC chip 1 is comprised of a
different material, e.g. Group III-V, than the second device IC
chip 2, e.g. SOI, thereby providing a higher performance component
than could be provided in the second IC chip 2.
[0019] The first component IC chip 1 may also include a mounting
base 8 on which the substrate 5 is mounted or supported, which has
an upper surface area greater than that of the substrate 5, whereby
a flat ledge or step 9 is formed all the way around the substrate
5. A sealing ring 11 may be provided extending along the ledge 9
surrounding the substrate 5 for hermetically sealing the first
component IC chip 1 onto the second device IC chip 2. Accordingly,
the ledge 9 forms an integral covering lid for the first component
IC chip 1, as hereinafter described.
[0020] The base 8 and the ledge 9 may be formed integral with the
substrate 5 in a process including forming the sides of the
substrate 5 and the waveguides 3a and 3b along with the optical
facets 4a and 4b from the base 8 by removal of portions of a block
of material, which includes the substrate 5 and the waveguides 3a
and 3b, from around the substrate 5. Alternatively, the base 8 may
be fabricated in a separate process step and fixed to the substrate
5. The sealing ring 11 on the ledge 9 is lower than the optical
component waveguides 3a and 3b, so that when the first component IC
chip 1 is flipped over during the bonding process, the sealing ring
11 will be above the optical component waveguides 3a and 3b.
[0021] The second device chip 2, see FIG. 2, includes a substrate
12, which may include at least one cavity or pit 13 extending
downwardly from an upper surface 14 thereof and/or at least one
surface mounting site. At least one buried optical device waveguide
15, with a core surrounded by cladding, formed in the substrate 12
extends to at least one edge of the pit 13 or surface mounting
site. In the illustrated embodiment, the optical device waveguide
15 extends to opposite edges of the pit 13, i.e. includes a break
therein, for optically coupling with one or more of the component
waveguides 3a and 3b forming one or more continuous light paths
through the component IC chip 1 when the first component IC chip 1
is mounted in the pit 13. Alternatively, the optical device
waveguides 15 may simply extend from one side of the pit 13 to
guide light to and/or from the first component IC chip 1.
[0022] In a preferred embodiment, the second device IC chip 2 may
be comprised of a silicon-on-insulator (SOI) structure formed using
CMOS manufacturing procedures, but other structures are also
possible. The pit 13 is formed in the second device IC chip 2, e.g.
in an etching step, to receive the first component IC chip 1 in a
flip chip bonding process described hereinafter. When the first and
second IC chips 1 and 2 are bonded together, the optical device
waveguide 15 runs underneath the localized hermetic seal ring 11 to
guide the light from at least one of the optical waveguides 3a and
3b of the first component IC chip 1 from inside the hermetically
sealed area to outside thereof.
[0023] In the illustrated first embodiment, the second electrical
connectors 7a and 7b are mounted at the bottom of the pit 13 for
mating with the corresponding first electrical connectors 6a and
6b, when the first component IC chip 1 is mounted in the pit 13.
For the first embodiment, the optical device waveguides 15 extend
to the edge of the pit 13 proximate the bottom of the pit 13,
whereby mounting of the first component IC chip 1 in the pit 13
aligns both the component waveguides 3a and 3b with the optical
device waveguides 15, and the first electrical connectors 6a and 6b
with the second electrical connectors 7a and 7b. Accordingly, the
depth of the pit 13 corresponds with the combined height of the
substrate 5 and component waveguides 3a and 3b. Alternative
arrangements are also possible, e.g. mounting the second electrical
connectors 7a and 7b in the sides of the pit 13 and the first
electrical connects 6a and 6b on the sides of the first component
IC chip 1 or mounting the first electrical connectors 6a and 6b in
or on the ledge 9, inside of the sealing ring 11, and the second
electrical connectors 7a and 7b on the upper surface of the second
device IC chip 2, inside the sealing ring 11. The electrical
connectors 6a and 6b may be any suitable connectors, including
metal leads with an electrically conductive material, e.g. solder,
therebetween, wire bonds, and flat pin leads. Electrical leads,
vias or traces may extend from the second electrical connectors 7a
and 7b through a layer of the second device IC chip 2 into contact
with electrical and opto-electrical components and devices outside
the hermetic area.
[0024] A second sealing ring 16 may also be provided on the upper
surface 14 of the second device IC chip 2 surrounding the opening
of the pit 13 for mating with the first sealing ring 11.
Alternatively, only one of the sealing rings 11 or 16 may be
provided for hermetically sealing the first component IC chip 1 to
the second device IC chip 2 forming a hermetically sealed area only
around the first component chip 1, but not the rest of the second
device IC chip 2. Typically, the sealing ring 11 and/or 16 may
comprise any appropriate material, such as but not limited to
metals and metal-alloys. The metallization of the sealing ring 11
may comprise any appropriate metal stack for soldering. The sealing
ring 11 may also be formed of alternative bonding materials, such
as glass or ceramic, capable of forming a hermetic seal.
[0025] The sealing ring 11 and/or 16 may comprise a thermally
conductive metal to provide heat dissipation from the first
component IC chip 1 to the substrate 12 for reducing or eliminating
the requirement for additional cooling of the first component IC
chip 1, thereby reducing cost.
[0026] The first embodiment is a self-sealing design in which the
first component chip 1 and the corresponding second device IC chip
2 have sealing surfaces, e.g. the ledge 9 and the upper surface 14
of the second device IC chip 2 that surround the chip-to-chip
optical interface.
[0027] With reference to FIG. 3, a second exemplary embodiment of
the present disclosure includes a first component IC chip 21, such
as a photonic integrated circuit (PIC), which includes an active or
passive opto-electronic component, such as a laser, semiconductor
optical amplifier (SOA) or photodetector, for integrating into a
second device IC chip 22, such as a PIC, which includes one or more
passive and active optical, opto-electronic and electronic
components. The first component chip 21 includes one or more
optical component waveguides 23 with one or more end facets 24,
respectively, to build a chip-to-chip waveguide interface between
the first component chip 21 and the second device chip 22. In the
second embodiment, the optical component waveguides 23 on the first
component chip 21 are buried waveguides mounted in the substrate
25. The first component chip 21 may also include first electrical
contacts 26a and 26b mounted on the upper surface (lower when
flipped over) of the substrate or cladding 25, separated from the
optical component waveguides 23 by a lower portion of the substrate
25, i.e. cladding, for electrically connecting with corresponding
second electrical contacts 27a and 27b on the second device chip
22. The opto-electronic components on the first component chip 21
may then be electrically connected to components on the second
device chip 22, e.g. for power, control or other forms of
communication. The first and second chips 21 and 22 may be
comprised of any material appropriate for PICs, such as but not
limited to Group III-V semiconductors, Silicon, polymers, and
glasses.
[0028] The first component chip 21 may also include a mounting base
28 on which the substrate 25 is mounted, which has an upper surface
area greater than that of the substrate 25, whereby a flat ledge or
step 29 is formed all the way around the substrate 25. A sealing
ring 31 may be provided extending along the ledge 29 surrounding
the substrate 25 for hermetically sealing the first chip 21 onto
the second device chip 22. Accordingly, the ledge 29 forms an
integral covering lid for the first component chip 21, as
hereinafter described.
[0029] The base 28 and the ledge 29 may be formed integral with the
substrate 25 in a process including forming the sides of the
substrate 25, along with the optical facets 24, from the base 28 by
removal of portions of a block of material, including the substrate
5, from around the substrate 5 forming a monolithic PIC structure
with the base 28. Alternatively, the base 28 may be fabricated in a
separate process step and fixed to the substrate 25. The sealing
ring 31 on the ledge 29 is lower than the optical component
waveguides 23, so that when the first component chip 21 is flipped
over during the bonding process, the sealing ring 31 will be above
the optical component waveguides 23.
[0030] The second device chip 22, includes a substrate 32, which
may include at least one cavity or pit 33 extending downwardly from
an upper surface 34 thereof and/or at least one surface mounting
site. At least one buried optical device waveguide 35 formed in the
substrate 32 extends to at least one edge of the pit 33 or surface
mounting site. In the illustrated embodiment, the optical device
waveguide 35 extends to opposite edges of the pit 33 or surface
mounting site, i.e. includes a break therein, for optically
coupling with one or more of the optical component waveguides 23
forming one or more continuous light paths through the component
chip 21 when the first component chip 21 is mounted in the pit 33.
Alternatively, the optical device waveguides 35 may simply extend
from one side of the pit 33 or surface mounting site to guide light
to and/or from the first component chip 21.
[0031] In a preferred embodiment the second device chip 22 may be
comprised of a silicon-on-insulator (SOI) structure formed using
CMOS manufacturing procedures, but other structures are also
possible. The pit 33 is formed in the second device chip 22, e.g.
in an etching step, to receive the first component chip 21 in a
flip chip bonding process described hereinafter. When the first and
second chips 21 and 22 are bonded together, the optical device
waveguide 35 runs underneath the localized hermetic seal ring 31 to
guide the light to or from at least one of the optical component
waveguides 23 of the first component chip 21 between inside the
hermetic area and outside thereof.
[0032] In the illustrated first embodiment, the second electrical
connectors 27a and 27b are mounted at the bottom of the pit 13 for
mating with the corresponding first electrical connectors 26a and
26b, when the first component chip 21 is mounted in the pit 33. For
the second embodiment, the optical device waveguides 15 extend to
the edge of the pit 33 proximate the middle of the side of the pit
33, whereby mounting of the first component chip 21 in the pit 33
aligns both the component waveguides 23 with the optical device
waveguides 35, and the first electrical connectors 26a and 26b with
the second electrical connectors 27a and 27b. Accordingly, the
depth of the pit 33 corresponds with the height of the substrate
25, including cladding and core, alone independent of the raised
component waveguides 23, thereby decoupling the height of the
component waveguides 23 from the bonding process. Alternative
arrangements are also possible, e.g. mounting the second electrical
connectors 27a and 27b in the sides of the pit 33 and the first
electrical connects 26a and 26b on the sides of the first component
chip 21 or mounting the first electrical connectors 26a and 26b in
or on the ledge 29, inside of the sealing ring 31, and the second
electrical connectors 27a and 27b on the upper surface 34 of the
second device chip 22, inside the sealing ring 31. The electrical
connectors 6a and 6b may be any suitable connectors, including
metal leads with an electrically conductive material, e.g. solder,
therebetween, wire bonds, and flat pin leads. Electrical leads,
vias or traces may extend from the second electrical connectors 27a
and 27b through a layer in the second device IC chip 22 into
contact with electrical and opto-electrical components and devices
outside the hermetically sealed area.
[0033] A second sealing ring 36 may also be provided on the upper
surface 34 of the second device chip 22 surrounding the opening of
the pit 33 for mating with the first sealing ring 31.
Alternatively, only one of the sealing rings 31 or 36 may be
provided for hermetically sealing the first component chip 21 to
the second device chip 22 providing a hermetically sealed area only
around the first component chip 21, but not the rest of the second
device chip 22. Typically, the sealing ring 31/36 may comprise any
appropriate material, such as but not limited to metals and
metal-alloys. The metallization of the sealing ring 11 may comprise
any appropriate metal stack for soldering. The sealing ring 11 may
also be formed of alternative bonding materials, such as glass or
ceramic, capable of forming a hermetic seal.
[0034] The sealing ring 31 and/or 36 may comprise a thermally
conductive metal to provide heat dissipation from the first
component chip 21 to the substrate 32 for reducing or eliminating
the requirement for additional cooling of the first component chip
21, thereby reducing cost.
[0035] The second embodiment is also a self-sealing design in which
the first component chip 21 and the corresponding second device
chip 22 have sealing surfaces, e.g. the ledge 29 and the upper
surface 34 of the second device chip 22 that surround the
chip-to-chip optical interface.
[0036] With reference to FIG. 4, a third embodiment includes a
second device IC chip 42 substantially identical to the second
device IC chip 2 of FIG. 2, with similar reference numerals
identifying like elements with similar functions. A first component
IC chip 41 includes a similar raised component waveguide 43 with
end facets 44, formed on a substrate 45, as in the first component
chip 1. The electrical connectors (not shown) are also essentially
the same as in the first embodiment.
[0037] With reference to FIG. 5, a fourth embodiment includes a
second device chip 52 substantially identical to the second device
chip 22 of FIG. 3, with similar reference numerals identifying like
elements with similar functions. A first component chip 51 includes
a similar buried component waveguide 53 with end facets 54, formed
on a substrate 55, as in the first component chip 21. First
electrical connectors 56a and 56b are also essentially the same as
in the second embodiment for mating with the second electrical
connectors 27a and 27b.
[0038] However, instead of the ledge 8, the hermetic sealing of the
first component chips 41 and 51 are achieved by placing a separate
covering lid 62 over the first component chips 41 and 51, and
sealing the cover lid 62 to the second device chip 42 and 52. The
covering lid 62 may also include a sealing ring 63, similar to the
sealing ring 11. The covering lid 62 may be comprised of any
appropriate material or combination of materials, such as but not
limited to metal, Silicon or glass, to ensure the hermetically
sealed area. The covering lid 62 may be a complex structure with
mechanical or functional features or may be some form of simple
metal, semiconductor wafer or glass part.
[0039] When the first component chip 41 or 51 extends upwardly out
of the pit 13 or 33 beyond the upper surface 14 or 34 of the second
device chip 2 or 22, a cavity 64, which locally receives and covers
an upper portion of the first component chip 41 or 51 may be
provided in the covering lid 62. A heat spreader 65 comprising a
thermally conductive material, e.g. aluminum or copper, may be
provided in the cavity 64 in contact with the covering lid 62 and
the first component chip 41 or 51 to dissipate heat from the first
component chip 41 or 51
[0040] Eliminating the need for the ledge 9 and 29 enables the
optical facets of the first and second chips 41, 51, 42 and 52 to
be fabricated by any appropriate method to form optical waveguide
facets, such as but not limited to cleaving, sawing, polishing, and
etching. Eliminating the need for the ledge 9 and 29 also decouples
the aligning of the first and second chips 41 (51) and 42 (52),
respectively, with the aligning and formation of the hermetic seal
11 (31).
[0041] FIG. 6 illustrates a fifth embodiment, in which a gap 81 is
provided between first and second chips 71 and 72, thereby forming
a free space coupling region between the first and second chips 71
and 72. The gap 81 may be provided to reduce coupling losses
between the first and second chips 71 and 72, e.g. if the modes
sizes of the waveguides 73 and 75 match best with the gap 81.
Typically, the spacing between the walls of the first and second
PIC chips 71 and 72 may be between 0 .mu.m and 2 .mu.m;
accordingly, the gap 81 may be greater than 2 .mu.m, e.g. between 2
.mu.m and 10 .mu.m.
[0042] The fifth embodiment also shows an alternative arrangement
in which the first component chip 71 may include a recessed optical
component waveguide 73, which do not extend to the edge of the
first component chip 71 leaving a cladding section 82 between the
end of the optical component waveguide 73 and the edge of the first
component chip 71 instead of an end facet 74. The fifth embodiment
also shows an alternative arrangement in which the second device
chip 72 may include a recessed optical device waveguide 75, which
does not extend to the edge of the pit 33 leaving a cladding
section 84 between the end of the optical device waveguide 75 and
the edge of the pit 33. As above, the recessed waveguides may be
provided to reduce coupling losses between the first and second
chips 71 and 72, e.g. if the modes sizes of the waveguides 73 and
75 match best with the cladding sections 82 and 84. The cladding
sections 82 and 84 may be between 0 .mu.m and 20 .mu.m depending on
the coupling requirements of the optical component waveguide 73 and
the optical device waveguide 75.
[0043] The gap 81 may also be filled with a material with a
refractive index closely matching that of the waveguides 73 and 75
or the cladding sections 82 and 84, such as epoxy, to reduce back
reflections. Alternatively, or in addition, the gap 81 may include
at least one lens to further increase the coupling efficiency and
reduce coupling losses.
[0044] First electrical connectors 26a and 26b are provided for
mating with corresponding second electrical connectors 27a and 27b,
as hereinbefore described. Like reference numerals define similar
elements with similar functions as the aforementioned embodiments.
For the fifth embodiment, the covering lid may be integral with the
first component chip 71, i.e. ledge 8 and 29, as in the first and
second embodiments, or separate, i.e. covering lid 62, as shown in
the third and fourth embodiments.
[0045] The optical facets 4a and 4b, 24, 44 and 45 and the ledges 9
and 29, on the first component IC chip 1, 21, 41, 51 and 71 may be
formed by etching, milling or sawing, as is well known in the art.
The optical component waveguides 3a, 3b, 23, 43, 53 and 73, and the
optical device waveguides 15, 35, 44 and 76 may have any waveguide
angle at the optical facet interfaces; however, in a preferred
embodiment illustrated in FIG. 7, the device waveguides 15, 35 and
44 form an acute angle a relative to a normal to a sidewall of the
pit 13 or 33, and the component waveguides 3a, 23 and 43 from an
acute angle .beta. relative to the normal resulting in a waveguide
angle of between 3.degree. and 12.degree. to reduce back
reflections. The optical mode sizes at the optical facet interface,
between the first and second IC chips 1 and 2 (21 and 22, 41 and
42, 51 and 52, 71 and 72), are not limited in size or shape;
accordingly, the IC chips 1 and 2 (21 and 22, 41 and 42, 51 and 52,
71 and 72), may include optical spot size converters.
[0046] The second device chip 2, 22, 42, 52 and 72 may hold a
plurality of first component chips 1, 21, 41, 51 and 71 in either
the same pit 13 or 33 in a plurality of different pits. In
particular arrays of SOA's or lasers may be mounted in an array of
pits 13 or 33 or in a same pit 13 or 33. The plurality of the first
component chips 1, 21, 41, 51 and 71 may be made from different
materials or the same materials as each other and as the second
device chips 2, 22, 42, 52 and 72.
[0047] During the assembly process, see FIG. 3:
[0048] Step 1: the first component chip 1 (21, 41, 51, 71) is
flipped over and lowered into the pit 13 (or 33) of the second
device chip 2 (22, 42, 52, 72) utilizing flip chip bonding
alignment devices and procedures.
[0049] Step 2: the chip-to-chip waveguide interfaces, e.g.
component waveguide 3a (23, 43, 53, 73) and device waveguide 15
(35, 75) are aligned. For mounting the first component chip 1 (21,
41, 51, 71) to the second device chip 2 (22, 42, 52, 72) precise
vertical alignment features may be provided on one of both of the
first and second chips. For precise alignment of the first and
second chips 1 (21, 41, 51, 71) and 2 (22, 42, 52, 72) both chips
may also include corresponding fiducials for use as points of
reference during alignment, such as optical imaging alignment.
Index matching material, which itself might require hermetic
sealing, may be applied between the end facets 4a, 4b (24, 44, 54,
74) of the first component chip 1 (21, 41, 51, 71) and the end
facets of the device waveguides 15 (35, 75) on the second device
chip 2 (22, 42, 52, 72) i.e. in a gap between the first and second
chips 1 (21, 41, 51, 71) and 2 (22, 42, 52, 72), respectively, in
the pit 13 (or 33). Optical signals may be transmitted through the
combined first and second chips to test performance, before final
assembly, as is well known in the art.
[0050] Step 3: the electrical connectors, e.g. 6a and 6b (26a and
26b, 56a and 56b) to 7a and 7b (27a and 27b), are connected. In a
preferred embodiment, one of the first electrical connector 6a
(26a, 56a) or the second electrical connector 7a (27a) are provided
with a bonding metal, such as solder, which when heated and cooled
provides an electrical and a mechanical connection between the
first electrical connector 6a (26a, 56a) and the second electrical
connector 7a (27a), as well as the first component chip 1 (21, 41,
51, 71) and the second device chip 2 (22, 42, 52, 72). Step 3 may
be eliminated, if not required, e.g. for a passive optical
component. Steps 2 and 3 may be done consecutively in either order
or simultaneously. If the electrical connectors are not used to fix
the first and second chips together, the first component chip 1
(21, 41, 51, 71) is fixed to the second device chip 2 (22, 42, 52,
72) using any other suitable means.
[0051] Step 4: the hermetic seal ring 11 (31, 63) and/or 16 (36)
surrounding the first component chip 1 (21, 41, 51, 71) on the
upper surface 14 or 34 of the second device chip 2 (22, 42, 52, 72)
is closed, thereby providing a localized hermitically sealed area
for the component optical waveguides 3a (23, 43, 53, 73) and the
device optical waveguides 15 (35, 75), the facets 4a and 4b (24,
44, 54 and 74), and, if required, the electrical connectors 6a, 6b,
7a and 7b, (26a, 26b, 27a and 27b). When solder is used for the
hermetic seal, the solder is heated until fluid, and then cooled to
form a bond between the two surfaces. The assembly process
providing the hermetic seal may be done under vacuum or any
required inert gas atmosphere, such as but not limited to nitrogen
(N.sub.2) or noble gases. In the third, fourth and possibly fifth
embodiments step 4 includes mounting the separate covering lid 62
over the first component chip 41, 51 or 71.
[0052] Accordingly, the sealing process for the first embodiment
may effectively be a one-step self-sealing process, while the
second embodiment may be as simple as a two-step process. The
device disclosed herein eliminates the need to use an expensive
hermetic package for packaging the entire PIC device, including PIC
chips, to protect those chips from contamination and exposure to
environmental conditions that would reduce lifetime and
performance.
[0053] The foregoing description of one or more embodiments of the
invention has been presented for the purposes of illustration and
description. It is not intended to be exhaustive or to limit the
invention to the precise form disclosed. Many modifications and
variations are possible in light of the above teaching. It is
intended that the scope of the invention be limited not by this
detailed description, but rather by the claims appended hereto.
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