U.S. patent application number 14/671587 was filed with the patent office on 2016-09-29 for dual-port sram cell structure with vertical devices.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Jhon Jhy Liaw.
Application Number | 20160284712 14/671587 |
Document ID | / |
Family ID | 56975700 |
Filed Date | 2016-09-29 |
United States Patent
Application |
20160284712 |
Kind Code |
A1 |
Liaw; Jhon Jhy |
September 29, 2016 |
DUAL-PORT SRAM CELL STRUCTURE WITH VERTICAL DEVICES
Abstract
Dual-Port SRAM cells are described. In an embodiment, a cell
includes first and second pull-down, first and second pull-up, and
first through fourth pass-gate transistors. Each transistor
includes a first source/drain region in an active area, a channel
extending above the active area, and a second source/drain region
above the channel. First source/drain regions of pull-down
transistors are electrically coupled through a first active area.
First source/drain regions of pull-up transistors are electrically
coupled through a second active area. A first, and a second, gate
electrode is around channels of the first, and second, pull-down
and pull-up transistors, respectively. Second source/drain regions
of the first pull-down, first pull-up, and first and third
pass-gate transistors are electrically coupled to the second gate
electrode. Second source/drain regions of the second pull-down,
second pull-up, and second and fourth pass-gate transistors are
electrically coupled to the first gate electrode.
Inventors: |
Liaw; Jhon Jhy; (Zhudong
Township, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
56975700 |
Appl. No.: |
14/671587 |
Filed: |
March 27, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/665 20130101;
H01L 21/768 20130101; H01L 29/7827 20130101; H01L 29/66666
20130101; H01L 27/1104 20130101 |
International
Class: |
H01L 27/11 20060101
H01L027/11; H01L 21/768 20060101 H01L021/768; H01L 29/66 20060101
H01L029/66; H01L 29/78 20060101 H01L029/78; H01L 23/528 20060101
H01L023/528 |
Claims
1. A structure comprising: a dual-port static random access memory
cell comprising: a first pull-down transistor comprising a first
source/drain region in a first active area in a substrate, a first
vertical channel extending above the first active area, and a
second source/drain region above the first vertical channel, a
second pull-down transistor comprising a third source/drain region
in the first active area, a second vertical channel extending above
the first active area, and a fourth source/drain region above the
second vertical channel, the first source/drain region being
electrically coupled to the third source/drain region through the
first active area, a first pull-up transistor comprising a fifth
source/drain region in a second active area in the substrate, a
third vertical channel extending above the second active area, and
a sixth source/drain region above the third vertical channel, a
second pull-up transistor comprising a seventh source/drain region
in the second active area, a fourth vertical channel extending
above the second active area, and an eighth source/drain region
above the fourth vertical channel, the fifth source/drain region
being electrically coupled to the seventh source/drain region
through the second active area, a first pass-gate transistor
comprising a ninth source/drain region in a third active area in
the substrate, a fifth vertical channel extending above the third
active area, and a tenth source/drain region above the fifth
vertical channel, a second pass-gate transistor comprising an
eleventh source/drain region in a fourth active area in the
substrate, a sixth vertical channel extending above the fourth
active area, and a twelfth source/drain region above the sixth
vertical channel, a third pass-gate transistor comprising a
thirteenth source/drain region in a fifth active area in the
substrate, a seventh vertical channel extending above the fifth
active area, and a fourteenth source/drain region above the seventh
vertical channel, a fourth pass-gate transistor comprising a
fifteenth source/drain region in a sixth active area in the
substrate, an eighth vertical channel extending above the sixth
active area, and a sixteenth source/drain region above the eighth
vertical channel, a first gate electrode around each of the first
vertical channel and the third vertical channel, a second gate
electrode around each of the second vertical channel and the fourth
vertical channel, a third gate electrode around the fifth vertical
channel, a fourth gate electrode around the sixth vertical channel,
a fifth gate electrode around the seventh vertical channel, a sixth
gate electrode around the eighth vertical channel, a first
conductive feature above and physically coupled to the second
source/drain region and the sixth source/drain region, the first
conductive feature further being electrically coupled to the second
gate electrode, the tenth source/drain region, and the fourteenth
source/drain region, and a second conductive feature above and
physically coupled to the fourth source/drain region and the eighth
source/drain region, the second conductive feature further being
electrically coupled to the first gate electrode, the twelfth
source/drain region, and the sixteenth source/drain region.
2. The structure of claim 1, wherein each of the first active area,
the second active area, the third active area, the fourth active
area, the fifth active area, and the sixth active area extends
beyond an area of the dual-port static random access memory
cell.
3. The structure of claim 1, wherein the first active area
comprises a third conductive feature, the second active area
comprises a fourth conductive feature, the third active area
comprises a fifth conductive feature, the fourth active area
comprises a sixth conductive feature, the fifth active area
comprises a seventh conductive feature, and the sixth active area
comprises an eighth conductive feature.
4. The structure of claim 1, wherein the dual-port static random
access memory cell comprises a first p-well in the substrate, an
n-well in the substrate, and a second p-well in the substrate, the
n-well being disposed between the first p-well and the second
p-well, the first active area, the third active area, and the fifth
active area being disposed in the first p-well, the second active
area being disposed in the n-well, the fourth active area and the
sixth active area being disposed in the second p-well.
5. The structure of claim 1, wherein the first vertical channel,
the third vertical channel, the fifth vertical channel, and the
eighth vertical channel are aligned along a first direction, the
second vertical channel, the fourth vertical channel, the sixth
vertical channel, and the seventh vertical channel are aligned
along a second direction, each of the first direction and the
second direction intersecting each of the first active area, the
second active area, the third active area, the fourth active area,
the fifth active area, and the sixth active area.
6. The structure of claim 1, wherein the first conductive feature
is above and physically coupled to the tenth source/drain region,
and the second conductive feature is above and physically coupled
to the twelfth source/drain region.
7. The structure of claim 1, wherein the first vertical channel,
the third vertical channel, the fifth vertical channel, and the
sixth vertical channel are aligned along a first direction, the
second vertical channel, the fourth vertical channel, the seventh
vertical channel, and the eighth vertical channel are aligned along
a second direction, each of the first direction and the second
direction intersecting each of the first active area, the second
active area, the third active area, the fourth active area, the
fifth active area, and the sixth active area.
8. The structure of claim 1, wherein the first conductive feature
is above and physically coupled to the tenth source/drain region,
and the second conductive feature is above and coupled to the
sixteenth source/drain region.
9. The structure of claim 1, wherein no contact is physically
connected in an area of the dual-port static random access memory
cell to any of the first active area, the second active area, the
third active area, the fourth active area, the fifth active area,
and the sixth active area.
10. The structure of claim 1 further comprising: a first
metallization level over the dual-port static random access memory
cell and a second metallization level over the first metallization
level, the first metallization level comprising: a first trace
extending along the first active area, a second trace extending
along the second active area, a third trace extending along the
third active area, a fourth trace extending along the fourth active
area, a fifth trace extending along the fifth active area, and a
sixth trace extending along the sixth active area, wherein no via
extends to or from any of the first trace, the second trace, the
third trace, the fourth trace, the fifth trace, and the sixth trace
in an area of the dual-port static random access memory cell, the
second metallization level comprising: a seventh trace extending in
a direction intersecting the first trace, the second trace, the
third trace, the fourth trace, the fifth trace, and the sixth
trace, the seventh trace being electrically coupled to the third
gate electrode and the fourth gate electrode, and an eighth trace
extending in a direction intersecting the first trace, the second
trace, the third trace, the fourth trace, the fifth trace, and the
sixth trace, the eighth trace being electrically coupled to the
fifth gate electrode and the sixth gate electrode.
11. The structure of claim 1 further comprising: a first
metallization level over the dual-port static random access memory
cell and a second metallization level over the first metallization
level, the first metallization level comprising: a first trace
extending in a direction intersecting the first active area, the
second active area, the third active area, the fourth active area,
the fifth active area, and the sixth active area, the first trace
being electrically coupled to the third gate electrode and the
fourth gate electrode, an second trace extending in a direction
intersecting the first active area, the second active area, the
third active area, the fourth active area, the fifth active area,
and the sixth active area, the second trace being electrically
coupled to the fifth gate electrode and the sixth gate electrode,
the second metallization level comprising: a third trace extending
along the first active area, a fourth trace extending along the
second active area, a fifth trace extending along the third active
area, a sixth trace extending along the fourth active area, a
seventh trace extending along the fifth active area, and a eighth
trace extending along the sixth active area, wherein no via extends
to or from any of the third trace, the fourth trace, the fifth
trace, the sixth trace, the seventh trace, and the eighth trace in
an area of the dual-port static random access memory cell.
12. A structure comprising: a memory array comprising: a plurality
of dual-port static random access memory (DPSRAM) cells, the DPSRAM
cells being arranged in columns and rows, each of the DPSRAM cells
comprising a first pull-down vertical transistor, a second
pull-down vertical transistor, a first pull-up vertical transistor,
a second pull-up vertical transistor, a first pass-gate vertical
transistor, a second pass-gate vertical transistor, a third
pass-gate vertical transistor, and a fourth pass-gate vertical
transistor, respective first source/drain regions of the first
pull-down vertical transistor, the first pull-up vertical
transistor, the first pass-gate vertical transistor, and the third
pass-gate vertical transistor being coupled together and to
respective gates of the second pull-up vertical transistor and the
second pull-down vertical transistor, respective first source/drain
regions of the second pull-down vertical transistor, the second
pull-up vertical transistor, the second pass-gate vertical
transistor, and the fourth pass-gate vertical transistor being
coupled together and to respective gates of the first pull-up
vertical transistor and the first pull-down vertical transistor,
and in each of the columns of DPSRAM cells in the memory array: a
first power node active area in a substrate and extending along the
respective column, respective second source/drain regions of the
first pull-up vertical transistor and the second pull-up vertical
transistor of each of the DPSRAM cells in the respective column
being disposed in the first power node active area, a second power
node active area in the substrate and extending along the
respective column, respective second source/drain regions of the
first pull-down vertical transistor and the second pull-down
transistor of each of the DPSRAM cells in the respective column
being disposed in the second power node active area, a first bit
line node active area in the substrate and extending along the
respective column, a second source/drain region of the first
pass-gate vertical transistor of each of the DPSRAM cells in the
respective column being disposed in the first bit line node active
area, a complementary first bit line node active area in the
substrate and extending along the respective column, a second
source/drain region of the second pass-gate vertical transistor of
each of the DPSRAM cells in the respective column being disposed in
the complementary first bit line node active area, a second bit
line node active area in the substrate and extending along the
respective column, a second source/drain region of the third
pass-gate vertical transistor of each of the DPSRAM cells in the
respective column being disposed in the second bit line node active
area, and a complementary second bit line node active area in the
substrate and extending along the respective column, a second
source/drain region of the fourth pass-gate vertical transistor of
each of the DPSRAM cells in the respective column being disposed in
the complementary second bit line node active area.
13. The structure of claim 12, wherein the memory array further
comprises a first row of strap cells and a second row of strap
cells, the first row of strap cells being disposed on a first edge
of the columns of the DPSRAM cells, the second row being disposed
on a second edge of the columns of the DPSRAM cells opposite from
the first edge.
14. The structure of claim 13, wherein the memory array further
comprises a first metallization level over the substrate, the first
metallization level comprising, for each of the columns of DPSRAM
cells in the memory array: a first power node metallization trace
extending along the respective column, a first connection
electrically coupling the first power node metallization trace to
the first power node active area in the respective strap cell of
the first row of strap cells in the respective column, a second
connection electrically coupling the first power node metallization
trace to the first power node active area in the respective strap
cell of the second row of strap cells in the respective column, a
second power node metallization trace extending along the
respective column, a third connection electrically coupling the
second power node metallization trace to the second power node
active area in the respective strap cell of the first row of strap
cells in the respective column, a fourth connection electrically
coupling the second power node metallization trace to the second
power node active area in the respective strap cell of the second
row of strap cells in the respective column, a first bit line node
metallization trace extending along the respective column, a fifth
connection electrically coupling the first bit line node
metallization trace to the first bit line node active area in the
respective strap cell of the first row of strap cells in the
respective column, a sixth connection electrically coupling the
first bit line node metallization trace to the first bit line node
active area in the respective strap cell of the second row of strap
cells in the respective column, a complementary first bit line node
metallization trace extending along the respective column, a
seventh connection electrically coupling the complementary first
bit line node metallization trace to the complementary first bit
line node active area in the respective strap cell of the first row
of strap cells in the respective column, an eighth connection
electrically coupling the complementary first bit line node
metallization trace to the complementary first bit line node active
area in the respective strap cell of the second row of strap cells
in the respective column, a second bit line node metallization
trace extending along the respective column, a ninth connection
electrically coupling the second bit line node metallization trace
to the second bit line node active area in the respective strap
cell of the first row of strap cells in the respective column, a
tenth connection electrically coupling the second bit line node
metallization trace to the second bit line node active area in the
respective strap cell of the second row of strap cells in the
respective column, and a complementary second bit line node
metallization trace extending along the respective column, an
eleventh connection electrically coupling the complementary second
bit line node metallization trace to the complementary second bit
line node active area in the respective strap cell of the first row
of strap cells in the respective column, a twelfth connection
electrically coupling the complementary second bit line node
metallization trace to the complementary second bit line node
active area in the respective strap cell of the second row of strap
cells in the respective column.
15. The structure of claim 13, wherein the memory array further
comprises a first metallization level over the substrate and a
second metallization level over the substrate, the first
metallization level comprising, for each of the columns of DPSRAM
cells in the memory array, a first power node metallization trace
extending along the respective column and a second power node
metallization trace extending along the respective column, the
second metallization level comprising, for each of the first row of
strap cells and the second row of strap cells, a mesh first power
node metallization trace extending along the respective row of
strap cells and a mesh second power node metallization trace
extending along the respective row of strap cells, and for each of
the strap cells, a first connection electrically coupling the first
power node metallization trace at the respective strap cell to the
mesh first power node metallization trace at the respective strap
cell, and a second connection electrically coupling the second
power node metallization trace at the respective strap cell to the
mesh second power node metallization trace at the respective strap
cell.
16. The structure of claim 12, wherein each of the DPSRAM cells has
an area, the area having a first dimension along a row direction
and a second dimension along a column direction, a ratio of the
first dimension to the second dimension being at least 4.
17. The structure of claim 12, wherein the memory array further
comprises a metallization level over the substrate, the
metallization level comprising, for each of the rows of DPSRAM
cells, a first word line node metallization trace extending along
the respective row and a second word line node metallization trace
extending along the respective row, for each of the DPSRAM cells in
the respective row, respective gates of the first pass-gate
vertical transistor and the second pass-gate transistor being
electrically coupled to the first word line node metallization
trace, and respective gates of the third pass-gate vertical
transistor and the fourth pass-gate transistor being electrically
coupled to the second word line node metallization trace.
18.-20. (canceled)
21. A device comprising: a first power node active area in a
substrate; a second power node active area in the substrate; a
first bit line node active area in the substrate; a complementary
first bit line node active area in the substrate; a second bit line
node active area in the substrate; a complementary second bit line
node active area in the substrate; a memory area over the substrate
comprising: a first vertical channel structure, a first gate
electrode being around the first vertical channel structure; a
second vertical channel structure, a second gate electrode being
around the second vertical channel structure; a third vertical
channel structure, the first gate electrode being around the third
vertical channel structure; a fourth vertical channel structure,
the second gate electrode being around the fourth vertical channel
structure; a fifth vertical channel structure, a third gate
electrode being around the fifth vertical channel structure; a
sixth vertical channel structure, a fourth gate electrode being
around the sixth vertical channel structure; a seventh vertical
channel structure, a fifth gate electrode being around the seventh
vertical channel structure; and an eighth vertical channel
structure, a sixth gate electrode being around the eighth vertical
channel structure, each of the first, second, third, fourth, fifth,
sixth, seventh, and eighth vertical channel structures comprising a
first source/drain region disposed in a respective active area, a
channel region above the first source/drain region, and a second
source/drain region above the channel region, the first
source/drain region of the first vertical channel structure being
disposed in the first power node active area, the first
source/drain region of the second vertical channel structure being
disposed in the first power node active area, the first
source/drain region of the third vertical channel structure being
disposed in the second power node active area, the first
source/drain region of the fourth vertical channel structure being
disposed in the second power node active area, the first
source/drain region of the fifth vertical channel structure being
disposed in the first bit line node active area, the first
source/drain region of the sixth vertical channel structure being
disposed in the complementary first bit line node active area, the
first source/drain region of the seventh vertical channel structure
being disposed in the second bit line node active area, the first
source/drain region of the eighth vertical channel structure being
disposed in the complementary second bit line node active area;
first conductive features electrically coupling the respective
second source/drain regions of the first vertical channel
structure, the third vertical channel structure, the fifth vertical
channel structure, and the seventh vertical channel structure
together and to the second gate electrode; and second conductive
features electrically coupling the respective second source/drain
regions of the second vertical channel structure, the fourth
vertical channel structure, the sixth vertical channel structure,
and the eighth vertical channel structure together and to the first
gate electrode.
22. The device of claim 21, further comprising: a metallization
level comprising a first word line node metallization trace and a
second word line node metallization trace, the first word line node
metallization trace being electrically coupled to the third gate
electrode and the fourth gate electrode, the second word line node
metallization trace being electrically coupled to the fifth gate
electrode and the sixth gate electrode.
23. The device of claim 22, wherein no traces of the metallization
level physically contact any of the first power node active area,
the second power node active area, the first bit line node active
area, the complementary first bit line node active area, the second
bit line node active area, and the second bit line node active area
in the memory area.
Description
BACKGROUND
[0001] Static Random Access Memory (SRAM) is commonly used in
integrated circuits. SRAM cells have the advantageous feature of
holding data without a need for refreshing. With the increasingly
demanding requirement to the speed of integrated circuits, the read
speed and write speed of SRAM cells also become more important.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0003] FIG. 1 is a circuit diagram of a Dual-Port Static Random
Access Memory (SRAM) bit cell in accordance with some
embodiments.
[0004] FIGS. 2 through 23 and 24A are cross sectional views of
intermediate steps during a process for forming Vertical
Gate-All-Around (VGAA) device structures in accordance with some
embodiments.
[0005] FIGS. 24B and 24C are overlaid layout views of VGAA device
structures formed by the process discussed with respect to FIGS. 2
through 24A in accordance with some embodiments.
[0006] FIGS. 25A, 26, and 27 are respective levels of a first
Dual-Port SRAM bit cell in accordance with some embodiments.
[0007] FIG. 25B is a 2.times.2 array of cells in accordance with
some embodiments.
[0008] FIG. 28 is a first via level and a first metallization level
of the first Dual-Port SRAM bit cell in accordance with some
embodiments.
[0009] FIG. 29 is a second via level and a second metallization
level of the first Dual-Port SRAM bit cell in accordance with some
embodiments.
[0010] FIGS. 30, 31, and 32 are respective levels of a second
Dual-Port SRAM bit cell in accordance with some embodiments.
[0011] FIG. 33 is a first via level and a first metallization level
of the second Dual-Port SRAM bit cell in accordance with some
embodiments.
[0012] FIG. 34 is a second via level and a second metallization
level of the second Dual-Port SRAM bit cell in accordance with some
embodiments.
[0013] FIG. 35 is an array of Dual-Port SRAM bit cells in
accordance with some embodiments.
[0014] FIG. 36 is an array of Dual-Port SRAM bit cells with mesh
power voltage metallization traces in accordance with some
embodiments.
DETAILED DESCRIPTION
[0015] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the invention. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
[0016] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0017] Static Random Access Memory (SRAM) cells, such as Dual-Port
SRAM cells, comprising Vertical Gate-All-Around (VGAA) devices are
provided in accordance with various example embodiments. Some
variations of the embodiments are discussed. Throughout the various
views and illustrative embodiments, like reference numbers are used
to designate like elements. Further, method embodiments discussed
herein may be discussed as being performed in a particular order;
however, other method embodiments may be performed in any logical
order.
[0018] FIG. 1 illustrates a circuit diagram of a Dual-Port SRAM bit
cell in accordance with some embodiments. The cell includes pull-up
transistors PU1 and PU2, pull-down transistors PD1 and PD2, and
pass-gate transistors PG1, PG2, PG3, and PG4. As show in the
circuit diagram, pull-up transistors PU1 and PU2 are p-type
transistors, and transistors PD1, PD2, PG1, PG2, PG3, and PG4 are
n-type transistors.
[0019] The drains of pull-up transistor PU1 and pull-down
transistor PD1 are coupled together, and the drains of pull-up
transistor PU2 and pull-down transistor PD2 are coupled together.
Transistors PU1 and PD1 are cross-coupled with transistors PU2 and
PD2 to form a data latch. The gates of transistors PU1 and PD1 are
coupled together and to the drains of transistors PU2 and PD2, and
the gates of transistors PU2 and PD2 are coupled together and to
the drains of transistors PU1 and PD1. Sources of the pull-up
transistors PU1 and PU2 are coupled to a first power voltage Vdd,
and the sources of the pull-down transistors PD1 and PD2 are
coupled to a second power voltage Vss, e.g., ground. As
illustrated, the transistors PU1 and PD1 form a first inverter INV1
between the first power voltage Vdd and the second power voltage
Vss, and the transistors PU2 and PD2 form a second inverter INV2
between the first power voltage Vdd and the second power voltage
Vss. The inverters INV1 and INV2 are cross-coupled to form the data
latch.
[0020] Storage node N1 of the data latch is coupled to a first bit
line BL-A through the first pass-gate transistor PG1 and to a
second bit line BL-B through the third pass-gate transistor PG3,
and storage node N2 is coupled to a complementary first bit line
BLB-A through the second pass-gate transistor PG2 and to a
complementary second bit line BLB-B through the fourth pass-gate
transistor PG4. Storage nodes N1 and N2 are complementary nodes
that are often at opposite logic levels (logic high or logic low).
Gates of pass-gate transistors PG1 and PG2 are coupled to a first
word line WL-A, and gates of pass-gate transistors PG3 and PG4 are
coupled to a second word line WL-B.
[0021] Features of various embodiments discussed below may have
reference characters indicating a level, as will be discussed
subsequently, post-fixed with a node reference as discussed above
with respect to FIG. 1. For example, a first metallization trace
that is a node for the first bit line may be indicated as
"M1-BL-A."
[0022] FIGS. 2 through 24A illustrate cross sectional views of
intermediate steps during a process for forming VGAA device
structures in accordance with some embodiments. FIGS. 24B and 24C
illustrate overlaid layout views of VGAA device structures formed
by the process discussed with respect to FIGS. 2 through 24A. The
various views are not necessarily representative of a cross section
or layout of a Dual-Port SRAM cell discussed below. The cross
sectional and layout views, and a method discussed in the context
of these views, are provided to illustrate aspects of VGAA device
structures and how they are formed and to provide a reference for
features discussed with respect to subsequent layouts. One of
ordinary skill in the art will readily understand how to apply the
discussion of FIGS. 2 through 24C to the layouts discussed
subsequently.
[0023] FIG. 2 illustrates a substrate 60 with a mask layer 66 and
isolation regions 68. The substrate 60 can be a bulk semiconductor
substrate, a semiconductor-on-insulator (SOI) substrate, a
multi-layered or gradient substrate, or the like. The semiconductor
of the substrate 60 may include any semiconductor material, such as
elemental semiconductor like silicon, germanium, or the like; a
compound or alloy semiconductor including SiC, SiP, SiPC, GaAs,
GaP, InP, InAs, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs,
GaInAs, GaInP, and/or GaInAsP; the like; or a combinations thereof.
The substrate 60 may further be a wafer, for example, which may
further be a silicon wafer. The substrate 60 comprises a first
region 62 for forming a first device type, e.g., n-type, and a
second region 64 for forming a second device type, e.g.,
p-type.
[0024] The mask layer 66, such as a hardmask, is deposited on the
substrate 60. The mask layer 66 may be formed of, for example,
silicon nitride, silicon carbide, silicon oxynitride, silicon
carbon nitride, or the like, and may be formed using Chemical Vapor
Deposition (CVD), Plasma-Enhanced CVD (PECVD), Atomic Layer
Deposition (ALD), or the like. The mask layer 66 is then patterned
to expose the substrate 60, and recesses, or trenches, are etched
in the substrate 60. The patterning and etching may use an
acceptable photolithography and etching process, such as Reactive
Ion Etching (RIE) or the like.
[0025] The recesses in the substrate 60 are then filled with a
dielectric material to form the isolation regions 68. The isolation
regions 68 may be referred to as Shallow Trench Isolation (STI)
regions. The isolation regions 68 may be formed of silicon oxide
deposited by a high density plasma, for example, although other
dielectric materials formed according to various techniques may
also be used. A planarization process, such as a Chemical
Mechanical Polish (CMP), may be performed to remove excess
dielectric material and form the top surface of the isolation
regions 68 to be co-planar with the top surface of the mask layer
66. In other embodiments, the isolation regions can be formed by
thermal oxidation to grow a dielectric material, such as silicon
oxide.
[0026] In FIG. 3, the mask layer 66 is patterned with openings
corresponding to channel structures that are to be formed, and a
mask cap 70 is formed in each opening in the mask layer 66. The
mask layer 66 may be patterned using an acceptable photolithography
and etching process, such as RIE or the like. The mask caps 70 can
be formed by depositing a material with a different etch
selectivity than the mask layer 66 in the openings and on the mask
layer 66. The material of the mask cap 70 may be, for example,
silicon nitride, silicon carbide, silicon oxynitride, silicon
carbon nitride, or the like, and may be formed using CVD, PECVD,
ALD, or the like. The material of the mask cap 70 may then be
planarized, such as by a CMP, to form the mask caps 70 with top
surfaces co-planar with the top surface of the mask layer 66.
[0027] In FIG. 4, the mask layer 66 is removed, such as by an
appropriate etch selective to the mask layer 66. In FIG. 5,
vertical channel structures 72 are formed from the substrate 60.
Using the mask caps 70 as a mask, the substrate 60 is recessed,
such as by using an appropriate anisotropic etch such as RIE or the
like, to form the vertical channel structures 72. The vertical
channel structures 72 can have cross sections in a plane parallel
to a top surface of the substrate 60 that are circles, squares,
rectangles, ovals, ellipses, or the like. The vertical channel
structures 72 may be referred to as nanowires. Although one
vertical channel structure 72 is depicted for each transistor or
device that is formed in the process discussed herein, each
transistor or device can comprise multiple vertical channel
structures, which can have any appropriate shape or combination of
shapes. In other embodiments, the vertical channel structures 72
can include epitaxially growing the vertical channel structures 72.
The epitaxial growth can use Ge, SiGe, SiC, SiP, SiPC, a III-V
material, the like, or a combination thereof. Example III-V
materials include InP, InAs, GaAs, AlInAs, InGaP, InGaAs, GaAsSb,
GaPN, and AlPN.
[0028] In FIG. 6, a filler dielectric layer 74 is formed on the
substrate 60 and around the vertical channel structures 72. In some
embodiments, the filler dielectric layer 74 is an oxide formed by a
flowable CVD (FCVD) (e.g., a CVD-based material deposition in a
remote plasma system) and a post curing, such as an anneal. In
other embodiments, the filler dielectric layer 74 can be formed by
an another deposition technique, such as CVD, PECVD, the like, or a
combination thereof, and can be a dielectric material such as
silicon oxide, phosphosilicate glass (PSG), borosilicate glass
(BSG), borophosphosilicate glass (BPSG), un-doped silicate glass
(USG), a nitride, oxynitride, or the like. After deposition of the
filler dielectric layer 74, a CMP may be performed to planarize the
filler dielectric layer 74 to have a top surface co-planar with top
surface of the mask caps 70 and isolation regions 68. In FIG. 7,
the filler dielectric layer 74 and the isolation regions 68 are
etched back, such as by using an appropriate etch, such as RIE or
the like, such that the vertical channel structures 72 protrude
from the filler dielectric layer 74.
[0029] In FIG. 8, a bottom layer 76 and a photoresist 78 are formed
on the second region 64 of the substrate 60. The bottom layer 76
may comprise a hard mask material such as silicon nitride, silicon
carbide, silicon oxynitride, silicon carbon nitride, or the like
formed by using CVD, PECVD, ALD, or the like. The bottom layer 76
may be planarized, such as by CMP. The bottom layer 76 can be
initially formed in the first region 62 and the second region 64 of
the substrate 60. The photoresist 78 is then formed and patterned
on the bottom layer 76 in the second region 64. The photoresist 78
can be formed by using a spin-on technique and patterned using
acceptable photolithography techniques. The portion of the bottom
layer 76 in the first region 62 can then be removed, such as by
etching, such as RIE or the like, using the photoresist 78 as a
mask. The filler dielectric layer 74 can be removed from the first
region 62 of the substrate 60 after the bottom layer 76 is removed.
The bottom layer 76 can remain in the second region 64 of the
substrate 60 while exposing the first region 62 of the substrate
60.
[0030] Once the bottom layer 76 and the photoresist 78 are formed,
a p-type dopant is implanted in the first region 62 of the
substrate 60 to form a p-doped well 80. Example species for
implanting p-type dopants include boron (B), BF.sub.2, indium (In),
nitrogen (N), carbon (C), the like, or a combination thereof. A
concentration of a p-type dopant in the p-doped well 80 can be in a
range from about 1.times.10.sup.17 cm.sup.-3 to about
5.times.10.sup.19 cm.sup.-3. Then, an n-type dopant is implanted in
the p-doped well 80 in the first region 62 of the substrate 60 to
form an n+-doped source/drain region 82. Example species for
implanting n-type dopants include arsenic (As), phosphorus (P),
antimony (Sb), nitrogen (N), carbon (C), the like, or a combination
thereof. A concentration of an n-type dopant in the n+-doped
source/drain region 82 can be in a range from about
1.times.10.sup.20 cm.sup.-3 to about 7.times.10.sup.21 cm.sup.-3.
The bottom layer 76 and the photoresist 78 can then be removed,
such by as an appropriate ashing to remove the photoresist 78 and
an etching to remove the bottom layer 76.
[0031] In FIG. 9, a bottom layer 84 and a photoresist 86 are formed
on the first region 62 of the substrate 60. The bottom layer 84 may
comprise a hard mask material such as silicon nitride, silicon
carbide, silicon oxynitride, silicon carbon nitride, or the like
formed by using CVD, PECVD, ALD, or the like. The bottom layer 84
may be planarized, such as by CMP. The bottom layer 84 can be
initially formed in the first region 62 and the second region 64 of
the substrate 60. The photoresist 86 is then formed and patterned
on the bottom layer 84 in the second region 64. The photoresist 86
can be formed by using a spin-on technique and patterned using
acceptable photolithography techniques. The portion of the bottom
layer 84 in the second region 64 can then be removed, such as by
etching, such as RIE or the like, using the photoresist 86 as a
mask. The filler dielectric layer 74 can be removed from the second
region 64 of the substrate 60 after the bottom layer 84 is removed.
The bottom layer 84 can remain in the first region 62 of the
substrate 60 while exposing the second region 64 of the substrate
60.
[0032] Once the bottom layer 84 and the photoresist 86 are formed,
an n-type dopant is implanted in the second region 64 of the
substrate 60 to form an n-doped well 88. Example species for
implanting n-type dopants include arsenic (As), phosphorus (P),
antimony (Sb), nitrogen (N), carbon (C), the like, or a combination
thereof. A concentration of an n-type dopant in the n-doped well 88
can be in a range from about 1.times.10.sup.17 cm.sup.-3 to about
5.times.10.sup.19 cm.sup.-3. Then, a p-type dopant is implanted in
the n-doped well 88 in the second region 64 of the substrate 60 to
form a p+-doped source/drain region 90. Example species for
implanting p-type dopants include boron (B), BF.sub.2, indium (In),
nitrogen (N), carbon (C), the like, or a combination thereof. A
concentration of a p-type dopant in the p+-doped source/drain
region 90 can be in a range from about 5.times.10.sup.19 cm.sup.-3
to about 5.times.10.sup.21 cm.sup.-3. The bottom layer 84 and the
photoresist 86 can then be removed, such by as an appropriate
ashing to remove the photoresist 86 and an etching to remove the
bottom layer 84.
[0033] In FIG. 10, spacers 92 are formed around sidewalls of the
vertical channel structures 72. In some embodiments, a spacer layer
is conformally deposited over the substrate 60 and along the
sidewalls of the vertical channel structures 72 such that the
thickness of the spacer layer is substantially a same thickness
throughout the layer. In some embodiments, the spacer layer is made
of SiN, SiON, SiC, SiCN, SiOCN, the like, or a combination thereof.
The spacer layer may be deposited using an appropriate deposition
process, such as ALD, CVD, PVD, the like, or a combination thereof.
The spacer layer is then anisotropically etched, such as by using a
plasma etching like an RIE or the like, to remove substantially
horizontal portions of the conformal spacer layer. The remaining
vertical portions of the conformal spacer layer form the spacers 92
around and along the sidewalls of the vertical channel structures
72.
[0034] In FIG. 11, a metal-semiconductor compound region 94 in the
first region 62 and a metal-semiconductor compound region 96 in the
second region 64 are formed. The metal-semiconductor compound
regions 94 and 96 can be formed by depositing a metal on the
substrate 60 and reacting the metal with a semiconductor, such as
the semiconductor material of the substrate 60. In some
embodiments, the metal can include cobalt, titanium, nickel,
tungsten, the like, or a combination thereof, and can be deposited
by Physical Vapor Deposition (PVD), ALD, CVD, the like, or a
combination thereof. The metal can be caused to react with the
semiconductor by using an anneal. Any unreacted metal that remains
after the anneal can be removed using an etch selective to the
material of the unreacted metal. The metal-semiconductor compound
regions 94 and 96 can include CoSi, TiSi, NiSi, WSi, the like, or a
combination thereof. The spacers 92 and mask caps 70 prevent the
metal from reacting with the semiconductor material of the vertical
channel structures 72 during the anneal. The metal-semiconductor
compound regions 94 and 96 are formed on the exposed portions of
semiconductor material of the substrate 60 in the first region 62
and the second region 64. As illustrated, the metal-semiconductor
compound regions 94 and 96 are formed in, and consume, the
entireties of the exposed portions of source/drain regions 82 and
90, respectively, that are not under or protected by the spacers
92. In other embodiments, the metal-semiconductor compound regions
94 and 96 can be formed to a greater or lesser extent in the
substrate 60.
[0035] In other embodiments, other conductive features can be used
instead of or in combination with the metal-semiconductor compound
regions 94 and 96. For example, in the first region 62, an
epitaxially grown material may be used, such as SiP, SiC, SiPC, Si,
Ge, a III-V material, a combination thereof, or the like. For
example, in the second region 64, an epitaxially grown material may
be used, such as SiGe, Ge, a Ge-containing material, SiP, SiC, a
III-V material, a combination thereof, or the like.
[0036] In FIG. 12, a first dielectric layer 100 is formed on the
substrate 60 and around the vertical channel structures 72. The
first dielectric layer 100 can comprise silicon nitride, SiCN, or
the like deposited by CVD, PECVD, ALD, or the like. In some
embodiments, the first dielectric layer 100 is deposited with a
thickness greater than heights of the vertical channel structures
72. A planarization process, such as a CMP, is then performed to
form top surfaces of the mask caps 70 to be co-planar with a top
surface of the first dielectric layer 100. Subsequently, a
controlled etch back, such as an anisotropic etch, etches the first
dielectric layer 100 to an appropriate thickness. The first
dielectric layer 100 may serve various purposes, such as an etch
stop layer for forming contacts to the metal-semiconductor compound
regions 94 and 96 and/or as a gate spacer.
[0037] Although not illustrated, channel implants may be performed
to dope the vertical channel structures 72. The implantation
process may include masking regions, such as discussed above with
respect to FIGS. 8 and 9. An n-type dopant can be implanted in the
vertical channel structure 72 in the second region 64 of the
substrate 60 to form an n-doped channel. Example species for
implanting n-type dopants include arsenic (As), phosphorus (P),
antimony (Sb), germanium (Ge), nitrogen (N), carbon (C), the like,
or a combination thereof. A concentration of an n-type dopant in
the n-doped channel can be in a range from about 1.times.10.sup.12
cm.sup.-3 to about 5.times.10.sup.13 cm.sup.-3. A p-type dopant can
be implanted in the vertical channel structure 72 in the first
region 62 of the substrate 60 to form a p-doped channel. Example
species for implanting p-type dopants include boron (B), BF.sub.2,
indium (In), germanium (Ge), nitrogen (N), carbon (C), the like, or
a combination thereof. A concentration of a p-type dopant in the
p-doped channel can be in a range from about 1.times.10.sup.12
cm.sup.-3 to about 5.times.10.sup.13 cm.sup.-3.
[0038] In FIG. 13, gate dielectric layer 102 and gate electrode
layer 104 are formed. Gate dielectric layer 102 is deposited
conformally on the vertical channel structures 72, such as over the
top surfaces of the mask caps 70 and along the sidewalls of the
vertical channel structures 72. In accordance with some
embodiments, gate dielectric layer 102 comprises silicon oxide,
silicon nitride, or multilayers thereof. In other embodiments, gate
dielectric layer 102 comprises a high-k dielectric material, and in
these embodiments, gate dielectric layer 102 may have a k value
greater than about 7.0, or further, greater than about 10.0. A
high-k dielectric material may include SiON, Si.sub.3N.sub.4,
Ta.sub.2O.sub.5, Al.sub.2O.sub.3, a Hf oxide, a Ta oxide, an Al
oxide, the like, and a combination thereof. The formation methods
of gate dielectric layer 102 may include Molecular Beam Deposition
(MBD), ALD, PECVD, the like, or a combination thereof. Next, gate
electrode layer 104 is deposited over gate dielectric layer 102.
The gate electrode layer 104 may comprise a metal-containing
material such as TiN, TaN, TiAl, TaAl, a Ti-containing material, a
Ta-containing material, an Al-containing material, a W-containing
material, TiSi, NiSi, PtSi, polysilicon with a silicide, a
Cu-containing material, a refractory material, the like,
combinations thereof, or multi-layers thereof. In FIG. 14, the gate
electrode layer 104 and the gate dielectric layer 102 are
patterned, such as by using an acceptable photolithography and
etching process, such as RIE or the like.
[0039] In FIG. 15, a second dielectric layer 106 is formed on the
first dielectric layer 100 and the gate electrode layer 104 and
around the vertical channel structures 72. The second dielectric
layer 106 may comprise silicon oxide, tetraethyl orthosilicate
(TEOS), PSG, BPSG, fluorinated silicate glass (FSG),
SiO.sub.xC.sub.y, Spin-On-Glass, Spin-On-Polymers, silicon carbon
material, compounds thereof, composites thereof, combinations
thereof, or the like, formed by any suitable method, such as CVD,
PECVD, spinning, the like, or a combination thereof. In some
embodiments, the second dielectric layer 106 is deposited with a
thickness greater than heights of the gate electrode layer 104. A
planarization process, such as a CMP, is then performed to form top
surfaces of the gate electrode layer 104 to be co-planar with a top
surface of the second dielectric layer 106. Subsequently, a
controlled etch back, such as an anisotropic etch, etches the
second dielectric layer 106 to an appropriate thickness. The second
dielectric layer 106 may serve various purposes, such as an
Inter-Layer Dielectric (ILD).
[0040] In FIG. 16, the gate electrode layer 104 and the gate
dielectric layer 102 are etched back, and the mask caps 70 are
removed from over the vertical channel structures 72. The gate
electrode layer 104 and the gate dielectric layer 102 can be etched
back using a controlled etch back that uses an appropriate etch
process, such as an anisotropic or isotropic etch selective to the
materials of the gate electrode layer 104 and the gate dielectric
layer 102. After etching back the gate electrode layer 104 and the
gate dielectric layer 102, the mask caps 70 are removed, such as by
using an appropriate etching process selective to the material of
the mask caps 70. After the etch backs of the second dielectric
layer 106, the gate electrode layer 104, and the gate dielectric
layer 102, the vertical channel structures 72 protrude from and
above each of the second dielectric layer 106, gate electrode layer
104, and gate dielectric layer 102.
[0041] In FIG. 17, a photoresist 108 is formed on the second
dielectric layer 106, the gate electrode layer 104, the gate
dielectric layer 102, and the vertical channel structure 72 in the
second region 64 of the substrate 60. The photoresist 108 can be
formed by using a spin-on technique and patterned using acceptable
photolithography techniques. Once the photoresist 108 is formed, an
n-type dopant is implanted in the first region 62 of the substrate
60. The n-type dopant is implanted in the vertical channel
structure 72 in the first region 62 of the substrate 60 to form an
n+-doped source/drain region 110 in the portion of the vertical
channel structure 72 in the first region 62 that protrudes above
the second dielectric layer 106, the gate electrode layer 104, and
the gate dielectric layer 102. Example species for implanting
n-type dopants include arsenic (As), phosphorus (P), antimony (Sb),
nitrogen (N), carbon (C), the like, or a combination thereof. A
concentration of an n-type dopant in the n+-doped source/drain
region 110 can be in a range from about 1.times.10.sup.20 cm.sup.-3
to about 7.times.10.sup.21 cm.sup.-3. The photoresist 108 can then
be removed, such by as an appropriate ashing.
[0042] In FIG. 18, a photoresist 112 is formed on the second
dielectric layer 106, the gate electrode layer 104, the gate
dielectric layer 102, and the vertical channel structure 72 in the
first region 62 of the substrate 60. The photoresist 112 can be
formed by using a spin-on technique and patterned using acceptable
photolithography techniques. Once the photoresist 112 is formed, a
p-type dopant is implanted in the second region 64 of the substrate
60. The p-type dopant is implanted in the vertical channel
structure 72 in the second region 64 of the substrate 60 to form a
p+-doped source/drain region 114 in the portion of the vertical
channel structure 72 in the second region 64 that protrudes above
the second dielectric layer 106, the gate electrode layer 104, and
the gate dielectric layer 102. Example species for implanting
p-type dopants include boron (B), BF.sub.2, indium (In), nitrogen
(N), carbon (C), the like, or a combination thereof. A
concentration of a p-type dopant in the p+-doped source/drain
region 114 can be in a range from about 1.times.10.sup.20 cm.sup.-3
to about 5.times.10.sup.21 cm.sup.-3. The photoresist 112 can then
be removed, such by as an appropriate ashing.
[0043] In FIG. 19, spacers 116 are formed around and along
sidewalls of the portions of the vertical channel structures 72
that protrude above the second dielectric layer 106, the gate
electrode layer 104, and the gate dielectric layer 102. In some
embodiments, a spacer layer is conformally deposited over the
second dielectric layer 106, the gate electrode layer 104, and the
gate dielectric layer 102, and the vertical channel structures 72
and along the sidewalls of the vertical channel structures 72 such
that the thickness of the spacer layer is substantially a same
thickness throughout the layer. In some embodiments, the spacer
layer is made of SiN, SiON, SiC, SiCN, SiOCN, the like, or a
combination thereof. The spacer layer may be deposited using an
appropriate deposition process, such as ALD, CVD, PVD, the like, or
a combination thereof. The spacer layer is then anisotropically
etched, such as by using a plasma etching like an RIE or the like,
to remove substantially horizontal portions of the conformal spacer
layer. The remaining vertical portions of the conformal spacer
layer form the spacers 116 around and along the sidewalls of the
vertical channel structures 72 that protrude above the second
dielectric layer 106, the gate electrode layer 104, and the gate
dielectric layer 102.
[0044] In FIG. 20, a third dielectric layer 118 is formed on the
second dielectric layer 106 and the spacers 116 and around the
vertical channel structures 72. The third dielectric layer 118 may
comprise silicon oxide, TEOS, PSG, BPSG, FSG, SiO.sub.xC.sub.y,
Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds
thereof, composites thereof, combinations thereof, or the like,
formed by any suitable method, such as CVD, PECVD, spinning, the
like, or a combination thereof. In some embodiments, the third
dielectric layer 118 is deposited with a thickness greater than
heights of the vertical channel structures 72. A planarization
process, such as a CMP, is then performed to form top surfaces of
the vertical channel structures 72 to be co-planar with a top
surface of the third dielectric layer 118. This can cause the
source/drain regions 110 and 114 of the vertical channel structures
72 to be exposed through the third dielectric layer 118.
[0045] In FIG. 21, a semiconductor layer 120 is formed over the
third dielectric layer 118 and on the exposed surfaces of the
vertical channel structures 72. The semiconductor layer 120 can be
silicon, such as amorphous or polycrystalline, or the like. The
semiconductor layer 120 can be formed using any suitable method,
such as CVD, PECVD, the like, or a combination thereof.
[0046] In FIG. 22, metal-semiconductor compound regions 122 are
formed over the third dielectric layer 118 and on the exposed
surfaces of the vertical channel structures 72. In some
embodiments, the semiconductor layer 120 is patterned to correspond
to the metal-semiconductor compound regions 122. Then, a metal can
be deposited on remaining portions of the semiconductor layer 120
and on the third dielectric layer 118. The metal can be reacted
with the remaining portions of the semiconductor layer 120. In some
embodiments, the metal can include cobalt, titanium, nickel,
tungsten, the like, or a combination thereof, and can be deposited
by PVD, ALD, CVD, the like, or a combination thereof. The metal can
be caused to react with the semiconductor layer 120 by using an
anneal. Any unreacted metal that remains after the anneal can be
removed using an etch selective to the material of the unreacted
metal. The metal-semiconductor compound regions 122 can include
CoSi, TiSi, NiSi, WSi, PtSi, MoSi, the like, or a combination
thereof. In other embodiments, other conductive features can be
used instead of or in combination with the metal-semiconductor
compound regions 122, such as a semiconductor which may be doped; a
metal such as W, Cu, and Al; a metal-alloy such as TiN and TaN; the
like, or a combination thereof.
[0047] In FIG. 23, a fourth dielectric layer 124, such as an ILD,
is formed over the third dielectric layer 118 and the
metal-semiconductor compound regions 122, and contacts 126, 128,
130, and 132 are formed through various dielectric layers to
various components. The fourth dielectric layer 124 may comprise
silicon oxide, TEOS, PSG, BPSG, FSG, SiO.sub.xC.sub.y,
Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds
thereof, composites thereof, combinations thereof, or the like,
formed by any suitable method, such as CVD, PECVD, spinning, the
like, or a combination thereof. A planarization process, such as a
CMP, can be performed to planarize the second dielectric layer
106.
[0048] Openings for the contacts 126, 128, 130, and 132 can be
formed using one or more etching steps. An opening for contact 126
is etched through the fourth dielectric layer 124, third dielectric
layer 118, second dielectric layer 106, and first dielectric layer
100 to the metal-semiconductor compound region 94. Openings for
contacts 128 are etched through the fourth dielectric layer 124 to
respective metal-semiconductor compound regions 122. An opening for
contact 130 is etched through the fourth dielectric layer 124,
third dielectric layer 118, and second dielectric layer 106 to the
gate electrode layer 104. An opening for contact 132 may be etched
in a multi-step process through the fourth dielectric layer 124,
third dielectric layer 118, and second dielectric layer 106 to the
metal-semiconductor compound region 122 and the gate electrode
layer 104. The openings may be formed using acceptable
photolithography and etching techniques.
[0049] A liner, such as a diffusion barrier layer, an adhesion
layer, or the like, and a conductive material are formed in the
openings. The liner may include titanium, titanium nitride,
tantalum, tantalum nitride, or the like formed by ALD, CVD, or the
like. The conductive material may be copper, a copper alloy,
silver, gold, tungsten, aluminum, nickel, or the like formed by
ALD, CVD, PVD, or the like. A planarization process, such as a CMP,
may be performed to remove excess material from a surface of the
fourth dielectric layer 124. The remaining liner and conductive
material form contacts 126, 128, 130, and 132 in the openings.
Contact 126 is physically and electrically coupled to the
metal-semiconductor compound region 94. Contacts 128 are physically
and electrically coupled to respective metal-semiconductor compound
regions 122. Contact 130 is physically and electrically coupled to
the gate electrode layer 104. Contact 132 is physically and
electrically coupled to the metal-semiconductor compound region 122
and the gate electrode layer 104. Contact 126 may be referred to as
an active area contact. Contacts 128 may be referred to as top
plate contacts. Contact 130 may be referred to as a gate contact.
Contact 132 may be referred to as a local connection contact.
[0050] In FIG. 24A, a fifth dielectric layer 134 and a sixth
dielectric layer 140 are formed with metallizations 138 and 144 and
vias 136 and 142, respectively. The fifth dielectric layer 134,
such as an Inter-Metallization Dielectric (IMD), is formed over the
fourth dielectric layer 124. The fifth dielectric layer 134 may
comprise silicon oxide, TEOS, PSG, BPSG, FSG, SiO.sub.xC.sub.y,
Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds
thereof, composites thereof, combinations thereof, or the like,
formed by any suitable method, such as CVD, PECVD, spinning, the
like, or a combination thereof. A planarization process, such as a
CMP, can be performed to planarize the fifth dielectric layer
134.
[0051] Openings and recesses corresponding to the vias 136 and
metallization 138 are then formed in the fifth dielectric layer
134. The openings and recesses may be formed using acceptable
photolithography and etching techniques. A liner, such as a
diffusion barrier layer, an adhesion layer, or the like, and a
conductive material are formed in the openings and recesses. The
liner may include titanium, titanium nitride, tantalum, tantalum
nitride, or the like formed by ALD, CVD, or the like. The
conductive material can be copper, a copper alloy, silver, gold,
tungsten, aluminum, or the like formed by ALD, CVD, PVD, plating,
or the like. A planarization process, such as CMP, may be performed
to remove any excess material from the top surface of the fifth
dielectric layer 134. Remaining portions of the liner and the
conductive material form the vias 136 and metallization 138.
[0052] The sixth dielectric layer 140, such as an IMD, is formed
over the fifth dielectric layer 134. The sixth dielectric layer 140
may comprise silicon oxide, TEOS, PSG, BPSG, FSG, SiO.sub.xC.sub.y,
Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds
thereof, composites thereof, combinations thereof, or the like,
formed by any suitable method, such as CVD, PECVD, spinning, the
like, or a combination thereof. A planarization process, such as a
CMP, can be performed to planarize the sixth dielectric layer
140.
[0053] Openings and recesses corresponding to the vias 142 and
metallization 144 are then formed in the sixth dielectric layer
140. The openings and recesses may be formed using acceptable
photolithography and etching techniques. A liner, such as a
diffusion barrier layer, an adhesion layer, or the like, and a
conductive material are formed in the openings and recesses. The
liner may include titanium, titanium nitride, tantalum, tantalum
nitride, or the like formed by ALD, CVD, or the like. The
conductive material can be copper, a copper alloy, silver, gold,
tungsten, aluminum, or the like formed by ALD, CVD, PVD, plating,
or the like. A planarization process, such as CMP, may be performed
to remove any excess material from the top surface of the sixth
dielectric layer 140. Remaining portions of the liner and the
conductive material form the vias 142 and metallization 144.
[0054] FIG. 24A further illustrates locations of representative
various overlay cross sections that will be subsequently discussed.
The cross sections shown in FIG. 24A are not necessarily
representative of the various layouts discussed below, but are
representative of features of the various layouts to illustrate,
e.g., aspects of the various levels of the layouts. FIG. 24A
illustrates an active area level AA, a gate electrode level GL, a
top plate level TP, a first via level VL1, a first metallization
level M1, a second via level VL2, and a second metallization level
M2. FIG. 24B illustrates an overlaid layout of the active area
level AA and the gate electrode level GL of FIG. 24A. FIG. 24C
illustrates an overlaid layout of the top plate level TP of FIG.
24A. FIGS. 24B and 24C illustrate a cross section A-A that is shown
in FIG. 24A.
[0055] One having ordinary skill in the art will readily understand
that additional dielectric layers, such as IMDs, can be formed,
which dielectric layer can include additional metallizations and
vias. Further, one having ordinary skill in the art will readily
understand that the layers and/or levels discussed herein can be
modified. For example, contacts 126, 128, and 130 can be modified
and/or obviated if the vias 136 of the first via level VL1 extend
further from the first metallization level M1, such as when a via
136 physically and electrically couples a metal-semiconductor
compound region 122.
[0056] FIGS. 25A, 26, and 27 illustrate levels of a first Dual-Port
SRAM bit cell 200 defined by a boundary (dashed line) in accordance
with some embodiments. FIG. 25A illustrates an active area level AA
of the first Dual-Port SRAM bit cell 200. The respective vertical
channel structures (e.g., vertical channel structures 72) of the
first pull-down transistor PD1, the second pull-down transistor
PD2, the first pass-gate transistor PG1, and the third pass-gate
transistor PG3 are formed in and/or on a first p-well PW1 in the
substrate of the cell. The respective vertical channel structures
(e.g., vertical channel structures 72) of the second pass-gate
transistor PG2 and the fourth pass-gate transistor PG4 are formed
in and/or on a second p-well PW2 in the substrate of the cell. The
respective vertical channel structures (e.g., vertical channel
structures 72) of the first pull-up transistor PU1 and the second
pull-up transistor PU2 are formed in and/or on an n-well NW in the
substrate of the cell. The n-well NW is disposed between the first
p-well PW1 and the second p-well PW2.
[0057] An active area first bit line conductive feature AA-BL-A
(e.g., metal-semiconductor compound region 94) extends continuously
through a Y-direction of the cell 200. The vertical channel
structure of the first pass-gate transistor PG1 is formed on and/or
in the active area of the substrate on which the conductive feature
AA-BL-A is formed. An active area second bit line conductive
feature AA-BL-B (e.g., metal-semiconductor compound region 94)
extends continuously through a Y-direction of the cell 200. The
vertical channel structure of the third pass-gate transistor PG3 is
formed on and/or in the active area of the substrate on which the
conductive feature AA-BL-B is formed. An active area second power
voltage conductive feature AA-Vss (e.g., metal-semiconductor
compound region 94) extends continuously through a Y-direction of
the cell 200. The respective vertical channel structures of the
first pull-down transistor PD1 and the second pull-down transistor
PD2 are formed on and/or in the active area of the substrate on
which the conductive feature AA-Vss is formed. An active area first
power voltage conductive feature AA-Vdd (e.g., metal-semiconductor
compound region 96) extends continuously through a Y-direction of
the cell 200. The respective vertical channel structures of the
first pull-up transistor PU1 and the second pull-up transistor PU2
are formed on and/or in the active area of the substrate on which
the conductive feature AA-Vdd is formed. An active area
complementary first bit line conductive feature AA-BLB-A (e.g.,
metal-semiconductor compound region 94) extends continuously
through a Y-direction of the cell 200. The vertical channel
structure of the second pass-gate transistor PG2 is formed on
and/or in the active area of the substrate on which the conductive
feature AA-BLB-A is formed. An active area complementary second bit
line conductive feature AA-BLB-B (e.g., metal-semiconductor
compound region 94) extends continuously through a Y-direction of
the cell 200. The vertical channel structure of the fourth
pass-gate transistor PG4 is formed on and/or in the active area of
the substrate on which the conductive feature AA-BLB-B is formed.
The active area second power voltage conductive feature AA-Vss is,
in some embodiments, at least two times as wide, e.g., in an
X-direction, as the active area first power voltage conductive
feature AA-Vdd.
[0058] The conductive features AA-BL-A, AA-BL-B, and AA-Vss are
formed on the first p-well PW1 area of the substrate. The
conductive features AA-BLB-A and AA-BLB-B are formed on the second
p-well PW2 area of the substrate. The conductive feature AA-Vdd is
formed on the n-well NW area of the substrate.
[0059] The vertical channel structures of the first pass-gate
transistor PG1, the first pull-down transistor PD1, the first
pull-up transistor PU1, and the fourth pass-gate transistor PG4 are
aligned in an X-direction. Similarly, the vertical channel
structures of the third pass-gate transistor PG3, the second
pull-down transistor PD2, the second pull-up transistor PU2, and
the second pass-gate transistor PG2 are aligned in an
X-direction.
[0060] The cell 200 can have an aspect ratio of greater than or
equal to 4. The aspect ratio can be a dimension of the cell 200
perpendicular to the direction that the active area conductive
features extend to a dimension of the cell 200 parallel to the
direction that the active area conductive features extend. In the
illustration, the aspect ratio of the cell 200 is X:Y, which is
greater than or equal to 4.
[0061] FIG. 25B illustrates a 2.times.2 array of cells 200 in
accordance with some embodiments. Larger arrays are contemplated,
and the 2.times.2 array is depicted to clearly and simply
illustrate various aspects of some embodiments. In the array, each
cell 200 has an adjacent cell 200 that is mirrored across the X or
Y-direction boundary where the cells 200 adjoin. For example, cell
200b is a mirrored version of cell 200a along an X-direction
boundary between the cells 200a and 200b. Similarly, cell 200c is a
mirrored version of cell 200a along a Y-direction boundary between
the cells 200a and 200c.
[0062] Further, various p-wells and n-wells may extend across
multiple cells 200. FIG. 25B illustrates a first n-well NW1 that
extends along a Y-direction across the cells 200a and 200b, and
illustrates a second n-well NW2 that extends along a Y-direction
across the cells 200c and 200d. A first p-well PW1 extends along a
Y-direction and across Y-direction boundaries of adjacent cells 200
between the first n-well NW1 and the second n-well NW2. As
illustrated, the first p-well PW1 crosses the Y-direction boundary
between cells 200a and 200c, crosses the Y-direction boundary
between cells 200b and 200d, and extends in a Y-direction. A first
second p-well PW21 is on an opposite side of the first n-well NW1
from the first p-well PW1. A second second p-well PW22 is on an
opposite side of the second n-well NW2 from the first p-well PW1.
The first second p-well PW21 and the second second p-well PW22 can
extend across boundaries of cells 200 similar to the first p-well
PW1, although additional cells are not depicted to illustrate such
features.
[0063] Active area conductive features (e.g., metal-semiconductor
compound regions 94 and 96) extend continuously in respective
Y-directions across multiple cells. As illustrated, first
conductive features AA-BL-A1, AA-BL-B1, AA-BLB-A1, AA-BLB-B1,
AA-Vss1, and AA-Vdd1 extend in respective Y-directions across cells
200a and 200b. Similarly, second conductive features AA-BL-A2,
AA-BL-B2, AA-BLB-A2, AA-BLB-B2, AA-Vss2, and AA-Vdd2 extend in
respective Y-directions across cells 200c and 200d. In this manner,
the various electrical signals can be electrically coupled to the
respective transistors in the cell 200 without a contact being
provided in the cell 200 to electrically couple the respective
transistors to the electrical signals. For example, a contact can
be provided to conductive feature AA-Vss1 to, e.g., provide a
ground or low voltage across cells 200a and 200b at a location
outside of the cells 200a and 200b (such as by providing the
contact in a strap cell as discussed subsequently) and without a
contact being formed to the conductive feature AA-Vss1 in either
cell 200a or cell 200b.
[0064] FIG. 26 illustrates a gate electrode level GL of the first
Dual-Port SRAM bit cell 200. A first gate electrode G1 (e.g., gate
electrode layer 104) extends in an X-direction and is around the
vertical channel structures of the first pull-down transistor PD1
and the first pull-up transistor PU1. A second gate electrode G2
(e.g., gate electrode layer 104) extends in an X-direction and is
around the vertical channel structures of the second pull-down
transistor PD2 and the second pull-up transistor PU2. A third gate
electrode G3 (e.g., gate electrode layer 104) extends in an
X-direction and is around the vertical channel structure of the
first pass-gate transistor PG1. A fourth gate electrode G4 (e.g.,
gate electrode layer 104) extends in an X-direction and is around
the vertical channel structure of the second pass-gate transistor
PG2. A fifth gate electrode G5 (e.g., gate electrode layer 104)
extends in an X-direction and is around the vertical channel
structure of the third pass-gate transistor PG3. A sixth gate
electrode G6 (e.g., gate electrode layer 104) extends in an
X-direction and is around the vertical channel structure of the
fourth pass-gate transistor PG4. Each of the third gate electrode
G3, the fourth gate electrode G4, fifth gate electrode G5, and the
sixth gate electrode G6 can extend across a respective Y-direction
boundary to an adjacent cell and be around the respective vertical
channel structure of the first pass-gate transistor PG1, the second
pass-gate transistor PG2, the third pass-gate transistor PG3, and
the fourth pass-gate transistor PG4 of the respective adjacent
cell.
[0065] Gate contacts GC1, GC2, GC3, and GC4 and local connection
contacts LC1 and LC2 are also illustrated in FIG. 26. Local
connection contact LC1 (e.g., contact 132) is formed to and
physically and electrically couples the second gate electrode G2.
Local connection contact LC2 (e.g., contact 132) is formed to and
physically and electrically couples the first gate electrode G1.
Gate contact GC1 (e.g., contact 130) is formed to and physically
and electrically couples the third gate electrode G3. Gate contact
GC2 (e.g., contact 130) is formed to and physically and
electrically couples the fourth gate electrode G4. Gate contact GC3
(e.g., contact 130) is formed to and physically and electrically
couples the fifth gate electrode G5. Gate contact GC4 (e.g.,
contact 130) is formed to and physically and electrically couples
the sixth gate electrode G6. The gate contacts GC1 and GC2 are
located at respective Y-direction boundaries of the cell 200, and
gate contacts GC3 and GC4 are located within the cell 200.
[0066] FIG. 27 illustrates a top plate level TP of the first
Dual-Port SRAM bit cell 200. A first top plate T1 (e.g.,
metal-semiconductor compound regions 122) extends in an X-direction
and is on and physically and electrically coupled to the vertical
channel structures (e.g., source/drain regions 110 or 114) of the
first pull-up transistor PU1, the first pull-down transistor PD1,
and the first pass-gate transistor PG1. A second top plate T2
(e.g., metal-semiconductor compound regions 122) extends in an
X-direction and is on and physically and electrically coupled to
the vertical channel structures (e.g., source/drain regions 110 or
114) of the second pull-up transistor PU2, the second pull-down
transistor PD2, and the second pass-gate transistor PG2. A third
top plate T3 (e.g., metal-semiconductor compound regions 122) is on
and physically and electrically coupled to the vertical channel
structure (e.g., source/drain region 110) of the third pass-gate
transistor PG3. A fourth top plate T4 (e.g., metal-semiconductor
compound regions 122) is on and physically and electrically coupled
to the vertical channel structure (e.g., source/drain region 110)
of the fourth pass-gate transistor PG4.
[0067] The first local connection contact LC1 is physically and
electrically coupled to the first top plate T1. The second local
connection contact LC2 is physically and electrically coupled to
the second top plate T2. A first top plate contact TC1 (e.g.,
contact 128) is physically and electrically coupled to the first
top plate T1 and the third top plate T3. A second top plate contact
TC2 (e.g., contact 128) is physically and electrically coupled to
the second top plate T2 and the fourth top plate T4. Gate contacts
GC1, GC2, GC3, and GC4 are illustrated extending through the top
plate level TP.
[0068] FIGS. 28 and 29 illustrate a first via level VL1, a first
metallization level M1, a second via level VL2, and a second
metallization level M2 of the first Dual-Port SRAM bit cell 200
defined by a boundary (dashed line) in accordance with some
embodiments. FIG. 28 illustrates the first via level VL1 and the
first metallization level M1. The first metallization level M1
includes metallization traces M1-BLB-B, M1-BLB-A, M1-Vdd, M1-Vss,
M1-BL-A, and M1-BL-B (e.g., metallization 138) and metallization
landing pads P1, P2, P3, and P4 (e.g., metallization 138). The
metallization traces M1-BLB-B, M1-BLB-A, M1-Vdd, M1-Vss, M1-BL-A,
and M1-BL-B extend along a Y-direction and generally correspond in
location to the conductive features AA-BLB-B, AA-BLB-A, AA-Vdd,
AA-Vss, AA-BL-A, and AA-BL-B. No vias extend from the metallization
traces M1-BLB-B, M1-BLB-A, M1-Vdd, M1-Vss, M1-BL-A, and M1-BL-B
within the cell 200. Vias may extend from the metallization traces
M1-BLB-B, M1-BLB-A, M1-Vdd, M1-Vss, M1-BL-A, and M1-BL-B at
locations outside of the cell 200, which may electrically couple
the metallization traces M1-BLB-B, M1-BLB-A, M1-Vdd, M1-Vss,
M1-BL-A, and M1-BL-B to the conductive features AA-BLB-B, AA-BLB-A,
AA-Vdd, AA-Vss, AA-BL-A, and AA-BL-B, respectively.
[0069] A first via V1 (e.g., via 136) extends from the first
landing pad P1. A second via V2 (e.g., via 136) extends from the
second landing pad P2. A third via V3 (e.g., via 136) extends from
the third landing pad P3. A fourth via V4 (e.g., via 136) extends
from the fourth landing pad P4. The first via V1 physically and
electrically couples the first gate contact GC1 (see FIG. 27). The
second via V2 physically and electrically couples the second gate
contact GC2 (see FIG. 27). The third via V3 physically and
electrically couples the third gate contact GC3 (see FIG. 27). The
fourth via V4 physically and electrically couples the fourth gate
contact GC4 (see FIG. 27).
[0070] FIG. 29 illustrates the second via level VL2 and the second
metallization level M2. The second metallization level M2 includes
metallization traces M2-WL-A and M2-WL-B (e.g., metallization 144).
The metallization traces M2-WL-A and M2-WL-B extend along an
X-direction. A fifth via V5 (e.g., via 142) and a sixth via V6
(e.g., via 142) each extend from the metallization trace M2-WL-A. A
seventh via V7 (e.g., via 142) and an eighth via V8 (e.g., via 142)
each extend from the metallization trace M2-WL-B. The fifth via V5
physically and electrically couples the first landing pad P1 (see
FIG. 28). The sixth via V6 physically and electrically couples the
second landing pad P2 (see FIG. 28). The seventh via V7 physically
and electrically couples the third landing pad P3 (see FIG. 28).
The eighth via V8 physically and electrically couples the fourth
landing pad P4 (see FIG. 28).
[0071] FIGS. 30 through 32 illustrate levels of a second Dual-Port
SRAM bit cell 202 defined by a boundary (dashed line) in accordance
with some embodiments. FIG. 30 illustrates an active area level AA
of the second Dual-Port SRAM bit cell 202 similar to the active
area level AA of FIG. 25A. For brevity of discussion, features
common to both FIGS. 25A and 30 will be omitted. The location of
the active area conductive features AA-BLB-A and AA-BLB-B are
swapped in FIG. 30 compared to FIG. 25A. The vertical channel
structure of the second pass-gate transistor PG2, which is formed
on and/or in the active area of the substrate on which the
conductive feature AA-BLB-A is formed, is aligned in an X-direction
with the vertical channel structures of the first pass-gate
transistor PG1, the first pull-down transistor PD1, and the first
pull-up transistor PU1. Similarly, the vertical channel structure
of the fourth pass-gate transistor PG4, which is formed on and/or
in the active area of the substrate on which the conductive feature
AA-BLB-B is formed, is aligned in an X-direction with the vertical
channel structures of the third pass-gate transistor PG3, the
second pull-down transistor PD2, and the second pull-up transistor
PU2.
[0072] FIG. 31 illustrates a gate electrode level GL of the second
Dual-Port SRAM bit cell 202 similar to the gate electrode level GL
of FIG. 26. For brevity of discussion, features common to both
FIGS. 26 and 31 will be omitted. FIG. 31 illustrates that the third
gate contact GC3 and the fourth gate contact GC4 physically and
electrically couple the fifth gate electrode G5 and the sixth gate
electrode G6, respectively, at a respective Y-direction boundary of
the cell 202. Further, the fourth gate electrode G4 is around the
vertical channel structure of the fourth pass-gate transistor PG4.
The sixth gate electrode G6 is around the vertical channel
structure of the second pass-gate transistor PG2. Each of the
fourth gate electrode G4 and the sixth gate electrode G6 can extend
across a respective Y-direction boundary to an adjacent cell and be
around the respective vertical channel structure of the fourth
pass-gate transistor PG4 and the second pass-gate transistor PG2 of
the respective adjacent cell.
[0073] FIG. 32 illustrates a top plate level TP of the second
Dual-Port SRAM bit cell 202 similar to the top plate level TP of
FIG. 27. For brevity of discussion, features common to both FIGS.
27 and 32 will be omitted. The second top plate T2 is on and
physically and electrically coupled to the vertical channel
structures of the second pull-up transistor PU2, the second
pull-down transistor PD2, and the fourth pass-gate transistor PG4.
The fourth top plate T4 is on and physically and electrically
coupled to the vertical channel structure of the second pass-gate
transistor PG2. In FIG. 32, each of the third top plate T3 and the
fourth top plate T4 extend further inward of the cell 202 along an
X-direction compared to FIG. 27. The respective locations of first
top plate contact TC1 and second top plate contact TC2 are shifted
inwardly compared to FIG. 27. FIG. 32 also illustrates the
locations of the third gate contact GC3 and the fourth gate contact
GC4 as discussed with respect to FIG. 31.
[0074] FIGS. 33 and 34 illustrate a first via level VL1, a first
metallization level M1, a second via level VL2, and a second
metallization level M2 of the second Dual-Port SRAM bit cell 202
defined by a boundary (dashed line) in accordance with some
embodiments. FIG. 33 illustrates the first via level VL1 and the
first metallization level M1. The first metallization level M1
includes metallization traces M1-WL-A and M1-WL-B (e.g.,
metallization 138). The metallization traces M1-WL-A and M1-WL-B
extend along an X-direction. A first via V1 (e.g., via 136) and a
fourth via V4 (e.g., via 136) each extend from the metallization
trace M1-WL-A. A second via V2 (e.g., via 136) and a third via V3
(e.g., via 136) each extend from the metallization trace M1-WL-B.
The first via V1 physically and electrically couples the first gate
contact GC1 (see FIG. 32). The second via V2 physically and
electrically couples the second gate contact GC2 (see FIG. 32). The
third via V3 physically and electrically couples the third gate
contact GC3 (see FIG. 32). The fourth via V4 physically and
electrically couples the fourth gate contact GC4 (see FIG. 32).
[0075] FIG. 34 illustrates the second via level VL2 and the second
metallization level M2. The second metallization level M2 includes
metallization traces M2-BLB-A, M2-BLB-B, M2-Vdd, M2-Vss, M2-BL-A,
and M2-BL-B (e.g., metallization 144). The metallization traces
M2-BLB-A, M2-BLB-B, M2-Vdd, M2-Vss, M2-BL-A, and M2-BL-B extend
along a Y-direction and generally correspond in location to the
conductive features AA-BLB-A, AA-BLB-B, AA-Vdd, AA-Vss, AA-BL-A,
and AA-BL-B. No vias extend from the metallization traces M2-BLB-A,
M2-BLB-B, M2-Vdd, M2-Vss, M2-BL-A, and M2-BL-B within the cell 202.
Vias may extend from the metallization traces M2-BLB-A, M2-BLB-B,
M2-Vdd, M2-Vss, M2-BL-A, and M2-BL-B at locations outside of the
cell 202, which may electrically couple the metallization traces
M2-BLB-A, M2-BLB-B, M2-Vdd, M2-Vss, M2-BL-A, and M2-BL-B to the
conductive features AA-BLB-A, AA-BLB-B, AA-Vdd, AA-Vss, AA-BL-A,
and AA-BL-B, respectively.
[0076] FIG. 35 illustrates an array of Dual-Port SRAM bit cells in
accordance with some embodiments. The array comprises a plurality
of sub-arrays. A first sub-array SA1 and a second sub-array SA2 are
illustrated in FIG. 35, and the array can include more or less
sub-arrays. Each sub-array can comprise the cells 200 or 202 in the
repeating pattern as discussed with respect to FIG. 25B. For
convenience, each row of the array extends along an X-direction,
and each column extends along a Y-direction. The array comprises
array columns AC. Each sub-array comprises sub-array rows SAR. The
array comprises a row edge cell REC on each end of each row. The
array comprises an edge strap cell ESC on each end of each column.
The array comprises a strap cell SC between a column of a first
neighboring sub-array, e.g., the first sub-array SA1, and a
corresponding column of a second neighboring sub-array, e.g., the
second sub-array SA2.
[0077] The strap cells SC and ESC may comprise active areas, e.g.,
with metal-semiconductor compound regions 94 and/or 96, which
active areas extend throughout the cells of the respective column.
For example, a strap cell SC can include an active area second bit
line AA-BL-B, and this active area second bit line AA-BL-B can
extend through each cell within the column. This active area second
bit line AA-BL-B can include a metal-semiconductor compound region,
e.g., metal-semiconductor compound region 94. Other active areas
can be similarly configured. The active areas in the strap cells SC
and ESC can include dummy vertical channel structures, e.g., to
provide improved uniformity, and/or can omit vertical channel
structures.
[0078] The array of FIG. 35 further includes metallization traces
MX-BLB-B, MX-BLB-A, MX-Vdd, MX-Vss, MX-BL-A, and MX-BL-B extending
along a Y-direction for a column. These metallization traces
MX-BLB-B, MX-BLB-A, MX-Vdd, MX-Vss, MX-BL-A, and MX-BL-B can be in
a first metallization M1 as discussed with respect to FIG. 28, a
second metallization M2 as discussed with respect to FIG. 34,
another metallization, or a combination of various metallizations.
Similar metallization traces can be in a similar pattern, such as
the same or in a mirrored arrangement, for the remaining columns of
the array columns AC.
[0079] A connection 210 is made in a strap cell SC and/or ESC
between a metallization trace MX-BLB-B, MX-BLB-A, MX-Vdd, MX-Vss,
MX-BL-A, and MX-BL-B and an active area conductive feature
AA-BLB-B, AA-BLB-A, AA-Vdd, AA-Vss, AA-BL-A, and AA-BL-B,
respectively. For example, if the metallization traces are in a
first metallization M1, the connection 210 can comprise a via
(e.g., via 136) and an active area contact (e.g., contact 126).
Further for example, if the metallization traces are in a second
metallization M2, the connection 210 can comprise a second level
via (e.g., via 142), a landing pad in a first metallization (e.g.,
in metallization 138), a first level via (e.g., via 136), and an
active area contact (e.g., contact 126). As illustrated, a
connection 210 is made in each strap cell SC and ESC in a first
column 1C between the complementary second bit line metallization
trace MX-BLB-B and the complementary second bit line active area
conductive feature AA-BLB-B. As illustrated, a connection 210 is
made in each strap cell SC and ESC in a first column 1C between the
complementary first bit line metallization trace MX-BLB-A and the
complementary first bit line active area conductive feature
AA-BLB-A. As illustrated, a connection 210 is made in each strap
cell SC and ESC in a first column 1C between the first power
voltage metallization trace MX-Vdd and the first power voltage
active area conductive feature AA-Vdd. As illustrated, a connection
210 is made in each strap cell SC and ESC in a first column 1C
between the second power voltage metallization trace MX-Vss and the
second power voltage active area conductive feature AA-Vss. As
illustrated, a connection 210 is made in each strap cell SC and ESC
in a first column 1C between the first bit line metallization trace
MX-BL-A and the first bit line active area conductive feature
AA-BL-A. As illustrated, a connection 210 is made in each strap
cell SC and ESC in a first column 1C between the second bit line
metallization trace MX-BL-B and the second bit line active area
conductive feature AA-BL-B. By providing these metallization traces
with connections at strap cells, a low resistance path may be
provided that helps ensure integrity of a signal or power source to
cells in the array without providing direct connections within each
cell of the array. In some embodiments, it is contemplated that the
metallization traces MX-BLB-B, MX-BLB-A, MX-Vdd, MX-Vss, MX-BL-A,
and MX-BL-B may be omitted when the number of rows in the array is
equal to or less than 64, such as between 4 and 64, and in other
embodiments, it is contemplated that the metallization traces
MX-BLB-B, MX-BLB-A, MX-Vdd, MX-Vss, MX-BL-A, and MX-BL-B may be
used when the number of rows in the array is greater than 64. The
metallization traces MX-BLB-B, MX-BLB-A, MX-Vdd, MX-Vss, MX-BL-A,
and MX-BL-B may be used or omitted with any number of cells.
[0080] FIG. 36 illustrates an array of Dual-Port SRAM bit cells in
accordance with some embodiments. The array of FIG. 36 includes
components that correspond to components discussed with respect to
FIG. 35, and for brevity, discussion of those components is not
repeated here. In FIG. 36, additional metallization traces
MX-BLB-B, MX-BLB-A, MX-Vdd, MX-Vss, MX-BL-A, and MX-BL-B are
illustrated for a column CC. Along the rows of strap cells SC and
ESC, mesh metallization traces MY-Vss and MY-Vdd extend in a
Y-direction. For each mesh metallization trace MY-Vss and MY-Vdd, a
connection 212 is between a mesh metallization trace MY-Vss and
MY-Vdd and a corresponding metallization trace MX-Vss and MX-Vdd
for each column. The mesh metallization traces MY-Vss and MY-Vdd
and the metallization traces MX-Vss and MX-Vdd are in different
metallizations. The connections 212 can comprise a via between the
metallizations, or a combination of multiple vias and one or more
intervening landing pad in an intervening metallization. By having
the mesh metallization traces MY-Vss and MY-Vdd coupled to the
metallization traces MX-Vss and MX-Vdd in each column as depicted,
the potential among the various second power voltage metallization
traces MX-Vss can remain more consistent throughout the array, and
similarly, the potential among the various first power voltage
metallization traces MX-Vdd can remain more consistent throughout
the array.
[0081] Some embodiments may achieve advantages. Some embodiments
can incorporate the emerging technology of VGAA transistors.
Further, some embodiments can implement active area conductive
features as conductors for power voltages Vdd and Vss, for bit
lines BL-A and BL-B, and for complementary bit lines BLB-A and
BLB-B, which can obviate some connectors within each cell. Some
embodiments can further improve a lithography patterning margin,
such as by using the VGAA layout, which can further decrease a cell
layout size. Even further, by increasing the aspect ratio, as
previously discussed, routes for signals can become shorter, which
can further increase the speed.
[0082] A first embodiment is a structure. The structure comprises a
dual-port static random access memory (DPSRAM) cell. The DPSRAM
cell comprises a first pull-down transistor, a second pull-down
transistor, a first pull-up transistor, a second pull-up
transistor, a first pass-gate transistor, a second pass-gate
transistor, a third pass-gate transistor, and a fourth pass-gate
transistor. The first pull-down transistor comprises a first
source/drain region in a first active area in a substrate, a first
vertical channel extending above the first active area, and a
second source/drain region above the first vertical channel. The
second pull-down transistor comprises a third source/drain region
in the first active area, a second vertical channel extending above
the first active area, and a fourth source/drain region above the
second vertical channel. The first source/drain region is
electrically coupled to the third source/drain region through the
first active area. The first pull-up transistor comprises a fifth
source/drain region in a second active area in the substrate, a
third vertical channel extending above the second active area, and
a sixth source/drain region above the third vertical channel. The
second pull-up transistor comprises a seventh source/drain region
in the second active area, a fourth vertical channel extending
above the second active area, and an eighth source/drain region
above the fourth vertical channel. The fifth source/drain region is
electrically coupled to the seventh source/drain region through the
second active area. The first pass-gate transistor comprises a
ninth source/drain region in a third active area in the substrate,
a fifth vertical channel extending above the third active area, and
a tenth source/drain region above the fifth vertical channel. The
second pass-gate transistor comprises an eleventh source/drain
region in a fourth active area in the substrate, a sixth vertical
channel extending above the fourth active area, and a twelfth
source/drain region above the sixth vertical channel. The third
pass-gate transistor comprises a thirteenth source/drain region in
a fifth active area in the substrate, a seventh vertical channel
extending above the fifth active area, and a fourteenth
source/drain region above the seventh vertical channel. The fourth
pass-gate transistor comprises a fifteenth source/drain region in a
sixth active area in the substrate, an eighth vertical channel
extending above the sixth active area, and a sixteenth source/drain
region above the eighth vertical channel. A first gate electrode is
around each of the first vertical channel and the third vertical
channel. A second gate electrode is around each of the second
vertical channel and the fourth vertical channel. A third gate
electrode is around the fifth vertical channel. A fourth gate
electrode is around the sixth vertical channel. A fifth gate
electrode is around the seventh vertical channel. A sixth gate
electrode is around the eighth vertical channel. A first conductive
feature is above and physically coupled to the second source/drain
region and the sixth source/drain region. The first conductive
feature is further electrically coupled to the second gate
electrode, the tenth source/drain region, and the fourteenth
source/drain region. A second conductive feature is above and
physically coupled to the fourth source/drain region and the eighth
source/drain region. The second conductive feature is further
electrically coupled to the first gate electrode, the twelfth
source/drain region, and the sixteenth source/drain region.
[0083] Another embodiment is a structure. The structure comprises a
memory array. The memory array comprises a plurality of dual-port
static random access memory (DPSRAM) cells arranged in columns and
rows, and in each of the columns of DPSRAM cells in the memory
array a first power node active area, a second power node active
area, a first bit line node active area, a complementary first bit
line node active area, a second bit line node active area, and a
complementary second bit line node active area. Each of the DPSRAM
cells comprises a first pull-down vertical transistor, a second
pull-down vertical transistor, a first pull-up vertical transistor,
a second pull-up vertical transistor, a first pass-gate vertical
transistor, a second pass-gate vertical transistor, a third
pass-gate vertical transistor, and a fourth pass-gate vertical
transistor. Respective first source/drain regions of the first
pull-down vertical transistor, the first pull-up vertical
transistor, the first pass-gate vertical transistor, and the third
pass-gate vertical transistor are coupled together and to
respective gates of the second pull-up vertical transistor and the
second pull-down vertical transistor. Respective first source/drain
regions of the second pull-down vertical transistor, the second
pull-up vertical transistor, the second pass-gate vertical
transistor, and the fourth pass-gate vertical transistor are
coupled together and to respective gates of the first pull-up
vertical transistor and the first pull-down vertical transistor.
The first power node active area is in a substrate and extends
along the respective column. Respective second source/drain regions
of the first pull-up vertical transistor and the second pull-up
transistor of each of the DPSRAM cells in the respective column are
disposed in the first power node active area. The second power node
active area is in the substrate and extends along the respective
column. Respective second source/drain regions of the first
pull-down vertical transistor and the second pull-down transistor
of each of the DPSRAM cells in the respective column are disposed
in the second power node active area. The first bit line node
active area is in the substrate and extends along the respective
column. A second source/drain region of the first pass-gate
vertical transistor of each of the DPSRAM cells in the respective
column is disposed in the first bit line node active area. The
complementary first bit line node active area is in the substrate
and extends along the respective column. A second source/drain
region of the second pass-gate vertical transistor of each of the
DPSRAM cells in the respective column is disposed in the
complementary first bit line node active area. The second bit line
node active area is in the substrate and extends along the
respective column. A second source/drain region of the third
pass-gate vertical transistor of each of the DPSRAM cells in the
respective column is disposed in the second bit line node active
area. The complementary second bit line node active area is in the
substrate and extends along the respective column. A second
source/drain region of the fourth pass-gate vertical transistor of
each of the DPSRAM cells in the respective column is disposed in
the complementary second bit line node active area.
[0084] A further embodiment is a method. A first power node active
area, a second power node active area, a first bit line node active
area, a complementary first bit line node active area, a second bit
line node active area, and a complementary second bit line node
active area are defined in a substrate. A first vertical channel
structure, a second vertical channel structure, a third vertical
channel structure, a fourth vertical channel structure, a fifth
vertical channel structure, a sixth vertical channel structure, a
seventh vertical channel structure, and an eighth vertical channel
structure are formed in an area. Each of the first, second, third,
fourth, fifth, and sixth vertical channel structures comprise a
first source/drain region disposed in a respective active area, a
channel region above the first source/drain region, and a second
source/drain region above the channel region. The first
source/drain region of the first vertical channel structure is
disposed in the first power node active area. The first
source/drain region of the second vertical channel structure is
disposed in the first power node active area. The first
source/drain region of the third vertical channel structure is
disposed in the second power node active area. The first
source/drain region of the fourth vertical channel structure is
disposed in the second power node active area. The first
source/drain region of the fifth vertical channel structure is
disposed in the first bit line node active area. The first
source/drain region of the sixth vertical channel structure is
disposed in the complementary first bit line node active area. The
first source/drain region of the seventh vertical channel structure
is disposed in the second bit line node active area. The first
source/drain region of the eighth vertical channel structure is
disposed in the complementary second bit line node active area. A
first gate electrode, a second gate electrode, a third gate
electrode, a fourth gate electrode, a fifth gate electrode, and a
sixth gate electrode are formed over the substrate. The first gate
electrode is around the first vertical channel structure and the
third vertical channel structure. The second gate electrode is
around the second vertical channel structure and the fourth
vertical channel structure. The third gate electrode is around the
fifth vertical channel structure. The fourth gate electrode is
around the sixth vertical channel structure. The fifth gate
electrode is around the seventh vertical channel structure. The
sixth gate electrode is around the eighth vertical channel
structure. The respective second source/drain regions of the first
vertical channel structure, the third vertical channel structure,
the fifth vertical channel structure, and the seventh vertical
channel structure are electrically coupled together and to the
second gate electrode, and the respective second source/drain
regions of the second vertical channel structure, the fourth
vertical channel structure, the sixth vertical channel structure,
and the eighth vertical channel structure are electrically coupled
together and to the first gate electrode.
[0085] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *