U.S. patent application number 15/168291 was filed with the patent office on 2016-09-22 for semiconductor device and manufacturing method thereof.
This patent application is currently assigned to Semiconductor Energy Laboratory Co., Ltd.. The applicant listed for this patent is Yosuke KANZAKI, Hiroshi MATSUKIZONO, Takuya MATSUO, Kenichi OKAZAKI, Masayuki SAKAKURA, Yukinori SHIMA, Yoshitaka YAMAMOTO, Masatoshi YOKOYAMA. Invention is credited to Yosuke KANZAKI, Hiroshi MATSUKIZONO, Takuya MATSUO, Kenichi OKAZAKI, Masayuki SAKAKURA, Yukinori SHIMA, Yoshitaka YAMAMOTO, Masatoshi YOKOYAMA.
Application Number | 20160276489 15/168291 |
Document ID | / |
Family ID | 49324277 |
Filed Date | 2016-09-22 |
United States Patent
Application |
20160276489 |
Kind Code |
A1 |
OKAZAKI; Kenichi ; et
al. |
September 22, 2016 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Abstract
An object is to suppress conducting-mode failures of a
transistor that uses an oxide semiconductor film and has a short
channel length. A semiconductor device includes a gate electrode
304, a gate insulating film 306 formed over the gate electrode, an
oxide semiconductor film 308 over the gate insulating film, and a
source electrode 310a and a drain electrode 310b formed over the
oxide semiconductor film. The channel length L of the oxide
semiconductor film is more than or equal to 1 .mu.m and less than
or equal to 50 .mu.m. The oxide semiconductor film has a peak at a
rotation angle 2.theta. in the vicinity of 31.degree. in X-ray
diffraction measurement.
Inventors: |
OKAZAKI; Kenichi; (Tochigi,
JP) ; YOKOYAMA; Masatoshi; (Tochigi, JP) ;
SAKAKURA; Masayuki; (Isehara, JP) ; SHIMA;
Yukinori; (Isehara, JP) ; KANZAKI; Yosuke;
(Osaka, JP) ; MATSUKIZONO; Hiroshi; (Osaka,
JP) ; MATSUO; Takuya; (Osaka, JP) ; YAMAMOTO;
Yoshitaka; (Yamatokoriyama, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
OKAZAKI; Kenichi
YOKOYAMA; Masatoshi
SAKAKURA; Masayuki
SHIMA; Yukinori
KANZAKI; Yosuke
MATSUKIZONO; Hiroshi
MATSUO; Takuya
YAMAMOTO; Yoshitaka |
Tochigi
Tochigi
Isehara
Isehara
Osaka
Osaka
Osaka
Yamatokoriyama |
|
JP
JP
JP
JP
JP
JP
JP
JP |
|
|
Assignee: |
Semiconductor Energy Laboratory
Co., Ltd.
Atsugi-shi
JP
SHARP KABUSHIKI KAISHA
Osaka
JP
|
Family ID: |
49324277 |
Appl. No.: |
15/168291 |
Filed: |
May 31, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13861587 |
Apr 12, 2013 |
9362411 |
|
|
15168291 |
|
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/66969 20130101;
H01L 29/78696 20130101; H01L 29/66742 20130101; H01L 29/78606
20130101; H01L 29/7869 20130101; H01L 21/02172 20130101 |
International
Class: |
H01L 29/786 20060101
H01L029/786; H01L 29/66 20060101 H01L029/66 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 16, 2012 |
JP |
2012-093303 |
Claims
1. A semiconductor device comprising: an oxide semiconductor layer,
wherein a length of a channel formed in the oxide semiconductor
layer is more than or equal to 1 .mu.m and less than or equal to 50
.mu.m, and wherein a diffraction intensity of the oxide
semiconductor layer in X-ray diffraction measurement has a peak at
a rotation angle 2.theta. of more than or equal to 30.degree. and
less than or equal to 32.degree..
2. The semiconductor device according to claim 1 further
comprising: a gate electrode; a gate insulating layer over the gate
electrode; and a source electrode and a drain electrode over the
oxide semiconductor layer, wherein the oxide semiconductor layer is
over the gate insulating layer.
3. The semiconductor device according to claim 1, wherein the
length of the channel is less than 5 .mu.m.
4. The semiconductor device according to claim 1, wherein a band
gap of the oxide semiconductor layer is more than or equal to 3.1
eV.
5. The semiconductor device according to claim 1, wherein the oxide
semiconductor layer includes at least one oxide selected from the
group consisting of indium oxide, zinc oxide, gallium oxide, tin
oxide and a combination thereof.
6. The semiconductor device according to claim 1, wherein the oxide
semiconductor layer is an In--Ga--Zn-based oxide semiconductor
layer.
7. The semiconductor device according to claim 1, wherein the oxide
semiconductor layer includes a crystal part, and wherein a c-axis
of the crystal part is aligned in a direction substantially
parallel to a normal vector of a surface on which the oxide
semiconductor layer is formed.
8. A semiconductor device comprising: an oxide semiconductor layer,
wherein a length of a channel formed in the oxide semiconductor
layer is more than or equal to 1 .mu.m and less than or equal to 50
.mu.m, wherein the oxide semiconductor layer includes a crystal
part, and wherein a c-axis of the crystal part is aligned in a
direction substantially parallel to a normal vector of a surface on
which the oxide semiconductor layer is formed.
9. The semiconductor device according to claim 8 further
comprising: a gate electrode; a gate insulating layer over the gate
electrode; and a source electrode and a drain electrode over the
oxide semiconductor layer, wherein the oxide semiconductor layer is
over the gate insulating layer.
10. The semiconductor device according to claim 8, wherein the
length of the channel is less than 5 .mu.m.
11. The semiconductor device according to claim 8, wherein the
oxide semiconductor layer is an In--Ga--Zn-based oxide
semiconductor layer.
12. The semiconductor device according to claim 1 further
comprising: a substrate; and a base insulating film between the
substrate and the oxide semiconductor layer.
13. The semiconductor device according to claim 12, wherein the
base insulating film is one of a silicon oxide film, a silicon
oxynitride film, a silicon nitride oxide film, a silicon nitride
film and an aluminum oxide film.
14. The semiconductor device according to claim 13, wherein the
base insulating film is the aluminum oxide film, and wherein a
density of the aluminum oxide film is 3.2 g/cm.sup.3 or more.
15. The semiconductor device according to claim 13, wherein the
base insulating film is the aluminum oxide film, and wherein an
amount of water (H.sub.2O) released from the aluminum oxide film is
less than or equal to 5.times.10.sup.15 atoms/cm.sup.3.
16. The semiconductor device according to claim 13, wherein the
base insulating film is the aluminum oxide film, and wherein an
amount of hydrogen (H.sub.2) released from the aluminum oxide film
is less than or equal to 5.times.10.sup.15 atoms/cm.sup.3.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser.
No. 13/861,587, filed Apr. 12, 2013, now allowed, which claims the
benefit of a foreign priority application filed in Japan as Serial
No. 2012-093303 on Apr. 16, 2012, both of which are incorporated by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device
using an oxide semiconductor and a manufacturing method thereof.
Note that in this specification, a semiconductor device refers to a
semiconductor element itself or a device including a semiconductor
element. As an example of such a semiconductor element, for
example, a transistor (e.g., a thin film transistor) can be given.
In addition, a semiconductor device also refers to a display device
such as a liquid crystal display device.
[0004] 2. Description of the Related Art
[0005] A thin film transistor formed over a flat plate such as a
glass substrate is manufactured using amorphous silicon or
polycrystalline silicon, as typically seen in a liquid crystal
display device. A thin film transistor manufactured using amorphous
silicon has low field effect mobility, but can be formed over a
larger glass substrate. In contrast, a thin film transistor
manufactured using crystalline silicon has high field effect
mobility, but due to a crystallization step such as laser
annealing, such a transistor is not always suitable for being
formed over a larger glass substrate.
[0006] In view of the foregoing, attention has been drawn to a
technique by which a thin film transistor is manufactured using an
oxide semiconductor, and such a transistor is applied to an
electronic device or an optical device. For example, Patent
Document 1 and Patent Document 2 disclose a technique by which a
thin film transistor is manufactured using zinc oxide or an
In--Ga--Zn--O-based oxide semiconductor as an oxide semiconductor
film and such a transistor is used as a switching element or the
like of an image display device.
[0007] However, it is difficult to reduce a channel length of a
thin film transistor using an amorphous In--Ga--Zn-based oxide
semiconductor film (hereinafter referred to as an a-IGZO film)
because it is brought into a conducting mode in a region with short
channel length. Note that the conducting mode in this specification
refers to a mode in which normally on characteristics or
characteristics of a low on/off ratio which causes flow of current
are exhibited.
REFERENCE
Patent Document
[0008] [Patent Document 1] Japanese Published Patent Application
No. 2007-123861 [0009] [Patent Document 2] Japanese Published
Patent Application No. 2007-096055
SUMMARY OF THE INVENTION
[0010] An object of one embodiment of the present invention is to
suppress conducting-mode failures of a transistor that uses an
oxide semiconductor film and has a short channel length.
[0011] One embodiment of the present invention is a semiconductor
device including a gate electrode, an oxide semiconductor film, and
a source electrode and a drain electrode, in which the length of a
channel formed in the oxide semiconductor film is more than or
equal to 1 .mu.m and less than or equal to 50 .mu.m, and in which
the oxide semiconductor film has a peak at a rotation angle
2.theta. of 31.degree. in X-ray diffraction measurement.
[0012] Another embodiment of the present invention is a
semiconductor device including a gate electrode, an oxide
semiconductor film, and a source electrode and a drain electrode,
in which the length of a channel formed in the oxide semiconductor
film is more than or equal to 1 .mu.m and less than or equal to 50
.mu.m, and in which the oxide semiconductor film has a peak at a
rotation angle 2.theta. in the vicinity of 31.degree. in X-ray
diffraction measurement.
[0013] In one embodiment of the present invention, it is preferable
that the length of the channel be less than 5 .mu.m.
[0014] Further in one embodiment of the present invention, it is
preferable that the oxide semiconductor film have a band gap of
more than or equal to 3.1 eV.
[0015] Furthermore in one embodiment of the present invention, it
is preferable that the oxide semiconductor film be a film including
at least one oxide selected from the group consisting of indium
oxide, zinc oxide, gallium oxide, and tin oxide.
[0016] Moreover in one embodiment of the present invention, it is
preferable that the oxide semiconductor film be an In--Ga--Zn-based
oxide semiconductor film. Further in one embodiment of the present
invention, it is preferable that the oxide semiconductor film
include a crystal part, and that a c-axis of the crystal part be
aligned in a direction parallel to a normal vector of a surface on
which the oxide semiconductor film is formed.
[0017] Still another embodiment of the present invention is a
semiconductor device including a gate electrode, an oxide
semiconductor film, and a source electrode and a drain electrode,
in which the length of a channel formed in the oxide semiconductor
film is more than or equal to 1 .mu.m and less than or equal to 50
.mu.m, in which the oxide semiconductor film includes a crystal
part, and in which a c-axis of the crystal part is aligned in a
direction parallel to a normal vector of a surface on which the
oxide semiconductor film is formed. It is preferable that the
length of the channel be less than 5 .mu.m. Further, it is
preferable that the oxide semiconductor film be an In--Ga--Zn-based
oxide semiconductor film.
[0018] A still further embodiment of the present invention is a
method for manufacturing a semiconductor device, which includes the
steps of forming a gate electrode over a substrate; forming a gate
insulating film over the gate electrode; forming an oxide
semiconductor film over the gate insulating film by heating the
substrate and sputtering a metal oxide target under conditions
using an oxygen gas and a rare gas; forming an active layer over
the gate insulating film by processing the oxide semiconductor
film; and forming a source electrode and a drain electrode over the
active layer so that the length of a channel formed in the active
layer is more than or equal to 1 .mu.m and less than or equal to 50
.mu.m. In the method, the conditions are conditions where the
heating temperature of the substrate is more than or equal to
100.degree. C. and the ratio of the flow rate of the oxygen gas to
the total gas flow is more than or equal to 70% or conditions where
the heating temperature of the substrate is more than or equal to
170.degree. C. and the ratio of the flow rate of the oxygen gas to
the total gas flow is more than or equal to 30%. Further, the oxide
semiconductor film has a peak at a rotation angle 2.theta. in the
vicinity of 31.degree. in X-ray diffraction measurement.
[0019] In one embodiment of the present invention, it is preferable
that the metal oxide target be an In--Ga--Zn-based oxide
target.
[0020] With one embodiment of the present invention,
conducting-mode failures of a transistor that uses an oxide
semiconductor film and has a short channel length can be
suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In the accompanying drawings:
[0022] FIG. 1A is a plan view of a semiconductor device of one
embodiment of the present invention and FIG. 1B is a
cross-sectional view along line X1-Y1 in FIG. 1A;
[0023] FIG. 2A shows results for Sample 1 to Sample 3 and FIG. 2B
shows results for Sample 4 to Sample 8 in Example 1;
[0024] FIG. 3A shows results for Sample 9 to Sample 13 and FIG. 3B
shows results for Sample 14 to Sample 18 in Example 1;
[0025] FIG. 4A shows results for Sample 1 to Sample 3 and FIG. 4B
shows results for Sample 4 to Sample 8 in Example 1;
[0026] FIG. 5A shows results for Sample 9 to Sample 13 and FIG. 5B
shows results for Sample 14 to Sample 18 in Example 1;
[0027] FIGS. 6A to 6C show results of electrical characteristics of
transistors with channel lengths of 2, 3, 4 .mu.m formed under
Conditions A in Example 2;
[0028] FIGS. 7A to 7C show results of electrical characteristics of
transistors with channel lengths of 12, 46, 96 .mu.m formed under
Conditions A in Example 2;
[0029] FIGS. 8A to 8C show results of electrical characteristics of
transistors with channel lengths of 2, 3, 4 .mu.m formed under
Conditions B in Example 2;
[0030] FIGS. 9A to 9C show results of electrical characteristics of
transistors with channel lengths of 12, 46, 96 .mu.m formed under
Conditions B in Example 2;
[0031] FIGS. 10A to 10C show results of electrical characteristics
of transistors with channel lengths of 2, 3, 4 .mu.m formed under
Conditions C in Example 2;
[0032] FIGS. 11A to 11C show results of electrical characteristics
of transistors with channel lengths of 12, 46, 96 .mu.m formed
under Conditions C in Example 2;
[0033] FIGS. 12A to 12C show results of electrical characteristics
of transistors with channel lengths of 2, 3, 4 .mu.m formed under
Conditions D in Example 2; and
[0034] FIGS. 13A to 13C show results of electrical characteristics
of transistors with channel lengths of 12, 46, 96 .mu.m formed
under Conditions D in Example 2.
DETAILED DESCRIPTION OF THE INVENTION
[0035] An embodiment of the present invention will be described
below in detail with reference to the accompanying drawings.
However, the present invention is not limited to the following
description and it is easily understood by those skilled in the art
that the mode and details can be variously changed without
departing from the scope and spirit of the present invention.
Therefore, the invention should not be construed as being limited
to the description in the following embodiment.
<CE (Channel-Etched) Structure>
[0036] FIG. 1A is a plan view of a semiconductor device of one
embodiment of the present invention, and FIG. 1B is a
cross-sectional view along line X1-Y1 in FIG. 1A. This
semiconductor device includes a transistor having a bottom-gate
structure (also referred to as an inverted staggered structure).
Note that in FIG. 1A, some components of the transistor (e.g., a
gate insulating film 306) are not illustrated for simplicity.
[0037] In FIG. 1B, a base insulating film (not shown) is formed
over a substrate 302. It is preferable that a region that spreads
from a surface to a depth of 3 nm of the base insulating film have
a concentration of a metal element that is included in the
substrate 302 of 1.times.10.sup.18 atoms/cm.sup.3 or lower.
[0038] A gate electrode 304 is formed over the base insulating
film. The gate insulating film 306 is formed over the base
insulating film and the gate electrode 304. An island-shaped oxide
semiconductor film 308 having a channel region is formed over the
gate insulating film 306. The oxide semiconductor film 308 is
provided in contact with the gate insulating film 306 in a position
that overlaps with the gate electrode 304. A source electrode 310a
and a drain electrode 310b are formed over the oxide semiconductor
film 308 and the gate insulating film 306. The source electrode
310a and the drain electrode 310b are electrically connected to the
oxide semiconductor film 308.
[0039] The oxide semiconductor film 308 has a channel length of
more than or equal to 1 .mu.m and less than or equal to 50 .mu.m
(preferably less than 5 .mu.m) and a channel width W (see FIG. 1A).
Further, it is preferable that the oxide semiconductor film 308
have a peak at a rotation angle 2.theta. in the vicinity of
31.degree. in X-ray diffraction measurement and the band gap of the
oxide semiconductor film 308 be more than or equal to 3.1 eV. The
details of the oxide semiconductor film 308 are described
later.
[0040] Further, an interlayer insulating film 312 and a
planarization insulating film 314 may be provided over the
transistor. In detail, the interlayer insulating film 312 may be
provided over the oxide semiconductor film 308, the source
electrode 310a, and the drain electrode 310b, and the planarization
insulating film 314 may be provided over the interlayer insulating
film 312.
[0041] With this embodiment using the oxide semiconductor film 308
having a peak at a rotation angle 2.theta. in the vicinity of
31.degree. in X-ray diffraction measurement and having a band gap
of more than or equal to 3.1 eV, the transistor that uses the oxide
semiconductor film and has a short channel length can have
suppressed conducting-mode failures. In this specification and the
like, having a peak at a rotation angle 2.theta. in the vicinity of
31.degree. means having a peak at a rotation angle 2.theta. of
31.degree. with an error of plus or minus 1.degree..
[Detailed Description of Oxide Semiconductor Film]
[0042] The oxide semiconductor film 308 is preferably a CAAC-OS
(c-axis aligned crystalline oxide semiconductor) film.
[0043] The CAAC-OS film is not completely single crystal nor
completely amorphous. The CAAC-OS film is an oxide semiconductor
film with a crystal-amorphous mixed phase structure where crystal
parts are included in an amorphous phase. Note that in most cases,
the crystal part fits inside a cube whose one side is less than 100
nm. From an observation image obtained with a transmission electron
microscope (TEM), a boundary between an amorphous part and a
crystal part in the CAAC-OS film is not clear. Further, with the
TEM, a grain boundary is not found in the CAAC-OS film. Thus, in
the CAAC-OS film, a reduction in electron mobility due to the grain
boundary is suppressed.
[0044] In each of the crystal parts included in the CAAC-OS film, a
c-axis is aligned in a direction parallel to a normal vector of a
surface on which the CAAC-OS film is formed or a normal vector of a
surface of the CAAC-OS film, triangular or hexagonal atomic
arrangement which is seen from the direction perpendicular to the
a-b plane is formed, and metal atoms are arranged in a layered
manner or metal atoms and oxygen atoms are arranged in a layered
manner when seen from the direction perpendicular to the c-axis.
Note that, among crystal parts, the directions of the a-axis and
the b-axis of one crystal part may be different from those of
another crystal part. In this specification and the like, a simple
term "perpendicular" includes a range from 85.degree. to
95.degree.. In addition, a simple term "parallel" includes a range
from -5.degree. to 5.degree..
[0045] In the CAAC-OS film, distribution of crystal parts is not
necessarily uniform. For example, in the formation process of the
CAAC-OS film, in the case where crystal growth occurs from a
surface side of the oxide semiconductor film, the proportion of
crystal parts in the vicinity of the surface of the oxide
semiconductor film is higher in some cases. Further, when an
impurity is added to the CAAC-OS film, the crystal part in a region
to which the impurity is added becomes amorphous in some cases.
[0046] Since the c-axes of the crystal parts included in the
CAAC-OS film are aligned in the direction parallel to a normal
vector of a surface on which the CAAC-OS film is formed or a normal
vector of a surface of the CAAC-OS film, the directions of the
c-axes may be different from each other depending on the shape of
the CAAC-OS film (the cross-sectional shape of the surface on which
the CAAC-OS film is formed or the cross-sectional shape of the
surface of the CAAC-OS film).
[0047] Note that the c-axes of the crystal parts are aligned in the
direction parallel to a normal vector of the surface on which the
CAAC-OS film is formed or a normal vector of the surface of the
CAAC-OS film. The crystal parts are formed by film formation or by
performing treatment for crystallization such as heat treatment
after film formation.
[0048] With use of the CAAC-OS film in a transistor, change in
electrical characteristics of the transistor due to irradiation
with visible light or ultraviolet light can be reduced. Change and
variation in threshold voltage can be suppressed. Thus, the
transistor has high reliability.
[0049] In a crystal part or a crystalline oxide semiconductor film,
defects in the bulk can be further reduced. Further, when the
surface flatness of the crystal part or the crystalline oxide
semiconductor film is enhanced, a transistor including the oxide
semiconductor film can have higher field-effect mobility than a
transistor including an amorphous oxide semiconductor film. In
order to improve the surface flatness of the oxide semiconductor
film, the oxide semiconductor film is preferably formed over a flat
surface. Specifically, the oxide semiconductor is preferably formed
over a surface with an average surface roughness (Ra) of less than
or equal to 0.15 nm, preferably less than or equal to 0.1 nm.
[0050] Note that the average surface roughness Ra is obtained by
expanding center line average surface roughness that is defined by
JIS B 0601 into three dimensions for application to a surface, and
Ra can be expressed as the average value of the absolute values of
deviations from a reference surface to a specific surface and is
defined by Formula 1.
Ra = 1 S 0 .intg. y 2 y 1 .intg. x 2 x 1 f ( x , y ) - Z 0 x y [
FORMULA 1 ] ##EQU00001##
[0051] In the above formula, S.sub.0 represents the area of a
measurement surface (a rectangular region which is defined by four
points at coordinates (x.sub.1, y.sub.1), (x.sub.1, y.sub.2),
(x.sub.2, y.sub.1), and (x.sub.2, y.sub.2)), and Z.sub.0 represents
the average height of the measurement surface. Ra can be measured
using an atomic force microscope (AFM).
[0052] For the oxide semiconductor film, an oxide semiconductor
having a wider band gap than that of silicon, i.e., 1.1 eV, is
preferably used. For example, an In--Ga--Zn-based oxide having a
band gap of 3.15 eV, an indium oxide having a band gap of about 3.0
eV, an indium tin oxide having a band gap of about 3.0 eV, an
indium gallium oxide having a band gap of about 3.3 eV, an indium
zinc oxide having a band gap of about 2.7 eV, a tin oxide having a
band gap of about 3.3 eV a zinc oxide having a band gap of about
3.37 eV, or the like can be preferably used. With the use of such a
material, the off-state current of the transistor can be kept
extremely low. Note that in one embodiment of the present
invention, the band gap of the oxide semiconductor film is
preferably more than or equal to 3.1 eV.
[0053] An oxide semiconductor used for the oxide semiconductor film
preferably includes at least one selected from the group consisting
of indium (In), zinc (Zn), and gallium (Ga). In particular, In and
Zn are preferably included. As a stabilizer for reducing a
variation in electrical characteristics among transistors including
the oxide semiconductor, tin (Sn) is preferably included.
[0054] For example, as the oxide semiconductor, any of the
following can be used: indium oxide; tin oxide; zinc oxide; a
two-component metal oxide such as an In--Zn-based oxide, a
Sn--Zn-based oxide, or In--Ga-based oxide; a three-component metal
oxide such as an In--Ga--Zn-based oxide (also referred to as IGZO),
In--Sn--Zn-based oxide, Sn--Ga--Zn-based oxide; and a
four-component metal oxide such as an In--Sn--Ga--Zn-based
oxide.
[0055] Here, an "In--Ga--Zn-based oxide" means an oxide including
In, Ga, and Zn as its main components and there is no particular
limitation on the ratio of In:Ga:Zn. The In--Ga--Zn-based oxide may
include a metal element other than the In, Ga, and Zn.
[0056] Alternatively, a material represented by
InMO.sub.3(ZnO).sub.m (m>0, m is not an integer) may be used as
an oxide semiconductor. Note that M represents one or more metal
elements selected from Ga, Fe, Mn, and Co, or the above-described
element as a stabilizer. Alternatively, as the oxide semiconductor,
a material represented by In.sub.2SnO.sub.5(ZnO).sub.n (n>0, n
is an integer) may be used.
[0057] For example, an In--Ga--Zn-based oxide with an atomic ratio
where In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In:Ga:Zn=2:1:3, or an
oxide whose composition is in the neighborhood of the above
compositions can be used.
[0058] In a formation step of the oxide semiconductor film, it is
preferable that hydrogen or water be contained in the oxide
semiconductor film as little as possible. For example, it is
preferable that the substrate be preheated in a preheating chamber
of a sputtering apparatus as pretreatment for formation of the
oxide semiconductor film so that an impurity such as hydrogen or
moisture adsorbed to the substrate are eliminated and removed.
Then, the oxide semiconductor film is preferably formed in a film
formation chamber from which remaining moisture is removed.
[0059] In order to remove the moisture in the preheating chamber
and the film formation chamber, an entrapment vacuum pump, for
example, a cryopump, an ion pump, or a titanium sublimation pump is
preferably used. Further, an evacuation unit may be a turbo pump
provided with a cold trap. From the preheating chamber and the film
formation chamber which are evacuated with a cryopump, a hydrogen
atom, a compound containing a hydrogen atom such as water
(H.sub.2O) (preferably, also a compound containing a carbon atom),
and the like are removed, whereby the concentration of an impurity
such as hydrogen or moisture in the oxide semiconductor film can be
reduced.
[0060] Note that an In--Ga--Zn-based oxide film is formed as the
oxide semiconductor film by a sputtering method. The oxide
semiconductor film can be formed by a sputtering method in a rare
gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed
atmosphere of a rare gas and oxygen.
[0061] As a target used for forming an In--Ga--Zn-based oxide film
as the oxide semiconductor film by a sputtering method, for
example, a metal oxide target with an atomic ratio where
In:Ga:Zn=1:1:1, a metal oxide target with an atomic ratio where
In:Ga:Zn=3:1:2, or a metal oxide target with an atomic ratio where
In:Ga:Zn=2:1:3 can be used. However, a material and composition of
a target used for formation of the oxide semiconductor film are not
limited to the above.
[0062] Further, when the oxide semiconductor film is formed using
the above metal oxide target, the composition of the film formed
over the substrate is different from the composition of the target
in some cases. For example, when the metal oxide target of
In:Ga:Zn=1:1:1 [atomic ratio] is used, the composition of the oxide
semiconductor film, which is a thin film, becomes In:Ga:Zn=1:1:0.6
to 1:1:0.8 [atomic ratio] in some cases, although it depends on the
film formation conditions. This is because in formation of the
oxide semiconductor film, Zn is sublimed, or because the sputtering
rate differs between the components of In, Ga, and Zn.
[0063] Accordingly, in order to form a thin film having a desired
composition ratio, the composition of the metal oxide target needs
to be adjusted in advance. For example, in order to make the
composition of the oxide semiconductor film, which is a thin film,
be In:Ga:Zn=1:1:1 [atomic ratio], the composition of the metal
oxide target is preferably In:Ga:Zn=1:1:1.5 [atomic ratio]. In
other words, the percentage of Zn content in the metal oxide target
is preferably made higher in advance. The composition of the target
is not limited to the above value, and can be adjusted as
appropriate depending on the film formation conditions or the
composition of the thin film to be formed. Further, it is
preferable to increase the percentage of Zn content in the metal
oxide target because the obtained thin film can have higher
crystallinity.
[0064] The relative density of the metal oxide target with respect
to a single crystal consisting of the same material as the metal
oxide target is more than or equal to 90% and less than or equal to
100%, preferably more than or equal to 95% and less than or equal
to 99.9%. By using the metal oxide target with high relative
density with respect to a single crystal consisting of the same
material as the metal oxide target, a dense oxide semiconductor
film can be formed.
[0065] As a sputtering gas used for forming the oxide semiconductor
film, it is preferable to use a high-purity gas from which
impurities such as hydrogen, water, hydroxyl groups, or hydrides
are removed.
[0066] There are three methods for forming a CAAC-OS film when the
CAAC-OS film is used as the oxide semiconductor film. The first
method is to form an oxide semiconductor film at a temperature
higher than or equal to 100.degree. C. and lower than or equal to
450.degree. C., whereby crystal parts in which the c-axes are
aligned in the direction parallel to a normal vector of a surface
on which the oxide semiconductor film is formed or a normal vector
of a surface of the oxide semiconductor film are formed in the
oxide semiconductor film. The second method is to form an oxide
semiconductor film with a small thickness and then heat it at a
temperature higher than or equal to 200.degree. C. and lower than
or equal to 700.degree. C., whereby crystal parts in which the
c-axes are aligned in the direction parallel to a normal vector of
a surface on which the oxide semiconductor film is formed or a
normal vector of a surface of the oxide semiconductor film are
formed in the oxide semiconductor film. The third method is to form
a first oxide semiconductor film with a small thickness, then heat
it at a temperature higher than or equal to 200.degree. C. and
lower than or equal to 700.degree. C., and form a second oxide
semiconductor film, whereby crystal parts in which the c-axes are
aligned in the direction parallel to a normal vector of a surface
on which the oxide semiconductor film is formed or a normal vector
of a surface of the oxide semiconductor film are formed in the
second oxide semiconductor film.
[0067] By heating the substrate during film formation, the
concentration of an impurity such as hydrogen or water in the
formed oxide semiconductor film can be reduced. In addition, damage
by sputtering can be reduced, which is preferable. The oxide
semiconductor film may be formed by an ALD (atomic layer
deposition) method, an evaporation method, a coating method, or the
like.
[0068] Note that when a crystalline (single-crystal or
microcrystalline) oxide semiconductor film other than a CAAC-OS
film is formed as the oxide semiconductor film, the film formation
temperature is not particularly limited.
[0069] As a method for processing the oxide semiconductor film, a
wet etching method or a dry etching method can be used to etch the
oxide semiconductor film. An etching gas such as BCl.sub.3,
Cl.sub.2, or O.sub.2 can be used in the dry etching method.
Further, a dry etching apparatus using a high-density plasma source
such as electron cyclotron resonance (ECR) or inductive coupled
plasma (ICP) can be used to improve a dry etching rate.
[0070] After the oxide semiconductor film is formed, the oxide
semiconductor film may be subjected to heat treatment. The
temperature of the heat treatment is higher than or equal to
300.degree. C. and lower than or equal to 700.degree. C., or lower
than the strain point of the substrate. Through the heat treatment,
excess hydrogen (including water and a hydroxyl group) contained in
the oxide semiconductor film can be removed. Note that the heat
treatment is also referred to as dehydration treatment
(dehydrogenation treatment) in this specification and the like in
some cases.
[0071] The heat treatment can be performed in such a manner that,
for example, an object is introduced into an electric furnace in
which a resistance heater or the like is used and heated at
450.degree. C. in a nitrogen atmosphere for an hour. The oxide
semiconductor film is not exposed to the air during the heat
treatment so that entry of water or hydrogen can be prevented.
[0072] Note that a heat treatment apparatus is not limited to an
electric furnace, and may be a device for heating an object by heat
conduction or heat radiation from a medium such as a heated gas.
For example, an RTA (rapid thermal anneal) apparatus such as a GRTA
(gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal
anneal) apparatus can be used. An LRTA apparatus is an apparatus
for heating an object by radiation of light (an electromagnetic
wave) emitted from a lamp such as a halogen lamp, a metal halide
lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium
lamp, or a high pressure mercury lamp. A GRTA apparatus is an
apparatus for performing heat treatment using a high-temperature
gas. As the gas, an inert gas which does not react with an object
by heat treatment, such as nitrogen or a rare gas such as argon is
used.
[0073] For example, as the heat treatment, the GRTA process may be
performed as follows. The object is put in a heated inert gas
atmosphere, heated for several minutes, and taken out of the inert
gas atmosphere. The GRTA process enables high-temperature heat
treatment in a short time. Moreover, the GRTA process can be
employed even when the temperature exceeds the upper temperature
limit of the object. Note that the inert gas may be switched to a
gas including oxygen during the process.
[0074] Note that as the inert gas atmosphere, an atmosphere that
contains nitrogen or a rare gas (e.g., helium, neon, or argon) as
its main component and does not contain water, hydrogen, or the
like is preferably used. For example, the purity of nitrogen or a
rare gas such as helium, neon, or argon introduced into a heat
treatment apparatus is greater than or equal to 6 N (99.9999%),
preferably greater than or equal to 7 N (99.99999%) (that is, the
concentration of the impurities is less than or equal to 1 ppm,
preferably less than or equal to 0.1 ppm).
[0075] The dehydration treatment (dehydrogenation treatment) might
be accompanied by elimination of oxygen which is a main constituent
material for an oxide semiconductor film, leading to a reduction in
oxygen. An oxygen vacancy exists in a portion where oxygen is
eliminated in an oxide semiconductor film, and a donor level which
leads to a change in the electrical characteristics of a transistor
is formed owing to the oxygen vacancy. Therefore, in the case where
the dehydration treatment (dehydrogenation treatment) is performed,
oxygen is preferably supplied to the oxide semiconductor film. By
supply of oxygen to the oxide semiconductor film, an oxygen vacancy
in the film can be filled.
[0076] The oxygen vacancy in the oxide semiconductor film may be
filled in the following manner for example: after the oxide
semiconductor film is subjected to the dehydration treatment
(dehydrogenation treatment), a high-purity oxygen gas, a nitrous
oxide gas, a high-purity nitrous oxide gas, or ultra dry air (the
moisture amount is less than or equal to 20 ppm (-55.degree. C. by
conversion into a dew point), preferably less than or equal to 1
ppm, further preferably less than or equal to 10 ppb, in the
measurement with the use of a dew point meter of a cavity ring down
laser spectroscopy (CRDS) system) is introduced into the same
furnace. It is preferable that water, hydrogen, and the like be not
contained in the oxygen gas or the nitrous oxide gas. The purity of
the oxygen gas or the nitrous oxide gas which is introduced into
the heat treatment apparatus is preferably 6N (99.9999%) or more,
further preferably 7N (99.99999%) or more (i.e., the impurity
concentration in the oxygen gas or the nitrous oxide gas is
preferably less than or equal to 1 ppm, further preferably less
than or equal to 0.1 ppm).
[0077] As an example of a method of supplying oxygen to the oxide
semiconductor film, oxygen (including at least any one of oxygen
radicals, oxygen atoms, and oxygen ions) may be added to the oxide
semiconductor film. An ion implantation method, an ion doping
method, a plasma immersion ion implantation method, plasma
treatment, or the like can be used as a method for adding
oxygen.
[0078] As another example of a method for supplying oxygen to the
oxide semiconductor film, the base insulating film, the gate
insulating film to be formed later, or the like may be heated to
release part of oxygen and supply oxygen to the oxide semiconductor
film.
[0079] As described above, after formation of the oxide
semiconductor film, it is preferable that dehydration treatment
(dehydrogenation treatment) be performed to remove hydrogen or
moisture from the oxide semiconductor film so that the oxide
semiconductor film is highly purified to contain as few impurities
as possible, and that oxygen be added to the oxide semiconductor in
which oxygen is reduced by the dehydration treatment
(dehydrogenation treatment) or excess oxygen is supplied to fill
oxygen vacancies in the oxide semiconductor film. Supplying oxygen
to an oxide semiconductor film may be expressed as oxygen adding
treatment or treatment for making an oxygen-excess state.
[0080] In this manner, hydrogen or moisture is removed from the
oxide semiconductor film by dehydration treatment (dehydrogenation
treatment) and an oxygen vacancy therein is filled by oxygen adding
treatment, whereby the oxide semiconductor film can be turned into
an electrically i-type (intrinsic) or substantially i-type oxide
semiconductor film. Specifically, the concentration of hydrogen in
the oxide semiconductor film is lower than or equal to
5.times.10.sup.19 atoms/cm.sup.3, preferably lower than or equal to
5.times.10.sup.18 atoms/cm.sup.3, further preferably lower than or
equal to 5.times.10.sup.17 atoms/cm.sup.3. Note that the
concentration of hydrogen in the oxide semiconductor film is
measured by secondary ion mass spectrometry (SIMS).
[0081] The number of carriers generated due to a donor in the oxide
semiconductor film, in which hydrogen concentration is reduced to a
sufficiently low concentration so that the oxide semiconductor film
is purified and in which defect states in an energy gap due to
oxygen deficiency are reduced by sufficiently supplying oxygen as
described above, is very small (close to zero); the carrier
concentration in the oxide semiconductor film is less than
1.times.10.sup.12/cm.sup.3, preferably less than
1.times.10.sup.11/cm.sup.3, further preferably less than
1.45.times.10.sup.10/cm.sup.3. In a transistor including such an
oxide semiconductor film, the off-state current (per unit channel
width (1 .mu.m) here) at room temperature (25.degree. C.), for
example, is less than or equal to 100 zA (1 zA (zeptoampere) is
1.times.10.sup.-21 A), preferably less than or equal to 10 zA,
further preferably less than or equal to 100 yA (1 yA (yoctoampere)
is 1.times.10.sup.-24 A). The transistor with very excellent
off-state current characteristics can be obtained with the use of
such an i-type (intrinsic) or substantially i-type oxide
semiconductor.
<Method for Manufacturing Transistor>
[0082] Next, a method for manufacturing the semiconductor device
illustrated in FIG. 1B is described. First, a base insulating film
(not shown) is formed over the substrate 302.
[0083] As the substrate 302, a substrate of a glass material such
as aluminosilicate glass, aluminoborosilicate glass, barium
borosilicate glass, or the like is used. In terms of mass
production, a mother glass with the following size is preferably
used for the substrate 302: the 8th generation (2160 mm.times.2460
mm); the 9th generation (2400 mm.times.2800 mm, or 2450
mm.times.3050 mm); the 10th generation (2950 mm.times.3400 mm); or
the like. A mother glass considerably shrinks when the treatment
temperature is high and the treatment time is long. Thus, in the
case where mass production is performed with the use of the mother
glass, the heating temperature in the manufacturing process is
preferably 600.degree. C. or lower, further preferably 450.degree.
C. or lower, still further preferably 350.degree. C. or lower.
[0084] As the base insulating film, a film of silicon oxide,
silicon oxynitride, silicon nitride oxide, silicon nitride,
aluminum oxide, or the like can be used. The aluminum oxide film is
formed by a sputtering method and preferably has a density of 3.2
g/cm.sup.3 or more, further preferably 3.6 g/cm.sup.3 or more. With
the use of the above-described aluminum oxide film as the base
insulating film, an impurity can be prevented from being diffused
from the substrate 302 into the transistor. The impurity from the
substrate 302 is, for example, hydrogen, a metal element, or the
like. As the metal element, elements such as sodium, aluminum,
magnesium, calcium, strontium, barium, silicon, and boron can be
given. The base insulating film can be formed to a thickness of
more than or equal to 5 nm and less than or equal to 150 nm
(preferably more than or equal to 10 nm and less than or equal to
100 nm).
[0085] In a region that spreads from a surface to a depth of 3 nm
of the base insulating film, the concentration of a metal element
that is included in the glass substrate is preferably
1.times.10.sup.18 atoms/cm.sup.3 or lower.
[0086] The base insulating film is preferably a film which releases
a small amount of water (H.sub.2O) or hydrogen (H.sub.2). For
example, an aluminum oxide film can be used as the base insulating
film. It is preferable that the amount of water (H.sub.2O) released
from the aluminum oxide film be less than or equal to
5.times.10.sup.15 atoms/cm.sup.3, further preferably less than or
equal to 1.times.10.sup.15 atoms/cm.sup.3. Further, it is
preferable that the amount of hydrogen (H.sub.2) released from the
aluminum oxide film be less than or equal to 5.times.10.sup.15
atoms/cm.sup.3, further preferably less than or equal to
1.times.10.sup.15 atoms/cm.sup.3.
[0087] For example, in the case where a film which releases a large
amount of hydrogen or water is used as the base insulating film,
there is a possibility that water or hydrogen is released from the
base insulating film in a process of forming the transistor and
diffused into the oxide semiconductor film 308 in the transistor.
By using the base insulating film which releases the
above-described amount of hydrogen or water, an impurity diffused
into the transistor can be reduced, which leads to a highly
reliable semiconductor device.
[0088] Note that the amount of released water and the amount of
released hydrogen can be measured by thermal desorption
spectroscopy (TDS).
[0089] Next, after a conductive film is formed over the base
insulating film, the gate electrode 304 is formed by a
photolithography step and an etching step, and then, the gate
insulating film 306 is formed over the base insulating film and the
gate electrode 304.
[0090] The gate electrode 304 can be formed by a sputtering method
or the like to have a single-layer structure or a stacked-layer
structure using a metal material such as molybdenum, titanium,
tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an
alloy material containing at least any one of these materials.
[0091] The gate insulating film 306 can be formed by, for example,
a PE-CVD method or the like, using silicon oxide, gallium oxide,
aluminum oxide, silicon nitride, silicon oxynitride, aluminum
oxynitride, silicon nitride oxide, or the like. The thickness of
the gate insulating film 306 can be, for example, more than or
equal to 10 nm and less than or equal to 500 nm, preferably more
than or equal to 50 nm and less than or equal to 300 nm. A film
that can prevent diffusion of an impurity from the substrate 302
can be used as the gate insulating film 306; in such a case, the
base insulating film can be omitted.
[0092] It is preferable that the gate insulating film 306 include
oxygen in a portion which is in contact with the oxide
semiconductor film 308 to be formed later. In particular, the gate
insulating film 306 preferably includes oxygen in an amount which
exceeds at least the stoichiometric composition. For example, in
the case where silicon oxide is used for the gate insulating film
306, the composition formula is preferably SiO.sub.2+a (a>0). In
this embodiment, silicon oxide of SiO.sub.2+a (a>0) is used for
the gate insulating film 306. By using this silicon oxide for the
gate insulating film 306, oxygen can be supplied to the oxide
semiconductor film 308 to be formed later and thus the oxide
semiconductor film 308 can have excellent electrical
characteristics.
[0093] The gate insulating film 306 can be formed using a high-k
material such as hafnium oxide, yttrium oxide, hafnium silicate
(HfSi.sub.xO.sub.y (x>0, y>0)), hafnium silicate to which
nitrogen is added (HfSiO.sub.xN.sub.y (x>0, y>0)), hafnium
aluminate (HfAl.sub.xO.sub.y (x>0, y>0)), or lanthanum oxide.
By using such a material, gate leakage current can be reduced.
Further, the gate insulating film 306 may have either a
single-layer structure or a stacked-layer structure.
[0094] Next, heat treatment may be performed on the substrate 302
provided with the gate insulating film 306.
[0095] The heat treatment can be performed using, for example, an
electric furnace or an apparatus for heating an object by heat
conduction or heat radiation from a heating element such as a
resistance heating element. A rapid thermal anneal (RTA) apparatus
such as a gas rapid thermal anneal (GRTA) apparatus or a lamp rapid
thermal anneal (LRTA) apparatus can be used. An LRTA apparatus is
an apparatus for heating an object by radiation of light (an
electromagnetic wave) emitted from a lamp such as a halogen lamp, a
metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high
pressure sodium lamp, or a high pressure mercury lamp. A GRTA
apparatus is an apparatus for heat treatment using a
high-temperature gas. As the high-temperature gas, an inert gas
which does not react with an object by heat treatment, such as
nitrogen or a rare gas like argon, is used. Alternatively, oxygen
may be used as another high-temperature gas. When oxygen is used,
release of oxygen from the gate insulating film 306 can be
inhibited or supply of oxygen to the gate insulating film 306 can
be performed.
[0096] In the case where the mother glass is used as the substrate
302, because high treatment temperature and long treatment time
considerably shrink the mother glass, the treatment temperature of
the heat treatment is preferably higher than or equal to
200.degree. C. and lower than or equal to 450.degree. C., further
preferably higher than or equal to 250.degree. C. and lower than or
equal to 350.degree. C.
[0097] An impurity such as water or hydrogen in the gate insulating
film 306 can be removed by the heat treatment. Further, by the heat
treatment, the defect density in the gate insulating film 306 can
be reduced. The reduction of the impurity in the gate insulating
film 306 or the defect density in the film leads to improvement in
reliability of the semiconductor device. For example, degradation
of the semiconductor device by a negative bias stress test with
light irradiation, which is one of the reliability tests for
semiconductor devices, can be suppressed.
[0098] The heat treatment may be performed as pretreatment for
formation of the oxide semiconductor film 308 to be formed later.
For example, after the gate insulating film 306 is formed, heat
treatment may be performed in a vacuum in a preheating chamber of a
sputtering apparatus and the oxide semiconductor film 308 may then
be formed.
[0099] Furthermore, the heat treatment may be performed more than
once. For example, after the gate insulating film 306 is formed,
heat treatment may be performed in a nitrogen atmosphere with an
electric furnace or the like, then heat treatment may be performed
in a vacuum in a preheating chamber of a sputtering apparatus, and
then the oxide semiconductor film 308 may then be formed.
[0100] Next, an oxide semiconductor film is formed over the gate
insulating film 306, and a photolithography step and an etching
step are performed; thus, the island-shaped semiconductor film 308
is formed.
[0101] The oxide semiconductor film 308 and a manufacturing method
thereof are described in detail in the section [Detailed
Description of Oxide Semiconductor Film]. In one embodiment of the
present invention, the oxide semiconductor film 308 serving as an
active layer over the gate insulating film 306 is preferably formed
in such a manner that an In--Ga--Zn-based oxide target is sputtered
under first and second conditions using an oxygen gas and a rare
gas while the substrate 302 is heated to form an oxide
semiconductor film over the gate insulating film 306, and the oxide
semiconductor film is processed. The first conditions are
preferably conditions where the heating temperature of the
substrate 302 is more than or equal to 100.degree. C. and the ratio
of the flow rate of the oxygen gas to the total gas flow is more
than or equal to 70%. The second conditions are preferably
conditions where the heating temperature of the substrate 302 is
more than or equal to 170.degree. C. and the ratio of the flow rate
of the oxygen gas to the total gas flow is more than or equal to
30%. In this manner, the oxide semiconductor film 308 having a peak
at a rotation angle 2.theta. in the vicinity of 31.degree. in X-ray
diffraction measurement and having a band gap of more than or equal
to 3.1 eV can be formed.
[0102] Next, a conductive film is formed over the gate insulating
film 306 and the oxide semiconductor film 308 and is subjected to a
photolithography step and an etching step, whereby the source
electrode 310a and the drain electrode 310b which are electrically
connected to the oxide semiconductor film 308 are formed. The
channel length L of the oxide semiconductor film 308 is more than
or equal to 1 .mu.m and less than or equal to 50 .mu.m, preferably
less than 5 .mu.m. At this stage, the transistor is formed.
[0103] A conductive film used for the source electrode 310a and the
drain electrode 310b is fanned using a metal film including an
element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal
nitride film including any of the above elements as a component (a
titanium nitride film, a molybdenum nitride film, or a tungsten
nitride film) can be used. Alternatively, a structure in which a
film of a high-melting-point metal such as Ti, Mo, or W or a metal
nitride film thereof (a titanium nitride film, a molybdenum nitride
film, or a tungsten nitride film) is fanned over or/and below a
metal film such as an Al film or a Cu film, may be employed.
[0104] Next, the interlayer insulating film 312 and the
planarization insulating film 314 are formed over the transistor.
The interlayer insulating film 312 can be formed using the same
material and method as the gate insulating film 306.
[0105] As the planarization insulating film 314, for example, an
organic resin material such as a polyimide-based resin, an
acrylic-based resin, or a benzocyclobutene-based resin can be used.
With the planarization insulating film 314, the surface roughness
of the transistor can be reduced.
[0106] Further, a conductive film (not shown) may be formed over
the planarization insulating film 314. For the conductive film, a
conductive material with a light-transmitting property such as
indium oxide-tin oxide (ITO: indium tin oxide) or indium oxide-zinc
oxide can be used. Note that the material of the conductive film is
not limited to the above. For example, a metal film (a film of
aluminum, titanium, or the like) may be used. Such a metal film is
preferably used because the transistor can be shielded from
external light.
[0107] The conductive film also has a function of shielding the
transistor from static charges (what is called an electrostatic
discharge: ESD). With the conductive film over the transistor,
charge due to electrostatic discharge or the like can be
dissipated.
[0108] Through the above-described manufacturing steps, the
semiconductor device illustrated in FIG. 1B can be
manufactured.
[0109] The back channel side in the channel-etched structure is
exposed to plasma treatment at the time of channel etching. In the
case where vacancies are generated in the active layer, long
channel length L makes it difficult to generate conducting-mode
failures, and short channel length L makes it easy to generate
conducting-mode failures. However, in the channel-etched structure
in one embodiment of the present invention, the oxide semiconductor
film 308 formed using IGZO that has a peak at a rotation angle
2.theta. in the vicinity of 31.degree. in X-ray diffraction
measurement and has a band gap of more than or equal to 3.1 eV is
used. The use of the oxide semiconductor film 308 can decrease the
probability of generating vacancies in the oxide semiconductor film
308, thereby suppressing conducting-mode failures.
[0110] As described above, even the transistor that uses an oxide
semiconductor film and has a short channel length L can have
suppressed conducting-mode failures. Accordingly, manufacture of a
transistor with short channel length is possible; the channel
length can be less than 5 .mu.m, or less than or equal to 2 .mu.m.
Consequently, transistors with a wide range of channel
length/channel width (L/W) can be manufactured. Further, since the
channel length can be shortened, the size of the transistor can be
reduced. This is advantageous for improvements in aperture ratio
and definition in the case of using the transistor in a panel, or
can reduce a driver region to reduce the frame size in the case of
using the transistor in a driver.
EXAMPLE 1
[0111] In Example 1, oxide semiconductor films including indium,
gallium, and zinc (expressed as IGZO films below) were formed, and
the band gap (also referred to as energy gap and expressed as Eg
below) and the crystallinity of each of the IGZO films were
evaluated. Note that in Eg evaluation, values measured by
spectroscopic ellipsometry were evaluated, and in crystallinity
evaluation, measurement was performed using X-ray diffraction (XRD)
(this measurement is expressed as XRD measurement below).
[0112] The IGZO films (Sample 1 to Sample 18) were formed using a
metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1 under
fixed conditions where the film formation pressure was 0.6 Pa, the
film formation power was 5 kw, and the film thickness was 100 nm,
at various substrate temperatures and various O.sub.2 flow rates
(various ratios of O.sub.2 flow rate). The details of the
conditions for Sample 1 to Sample 18 are described below.
(Sample 1)
[0113] Substrate temperature=room temperature (R.T.), O.sub.2 flow
rate=200 sccm (ratio of O.sub.2 flow rate=100%)
(Sample 2)
[0113] [0114] Substrate temperature=room temperature (R.T.),
Ar/O.sub.2 flow rates=100/100 sccm (ratio of O.sub.2 flow
rate=50%)
(Sample 3)
[0114] [0115] Substrate temperature=room temperature (R.T.),
Ar/O.sub.2 flow rates=180/20 sccm (ratio of O.sub.2 flow
rate=10%)
(Sample 4)
[0115] [0116] Substrate temperature=100.degree. C., O.sub.2 flow
rate=200 sccm (ratio of O.sub.2 flow rate=100%)
(Sample 5)
[0116] [0117] Substrate temperature=100.degree. C., Ar/O.sub.2 flow
rates=60/140 sccm (ratio of O.sub.2 flow rate=70%)
(Sample 6)
[0117] [0118] Substrate temperature=100.degree. C., Ar/O.sub.2 flow
rates=100/100 sccm (ratio of O.sub.2 flow rate=50%)
(Sample 7)
[0118] [0119] Substrate temperature=100.degree. C., Ar/O.sub.2 flow
rates=140/60 sccm (ratio of O.sub.2 flow rate=30%)
(Sample 8)
[0119] [0120] Substrate temperature=100.degree. C., Ar/O.sub.2 flow
rates=180/20 sccm (ratio of O.sub.2 flow rate=10%)
(Sample 9)
[0120] [0121] Substrate temperature=170.degree. C., O.sub.2 flow
rate=200 sccm (ratio of O.sub.2 flow rate=100%)
(Sample 10)
[0121] [0122] Substrate temperature=170.degree. C., Ar/O.sub.2 flow
rates=60/140 sccm (ratio of O.sub.2 flow rate=70%)
(Sample 11)
[0122] [0123] Substrate temperature=170.degree. C., Ar/O.sub.2 flow
rates=100/100 sccm (ratio of O.sub.2 flow rate=50%)
(Sample 12)
[0123] [0124] Substrate temperature=170.degree. C., Ar/O.sub.2 flow
rates=140/60 seem (ratio of O.sub.2 flow rate=30%)
(Sample 13)
[0124] [0125] Substrate temperature=170.degree. C., Ar/O.sub.2 flow
rates=180/20 sccm (ratio of O.sub.2 flow rate=10%)
(Sample 14)
[0125] [0126] Substrate temperature=200.degree. C., O.sub.2 flow
rate=200 sccm (ratio of O.sub.2 flow rate=100%)
(Sample 15)
[0126] [0127] Substrate temperature=200.degree. C., Ar/O.sub.2 flow
rates=60/140 sccm (ratio of O.sub.2 flow rate=70%)
(Sample 16)
[0127] [0128] Substrate temperature=200.degree. C., Ar/O.sub.2 flow
rates=100/100 sccm (ratio of O.sub.2 flow rate=50%)
(Sample 17)
[0128] [0129] Substrate temperature=200.degree. C., Ar/O.sub.2 flow
rates=140/60 sccm (ratio of O.sub.2 flow rate=30%)
(Sample 18)
[0129] [0130] Substrate temperature=200.degree. C., Ar/O.sub.2 flow
rates=180/20 sccm (ratio of O.sub.2 flow rate=10%)
[0131] First, the results of the Eg measurement by spectroscopic
ellipsometry are shown in FIGS. 2A and 2B and FIGS. 3A and 3B. FIG.
2A shows the results for Sample 1 to Sample 3, FIG. 2B shows the
results for Sample 4 to Sample 8, FIG. 3A shows the results for
Sample 9 to Sample 13, and FIG. 3B shows the results for Sample 14
to 18. In FIGS. 2A and 2B and FIGS. 3A and 3B, the vertical axis
represents Eg (eV), and the horizontal axis represents the ratio of
O.sub.2 flow rate (%).
[0132] FIG. 2A indicates that under the condition where the
substrate temperature is room temperature (R.T.), Eg is almost
constant at around 3.06 eV with varying ratio of O.sub.2 flow rate.
Further, FIG. 2B indicates that under the condition where the
substrate temperature is 100.degree. C., Eg increases in accordance
with an increase in the ratio of O.sub.2 flow rate and that Sample
5 with a ratio of O.sub.2 flow rate of 70% and Sample 4 with a
ratio of O.sub.2 flow rate of 100% have an Eg value of more than
3.10 eV. Furthermore, FIG. 3A indicates that under the condition
where the substrate temperature is 170.degree. C., Eg increases in
accordance with an increase in the ratio of O.sub.2 flow rate and
that Sample 12 with a ratio of O.sub.2 flow rate of 30%, Sample 11
with a ratio of O.sub.2 flow rate of 50%, Sample 10 with a ratio of
O.sub.2 flow rate of 70%, and Sample 9 with a ratio of O.sub.2 flow
rate of 100% have an Eg value of more than 3.10 eV. Further, FIG.
3B indicates that under the condition where the substrate
temperature is 200.degree. C., Eg increases in accordance with an
increase in the ratio of O.sub.2 flow rate and that Sample 17 with
a ratio of O.sub.2 flow rate of 30%, Sample 16 with a ratio of
O.sub.2 flow rate of 50%, Sample 15 with a ratio of O.sub.2 flow
rate of 70%, and Sample 14 with a ratio of O.sub.2 flow rate of
100% have an Eg value of more than 3.10 eV.
[0133] The above results show that Eg of the IGZO film can be
controlled by changing the substrate temperature and the ratio of
O.sub.2 flow rate, which are film formation conditions of the IGZO
film.
[0134] Next, the results of XRD measurement are shown in FIGS. 4A
and 4B and FIGS. 5A and 5B. FIG. 4A shows the results for Samples 1
to Sample 3, FIG. 4B shows the results for Sample 4 to Sample 8,
FIG. 5A shows the results for Sample 9 to Sample 13, and FIG. 5B
shows the results for Sample 14 to Sample 18. In FIGS. 4A and 4B
and FIGS. 5A and 5B, the vertical axis represents the intensity of
X-ray diffraction (arbitrary unit), and the horizontal axis
represents the rotation angle 2.theta. (deg.).
[0135] In FIG. 4A, no peak that indicates crystallinity is observed
for Sample 1 to Sample 3 with a substrate temperature of room
temperature (R.T.). In FIG. 4B, no peak that indicates
crystallinity is observed for Sample 8, Sample 7, and Sample 6 with
a substrate temperature of 100.degree. C. and ratios of O.sub.2
flow rate of 10%, 30%, and 50%. Meanwhile for Sample 5 and Sample 4
with a substrate temperature of 100.degree. C. and ratios of
O.sub.2 flow rate of 70% and 100%, peaks indicating crystallinity
are observed at 2.theta. of in the vicinity of 31.degree.. Further
in FIG. 5A, no peak that indicates crystallinity is observed for
Sample 13 with a substrate temperature of 170.degree. C. and a
ratio of O.sub.2 flow rate of 10%. Meanwhile for Sample 12, Sample
11, Sample 10, and Sample 9 with a substrate temperature of
170.degree. C. and ratios of O.sub.2 flow rate of 30%, 50%, 70%,
and 100%, peaks indicating crystallinity are observed at 2.theta.
of in the vicinity of 31.degree.. Furthermore, in FIG. 5B, no peak
that indicates crystallinity is observed for Sample 18 with a
substrate temperature of 200.degree. C. and a ratio of O.sub.2 flow
rate of 10%. Meanwhile for Sample 17, Sample 16, Sample 15, and
Sample 14 with a substrate temperature of 200.degree. C. and ratios
of O.sub.2 flow rate of 30%, 50%, 70%, and 100%, peaks indicating
crystallinity are observed at 2.theta. in the vicinity of
31.degree..
[0136] Note that the peak indicating crystallinity at 2.theta. in
the vicinity of 31.degree. indicates a crystal part having a c-axis
aligned in a direction parallel to a normal vector of a surface on
which the IGZO film is formed, and therefore indicates that the
IGZO film is what is called in this specification a CAAC-OS
film.
[0137] The above results show that the crystallinity of the IGZO
film can be controlled by changing the substrate temperature and
the ratio of O.sub.2 flow rate, which are film formation conditions
of the IGZO film.
[0138] Here, the substrate temperature, ratio of O.sub.2 flow rate,
Eg, and peak at 2.theta. in the vicinity of 31.degree. of Sample 1
to Sample 18 are shown in Table 1.
TABLE-US-00001 TABLE 1 Substrate Ratio of O.sub.2 flow Eg Peak at
2.theta. in the temperature (.degree. C.) rate (%) (eV) vicinity of
31.degree. Sample 1 R.T. 100% 3.06 Not observed Sample 2 R.T. 50%
3.06 Not observed Sample 3 R.T. 10% 3.06 Not observed Sample 4
100.degree. C. 100% 3.18 Observed Sample 5 100.degree. C. 70% 3.11
Observed Sample 6 100.degree. C. 50% 3.07 Not observed Sample 7
100.degree. C. 30% 3.08 Not observed Sample 8 100.degree. C. 10%
3.06 Not observed Sample 9 170.degree. C. 100% 3.21 Observed Sample
10 170.degree. C. 70% 3.16 Observed Sample 11 170.degree. C. 50%
3.13 Observed Sample 12 170.degree. C. 30% 3.10 Observed Sample 13
170.degree. C. 10% 3.07 Not observed Sample 14 200.degree. C. 100%
3.21 Observed Sample 15 200.degree. C. 70% 3.16 Observed Sample 16
200.degree. C. 50% 3.14 Observed Sample 17 200.degree. C. 30% 3.11
Observed Sample 18 200.degree. C. 10% 3.08 Not observed
[0139] As shown in FIGS. 2A and 2B, FIGS. 3A and 3B, FIGS. 4A and
4B, FIGS. 5A and 5B, and Table 1, there is a correlation between Eg
and the peak at 2.theta. in the vicinity of 31.degree. indicating
crystallinity of the IGZO film: the IGZO films having Eg of more
than 3.1 eV exhibit peaks indicating crystallinity at 2.theta. in
the vicinity of 31.degree.. In other words, it can be said that an
IGZO film having Eg of 3.1 eV or more is a CAAC-OS film.
EXAMPLE 2
[0140] In Example 2, transistors with the use of oxide
semiconductor films including indium, gallium, and zinc (expressed
as IGZO films below) were made, and electrical characteristics of
the transistors were evaluated.
[0141] A plan view of the transistors made in this example is
illustrated in FIG. 1A, and a cross-sectional view of the
transistors is illustrated in FIG. 1B. FIG. 1B corresponds to a
cross-sectional view taken along line X1-Y1 in FIG. 1A. Note that
in FIG. 1A, some components of the transistors (e.g., a gate
insulating film 306) are not illustrated for simplicity. The
details of the transistors made in this example are described
below.
[0142] A glass substrate was used as a substrate 302. A titanium
film (thickness: 100 nm) was used as a gate electrode 304. A film
of stacked layers of a silicon nitride film (thickness: 325 nm) and
a silicon oxynitride film (thickness: 50 nm) was used as a gate
insulating film 306. Further, an IGZO film (thickness: 50 nm)
formed by a sputtering method using a metal oxide target with an
atomic ratio of In:Ga:Zn=1:1:1 was used as an IGZO film 308. The
IGZO film was, after the film formation, subjected to heat
treatment at 450.degree. C. for 1 hour in the air. Then, a titanium
film (thickness: 100 nm) was used as a source electrode 310a and a
drain electrode 310b. Further, a silicon oxynitride film
(thickness: 265 nm) was used as an interlayer insulating film 312,
and an acrylic resin (thickness: 2.3 .mu.m) was used as a
planarization insulating film 314.
[0143] The IGZO film 308 was formed under fixed conditions where
the film formation pressure was 0.3 Pa, and the film formation
power was 11 kw (DC power source, the power density was 3.3
W/cm.sup.2), at various substrate temperatures and various O.sub.2
flow rates (various ratios of O.sub.2 flow rate) (Conditions A to
Conditions D). The details of Conditions A to Conditions D are
described below.
(Conditions A)
[0144] Substrate temperature=100.degree. C., Ar/O.sub.2 flow
rates=90/10 sccm (ratio of O.sub.2 flow rate=10%)
(Conditions B)
[0144] [0145] Substrate temperature=100.degree. C., Ar/O.sub.2 flow
rates=50/50 sccm (ratio of O.sub.2 flow rate=50%)
(Conditions C)
[0145] [0146] Substrate temperature=200.degree. C., Ar/O.sub.2 flow
rates=90/10 sccm (ratio of O.sub.2 flow rate=10%)
(Conditions D)
[0146] [0147] Substrate temperature=200.degree. C., Ar/O.sub.2 flow
rates=50/50 sccm (ratio of O.sub.2 flow rate=50%)
[0148] A plurality of transistors each having the structure
illustrated in FIGS. 1A and 1B was formed under each of the
above-described Conditions A to Conditions D. Note that six
conditions of the channel length L (L is indicated in FIG. 1A) were
set for the transistors: 2 .mu.m, 3 .mu.m, 4 .mu.m, 12 .mu.m, 46
.mu.m, and 96 .mu.m; and the channel widths W (W is indicated in
FIG. 1A) of the transistors were fixed at 28 .mu.m. Twelve
transistors were formed for each channel length L for each
conditions, and electrical characteristics of the transistors were
evaluated.
[0149] FIG. 6A shows results of the electrical characteristics of
the transistors with a channel length L of 2 .mu.m which are formed
under Conditions A, FIG. 6B shows results of the electrical
characteristics of the transistors with a channel length L of 3
.mu.m which are formed under Conditions A, and FIG. 6C shows
results of the electrical characteristics of the transistors with a
channel length of 4 .mu.m which are formed under Conditions A. FIG.
7A shows results of the electrical characteristics of the
transistors with a channel length L of 12 .mu.m which are formed
under Conditions A, FIG. 7B shows results of the electrical
characteristics of the transistors with a channel length L of 46
.mu.m which are formed under Conditions A, and FIG. 7C shows
results of the electrical characteristics of the transistors with a
channel length L of 96 .mu.m which are formed under Conditions A.
Further, FIG. 8A shows results of the electrical characteristics of
the transistors with a channel length L of 2 .mu.m which are formed
under Conditions B, FIG. 8B shows results of the electrical
characteristics of the transistors with a channel length L of 3
.mu.m which are formed under Conditions B, and FIG. 8C shows
results of the electrical characteristics of the transistors with a
channel length L of 4 .mu.m which are formed under Conditions B.
FIG. 9A shows results of the electrical characteristics of the
transistors with a channel length L of 12 .mu.m which are formed
under Conditions B, FIG. 9B shows results of the electrical
characteristics of the transistors with a channel length L of 46
.mu.m which are formed under Conditions B, and FIG. 9C shows
results of the electrical characteristics of the transistors with a
channel length L of 96 .mu.m which are formed under Conditions B.
Furthermore, FIG. 10A shows results of the electrical
characteristics of the transistors with a channel length L of 2
.mu.m which are formed under Conditions C, FIG. 10B shows results
of the electrical characteristics of the transistors with a channel
length L of 3 .mu.m which are formed under Conditions C, and FIG.
10C shows results of the electrical characteristics of the
transistors with a channel length L of 4 .mu.m which are formed
under Conditions C. FIG. 11A shows results of the electrical
characteristics of the transistors with a channel length L of 12
.mu.m which are formed under Conditions C, FIG. 11B shows results
of the electrical characteristics of the transistors with a channel
length L of 46 .mu.m which are formed under Conditions C, and FIG.
11C shows results of the electrical characteristics of the
transistors with a channel length L of 96 .mu.m which are formed
under Conditions C. In addition, FIG. 12A shows results of the
electrical characteristics of the transistors with a channel length
L of 2 .mu.m which are formed under Conditions D, FIG. 12B shows
results of the electrical characteristics of the transistors with a
channel length L of 3 .mu.m which are formed under Conditions D,
and FIG. 12C shows results of the electrical characteristics of the
transistors with a channel length L of 4 .mu.m which are formed
under Conditions D. FIG. 13A shows results of the electrical
characteristics of the transistors with a channel length L of 12
.mu.m which are formed under Conditions D, FIG. 13B shows results
of the electrical characteristics of the transistors with a channel
length L of 46 .mu.m which are formed under Conditions D, and FIG.
13C shows results of the electrical characteristics of the
transistors with a channel length L of 96 .mu.m which are formed
under Conditions D.
[0150] In each of FIG. 6A to FIG. 13C showing the electrical
characteristics of the transistors, the horizontal axis represents
the gate voltage (V) (expressed as Vg below), the vertical axis
represents the drain current (A) (expressed as Id below), and data
for the twelve transistors are shown at a time. Further, the
voltage (V) between the source electrode and the drain electrode
(expressed as Vd below) was set at 10 V, and Vg was applied from
-15 V to 35 V at intervals of 0.5 V.
[0151] According to FIG. 6A to FIG. 13C, some of the transistors
with a channel length L of 2 .mu.m formed under Conditions A,
Conditions B, and Conditions C are brought into a conducting mode
(normally on characteristics). Meanwhile the transistors with a
channel length L of 2 .mu.m manufactured under Conditions D are not
brought into a conducting mode (normally on characteristics) and
are thus found to have favorable transistor characteristics.
[0152] The results of Example 1 and Example 2 show that a higher
ratio of O.sub.2 flow rate and a higher substrate temperature at
the time of forming an IGZO film tend to suppress conduction
failures.
[0153] Further, the results show that in order for a transistor
using an IGZO film with a channel length of 2 .mu.m to be free from
conducting-mode failures, the substrate temperature is preferably
200.degree. C. and the ratio of O.sub.2 flow rate at the time of
forming the IGZO film is preferably 50%.
[0154] As described above, a change in film formation conditions of
the IGZO film 308 influences electrical characteristics of the
transistor, and the influence is particularly noticeable in the
case of a transistor with a short channel length L of 2 .mu.m. The
transistors formed under Conditions D each have a peak indicating
crystallinity at 2.theta. in the vicinity of 31.degree., which is
described in Example 1, and thus each include a CAAC-OS film having
a c-axis aligned in a direction parallel to a normal vector of a
surface on which the IGZO film is formed.
[0155] Thus, it was revealed that the use of a CAAC-OS film in a
transistor can suppress conducting mode (normally on
characteristics) of electrical characteristics in the case where
the transistor has a short channel length. That is, a transistor
with a short channel length can be manufactured by using a CAAC-OS
film.
[0156] This application is based on Japanese Patent Application
serial no. 2012-093303 filed with Japan Patent Office on Apr. 16,
2012, the entire contents of which are hereby incorporated by
reference.
* * * * *