U.S. patent application number 14/754627 was filed with the patent office on 2016-09-22 for semiconductor device and manufacturing method thereof.
The applicant listed for this patent is TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.. Invention is credited to Che-Cheng CHANG, Wei-Ting CHEN, Chih-Han LIN.
Application Number | 20160276340 14/754627 |
Document ID | / |
Family ID | 56852987 |
Filed Date | 2016-09-22 |
United States Patent
Application |
20160276340 |
Kind Code |
A1 |
CHANG; Che-Cheng ; et
al. |
September 22, 2016 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Abstract
A semiconductor device includes a substrate, a first gate, a
second gate, and an insulating structure. The substrate includes a
first fin and a second fin. The first gate is disposed over the
first fin. The second gate is disposed over the second fin. A gap
is formed between the first gate and the second gate, and the gap
gets wider toward the substrate. The insulating structure is
disposed in the gap. The insulating structure has a top surface and
a bottom surface opposite to each other. The bottom surface faces
the substrate. An edge of the top surface facing the first gate is
curved inward the top surface.
Inventors: |
CHANG; Che-Cheng; (New
Taipei City, TW) ; LIN; Chih-Han; (Hsinchu City,
TW) ; CHEN; Wei-Ting; (Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
Hsinchu |
|
TW |
|
|
Family ID: |
56852987 |
Appl. No.: |
14/754627 |
Filed: |
June 29, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62136295 |
Mar 20, 2015 |
|
|
|
62158911 |
May 8, 2015 |
|
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62171050 |
Jun 4, 2015 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/823431 20130101;
H01L 21/823481 20130101; H01L 27/0886 20130101; H01L 29/66477
20130101; H01L 29/7848 20130101; H01L 29/66545 20130101; H01L
21/845 20130101; H01L 29/66795 20130101; H01L 27/1211 20130101 |
International
Class: |
H01L 27/088 20060101
H01L027/088; H01L 21/8234 20060101 H01L021/8234; H01L 29/66
20060101 H01L029/66 |
Claims
1. A semiconductor device, comprising: a substrate comprising a
first fin and a second fin; a first gate disposed over the first
fin; a second gate disposed over the second fin, wherein a gap is
formed between the first gate and the second gate, and the gap gets
wider toward the substrate; and an insulating structure disposed in
the gap, wherein the insulating structure has a top surface and a
bottom surface opposite to each other, the bottom surface faces the
substrate, and an edge of the top surface facing the first gate is
curved inward at the top surface.
2. The semiconductor device of claim 1, wherein an edge of the top
surface facing the second gate is curved inward at the top
surface.
3. The semiconductor device of claim 1, further comprising: a
dielectric layer disposed between adjacent two of the first
gates.
4. The semiconductor device of claim 3, wherein the dielectric
layer further disposed between adjacent two of the second
gates.
5. The semiconductor device of claim 1, wherein a first angle is
formed between the bottom surface of the insulating structure and a
side wall of the first gate facing the insulating structure, and
the first angle is less than 90 degrees.
6. The semiconductor device of claim 5, wherein a second angle is
formed between the bottom surface of the insulating structure and a
side wall of the second gate facing the insulating structure, and
the second angle is less than 90 degrees.
7. The semiconductor device of claim 1, wherein the first gate has
a round corner facing the insulating structure and the
substrate.
8. The semiconductor device of claim 7, wherein the second gate has
a round corner facing the insulating structure and the
substrate.
9. A semiconductor device, comprising: a substrate comprising a
first fin and a second fin; a first gate disposed over the first
fin; a second gate disposed over the second fin and separated from
the first gate; and an insulating structure disposed between the
first gate and the second gate, wherein the insulating structure
has a top surface and a bottom surface opposite to each other, the
bottom surface of the insulating structure faces the substrate, an
area of the bottom surface of the insulating structure is greater
than an area of the top surface of the insulating structure, and an
edge of the top surface of the insulating structure facing the
first gate is curved inward at the top surface.
10. The semiconductor device of claim 9, wherein the first gate has
a bottom surface facing the substrate, a first angle is formed
between the bottom surface of the first gate and a side wall of the
first gate facing the second gate, and the first angle is greater
than 90 degrees.
11. The semiconductor device of claim 10, wherein the second gate
has a bottom surface facing the substrate, a second angle is formed
between the bottom surface of the second gate and a side wall of
the second gate facing the first gate, and the second angle is
greater than 90 degrees.
12. The semiconductor device of claim 10, wherein the insulating
structure has a top portion and a bottom portion disposed between
the top portion and the substrate, and a width of the top portion
is shorter than a width of the bottom portion.
13-20. (canceled)
21. The semiconductor device of claim 1, wherein the first fin and
the second fin are epitaxy structures.
22. The semiconductor device of claim 1, wherein the first gate has
a top surface and a bottom surface opposite to each other, the top
surface of the first gate has an edge facing the insulating
structure, and the edge is curved toward the top surface of the
insulating structure.
23. The semiconductor device of claim 1, wherein the second gate
has a top surface and a bottom surface opposite to each other, the
top surface of the second gate has an edge facing the insulating
structure, and the edge is curved toward the top surface of the
insulating structure.
24. The semiconductor device of claim 1, wherein the first gate has
a top surface and a bottom surface opposite to each other, and the
first gate gets wider toward the top surface and gets narrower
toward the bottom surface.
25. The semiconductor device of claim 1, wherein the second gate
has a top surface and a bottom surface opposite to each other, and
the second gate gets wider toward the top surface and gets narrower
toward the bottom surface.
26. The semiconductor device of claim 1, wherein the insulating
structure has a top portion and a bottom portion, the bottom
portion is disposed between the top portion and the substrate, the
top portion has a substantially constant width, and the width of
the bottom portion gets wider toward the substrate.
27. The semiconductor device of claim 1, wherein the insulating
structure has a top portion and a bottom portion, the bottom
portion is disposed between the top portion and the substrate, a
side wall of the first gate adjacent to the top portion is
substantially straight, and the side wall adjacent to the bottom
portion is substantially round.
28. The semiconductor device of claim 1, wherein the insulating
structure has a top portion and a bottom portion, the bottom
portion is disposed between the top portion and the substrate, a
side wall of the second gate adjacent to the top portion is
substantially straight, and the side wall adjacent to the bottom
portion is substantially round.
Description
PRIORITY CLAIM AND CROSS-REFERENCE
[0001] This application claims priority to U.S. Provisional
Application Ser. No. 62/136,295, filed Mar. 20, 2015, U.S.
Provisional Application Ser. No. 62/158,911, filed May 8, 2015, and
U.S. Provisional Application Ser. No. 62/171,050, filed Jun. 4,
2015, which are herein incorporated by reference.
BACKGROUND
[0002] As the semiconductor industry has progressed into nanometer
technology process nodes in pursuit of higher device density,
higher performance, and lower costs, challenges from both
fabrication and design issues have resulted in the development of
three dimensional designs, such as a fin-like field effect
transistor (FinFET). A FinFET includes an extended semiconductor
fin that is elevated above a substrate in a direction normal to the
plane of the substrate. The channel of the FET is formed in this
vertical fin. A gate is provided over (e.g., wrapping) the fin. The
FinFETs further can reduce the short channel effect.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIGS. 1A to 6A are top views of a method for manufacturing a
semiconductor device at various stages in accordance with some
embodiments of the present disclosure.
[0005] FIGS. 1B to 6B are cross-sectional views respectively taking
along line B-B of FIGS. 1A to 6A.
[0006] FIG. 7 is a cross-sectional view of a semiconductor device
in accordance with some embodiments of the present disclosure.
[0007] FIG. 8 is a cross-sectional view of a semiconductor device
in accordance with some embodiments of the present disclosure.
[0008] FIG. 9 is a cross-sectional view of a semiconductor device
in accordance with some embodiments of the present disclosure.
DETAILED DESCRIPTION
[0009] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0010] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0011] Embodiments of the present disclosure provide some improved
methods for the formation of semiconductor devices and the
resulting structures. These embodiments are discussed below in the
context of forming finFET transistors having a single fin or
multiple fins on a bulk silicon substrate. One of ordinary skill in
the art will realize that embodiments of the present disclosure may
be used with other configurations.
[0012] FIGS. 1A to 6A are top views of a method for manufacturing a
semiconductor device at various stages in accordance with some
embodiments of the present disclosure, and FIGS. 1B to 6B are
cross-sectional views respectively taking along line B-B of FIGS.
1A to 6A. Reference is made to FIGS. 1A and 1B. A substrate 110 is
provided. The substrate 110 includes first fins 112 and second fins
114 protruded from a top surface 111 of the substrate 110. In some
embodiments, the first fins 112 and the second fins 114 include
silicon. In some embodiments, the widths W of the first fins 112
and the second fins 114 may be about 10 nm, and the distance D
between the adjacent first fin 112 and second fin 114 may be about
35 nm, and the claimed scope of the present disclosure is not
limited in this respect. Moreover, it is note that the numbers of
the first fins 112 and the second fins 114 in FIGS. 1A and 1B are
illustrative, and should not limit the claimed scope of the present
disclosure. A person having ordinary skill in the art may select
suitable numbers for the first fins 112 and the second fins 114
according to actual situations.
[0013] In some embodiments, the substrate 110 may be a
semiconductor material and may include known structures including a
graded layer or a buried oxide, for example. In some embodiments,
the substrate 110 includes bulk silicon that may be undoped or
doped (e.g., p-type, n-type, or a combination thereof). Other
materials that are suitable for semiconductor device formation may
be used. Other materials, such as germanium, quartz, sapphire, and
glass could alternatively be used for the substrate 110.
Alternatively, the silicon substrate 110 may be an active layer of
a semiconductor-on-insulator (SOI) substrate or a multi-layered
structure such as a silicon-germanium layer formed on a bulk
silicon layer.
[0014] The first fins 112 and the second fins 114 may be formed,
for example, by patterning and etching the substrate 110 using
photolithography techniques. In some embodiments, a layer of
photoresist material (not shown) is deposited over the substrate
110. The layer of photoresist material is irradiated (exposed) in
accordance with a desired pattern (the first fins 112 and the
second fins 114 in this case) and developed to remove a portion of
the photoresist material. The remaining photoresist material
protects the underlying material from subsequent processing steps,
such as etching. It should be noted that other masks, such as an
oxide or silicon nitride mask, may also be used in the etching
process.
[0015] In some other embodiments, the first fins 112 and the second
fins 114 may be epitaxially grown. For example, exposed portions of
an underlying material, such as an exposed portion of the substrate
110, may be used in an epitaxial process to form the first fins 112
and the second fins 114. A mask may be used to control the shape of
the first fins 112 and the second fins 114 during the epitaxial
growth process.
[0016] In FIG. 1B, the substrate 110 further includes isolation
structures 116. The isolation structures 116, which acts as a
shallow trench isolation (STI) around the first fins 112 and the
second fins 114, may be formed by chemical vapor deposition (CVD)
techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a
precursor. In some other embodiments, the isolation structures 116
may be formed by implanting ions, such as oxygen, nitrogen, carbon,
or the like, into the substrate 110. In yet some other embodiments,
the isolation structures 116 are insulator layers of a SOI
wafer.
[0017] In FIG. 1B, a gate insulator layer 120 is formed on the
first fins 112 and the second fins 114. The gate insulator layer
120, which prevents electron depletion, may include, for example, a
high-k dielectric material such as metal oxides, metal nitrides,
metal silicates, transition metal-oxides, transition
metal-nitrides, transition metal-silicates, oxynitrides of metals,
metal aluminates, zirconium silicate, zirconium aluminate, or
combinations thereof. Some embodiments may include hafnium oxide
(HfO.sub.2) hafnium silicon oxide (HfSiO), hafnium silicon
oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium
oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide
(LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide
(Ta.sub.2O.sub.5), yttrium oxide (Y.sub.2O.sub.3), strontium
titanium oxide (SrTiO.sub.3, STO), barium titanium oxide
(BaTiO.sub.3, BTO), barium zirconium oxide (BaZrO), hafnium
lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum
silicon oxide (AlSiO), aluminum oxide (Al.sub.2O.sub.3), silicon
nitride (Si.sub.3N.sub.4), oxynitrides (SiON), and combinations
thereof. The gate insulator layer 120 may have a multilayer
structure such as one layer of silicon oxide (e.g., interfacial
layer) and another layer of high-k material. The gate insulator
layer 120 may have a thickness T ranging from about 10 to about 30
angstroms (A). The gate insulator layer 120 may be formed using
chemical vapor deposition (CVD), physical vapor deposition (PVD),
atomic layer deposition (ALD), thermal oxide, ozone oxidation,
other suitable processes, or combinations thereof.
[0018] In FIGS. 1A and 1B, a dummy layer 130 is formed over the
substrate 110 to cover the gate insulator layer 120, the first fins
112, and the second fins 114. In other words, the gate insulator
layer 120 is disposed between the dummy layer 130 and the substrate
110. In some embodiments, the dummy layer 130 includes a
semiconductor material such as polysilicon, amorphous silicon, or
the like. The dummy layer 130 may be deposited doped or undoped.
For example, in some embodiments the dummy layer 130 includes
polysilicon deposited undoped by low-pressure chemical vapor
deposition (LPCVD). The polysilicon may also be deposited, for
example, by furnace deposition of an in-situ doped polysilicon.
Alternatively, the dummy layer 130 may includes other suitable
materials.
[0019] In some embodiments, one or more dielectric layer(s) is
formed on opposing sides of the dummy layer 130. For example, in
FIGS. 1A and 1B, first dielectric layers 142 and second dielectric
layers 144 are together formed at opposing sides of the dummy layer
130. One of the first dielectric layers 142 is disposed between two
of the second dielectric layers 144, and one of the second
dielectric layers 144 is disposed between one of the first
dielectric layers 142 and the dummy layer 130. The first dielectric
layer 142 may be made of oxide, and the second dielectric layers
144 may be made of silicon nitride, and the claimed scope is not
limited in this respect. The first dielectric layers 142 and the
second dielectric layers 144 are typically formed by blanket
depositing one or more dielectric layer(s) (not shown) on the
previously formed structure. The dielectric layer(s) may include
silicon nitride (SiN), oxynitride, silicion carbon (SiC), silicon
oxynitride (SiON), oxide, and the like and may be formed by methods
utilized to form such a layer, such as chemical vapor deposition
(CVD), plasma enhanced CVD, sputter, and other methods known in the
art. The first dielectric layer 142 and the second dielectric
layers 144 may include different materials with different etch
characteristics than the dummy layer 130 so that the first
dielectric layers 142 and the second dielectric layers 144 may be
used as masks for the patterning of the dummy layer 130 (described
below with references to FIGS. 3A-3B). The first dielectric layers
142 and the second dielectric layers 144 may then be patterned,
such as by one or more etches to remove the portions of the first
dielectric layers 142 and the second dielectric layers 144 from the
horizontal surfaces of the structure.
[0020] Reference is made to FIGS. 2A and 2B. A mask 150 is formed
over the dummy layer 130, the first dielectric layers 142, and the
second dielectric layers 144, and is patterned to define an
insulation area between gates (see FIGS. 6A and 6B), i.e., to
define the ends of the gates. In some embodiments, the mask 150 is
a photoresist mask formed by depositing, exposing, and developing a
layer of photoresist material. The mask 150 is patterned to form
the insulation area between the gates in subsequent processing
steps as discussed in greater detail below.
[0021] In some embodiments, the mask 150 is trimmed after
patterning the mask 150. For example, the mask 150 is etched using
isotropic wet etching process, for example, with a plasma process
in an HBr/O.sub.2 ambient environment for further reducing the
critical dimension of the mask 150.
[0022] Reference is made to FIGS. 3A and 3B. For clarity, the gate
insulator layer 120 is depicted in FIG. 3B and is omitted in FIG.
3A. The dummy layer 130 (see FIGS. 2A and 2B) is removed (or
patterned) in the regions exposed by the mask 150 by an etching
back process or other suitable process to form a dummy structure
136. For example, the dummy layer 130 may be selectively etched
thereby forming a first trench 132 and a second trench 134 between
the second dielectric layers 144. The dummy structure 136 is
disposed between the first trench 132 and the second trench 134.
The first trench 132 exposes portions of the gate insulator layer
120 disposed on the first fins 112, and the second trench 134
exposes some other portions of the gate insulator layer 120
disposed on the second fins 114. The exposed portions of the dummy
layer 130 may be removed by a wet etch process that includes
exposure to hydroxide containing solution (e.g., ammonium
hydroxide), deionized water, and/or other suitable etchant
solutions.
[0023] Reference is made to FIGS. 4A and 4B. For clarity, the gate
insulator layer 120 is depicted in FIG. 4B and is omitted in FIG.
4A. The mask 150 (see FIGS. 3A and 3B) is removed by an ashing,
stripping, or other suitable technique. The remained portion of the
dummy layer 130 (see FIG. 2B) forms the dummy structure 136 between
the first trench 132 and the second trench 134. The dummy structure
136 may be a plug which is surrounded by two adjacent second
dielectric layers 144, the first trench 132, and the second trench
134. The dummy structure 136 has a top surface 136t and a bottom
surface 136b opposite to each other. The bottom surface 136b faces
the substrate 110. That is, the bottom surface 136b is adjacent to
the gate insulator layer 120. In FIG. 4A, the top surface 136t of
the dummy structure 136 has two opposite edges 137a and 137b. The
edge 137a faces the first trench 132, and the edge 137b faces the
second trench 134. Both of the edges 137a and 137b are curved
inward the top surface 136t. Furthermore, in FIG. 4B, an area of
the bottom surface 136b is greater than an area of the top surface
136t. The dummy structure 136 has two opposite side walls 138a and
138b. The side wall 138a faces the first trench 132, and the side
wall 138b faces the second trench 134. An angle .phi.1 formed
between the bottom surface 136b and the side wall 138a is
substantially less than 90 degrees, i.e., the angle .phi.1 is an
acute angle. Another angle .phi.2 formed between the bottom surface
136b and the side wall 138b is substantially less than 90 degrees,
i.e., the angle .phi.2 is an acute angle. Therefore, the dummy
structure 130 gets narrower toward the top surface 136t thereof,
and gets wider toward the bottom surface 136b thereof.
[0024] The terms "substantially" as used herein may be applied to
modify any quantitative representation which could permissibly vary
without resulting in a change in the basic function to which it is
related. For example, the angles .phi.1 and .phi.2 as disclosed
herein being substantially less than 90 degrees may permissibly
vary within the scope of the disclosure if the angles .phi.1 and
.phi.2 are not structurally altered.
[0025] In some embodiments, the dummy structure 136 is trimmed
after removing the mask 150 (see FIGS. 3A and 3B). For example, the
dummy structure 136 is etched using an isotropic wet etching
process for further reducing the critical dimension of the dummy
structure 136.
[0026] In FIGS. 4A and 4B, the aperture of the first trench 132
near the top surface 136t of the dummy structure 136 is greater
than the aperture of the first trench 132 near the bottom surface
136b of the dummy structure 136. Also, the aperture of the second
trench 134 near the top surface 136t of the dummy structure 136 is
greater than the aperture of the second trench 134 near the bottom
surface 136b of the dummy structure 136. A configuration such as
this provides a larger process window for a first gate 160 and a
second gate 165 filling (see FIGS. 5A and 5B) as discussed in
greater detail below.
[0027] Reference is made to FIGS. 5A and 5B. A first gate 160 is
formed to fill the first trench 132, and a second gate 165 is
formed to fill the second trench 134. Therefore, the first gate 160
covers the first fins 112, and the second gate 165 covers the
second fins 114. The process from FIGS. 3A to 5B is referred as a
replacement gate loop process. Furthermore, if the dummy layer 130
of FIGS. 2A and 2B is made of polysilicon, the process from FIGS.
3A to 5B is referred as a replacement polysilicon gate (RPG) loop
process. In some embodiments, the first trench 132 and the second
trench 134 may be filled with one or more metal layers. The filling
process include chemical vapor deposition (CVD), physical vapor
deposition (PVD), atomic layer deposition (ALD), high density
plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD
(RPCVD), plasma enhanced CVD (PECVD), plating, other suitable
methods, and/or combinations thereof. Subsequently, a metal
chemical mechanical planarization (CMP) process may then be
performed to etch back and planarize the metal layers to form the
first gate 160 and the second gate 165. The first gate 160 and the
second gate 165 may be configured to be coupled to metal
interconnects and may be disposed overlying the gate insulator
layer 120. The first gate 160 and the second gate 165 may include
high-k materials, titanium nitride (TiN), tantalum nitride (TaN),
tantalum carbon (TaC), cobalt silicon (CoSi), zirconium silicon
(ZrSi.sub.2), molybdenum silicon (MoSi.sub.2), tantalum silicon
(TaSi.sub.2), nickel silicon (NiSi.sub.2), tungsten nitride (WN),
titanium aluminum (TiAl), titanium aluminum nitride (TiNAl),
aluminum (Al), titanium (Ti), silver (Ag), tantalum carbon nitride
(TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium
(Zr), ruthenium (Ru), molybdenum (Mo), copper (Cu), tungsten (W),
cobalt (Co), nickel (Ni), titanium carbon (TiC), titanium aluminum
carbon (TiAlC), tantalum aluminum carbon (TaAlC), other suitable
conductive materials, or combinations thereof. The first gate 160
and the second gate 165 may be formed by chemical vapor deposition
(CVD), physical vapor deposition (PVD), plating, or other suitable
processes, and may be followed by a metal CMP process to planarize
the gate structure. The first gate 160 and the second gate 165 may
have a multilayer structure and may be formed in a multiple-step
process.
[0028] The first gate 160 has a top surface 160t and a bottom
surface 160b opposite to each other. The bottom surface 160b faces
the substrate 110. That is, the bottom surface 160b is adjacent to
the gate insulator layer 120. In FIG. 5A, the top surface 160t of
the first gate 160 has an edge 162 facing the dummy structure 136.
The edge 162 is curved toward the top surface 136t of the dummy
structure 136. Furthermore, in FIG. 5B, the first gate 160 has a
side wall 164 facing the dummy structure 136 and the second gate
165. The side wall 164 is an end of the first gate 160. An angle
.theta.1 formed between the bottom surface 160b and the side wall
164 is substantially greater than 90 degrees, i.e., the angle
.theta.1 is an obtuse angle. Therefore, the first gate 160 gets
wider toward the top surface 160t thereof, and gets narrower toward
the bottom surface 160b thereof.
[0029] Moreover, the second gate 165 has a top surface 165t and a
bottom surface 165b opposite to each other. The bottom surface 165b
faces the substrate 110. That is, the bottom surface 165b is
adjacent to the gate insulator layer 120. In FIG. 5A, the top
surface 165t of the second gate 165 has an edge 167 facing the
dummy structure 136. The edge 137 is curved toward the top surface
136t of the dummy structure 136. Furthermore, in FIG. 5B, the
second gate 165 has a side wall 169 facing the dummy structure 136
and the first gate 160. The side wall 169 is an end of the second
gate 165. An angle .theta.2 formed between the bottom surface 165b
and the side wall 169 is substantially greater than 90 degrees,
i.e., the angle .theta.2 is an obtuse angle. Therefore, the second
gate 165 gets wider toward the top surface 165t thereof, and gets
narrower toward the bottom surface 165b thereof.
[0030] Reference is made to FIGS. 6A and 6B. The dummy structure
136 in FIGS. 5A and 5B is removed by an etching back process or
other suitable process. For example, the dummy structure 136 may be
selectively etched thereby forming a gap G between the first gate
160 and the second gate 165. The gap G gets wider toward the
substrate 110. The dummy structure 136 may be removed by a wet etch
process that includes exposure to hydroxide containing solution
(e.g., ammonium hydroxide), deionized water, and/or other suitable
etchant solutions.
[0031] Subsequently, an insulating structure 170 is disposed in the
gap G. For example, an inter-layer dielectric (ILD) (not shown) is
formed over the first gate 160 and the second gate 165 and in the
gap G. In some embodiments, the ILD is formed of an oxide such as
phospho-silicate glass (PSG), boro-silicate glass (BSG),
boron-doped phospho-silicate glass (BPSG), TEOS, or the like. A CMP
process may then be performed to etch back and planarize the ILD to
form the insulating structure 170.
[0032] The insulating structure 170 may be a plug which is
surrounded by two adjacent second dielectric layers 144, the first
gate 160, and the second gate 165. The insulating structure 170 has
a top surface 170t and a bottom surface 170b opposite to each
other. The bottom surface 170b faces the substrate 110. That is,
the bottom surface 170b is adjacent to the gate insulator layer
120. In FIG. 6A, the top surface 170t of the insulating structure
170 has two opposite edges 172a and 172b. The edge 172a faces the
first gate 160, and the edge 172b faces the second gate 165. Both
of the edges 172a and 172b are curved inward the center of the top
surface 170t. Furthermore, in FIG. 6B, an area of the bottom
surface 170b is greater than an area of the top surface 170t. An
angle .theta.3 formed between the bottom surface 170b of the
insulating structure 170 and the side wall 164 of the first gate
160 is substantially less than 90 degrees, i.e., the angle .theta.3
is an acute angle. Another angle .theta.4 formed between the bottom
surface 170b of the insulating structure 170 and the side wall 169
of the second gate 165 is substantially less than 90 degrees, i.e.,
the angle .theta.4 is an acute angle. Therefore, the insulating
structure 170 gets narrower toward the top surface 170t thereof,
and gets wider toward the bottom surface 170b thereof.
[0033] In FIG. 6B, the first gate 160 and the first fins 112 form a
fin field effect transistor (finFET), and the second gate 165 and
the second fins 114 form another finFET. The first gate 160 and the
second gate 165 are isolated by the insulating structure 170. The
structure and the manufacturing method mentioned above can improve
the gate performance in the replacement gate loop process. A
configuration such as this provides a larger distance of gate
electrode line end (i.e., the side wall 164 of the first gate 160
in this case) to gate electrode line end (i.e., the side wall 169
of the second gate 165 in this case), thereby increasing the
process window and reducing leakage. Additionally, configurations
such as these may also provide a larger process window for the
first gate 160 and the second gate 165 filling.
[0034] FIG. 7 is a cross-sectional view of a semiconductor device
in accordance with some embodiments of the present disclosure. The
difference between the semiconductor devices of FIGS. 7 and 6B
pertains to the shapes of the insulating structure 170, the first
gate 160, and the second gate 165. In FIG. 7, the insulating
structure 170 has a top portion 174 and a bottom portion 176. The
bottom portion 176 is disposed between the top portion 174 and the
substrate 110. The top portion 174 has a substantially constant
width, and the width of the bottom portion 176 gets wider toward
the substrate 110. In greater detail, the top portion 174 has a
width Wt, the bottom portion 176 has a width Wb, and the insulating
structure 170 has a width Wm at the interface between the top
portion 174 and the bottom portion 176. In FIG. 7, the width Wt is
substantially equal to the width Wm and substantially shorter than
the width Wb. Furthermore, the side wall 164 adjacent to the top
portion 174 is substantially straight (vertical), and the side wall
164 adjacent to the bottom portion 174 is substantially round. In
other words, the first gate 160 has a substantially round corner
163 facing the insulating structure 170 and the substrate 110.
Moreover, the side wall 169 adjacent to the top portion 174 is
substantially straight (vertical), and the side wall 169 adjacent
to the bottom portion 174 is substantially round. In other words,
the second gate 165 has a substantially round corner 168 facing the
insulating structure 170 and the substrate 110. Other relevant
structural details of the semiconductor device in FIG. 7 are
similar to the semiconductor device in FIG. 6B, and, therefore, a
description in this regard will not be repeated hereinafter.
[0035] FIG. 8 is a cross-sectional view of a semiconductor device
in accordance with some embodiments of the present disclosure. The
difference between the semiconductor devices of FIGS. 8 and 7
pertains to the shapes of the bottom portion 176 of the insulating
structure 170. In FIG. 8, the bottom portion 176 has sharp corners,
and the width Wt is substantially equal to or shorter than the
width Wm and substantially shorter than the width Wb. In greater
detail, an angle .theta.3b formed between the bottom surface 170b
of the insulating structure 170 and the side wall 164 adjacent to
the bottom portion 176 is substantially less than 90 degrees, i.e.,
the angle .theta.3b is an acute angle. Another angle .theta.4b
formed between the bottom surface 170b of the insulating structure
170 and the side wall 169 adjacent to the bottom portion 176 is
substantially less than 90 degrees, i.e., the angle .theta.4b is an
acute angle. Furthermore, an angle .theta.3t formed between the top
surface 170t of the insulating structure 170 and the side wall 164
adjacent to the top portion 174 is greater than the angle
.theta.3b. Another angle .theta.4t formed between the bottom
surface 170b of the insulating structure 170 and the side wall 169
adjacent to the top portion 174 is greater than the angle
.theta.4b. Moreover, the height Hb of the bottom portion 176 of the
insulating structure 170 satisfies 0<Hb<200 nm. Other
relevant structural details of the semiconductor device in FIG. 8
are similar to the semiconductor device in FIG. 7, and, therefore,
a description in this regard will not be repeated hereinafter.
[0036] FIG. 9 is a cross-sectional view of a semiconductor device
in accordance with some embodiments of the present disclosure. The
difference between the semiconductor devices of FIGS. 9 and 8
pertains to the shapes of the top portion 174 and the bottom
portion 176 of the insulating structure 170. In FIG. 8, the width
Wt is substantially equal to or shorter than the width Wm and
substantially shorter than the width Wb. In greater detail, an
angle .theta.3b formed between the bottom surface 170b of the
insulating structure 170 and the side wall 164 adjacent to the
bottom portion 176 is about 80 degrees to about 90 degrees. Another
angle .theta.3b formed between the bottom surface 170b of the
insulating structure 170 and the side wall 169 adjacent to the
bottom portion 176 is about 80 degrees to about 90 degrees.
Furthermore, an angle .theta.3t formed between the top surface 170t
of the insulating structure 170 and the side wall 164 adjacent to
the top portion 174 is shorter than or equal to the angle
.theta.3b. Another angle .theta.4t formed between the bottom
surface 170b of the insulating structure 170 and the side wall 169
adjacent to the top portion 174 is shorter than or equal to the
angle .theta.4b. Moreover, the height Hb of the bottom portion 176
of the insulating structure 170 satisfies 0<Hb<200 nm. Other
relevant structural details of the semiconductor device in FIG. 9
are similar to the semiconductor device in FIG. 8, and, therefore,
a description in this regard will not be repeated hereinafter.
[0037] Moreover, the manufacturing methods of FIGS. 7-9 are similar
to the manufacturing method of FIG. 6B. The formation methods of
the first trench and the second trench in FIGS. 7-9 can be similar
to or different from the formation method mentioned in FIGS. 3A and
3B. The profile of the first trench and the second trench (and also
the first gate 160, the second gate 165, and the insulating
structure 170) can be modified using different etching method and
etching recipes.
[0038] As mentioned above, in FIGS. 3A and 3B, the dummy layer 130
is patterned to form the first trench 132 and the second trench
134. Therefore, the aperture of the first trench 132 near the top
surface 136t of the dummy structure 136 is greater than the
aperture of the first trench 132 near the bottom surface 136b of
the dummy structure 136, and the aperture of the second trench 134
near the top surface 136t of the dummy structure 136 is greater
than the aperture of the second trench 134 near the bottom surface
136b of the dummy structure 136. With this configuration, the first
gate 160 of FIG. 5B is easy to fill in the first trench 132 without
leaving a space between the first gate 160 and the substrate 110.
Also, the second first gate 165 of FIG. 5B is easy to fill in the
second trench 134 without leaving a space between the second gate
165 and the substrate 110. Hence, the electrical performance of the
first gate 160 and the second gate 165 can be improved.
[0039] According to some embodiments of the present disclosure, a
semiconductor device includes a substrate, a first gate, a second
gate, and an insulating structure. The substrate includes a first
fin and a second fin. The first gate is disposed over the first
fin. The second gate is disposed over the second fin. A gap is
formed between the first gate and the second gate, and the gap gets
wider toward the substrate. The insulating structure is disposed in
the gap. The insulating structure has a top surface and a bottom
surface opposite to each other. The bottom surface faces the
substrate. An edge of the top surface facing the first gate is
curved inward the top surface.
[0040] According to some embodiments of the present disclosure, a
semiconductor device includes a substrate, a first gate, a second
gate, and an insulating structure. The substrate includes a first
fin and a second fin. The first gate is disposed over the first
fin. The second gate is disposed over the second fin and separated
from the first gate. The insulating structure is disposed between
the first gate and the second gate. The insulating structure has a
top surface and a bottom surface opposite to each other. The bottom
surface of the insulating structure faces the substrate. An area of
the bottom surface of the insulating structure is greater than an
area of the top surface of the insulating structure. An edge of the
top surface of the insulating structure facing the first gate is
curved inward the top surface.
[0041] According to some embodiments of the present disclosure, a
method for manufacturing a semiconductor device includes providing
a substrate including a first fin and a second fin. A dummy layer
is formed over the substrate to cover the first fin and the second
fin. The dummy layer is patterned to form a dummy structure between
the first fin and the second fin and expose the first fin and the
second fin. A first gate and a second gate are respectively formed
at opposite sides of the dummy structure. The first gate covers the
first fin, and the second gate covers the second fin. The dummy
structure is removed to form a gap between the first gate and the
second gate. An insulating structure is formed in the gap.
[0042] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *