U.S. patent application number 14/423758 was filed with the patent office on 2016-08-25 for tft array substrate.
This patent application is currently assigned to Shenzhen China Star Optoelectronics Technology Co., Ltd.. The applicant listed for this patent is SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.. Invention is credited to Caiqin CHEN, Jehao HSU.
Application Number | 20160247822 14/423758 |
Document ID | / |
Family ID | 52159053 |
Filed Date | 2016-08-25 |
United States Patent
Application |
20160247822 |
Kind Code |
A1 |
CHEN; Caiqin ; et
al. |
August 25, 2016 |
TFT ARRAY SUBSTRATE
Abstract
The present invention provides a thin-film transistor (TFT)
array substrate. The TFT array substrate is structured to change
the way that sub-pixels are arranged so that during a displaying
period of a frame of image, the sub-pixels that have inconsistent
brightness/darkness become alternate with each other spatially so
that a displaying defect of vertical bright/dark lines can be
improved and the overall resistance of the data line can be reduced
to thereby reduce resistance-capacitance delay and prevent
incorrect charging at a tail end of a scan line or a data line.
Inventors: |
CHEN; Caiqin; (Shenzhen,
Guangdong, CN) ; HSU; Jehao; (Shenzhen, Guangdong,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. |
Shenzhen, Guangdong |
|
CN |
|
|
Assignee: |
Shenzhen China Star Optoelectronics
Technology Co., Ltd.
Shenzhen, Guangdong
CN
|
Family ID: |
52159053 |
Appl. No.: |
14/423758 |
Filed: |
November 5, 2014 |
PCT Filed: |
November 5, 2014 |
PCT NO: |
PCT/CN2014/090284 |
371 Date: |
February 25, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G09G 3/3677 20130101;
G09G 2320/0223 20130101; G09G 3/3275 20130101; G02F 1/136286
20130101; G09G 3/3266 20130101; H01L 27/124 20130101; G09G
2310/0278 20130101; G09G 3/3659 20130101; G09G 3/3614 20130101;
G09G 3/3688 20130101; G09G 2300/0809 20130101 |
International
Class: |
H01L 27/12 20060101
H01L027/12; G09G 3/3275 20060101 G09G003/3275; G09G 3/36 20060101
G09G003/36; G09G 3/3266 20060101 G09G003/3266 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 22, 2014 |
CN |
201410568875.1 |
Claims
1. A thin-film transistor (TFT) array substrate, comprising: a
plurality of data lines, a plurality of scan lines, and a plurality
of sub-pixels arranged in an array; in each row of the sub-pixels,
the sub-pixels of odd columns and the sub-pixels of even columns
being staggered laterally on a plane; each of the data lines being
electrically connected to two sub-pixels of each of the sub-pixel
rows that are located on left side and right side of the data line
respectively by TFTs and supplying data signals to the two
sub-pixels; two scan lines being provided, corresponding to and
located at upper and lower sides of each of the sub-pixel rows; the
nth scan line and the (n')th scan line being respectively located
on the upper and lower sides of the nth sub-pixel row; the (n+1)th
scan line and the (n'+1)th scan line being respectively located on
the upper and lower sides of the (n+1)th sub-pixel row, n being a
positive integer, so that the nth sub-pixel row and the (n+1)th
sub-pixel row collectively form a repeatable circuit formation
unit; the nth scan line being electrically connected via TFTs to
and driving the sub-pixels of even columns in the nth sub-pixel row
and the (n')th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the nth sub-pixel row;
and the (n+1)th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the (n+1)th sub-pixel
row and the (n'+1)th scan line being electrically connected via
TFTs to and driving the sub-pixels of even columns in the (n+1)th
sub-pixel row; whereby in the nth sub-pixel row, the sub-pixels of
even columns are driven earlier than the sub-pixels of odd columns
and in the (n+1)th sub-pixel row, the sub-pixels of even columns
are driven later than the sub-pixels of odd columns.
2. The TFT array substrate as claimed in claim 1, wherein the data
lines are driven in a manner of reversing polarity for every two
dots.
3. The TFT array substrate as claimed in claim 1, wherein during a
display period of a frame of image, in each row of the sub-pixels,
the nth sub-pixel row and the (n+1)th sub-pixel row show an
arrangement of alternating darkness and brightness.
4. A thin-film transistor (TFT) array substrate, comprising: a
plurality of data lines, a plurality of scan lines, and a plurality
of sub-pixels arranged in an array; in each row of the sub-pixels,
the sub-pixels of odd columns and the sub-pixels of even columns
being staggered laterally on a plane; each of the data lines being
electrically connected to two sub-pixels of each of the sub-pixel
rows that are located on left side and right side of the data line
respectively by TFTs and supplying data signals to the two
sub-pixels; two scan lines being provided, corresponding to and
located at upper and lower sides of each sub-pixel row; the nth
scan line and the (n')th scan line being respectively located on
the upper and lower sides of the nth sub-pixel row; the (n+1)th
scan line and the (n'+1)th scan line being respectively located on
the upper and lower sides of the (n+1)th sub-pixel row; the (n+2)th
scan line and the (n'+2)th scan line being respectively located on
the upper and lower sides of the (n+2)th sub-pixel row; and the
(n+3)th scan line and the (n'+3)th scan line being respectively
located on the upper and lower sides of the (n+3)th sub-pixel row,
n being a positive integer, so that the nth sub-pixel row, the
(n+1)th sub-pixel row, the (n+2)th sub-pixel row, and the (n+3)th
sub-pixel row collectively form a repeatable circuit formation
unit; the nth scan line being electrically connected via TFTs to
and driving the sub-pixels of even columns in the nth sub-pixel row
and the (n')th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the nth sub-pixel row;
the (n+1)th scan line being electrically connected via TFTs to and
driving the sub-pixels of even columns in the (n+1)th sub-pixel row
and the (n'+1)th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the (n+1)th sub-pixel
row; the (n+2)th scan line being electrically connected via TFTs to
and driving the (n+2)th the sub-pixels of odd columns in sub-pixel
row and the (n'+2)th scan line being electrically connected via
TFTs to and driving the sub-pixels of even columns of the (n+2)th
sub-pixel row; and the (n+3)th scan line being electrically
connected via TFTs to and driving the sub-pixels of odd columns of
the (n+3)th sub-pixel row and the (n'+3)th scan line being
electrically connected via TFTs to and driving the sub-pixels of
even columns of the (n+3)th sub-pixel row; whereby in the nth and
(n+1)th sub-pixel rows, the sub-pixels of even columns are driven
earlier than the sub-pixels of odd columns; and in the (n+2)th and
(n+3)th sub-pixel rows, the sub-pixels of even columns are driven
later than the sub-pixels of odd columns.
5. The TFT array substrate as claimed in claim 4, wherein the data
lines are driven in a manner of reversing polarity for every two
dots.
6. The TFT array substrate as claimed in claim 4, wherein during a
display period of a frame of image, in each row of the sub-pixels,
the nth and (n+1)th sub-pixel rows and the (n+2)th and (n+3)th
sub-pixel rows show an arrangement of alternating darkness and
brightness.
7. A thin-film transistor (TFT) array substrate, comprising: a
plurality of data lines, a plurality of scan lines, and a plurality
of sub-pixels arranged in an array; in each row of the sub-pixels,
the sub-pixels of odd columns and the sub-pixels of even columns
being staggered laterally on a plane; each of the data lines being
electrically connected to two sub-pixels of each of the sub-pixel
rows that are located on left side and right side of the data line
respectively by TFTs and supplying data signals to the two
sub-pixels; two scan lines being provided, corresponding to and
located at upper and lower sides of each of the sub-pixel rows; the
nth scan line and the (n')th scan line being respectively located
on the upper and lower sides of the nth sub-pixel row; the (n+1)th
scan line and the (n'+1)th scan line being respectively located on
the upper and lower sides of the (n+1)th sub-pixel row, n being a
positive integer, so that the nth sub-pixel row and the (n+1)th
sub-pixel row collectively form a repeatable circuit formation
unit; the nth scan line being electrically connected via TFTs to
and driving the sub-pixels of even columns in the nth sub-pixel row
and the (n')th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the nth sub-pixel row;
and the (n+1)th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the (n+1)th sub-pixel
row and the (n'+1)th scan line being electrically connected via
TFTs to and driving the sub-pixels of even columns in the (n+1)th
sub-pixel row; whereby in the nth sub-pixel row, the sub-pixels of
even columns are driven earlier than the sub-pixels of odd columns
and in the (n+1)th sub-pixel row, the sub-pixels of even columns
are driven later than the sub-pixels of odd columns; wherein the
data line are driven in a manner of reversing polarity for every
two dots; and wherein during a display period of a frame of image,
in each row of the sub-pixels, the nth sub-pixel row and the
(n+1)th sub-pixel row show an arrangement of alternating darkness
and brightness.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to the field of displaying
technology, and in particular to a TFT (Thin-Film Transistor) array
substrate.
[0003] 2. The Related Arts
[0004] In the field of displaying technology, flat panel displays,
such as liquid crystal displays (LCDs) and organic light-emitting
diodes (OLEDs) have gradually taken the place of cathode ray tube
(CRT) displays for wide applications in liquid crystal televisions,
mobile phones, personal digital assistants (PDAs), digital cameras,
computer monitors, and notebook computer screens.
[0005] A display panel is a major component of the LCDs and OLEDs.
Both the LCD display panels and the OLED display panels comprise a
thin-film transistor (TFT) array substrate. The TFT array substrate
comprises a plurality of red (R), green (G), and blue (B)
sub-pixels arranged in an array and a plurality of scan lines and a
plurality of data lines. Each of the sub-pixels receives a scan
signal from a corresponding scan line and a data signal from a
corresponding data line in order to display an image.
[0006] FIG. 1 is a schematic view showing a conventional TFT array
substrate. The conventional TFT array substrate comprises a
plurality of vertical data lines that is arranged in order and
parallel to each other, such as D1, D2, D3, D4, D5 and so on, and a
plurality of horizontal scan line that is arranged in order and
parallel to each other, such as G1, G2, G3, G4, G5 and so on, and
sub-pixels that are arranged in an array. The sub-pixels that are
arranged on the same row are each electrically connected via a TFT
to the scan line located above the row of sub-pixels. For example,
each of the sub-pixels that constitute a first row is electrically
connected via a TFT to the scan line G1; each of the sub-pixels
that constitute a second row is electrically connected via a TFT to
the scan line G2; and so on. The sub-pixels that are arranged on
the same column is electrically connected via a TFT to the data
line located leftward of the column of sub-pixels. For example,
each of the sub-pixels that constitute a first column is
electrically connected via a TFT to the data line D1; each of the
sub-pixels that constitute a second column is electrically
connected via a TFT to the data line D2; and so on.
[0007] FIG. 2 is a schematic view showing a conventional data line
share (DLS) TFT array substrate. The DLS TFT array substrate
comprises data lines each corresponding two columns of sub-pixels
and two scan lines respectively arranged above and below each row
of sub-pixels. For sub-pixels of each row, a sub-pixel of an even
column and a sub-pixel of an odd-column that are respectively
located on left and right sides of each data line are each
electrically connected by a TFT to the data line, namely sharing
the same data line. Also, for sub-pixels of each row, each of the
sub-pixels of even columns is electrically connected by a TFT to
the scan line above the row of the sub-pixels and each of the
sub-pixels of odd columns is electrically connected by a TFT to the
scan line below the row of the sub-pixels. For example, a second
row and a third row of sub-pixels share the data line D2; a fourth
row and a fifth row of sub-pixels share data line D3, and so on.
Each of the sub-pixels of the first row that are in even columns is
electrically connected by a TFT to the scan line G1 above the first
row of sub-pixels and each of the sub-pixels of the first row that
are in odd columns is electrically connected by a TFT to the scan
line G2 below the first row of sub-pixels; each of the sub-pixels
of the second row that are in even columns is electrically
connected by a TFT to the scan line G3 above the second row of
sub-pixels and each of the sub-pixels of the second row that are in
odd columns is electrically connected by a TFT to the scan line G4
below the second row of sub-pixels, and so on. Compared to the
traditional TFT array substrate shown in FIG. 1, the DLS TFT array
substrate allows for reduction of the number of data lines by half
and thus reduction of the cost; however, the number of scan lines
is doubled so that the charging time that each sub-pixel may have
is reduced by half due to the doubled number of scan lines and thus
delays of signals in the corresponding data lines and scan lines
would be more prominent. For example, at a tail end of a data line
(or a scan line), the delay in the data line (or the scan line)
could cause difference in charging rates between sub-pixels of the
odd row and the sub-pixel of the even rows, and consequently,
display defects of vertical bright and dark lines may result.
[0008] Specifically, reference is now made collectively to FIGS. 2,
3, and 4. As shown in FIG. 4, the manner of driving data lines is
that polarity is reversed for every two dots. Due to RC delay, the
data signals are not ideal square waves and the wave forms of the
actual signals are wave forms with curved edges as shown in FIG. 3.
For a specific sub-pixel Pxy, where x indicates the x-th row and y
indicates the y-th column, such as sub-pixel P12 shown in FIG. 2
indicating a sub-pixel of the second column in the first row, when
scan lines G1, G2, G3, and G4 are sequentially conducted on, the
odd-column sub-pixels that are connected a data line are
sequentially driven earlier than the odd-column sub-pixels. For
example, sub-pixels P12, P13, P22, P23 that are connected to the
data line D2 are driven in that sequence. In the period of the same
polarity of the data signal, the sub-pixel that is driven later is
better charged than that driven earlier. As such, P13 is better
charged than P12 and P23 is better charged than P22. After the
reverse of polarity of the data signal, the driving sequence
maintains the same, namely the odd-column sub-pixels are driven
first and then the odd-column sub-pixels are driven. As such, the
even-column sub-pixels that are driven first may suffer being
insufficiently charged so that the site corresponding to the
even-column sub-pixels become insufficiently bright, making the
overall displaying effect showing a defect of vertical bright and
dark lines.
SUMMARY OF THE INVENTION
[0009] An object of the present invention is to provide a thin-film
transistor (TFT) array substrate, wherein within a displaying
period of a frame of image, the sub-pixels that have inconsistent
brightness/darkness are alternate with each other spatially so that
a displaying defect of vertical bright/dark lines is improved and
since the overall resistance of a data line is reduced,
resistance-capacitance delay is reduced so as to prevent incorrect
charging at a tail end of a scan line or a data line.
[0010] To achieve the above object, the present invention provides
a TFT array substrate, which comprises: a plurality of data lines,
a plurality of scan lines, and a plurality of sub-pixels arranged
in an array;
[0011] in each row of the sub-pixels, the sub-pixels of odd columns
and the sub-pixels of even columns being staggered laterally on a
plane;
[0012] each of the data lines being electrically connected to two
sub-pixels of each of the sub-pixel rows that are located on left
side and right side of the data line respectively by TFTs and
supplying data signals to the two sub-pixels;
[0013] two scan lines being provided, corresponding to and located
at upper and lower sides of each of the sub-pixel rows; the nth
scan line and the (n')th scan line being respectively located on
the upper and lower sides of the nth sub-pixel row; the (n+1)th
scan line and the (n'+1)th scan line being respectively located on
the upper and lower sides of the (n+1)th sub-pixel row, n being a
positive integer, so that the nth sub-pixel row and the (n+1)th
sub-pixel row collectively form a repeatable circuit formation
unit;
[0014] the nth scan line being electrically connected via TFTs to
and driving the sub-pixels of even columns in the nth sub-pixel row
and the (n')th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the nth sub-pixel row;
and the (n+1)th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the (n+1)th sub-pixel
row and the (n'+1)th scan line being electrically connected via
TFTs to and driving the sub-pixels of even columns in the (n+1)th
sub-pixel row; whereby in the nth sub-pixel row, the sub-pixels of
even columns are driven earlier than the sub-pixels of odd columns
and in the (n+1)th sub-pixel row, the sub-pixels of even columns
are driven later than the sub-pixels of odd columns.
[0015] The data lines are driven in a manner of reversing polarity
for every two dots.
[0016] During a display period of a frame of image, in each row of
the sub-pixels, the nth sub-pixel row and the (n+1)th sub-pixel row
show an arrangement of alternating darkness and brightness.
[0017] A TFT array substrate comprises: a plurality of data lines,
a plurality of scan lines, and a plurality of sub-pixels arranged
in an array;
[0018] in each row of the sub-pixels, the sub-pixels of odd columns
and the sub-pixels of even columns being staggered laterally on a
plane;
[0019] each of the data lines being electrically connected to two
sub-pixels of each of the sub-pixel rows that are located on left
side and right side of the data line respectively by TFTs and
supplying data signals to the two sub-pixels;
[0020] two scan lines being provided, corresponding to and located
at upper and lower sides of each sub-pixel row; the nth scan line
and the (n')th scan line being respectively located on the upper
and lower sides of the nth sub-pixel row; the (n+1)th scan line and
the (n'+1)th scan line being respectively located on the upper and
lower sides of the (n+1)th sub-pixel row; the (n+2)th scan line and
the (n'+2)th scan line being respectively located on the upper and
lower sides of the (n+2)th sub-pixel row; and the (n+3)th scan line
and the (n'+3)th scan line being respectively located on the upper
and lower sides of the (n+3)th sub-pixel row, n being a positive
integer, so that the nth sub-pixel row, the (n+1)th sub-pixel row,
the (n+2)th sub-pixel row, and the (n+3)th sub-pixel row
collectively form a repeatable circuit formation unit;
[0021] the nth scan line being electrically connected via TFTs to
and driving the sub-pixels of even columns in the nth sub-pixel row
and the (n')th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the nth sub-pixel row;
the (n+1)th scan line being electrically connected via TFTs to and
driving the sub-pixels of even columns in the (n+1)th sub-pixel row
and the (n'+1)th scan line being electrically connected via TFTs to
and driving the sub-pixels of odd columns in the (n+1)th sub-pixel
row; the (n+2)th scan line being electrically connected via TFTs to
and driving the (n+2)th the sub-pixels of odd columns in sub-pixel
row and the (n'+2)th scan line being electrically connected via
TFTs to and driving the sub-pixels of even columns of the (n+2)th
sub-pixel row; and the (n+3)th scan line being electrically
connected via TFTs to and driving the sub-pixels of odd columns of
the (n+3)th sub-pixel row and the (n'+3)th scan line being
electrically connected via TFTs to and driving the sub-pixels of
even columns of the (n+3)th sub-pixel row; whereby in the nth and
(n+1)th sub-pixel rows, the sub-pixels of even columns are driven
earlier than the sub-pixels of odd columns; and in the (n+2)th and
(n+3)th sub-pixel rows, the sub-pixels of even columns are driven
later than the sub-pixels of odd columns.
[0022] The data lines are driven in a manner of reversing polarity
for every two dots.
[0023] During a display period of a frame of image, in each row of
the sub-pixels, the nth and (n+1)th sub-pixel rows and the (n+2)th
and (n+3)th sub-pixel rows show an arrangement of alternating
darkness and brightness.
[0024] The efficacy of the present invention is that the present
invention provides a TFT array substrate, which changes the way
that sub-pixels are arranged so that during a displaying period of
a frame of image, the sub-pixels that have inconsistent
brightness/darkness become alternate with each other spatially so
that a displaying defect of vertical bright/dark lines can be
improved and the overall resistance of the data line can be reduced
to thereby reduce resistance-capacitance delay and prevent
incorrect charging at a tail end of a scan line or a data line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The technical solution, as well as other beneficial
advantages, of the present invention will become apparent from the
following detailed description of an embodiment of the present
invention, with reference to the attached drawings.
[0026] In the drawings:
[0027] FIG. 1 is a schematic view showing a structure of a
conventional thin-film transistor (TFT) array substrate;
[0028] FIG. 2 is a schematic view showing a structure of a
conventional data line share (DLS) TFT array substrate;
[0029] FIG. 3 is a view illustrating wave forms of data signals of
FIG. 2;
[0030] FIG. 4 is a schematic view illustrating two dots polarity
reverse for a data line driving method of the DLS TFT array
substrate;
[0031] FIG. 5 is a schematic view showing a TFT array substrate
according to a first embodiment of the present invention;
[0032] FIG. 6 is a schematic view showing a TFT array substrate
according to a second embodiment of the present invention;
[0033] FIG. 7 is a schematic view illustrating the distribution of
brightness and darkness of sub-pixels of the TFT array substrate
according to the first embodiment of the present invention; and
[0034] FIG. 8 is a schematic view illustrating the distribution of
brightness and darkness of sub-pixels of the TFT array substrate
according to the second embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0035] To further expound the technical solution adopted in the
present invention and the advantages thereof, a detailed
description is given to a preferred embodiment of the present
invention and the attached drawings.
[0036] Referring to FIG. 5, a schematic view is given to illustrate
a thin-film transistor (TFT array substrate) according to a first
embodiment of the present invention. The TFT array substrate
comprises: a plurality of data lines, such as D1, D2, D3, D4, a
plurality of scan lines, and a plurality of sub-pixels arranged in
an array.
[0037] In each row of the sub-pixels, the sub-pixels of odd columns
and the sub-pixels of even columns are staggered laterally on a
plane.
[0038] Each of the data lines is electrically connected to two
sub-pixels of each sub-pixel row that are located on left side and
right side of the data line respectively by TFTs and supplies data
signals to the two sub-pixels.
[0039] Two scan lines are provided, corresponding to and located at
upper and lower sides of each sub-pixel row. The nth scan line G(n)
and the (n')th scan line G(n') are respectively located on the
upper and lower sides of the nth sub-pixel row P(n); the (n+1)th
scan line G(n+1) and the (n'+1)th scan line G(n'+1) are
respectively located on the upper and lower sides of the (n+1)th
sub-pixel row P(n+1), n being a positive integer, so that the nth
sub-pixel row P(n) and the (n+1)th sub-pixel row P(n+1)
collectively form a repeatable circuit formation unit, namely the
entirety of a circuit being formed by repeatedly arranging the
circuit formation unit. For example, the first sub-pixel row and
the second sub-pixel row form a circuit formation unit and the
third and fourth sub-pixel rows form a repeatable circuit formation
unit, and so on.
[0040] The nth scan line G(n) is electrically connected via TFTs to
and drives the sub-pixels of even columns in the nth sub-pixel row
P(n) and the (n')th scan line G(n') is electrically connected via
TFTs to and drives the sub-pixels of odd columns in the nth
sub-pixel row P(n); and the (n+1)th scan line G(n+1) is
electrically connected via TFTs to and drives the sub-pixels of odd
columns in the (n+1)th sub-pixel row P(n+1) and the (n'+1)th scan
line G(n'+1) is electrically connected via TFTs to and drives the
sub-pixels of even columns in the (n+1)th sub-pixel row P(n+1).
[0041] When the scan lines are sequentially turned on from top to
bottom, the sub-pixels of even columns in the nth sub-pixel row
P(n) are driven earlier than the sub-pixels of odd columns so that
the sub-pixels of odd columns of the nth sub-pixel row are provided
with a better effect of charging than the sub-pixels of even
columns, whereby the sub-pixels of odd columns in the nth sub-pixel
row become brighter while the sub-pixels of even columns are
darker; and in the (n+1)th sub-pixel row P(n+1), the sub-pixels of
even columns are driven later than the sub-pixels of odd columns so
that the sub-pixels of even columns of the (n+1)th sub-pixel row
are provided with a better effect of charging than the sub-pixels
of odd columns, whereby the sub-pixels of odd columns in the
(n+1)th sub-pixel row become darker while the sub-pixels of even
columns are brighter.
[0042] The data lines are driven in a manner of reversing polarity
for every two dots. After the reverse of polarity of the data
signals, the driving sequence remains unchanged so that eventually,
during the displaying period of a frame of image, in each row of
the sub-pixels, the nth sub-pixel row P(n) and the (n+1)th
sub-pixel row P(n+1) show an arrangement of alternating "dark" and
"bright", as shown in FIG. 7. In view of the overall displaying
effect, the sub-pixels that have inconsistent brightness/darkness
become alternate with each other spatially so that a displaying
defect of vertical bright/dark lines can be improved. Further, the
overall resistance of the data line can be reduced to thereby
reduce resistance-capacitance delay and prevent incorrect charging
at a tail end of a scan line or a data line.
[0043] Referring to FIG. 6, a schematic view is given to illustrate
a TFT array substrate according to a second embodiment of the
present invention. The TFT array substrate comprises: a plurality
of data lines, a plurality of scan lines, and a plurality of
sub-pixels arranged in an array.
[0044] In each row of the sub-pixels, the sub-pixels of odd columns
and the sub-pixels of even columns are staggered laterally on a
plane.
[0045] Each of the data lines is electrically connected to two
sub-pixels of each sub-pixel row that are located on left side and
right side of the data line respectively by TFTs and supplies data
signals to the two sub-pixels.
[0046] Two scan lines are provided, corresponding to and located at
upper and lower sides of each sub-pixel row. The nth scan line G(n)
and the (n')th scan line G(n') are respectively located on the
upper and lower sides of the nth sub-pixel row P(n); the (n+1)th
scan line G(n+1) and the (n'+1)th scan line G(n'+1) are
respectively located on the upper and lower sides of the (n+1)th
sub-pixel row P(n+1); the (n+2)th scan line G(n+2) and the (n'+2)th
scan line G(n'+2) are respectively located on the upper and lower
sides of the (n+2)th sub-pixel row P(n+2); and the (n+3)th scan
line G(n+3) and the (n'+3)th scan line G(n'+3) are respectively
located on the upper and lower sides of the (n+3)th sub-pixel row
P(n+3), n being a positive integer, so that the nth sub-pixel row
P(n), the (n+1)th sub-pixel row P(n+1), the (n+2)th sub-pixel row
P(n+2), and the (n+3)th sub-pixel row P(n+3) collectively form a
repeatable circuit formation unit, namely the entirety of a circuit
being formed by repeatedly arranging the circuit formation unit.
For example, the first, second, third, and fourth sub-pixel rows
form a circuit formation unit and the fifth, sixth, seventh, and
eighth sub-pixel rows form a repeatable circuit formation unit, and
so on.
[0047] The nth scan line G(n) is electrically connected via TFTs to
and drives the sub-pixels of even columns in the nth sub-pixel row
P(n) and the (n')th scan line G(n') is electrically connected via
TFTs to and drives the sub-pixels of odd columns in the nth
sub-pixel row P(n); the (n+1)th scan line G(n+1) is electrically
connected via TFTs to and drives the sub-pixels of even columns in
the (n+1)th sub-pixel row P(n+1) and the (n'+1)th scan line G(n'+1)
is electrically connected via TFTs to and drives the sub-pixels of
odd columns in the (n+1)th sub-pixel row P(n+1); the (n+2)th scan
line G(n+2) is electrically connected via TFTs to and drives the
(n+2)th the sub-pixels of odd columns in sub-pixel row P(n+2) and
the (n'+2)th scan line G(n'+2) is electrically connected via TFTs
to and drives the sub-pixels of even columns of the (n+2)th
sub-pixel row P(n+2); and the (n+3)th scan line G(n+3) is
electrically connected via TFTs to and drives the sub-pixels of odd
columns of the (n+3)th sub-pixel row P(n+3) and the (n'+3)th scan
line G(n'+3) is electrically connected via TFTs to and drives the
sub-pixels of even columns of the (n+3)th sub-pixel row P(n+3).
[0048] When the scan lines are sequentially turned on from top to
bottom, the sub-pixels of even columns in the nth and (n+1)th
sub-pixel rows P(n), P(n+1) are driven earlier than the sub-pixels
of odd columns so that the sub-pixels of odd columns of the nth and
(n+1)th sub-pixel rows are provided with a better effect of
charging than the sub-pixels of even columns, whereby the
sub-pixels of odd columns in the nth and (n+1)th sub-pixel rows
become brighter while the sub-pixels of even columns are darker;
and in the (n+2)th and (n+3)th sub-pixel rows P(n+2), P(n+3), the
sub-pixels of even columns are driven later than the sub-pixels of
odd columns so that the sub-pixels of even columns of the (n+2)th
and (n+3)th sub-pixel rows are provided with a better effect of
charging than the sub-pixels of odd columns, whereby the sub-pixels
of odd columns in the (n+2)th and (n+3)th sub-pixel rows become
darker while the sub-pixels of even columns are brighter.
[0049] The data lines are driven in a manner of reversing polarity
for every two dots. After the reverse of polarity of the data
signals, the driving sequence remains unchanged so that eventually,
during the displaying period of a frame of image, the nth and
(n+1)th sub-pixel rows P(n), P(n+1) and the (n+2)th and (n+3)th
sub-pixel rows P(n+2), P(n+3) show an arrangement of alternating
"dark" and "bright", as shown in FIG. 8. In view of the overall
displaying effect, the sub-pixels that have inconsistent
brightness/darkness become alternate with each other spatially so
that a displaying defect of vertical bright/dark lines can be
improved. Further, the overall resistance of the data line can be
reduced to thereby reduce resistance-capacitance delay and prevent
incorrect charging at a tail end of a scan line or a data line.
[0050] In summary, the present invention provides a TFT array
substrate, which changes the way that sub-pixels are arranged so
that during a displaying period of a frame of image, the sub-pixels
that have inconsistent brightness/darkness become alternate with
each other spatially so that a displaying defect of vertical
bright/dark lines can be improved and the overall resistance of the
data line can be reduced to thereby reduce resistance-capacitance
delay and prevent incorrect charging at a tail end of a scan line
or a data line.
[0051] Based on the description given above, those having ordinary
skills of the art may easily contemplate various changes and
modifications of the technical solution and technical ideas of the
present invention and all these changes and modifications are
considered within the protection scope of right for the present
invention.
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