U.S. patent application number 15/099662 was filed with the patent office on 2016-08-11 for nitride power transistor and manufacturing method thereof.
The applicant listed for this patent is ENKRIS SEMICONDUCTOR, INC.. Invention is credited to Kai CHENG.
Application Number | 20160233329 15/099662 |
Document ID | / |
Family ID | 49933480 |
Filed Date | 2016-08-11 |
United States Patent
Application |
20160233329 |
Kind Code |
A1 |
CHENG; Kai |
August 11, 2016 |
NITRIDE POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF
Abstract
A nitride power transistor comprises: a silicon substrate
comprising a differently doped semiconductor composite structure
for forming a space charge depletion region; and a nitride
epitaxial layer located on the silicon substrate. With introduction
of a differently doped semiconductor composite structure for
forming a space charge depletion region inside a silicon substrate
of a nitride power transistor, the nitride power transistor is
capable of withstanding a relatively high external voltage, and
thus a breakdown voltage of the device is improved.
Inventors: |
CHENG; Kai; (Suzhou,
CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
ENKRIS SEMICONDUCTOR, INC. |
Suzhou |
|
CN |
|
|
Family ID: |
49933480 |
Appl. No.: |
15/099662 |
Filed: |
April 15, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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PCT/CN2014/071352 |
Jan 24, 2014 |
|
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15099662 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/7787 20130101;
H01L 29/66462 20130101; H01L 29/2003 20130101; H01L 21/02573
20130101; H01L 29/7786 20130101; H01L 29/0634 20130101; H01L
21/02381 20130101; H01L 29/0611 20130101; H01L 21/0254 20130101;
H01L 29/7783 20130101 |
International
Class: |
H01L 29/778 20060101
H01L029/778; H01L 21/02 20060101 H01L021/02; H01L 29/06 20060101
H01L029/06; H01L 29/20 20060101 H01L029/20; H01L 29/66 20060101
H01L029/66 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 15, 2013 |
CN |
201310482335.7 |
Claims
1. A nitride power transistor, comprising: a silicon substrate
comprising a differently doped semiconductor composite structure
for forming a space charge depletion region; and a nitride
epitaxial layer located on the silicon substrate.
2. The nitride power transistor according to claim 1, wherein the
semiconductor composite structure is a multi-level structure formed
by transversely alternating n-type semiconductor and p-type
semiconductor.
3. The nitride power transistor according to claim 2, wherein a
longitudinal section of the semiconductor composite structure has
one of a longitudinal vertical arrangement, a triangular
arrangement and a square arrangement or any combination thereof, a
cross section of the semiconductor composite structure has one of a
longitudinal alternating grid arrangement, a longitudinal
alternating triangular arrangement, a longitudinal alternating
polygonal arrangement and a longitudinal alternating circular
arrangement or any combination thereof, and the semiconductor
composite structure occupies the entire silicon substrate in a
transverse direction.
4. The nitride power transistor according to claim 2, wherein a
height of the n-type semiconductor and the p-type semiconductor of
the semiconductor composite structure is more than 5 nm.
5. The nitride power transistor according to claim 2, wherein
doping concentration and doping distribution of each layer of the
silicon substrate and the semiconductor composite structure in the
silicon substrate includes light doping, graded doping, heavy
doping or any combination thereof.
6. The nitride power transistor according to claim 1, wherein the
semiconductor composite structure is located at a top layer of the
silicon substrate, in the middle of the silicon substrate, or at a
bottom of the silicon substrate, or any combination thereof.
7. The nitride power transistor according to claim 1, wherein
semiconductor in the semiconductor doped multilayer structure is
any one selected from silicon, germanium, germanium silicon,
silicon carbide, III-V compound, or any combination thereof.
8. The nitride power transistor according to claim 1, further
comprising a nitride epitaxial layer disposed on the nitride
channel layer, wherein two-dimensional electron gas is formed at an
interface between the nitride epitaxial layer and the nitride
barrier layer.
9. The nitride power transistor according to claim 8, further
comprising a dielectric layer disposed on the nitride barrier
layer, wherein the dielectric layer includes one selected from SiN,
SiO.sub.2, SiON, Al.sub.2O.sub.3, HfO.sub.2, HfAlOx and any
combination thereof.
10. The nitride power transistor according to claim 8, further
comprising a GaN capping layer disposed on the nitride barrier
layer.
11. The nitride power transistor according to claim 8, further
comprising an AlN insertion layer disposed between the nitride
barrier layer and the nitride epitaxial layer.
12. The nitride power transistor according to claim 1, wherein the
nitride epitaxial layer comprises: a nitride nucleation layer
located on the silicon substrate; a nitride buffer layer located on
the nitride nucleation layer; and a nitride channel layer located
on the nitride buffer layer, and wherein the nitride power
transistor further comprises a source electrode and a drain
electrode contacting the nitride channel layer and a gate electrode
located between the source electrode and the drain electrode.
13. The nitride power transistor according to claim 12, further
comprising an AlGaN back barrier layer disposed between the nitride
buffer layer and the nitride channel layer.
14. The nitride power transistor according to claim 12, wherein
regions of the nitride channel layer which are respectively located
below the source electrode and the drain electrode are n-type
heavily doped, and a region of the nitride channel layer which is
located below the gate electrode is unintentionally doped, p-type
lightly doped or n-type lightly doped.
15. The nitride power transistor according to claim 1, further
comprising metal deposited at a bottom of the silicon
substrate.
16. A method of manufacturing a nitride power transistor,
comprising: introducing a differently doped semiconductor composite
structure for forming a space charge depletion region inside a
silicon substrate; and growing a nitride epitaxial layer on the
silicon substrate having the semiconductor composite structure.
17. The method according to claim 16, wherein a manufacturing
method of the semiconductor composite structure comprises etching
and epitaxial growth.
18. The method according to claim 16, wherein a manufacturing
method of the semiconductor composite structure comprises ion
implantation.
19. The method according to claim 16, wherein the semiconductor
composite structure is a multi-level structure formed by
transversely alternating n-type semiconductor and p-type
semiconductor.
20. The method according to claim 16, wherein a longitudinal
section of the semiconductor composite structure has one of a
longitudinal vertical arrangement, a triangular arrangement and a
square arrangement or any combination thereof, a cross section of
the semiconductor composite structure has one of a longitudinal
alternating grid arrangement, a longitudinal alternating triangular
arrangement, a longitudinal alternating polygonal arrangement and a
longitudinal alternating circular arrangement or any combination
thereof, and the semiconductor composite structure occupies the
entire silicon substrate in a transverse direction.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of International Patent
Application No. PCT/CN2014/071352 filed on Jan. 24, 2014, which
claims priority of Chinese Patent Application No. 201310482335.7
filed on Oct. 15, 2013, the contents of which are incorporated by
reference herein in their entirety.
TECHNICAL FIELD
[0002] The present invention relates to microelectronics
technology, in particular, relates to a nitride power transistor
and a method of manufacturing the nitride power transistor.
BACKGROUND
[0003] As the third-generation semiconductor material, Gallium
Nitride (GaN) has become a hot research topic due to its features
such as large band gap, high electron saturation velocity, high
breakdown voltage and good thermal conductivity. In aspects of
electrical devices, compared with silicon and gallium arsenide,
gallium nitride material is more suitable to be used to manufacture
electronic devices which are capable of withstanding high
temperature, high frequency, high pressure and has high power, thus
gallium nitride based electronic devices have broad application
prospects.
[0004] In the past, gallium nitride power transistors were
manufactured on sapphire substrates or silicon carbide substrates.
Due to particularity and processing difficulty of gallium nitride
heterojunction conductive channels, most gallium nitride power
transistors have flat structures. Because of thick substrates and
high breakdown voltages, the devices are usually broken down
transversely. Some plane optimization techniques, such as using
field plate structure and increasing the distance between a gate
electrode and a drain electrode, can be used to increase the
breakdown voltages of the devices, however, the materials used for
sapphire substrates and silicon carbide substrates are expensive
and difficult to manufacture substrates and epitaxial layers with
large sizes, so the gallium nitride power transistors are costly
and difficult to be commercialized.
[0005] At present, the technology of manufacturing gallium nitride
power transistors on large-size silicon substrates is becoming
mature and costs are lowering, which facilitates commercialization
of gallium nitride power transistors. However, due to the
electrical conductivity of the silicon materials and their low
critical electric fields, every silicon-based gallium nitride power
transistor has a saturation breakdown voltage, which is determined
by the thickness of the nitride epitaxial layer grown on a silicon
substrate. In addition, to avoid electrostatic discharge (ESD)
caused by accumulation of static electricity in the devices and
realize voltage matching in the circuits, it is necessary to ground
the substrates, which reduces the breakdown voltage half when a
substrate of a silicon-based gallium nitride power transistor is
grounded. Therefore, improving breakdown voltage of the nitride
power transistors on the silicon substrates is an urgent problem
currently.
[0006] Therefore, in order to address the above-described technical
issues, it is required to provide a nitride power transistor and a
manufacturing method thereof.
SUMMARY
[0007] In view of this, an object of the present invention is to
provide a nitride power transistor having a high breakdown voltage
and a manufacturing method thereof. With introduction of
longitudinal P-type doped semiconductor layers and N-type doped
semiconductor layers inside a silicon substrate through epitaxial
doping or ion implantation, a space charge region is formed inside
the P-type doped semiconductor layers and the N-type doped
semiconductor layers. Conductive electrons and holes inside the
space charge region are completely exhausted so that conductive
channels do not exist, similar to a high-resistance region, thus
the nitride power transistor can withstand a certain external
voltage. The bearable voltage of the space charge region depends on
its height. The higher the space charge region is, the higher
voltage it can withstand.
[0008] The space charge region formed by the P-type doped
semiconductor layers and the N-type doped semiconductor layers
introduced in the silicon substrate serves as a
high-voltage-resistance layer inserted in the conductive silicon
substrate, which improves the voltage resistance of the silicon
substrate and hence improves the breakdown voltage of the whole
device. Especially when the silicon substrate is grounded, the
longitudinal breakdown voltage between the drain electrode and the
substrate electrode is greatly increased.
[0009] To achieve the above object, a technical scheme according to
an embodiment of the present invention is provided as follows.
[0010] A nitride power transistor comprises: a silicon substrate
comprising a differently doped semiconductor composite structure
for forming a space charge depletion region; and a nitride
epitaxial layer located on the silicon substrate.
[0011] Preferably, the semiconductor composite structure is a
multi-level structure formed by transversely alternating n-type
semiconductor and p-type semiconductor.
[0012] Preferably, a longitudinal section of the semiconductor
composite structure has one of a longitudinal vertical arrangement,
a triangular arrangement and a square arrangement or any
combination thereof, a cross section of the semiconductor composite
structure has one of a longitudinal alternating grid arrangement, a
longitudinal alternating triangular arrangement, a longitudinal
alternating polygonal arrangement and a longitudinal alternating
circular arrangement or any combination thereof, and the
semiconductor composite structure occupies the entire silicon
substrate in a transverse direction.
[0013] Preferably, a height of the n-type semiconductor and the
p-type semiconductor of the semiconductor composite structure is
more than 5 nm.
[0014] Preferably, doping concentration and doping distribution of
each layer of the silicon substrate and the semiconductor composite
structure in the silicon substrate includes light doping, graded
doping, heavy doping or any combination thereof.
[0015] Preferably, the semiconductor composite structure is located
at a top layer of the silicon substrate, in the middle of the
silicon substrate, or at a bottom of the silicon substrate, or any
combination thereof.
[0016] Preferably, semiconductor in the semiconductor doped
multilayer structure is any one selected from silicon, germanium,
germanium silicon, silicon carbide, III-V compound, or any
combination thereof.
[0017] Preferably, the nitride power transistor further comprises a
nitride epitaxial layer disposed on the nitride channel layer,
two-dimensional electron gas is formed at an interface between the
nitride epitaxial layer and the nitride barrier layer.
[0018] Preferably, the nitride power transistor further comprises a
dielectric layer disposed on the nitride barrier layer, the
dielectric layer includes one selected from SiN, SiO.sub.2, SiON,
Al.sub.2O.sub.3, HfO.sub.2, HfAlOx and any combination thereof. The
nitride power transistor further comprises a GaN capping layer
disposed on the nitride barrier layer and/or an AlN insertion layer
disposed between the nitride barrier layer and the nitride
epitaxial layer.
[0019] Preferably, the nitride epitaxial layer comprises: a nitride
nucleation layer located on the silicon substrate; a nitride buffer
layer located on the nitride nucleation layer; and a nitride
channel layer located on the nitride buffer layer. And the nitride
power transistor further comprises a source electrode and a drain
electrode contacting the nitride channel layer and a gate electrode
located between the source electrode and the drain electrode.
[0020] Preferably, the nitride power transistor further comprises
an AlGaN back barrier layer disposed between the nitride buffer
layer and the nitride channel layer.
[0021] Preferably, regions of the nitride channel layer which are
respectively located below the source electrode and the drain
electrode are n-type heavily doped, and a region of the nitride
channel layer which is located below the gate electrode is
unintentionally doped, p-type lightly doped or n-type lightly
doped.
[0022] Preferably, the nitride power transistor further comprises
metal deposited at a bottom of the silicon substrate.
[0023] Corresponding, a method of manufacturing a nitride power
transistor comprises: introducing a differently doped semiconductor
composite structure for forming a space charge depletion region
inside a silicon substrate; and growing a nitride epitaxial layer
on the silicon substrate having the semiconductor composite
structure.
[0024] Preferably, a manufacturing method of the semiconductor
composite structure comprises etching and epitaxial growth, or ion
implantation.
[0025] Preferably, the semiconductor composite structure is a
multi-level structure formed by transversely alternating n-type
semiconductor and p-type semiconductor.
[0026] Preferably, a longitudinal section of the semiconductor
composite structure has one of a longitudinal vertical arrangement,
a triangular arrangement and a square arrangement or any
combination thereof, a cross section of the semiconductor composite
structure has one of a longitudinal alternating grid arrangement, a
longitudinal alternating triangular arrangement, a longitudinal
alternating polygonal arrangement and a longitudinal alternating
circular arrangement or any combination thereof, and the
semiconductor composite structure occupies the entire silicon
substrate in a transverse direction.
[0027] With introduction of a differently doped semiconductor
composite structure for forming a space charge depletion region
inside a silicon substrate of a nitride power transistor, the
nitride power transistor is capable of withstanding a relatively
high external voltage, and thus a breakdown voltage of the device
is improved. Growing a GaN layer on the surface of the barrier
layer as a protection layer can effectively decrease impact on the
characteristics of the device by the surface defect and the surface
state density of the barrier layer material. The AlN insertion
layer increases the concentration of the two-dimensional electron
gas, improves the mobility of electrons and the overall
characteristics of the device. The AlGaN back barrier layer can
separate the channel electrons from the buffer layer and
effectively confine the two-dimensional electron gas in the channel
layer, which avoids the short-channel effect and the current
collapse effect.
BRIEF DESCRIPTION OF DRAWINGS
[0028] In order to more clearly illustrate the technical schemes
according to the embodiments of the present invention or the prior
art, the accompanying drawings used in the embodiments of the
present invention or the prior art will be introduced briefly.
Apparently, the accompanying drawings described below illustrate
only some of the embodiments of the present invention, other
accompanying drawings can be obtained by those skilled in the art
based on these accompanying drawings without creative efforts.
[0029] FIGS. 1A and 1B are schematic views illustrating processes
of forming a semiconductor composite structure inside a silicon
substrate of a nitride power transistor according to the present
invention;
[0030] FIGS. 2A and 2B are schematic views illustrating a structure
of a nitride HEMT device according to a first embodiment of the
present invention;
[0031] FIG. 3 is a schematic view illustrating a structure of a
nitride HEMT device according to a second embodiment of the present
invention;
[0032] FIG. 4 is a schematic view illustrating a structure of a
nitride HEMT device according to a third embodiment of the present
invention;
[0033] FIG. 5 is a schematic view illustrating a structure of a
nitride HEMT device according to a fourth embodiment of the present
invention;
[0034] FIG. 6 is a schematic view illustrating a structure of a
nitride MOSFET device according to a fifth embodiment of the
present invention;
[0035] FIG. 7 is a schematic view illustrating a structure of a
nitride MIS-HEMT device according to a sixth embodiment of the
present invention;
[0036] FIG. 8 is a schematic view illustrating a structure of a
nitride MESFET device according to a seventh embodiment of the
present invention;
[0037] FIG. 9 is a schematic view illustrating a structure of a
nitride HEMT device according to an eighth embodiment of the
present invention;
[0038] FIG. 10 is a schematic view illustrating a structure of a
nitride HEMT device according to a ninth embodiment of the present
invention;
[0039] FIG. 11 is a schematic view illustrating a structure of a
nitride HEMT device according to a tenth embodiment of the present
invention.
DETAILED DESCRIPTION
[0040] The present invention will be described in detail with
reference to specific embodiments illustrated in the accompanying
drawings. However, the present invention is not limited to the
disclosed embodiments, rather, modifications on structures, methods
or functions made by those skilled in the art based on the
embodiments are included within the scope of the present
invention.
[0041] Further, duplicate reference numerals or identifications may
be used in different embodiments. These duplications are just for
describing the present invention briefly and clearly, and do not
mean that there is any association between different embodiments
and/or structures.
[0042] FIG. 1A is a schematic view illustrating a process of
forming a semiconductor composite structure inside a silicon
substrate of a nitride power transistor according to the present
invention (due to the length of the view, FIG. 1A is divided into
two parts respectively shown in Pages 1 and 2 of the accompanying
drawings).
[0043] Referring to FIG. 1a, firstly an n-doped semiconductor
epitaxial layer is grown on a silicon substrate. Then, referring to
FIG. 1b, the n-type semiconductor epitaxial layer is etched with an
etching method so as to form a comb-shaped structure. Next,
referring to FIG. 1c, etched grooves of the comb-shaped structure
are filled by epitaxially growing p-type semiconductor, so as to
form a differently doped semiconductor composite structure 10
vertically disposed in the longitudinal direction. Then, a layer of
epitaxial silicon is grown thereon, so as to form a silicon
substrate having the differently doped semiconductor composite
structure 10 vertically disposed in the longitudinal direction
therein as shown in FIG. 1d. Here, doping concentration and doping
distribution of the silicon substrate, the semiconductor composite
structure in the silicon substrate and the epitaxial layers on or
below the semiconductor composite structure can be optimized
according to design requirements for the device and the process,
and can be lightly doped, graded doped, heavily doped or any
combination thereof. Since difficult deep groove etching processes
will be used in forming the differently doped semiconductor
composite structure with a longitudinal vertical arrangement,
differently doped semiconductor composite structures having other
arrangements may be used. For example, in a side view, a
longitudinal section of the semiconductor composite structure has
one of a longitudinal vertical arrangement, a triangular
arrangement and a square arrangement or any combination thereof. In
a bottom view, a cross section of the semiconductor composite
structure has one of a longitudinal alternating grid arrangement, a
longitudinal alternating triangular arrangement, a longitudinal
alternating polygonal arrangement and a longitudinal alternating
circular arrangement or any combination thereof. The semiconductor
composite structure occupies the entire silicon substrate in the
transverse direction. FIGS. 1e and if respectively illustrate
semiconductor composite structures having a triangular arrangement
and a square arrangement in the side view, while FIGS. 1g, 1h and
1i respectively illustrate semiconductor composite structures
having a longitudinal alternating grid arrangement, a longitudinal
alternating triangular arrangement and a longitudinal alternating
polygonal arrangement in the bottom view.
[0044] In the present embodiment, etching and epitaxially growing
is used to form the differently doped semiconductor composite
structure, in other embodiments, ion implantation may be used
instead to form the differently doped semiconductor composite
structure. The above-described semiconductor composite structure 10
is a multi-level structure formed by transversely alternating
n-type semiconductor and p-type semiconductor. The semiconductor
composite structure occupies the entire silicon substrate in the
transverse direction. The semiconductor in the composite structure
may be any one selected from silicon, germanium, germanium silicon,
silicon carbide, III-V compound, or any combination thereof. The
n-type semiconductor and the p-type semiconductor generally have a
height of more than 5 nm. Doping concentration, doping distribution
and the overall height of the differently doped semiconductor
composite structure can be adjusted according to the required
bearable voltage.
[0045] FIG. 1B is a schematic view illustrating another process of
forming a semiconductor composite structure inside a silicon
substrate of a nitride power transistor according to the present
invention. Firstly a p-doped semiconductor epitaxial layer is grown
on a silicon substrate. Then, referring to FIG. 1b', the p-type
semiconductor epitaxial layer is etched with an etching method so
as to form a comb-shaped structure. Next, referring to FIG. 1c',
etched grooves of the comb-shaped structure are filled by
epitaxially growing n-type semiconductor, so as to form a
differently doped semiconductor composite structure 10 vertically
disposed in the longitudinal direction. Then, a layer of epitaxial
silicon is grown thereon, so as to form a silicon substrate having
the differently doped semiconductor composite structure 10
vertically disposed in the longitudinal direction therein as shown
in FIG. 1d'. Here, doping concentration and doping distribution of
the silicon substrate, the semiconductor composite structure in the
silicon substrate and the epitaxial layers on or below the
semiconductor composite structure can be optimized according to
design requirements for the device and the process, and can be
lightly doped, graded doped, heavily doped or any combination
thereof. Since difficult deep groove etching processes will be used
in forming the differently doped semiconductor composite structure
with a longitudinal vertical arrangement, differently doped
semiconductor composite structures having other arrangements may be
used. For example, in a side view, a longitudinal section of the
semiconductor composite structure has one of a longitudinal
vertical arrangement, a triangular arrangement and a square
arrangement or any combination thereof. In a bottom view, a cross
section of the semiconductor composite structure has one of a
longitudinal alternating grid arrangement, a longitudinal
alternating triangular arrangement, a longitudinal alternating
polygonal arrangement and a longitudinal alternating circular
arrangement or any combination thereof. The semiconductor composite
structure occupies the entire silicon substrate in the transverse
direction. FIGS. 1e' and if respectively illustrate semiconductor
composite structures having a triangular arrangement and a square
arrangement in the side view. In the present embodiment, etching
and epitaxially growing is used to form the differently doped
semiconductor composite structure, in other embodiments, ion
implantation may be used instead to form the differently doped
semiconductor composite structure.
[0046] FIG. 2A is a schematic view illustrating a structure of a
nitride HEMT device according to a first embodiment of the present
invention. A first layer of a nitride power transistor is a silicon
substrate 1 inside which a differently doped semiconductor
composite structure 10 having a longitudinal vertical arrangement
is disposed. A nitride nucleation layer 2 and a nitride buffer
layer 3 are epitaxially grown on the silicon substrate 1. The
buffer layer 3 contains GaN, AlN or other nitrides, and is used to
match substrate material and epitaxially grow the GaN layer with a
high quality, and also affects crystal quality, surface morphology,
electrical property and other parameters of heterojunctions made by
GaN/AlGaN thereon. A nitride channel layer 4 including a non-doped
GaN layer is grown on the nitride buffer layer 3. A nitride barrier
layer 5 including AlGaN or other nitrides is grown on the nitride
channel layer 4, and forms a semiconductor heterojunction structure
together with the nitride channel layer 4. High-concentration
two-dimensional electron gas is formed at the interface and a
conductive channel is formed at the heterojunction interface in the
GaN channel layer. A dielectric layer 9 is deposited on the nitride
barrier layer 5 to protect a surface of the material through
passivation. The dielectric layer includes one selected from SiN,
SiO.sub.2, SiON, Al.sub.2O.sub.3, HfO.sub.2, HfAlOx or any
combination thereof. A source electrode 6 and a drain electrode 7
are disposed on the nitride barrier layer 5, and a groove is etched
in the dielectric layer 9 between the source electrode 6 and the
drain electrode 7 and metal is deposited on the groove so that a
gate electrode 8 is formed. Herein, the nitride nucleation layer 2,
the nitride buffer layer 3 and the nitride channel layer 4 are
collectively referred to as a nitride epitaxial layer.
[0047] With a certain external voltage, each layer of doped
semiconductor will be completely exhausted so as to form a space
charge depletion region, and the whole differently doped
semiconductor composite structure will form a thick space charge
depletion region, as if a relatively thick high resistance region
is inserted inside the silicon substrate, thus a relatively high
external voltage can be withstood. With this method, the resistance
to pressure of the silicon substrate is improved, and the breakdown
voltage of the nitride power transistor is improved
accordingly.
[0048] FIG. 2B is a schematic view illustrating a modified
structure of a nitride HEMT device according to a first embodiment
of the present invention. As a substrate ground electrode, metal is
deposited at the bottom of the silicon substrate. With a certain
external voltage, the whole differently doped semiconductor
composite structure will be exhausted more completely so as to form
a space charge depletion region with high resistance. Thus the
resistance to pressure of the silicon substrate is improved, and
the breakdown voltage of the nitride power transistor is improved
accordingly.
[0049] FIG. 3 is a schematic view illustrating a structure of a
nitride HEMT device according to a second embodiment of the present
invention. Compared with the first embodiment, in the present
embodiment, the epitaxial growth or doping process is directly
performed at a top layer of the silicon substrate 1 of the nitride
HEMT device, so that the differently doped semiconductor composite
structure 10 is located at the top layer of the silicon substrate
1, the nitride nucleation layer 2 and the nitride buffer layer 3
may be directly grown on the differently doped semiconductor
composite structure 10. Compared with the condition in which the
differently doped semiconductor composite structure is located in
the middle of the silicon substrate, the structure and
manufacturing process thereof are simpler.
[0050] FIG. 4 is a schematic view illustrating a structure of a
nitride HEMT device according to a third embodiment of the present
invention. Compared with the first embodiment, in the present
embodiment, the epitaxial growth or doping process is directly
performed at a bottom of the silicon substrate 1 of the nitride
HEMT device, so that the differently doped semiconductor composite
structure 10 is located at the bottom of the silicon substrate 1.
Compared with the second embodiment, the condition in which the
nitride nucleation layer 2 and the nitride buffer layer 3 are
directly grown on the differently doped semiconductor composite
structure 10 is avoided, thus the processing is simplified.
[0051] FIG. 5 is a schematic view illustrating a structure of a
nitride HEMT device according to a fourth embodiment of the present
invention. Compared with the first embodiment, in the present
embodiment, two differently doped semiconductor composite
structures 10 are formed at the top layer and the bottom of the
silicon substrate 1 of the nitride HEMT device respectively, thus
the height of the whole space charge depletion region is increased,
and the breakdown voltage of the device is further improved.
[0052] FIG. 6 is a schematic view illustrating a structure of a
nitride MOSFET device according to a fifth embodiment of the
present invention. In the present embodiment, the differently doped
semiconductor composite structure 10 is introduced in a silicon
substrate 1 of a nitride n-channel MOSFET device, thus the
breakdown voltage of the device is greatly improved. The regions of
the nitride channel layer 4 which are respectively located below
the source electrode 6 and the drain electrode 7 are n-type heavily
doped regions in which silicon is generally doped, and the region
below the gate electrode 8 is a p-type lightly doped region in
which magnesium is generally doped. The dielectric layer 9 below
the gate metal typically contains SiO.sub.2 or other oxide.
[0053] FIG. 7 is a schematic view illustrating a structure of a
nitride MIS-HEMT device according to a sixth embodiment of the
present invention. In the present embodiment, the differently doped
semiconductor composite structure 10 is introduced in a silicon
substrate 1 of a nitride MIS-HEMT device, thus the breakdown
voltage of the device is improved. The gate dielectric layer 11
under the gate electrode 8 comprises one selected from SiN,
SiO.sub.2, SiON, Al.sub.2O.sub.3, HfO.sub.2, HfAlO.sub.x or any
combination thereof.
[0054] FIG. 8 is a schematic view illustrating a structure of a
nitride MESFET device according to a seventh embodiment of the
present invention. In the present embodiment, the differently doped
semiconductor composite structure 10 is introduced in a silicon
substrate 1 of a nitride MESFET device, thus the breakdown voltage
of the device is improved. Here, the nitride channel layer 4 is
typically n-type lightly doped, the portions of the nitride channel
4 below the source electrode 6 and the drain electrode 7 are n-type
heavily doped, and the gate electrode 8 is a Schottky junction.
[0055] FIG. 9 is a schematic view illustrating a structure of a
nitride MESFET device according to an eighth embodiment of the
present invention. In the present embodiment, a GaN capping layer
12 is grown on the nitride barrier layer 5. Due to surface defect
and high surface state density of the AlGaN barrier layer material,
a large amount of electrons will be captured, which will affect the
two-dimensional electron gas in the channel and hence reduce
characteristics and reliability of the device. Growing a GaN layer
on the surface of the barrier layer as a protection layer can
effectively decrease impact on the characteristics of the device by
the surface defect and the surface state density of the barrier
layer material.
[0056] FIG. 10 is a schematic view illustrating a structure of a
nitride MESFET device according to a ninth embodiment of the
present invention. In the present embodiment, an AlN insertion
layer 13 is introduced between the barrier layer and the channel
layer. Since AlN has a large band gap, electrons can be confined in
a heterojunction potential well effectively, which increases the
concentration of the two-dimensional electron gas. In addition, the
AlN insertion layer separates the conductive channel from the AlGaN
barrier layer, which reduces the scattering effect on electrons by
the barrier layer, thus improving the mobility of electrons and
improving the overall characteristics of the device.
[0057] FIG. 11 is a schematic view illustrating a structure of a
nitride MESFET device according to a tenth embodiment of the
present invention. In the present embodiment, an AlGaN back barrier
layer 14 is introduced between the nitride buffer layer 3 and the
nitride channel layer 4. Under a certain external voltage,
electrons in the channel will enter into the buffer layer. This
phenomenon is very serious in a short-channel device. In this case,
the control on electrons in the channel by the gate electrode
becomes weak, leading to the short-channel effect. Moreover, there
are a large amount of defects and impurities in the buffer layer,
which affects the two-dimensional electron gas in the channel, for
example results in current collapse. The AlGaN back barrier layer
14 can separate the channel electrons from the buffer layer and
effectively confine the two-dimensional electron gas in the channel
layer, which avoids the short-channel effect and the current
collapse effect.
[0058] Further, on the basis of the present invention, an enhanced
nitride power transistor device can be manufactured by changing the
structure or manufacturing process of the nitride channel layer or
the barrier layer on the silicon substrate, for example, by
bombarding the material region below the gate metal with fluorine
ions.
[0059] With the above-described embodiments, the nitride power
transistor obtained by the method of manufacturing the nitride
power transistor according to the present invention has the
following advantageous effects.
[0060] With introduction of a differently doped semiconductor
composite structure for forming a space charge depletion region
inside a silicon substrate of a nitride power transistor, the
nitride power transistor is capable of withstanding a relatively
high external voltage, and thus a breakdown voltage of the device
is improved. Growing a GaN layer on the surface of the barrier
layer as a protection layer can effectively decrease impact on the
characteristics of the device by the surface defect and the surface
state density of the barrier layer material. The AlN insertion
layer increases the concentration of the two-dimensional electron
gas, improves the mobility of electrons and the overall
characteristics of the device. The AlGaN back barrier layer can
separate the channel electrons from the buffer layer and
effectively confine the two-dimensional electron gas in the channel
layer, which avoids the short-channel effect and the current
collapse effect.
[0061] For those skilled in the art, apparently the present
invention is not limited to the details of the above-described
exemplary embodiments, rather, other implementations can be used to
realize the present invention without departing from the spirit or
essential characteristics of the present invention. Thus, in all
cases the embodiments should be construed as exemplary, rather than
limiting. The scope of the present invention is defined by the
appended claims rather than the foregoing description, thus all
modifications within meaning and range of the appended claims and
equivalents thereof are included in the present invention. Any
reference numeral in the claims should not be construed as limiting
the claims.
[0062] Further, it should be understood that although the present
specification is described with reference to embodiments, not each
embodiment contains only one independent technical scheme. The
specification is so described just for clarity. Those skilled in
the art should regard the specification as a whole, technical
schemes of various embodiments can be combined appropriately to
form other implementations which can be understood by those skilled
in the art.
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