U.S. patent application number 15/018563 was filed with the patent office on 2016-08-11 for semiconductor device.
The applicant listed for this patent is J-DEVICES CORPORATION. Invention is credited to Masao HIROBE.
Application Number | 20160233141 15/018563 |
Document ID | / |
Family ID | 56566128 |
Filed Date | 2016-08-11 |
United States Patent
Application |
20160233141 |
Kind Code |
A1 |
HIROBE; Masao |
August 11, 2016 |
SEMICONDUCTOR DEVICE
Abstract
There is provided a semiconductor device including a substrate
whose surface is made of an insulation material, a semiconductor
chip flip-chip connected on the substrate, and a heat sink bonded
to the semiconductor chip via a thermal interface material and
fixed to the substrate outside the semiconductor chip, in which the
heat sink has a protrusion part protruding toward the substrate and
bonded to the substrate via a conductive resin between a part
bonded to semiconductor chip and a part fixed to the substrate and
the heat sink has a stress absorbing part. According to the present
invention, the protrusion part of the heat sink is prevented from
being peeled off from the substrate at the part where the
protrusion part of the heat sink is bonded to the substrate.
Inventors: |
HIROBE; Masao; (Yokohama,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
J-DEVICES CORPORATION |
Oita |
|
JP |
|
|
Family ID: |
56566128 |
Appl. No.: |
15/018563 |
Filed: |
February 8, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/13139
20130101; H01L 2224/73204 20130101; H01L 2224/32225 20130101; H01L
24/13 20130101; H01L 23/10 20130101; H01L 2224/13101 20130101; H01L
2924/10272 20130101; H01L 2924/01029 20130101; H01L 2924/10253
20130101; H01L 2224/2919 20130101; H01L 2224/16225 20130101; H01L
2924/1033 20130101; H01L 2224/29193 20130101; H01L 24/29 20130101;
H01L 2924/01013 20130101; H01L 2224/73253 20130101; H01L 2924/01014
20130101; H01L 2924/3511 20130101; H01L 24/16 20130101; H01L
2224/13144 20130101; H01L 24/32 20130101; H01L 2924/14 20130101;
H01L 2224/13147 20130101; H01L 2924/16153 20130101; H01L 23/04
20130101; H01L 2924/1616 20130101; H01L 23/3736 20130101; H01L
23/3675 20130101; H01L 24/73 20130101; H01L 2924/059 20130101; H01L
24/17 20130101; H01L 23/562 20130101; H01L 2224/32245 20130101;
H01L 2224/13101 20130101; H01L 2924/014 20130101; H01L 2924/00014
20130101; H01L 2224/13147 20130101; H01L 2924/00014 20130101; H01L
2224/13139 20130101; H01L 2924/00014 20130101; H01L 2224/13144
20130101; H01L 2924/00014 20130101; H01L 2224/2919 20130101; H01L
2924/0655 20130101; H01L 2224/2919 20130101; H01L 2924/07025
20130101; H01L 2224/2919 20130101; H01L 2924/0715 20130101; H01L
2224/2919 20130101; H01L 2924/0635 20130101; H01L 2224/2919
20130101; H01L 2924/0675 20130101; H01L 2224/73204 20130101; H01L
2224/16225 20130101; H01L 2224/32225 20130101; H01L 2924/00
20130101 |
International
Class: |
H01L 23/367 20060101
H01L023/367; H01L 23/00 20060101 H01L023/00; H01L 23/373 20060101
H01L023/373 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 9, 2015 |
JP |
2015-023153 |
Claims
1. A semiconductor device comprising: a substrate whose surface is
made of an insulation material; a semiconductor chip flip-chip
connected on the substrate; and a heat sink bonded to the
semiconductor chip via a thermal interface material and fixed to
the substrate outside the semiconductor chip; wherein the heat sink
has a protrusion part protruding toward the substrate and bonded to
the substrate via a conductive resin between a part bonded to
semiconductor chip and a part fixed to the substrate, and wherein
the heat sink has a stress absorbing part.
2. The semiconductor device according to claim 1, wherein the
stress absorbing part has lower rigidity than the part excluding
the stress absorbing part of the heat sink.
3. The semiconductor device according to claim 1, wherein the
stress absorbing part is thinned by a groove provided on the
surface of the heat sink opposing the substrate.
4. The semiconductor device according to claim 3, wherein the
number of the grooves provided thereon is two or more.
5. The semiconductor device according to claim 1, wherein he
protrusion part is arranged to surround the semiconductor chip and
the stress absorbing part is arranged inside or outside the
protrusion part.
6. The semiconductor device according to claim 5, wherein the
stress absorbing part is arranged adjacent to the protrusion
part.
7. The semiconductor device according to claim 1, wherein the
stress absorbing part includes a bottomed hole provided in the
surface of the heat sink opposing the substrate or a through
hole.
8. The semiconductor device according to claim 1, wherein the heat
sink is made of Cu, Al, or AlSiCu ceramic.
9. The semiconductor device according to claim 1, wherein the
protrusion part is bonded an electrode arranged on the substrate
via the conductive resin, and the electrode is electrivally
connected to a ground.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is based on and claims the benefit of
priority from the prior Japanese Patent Application No.
2015-023153, filed on Feb. 9, 2015, the entire contents of which
are incorporated herein by reference.
FIELD
[0002] The present invention relates to a semiconductor device and
in particular to a technique for a flip-chip bonding (FCB) package
with a low-stress heat sink.
BACKGROUND
[0003] According to increase in the speed of the operation of a
semiconductor device and the number of inputs/outputs thereof, heat
generated from the semiconductor device also increases. For this
reason, there has been known a semiconductor package in which a
heat sink is bonded to a semiconductor chip. There also has been
known that a ground is stabilized such that the heat sink is
connected to the ground of a substrate of the package to decrease
noise of a high speed device.
[0004] A Japanese Patent Laid-Open No. 2012-33559, for example,
discloses a semiconductor device in which a heat radiation member
is embedded in a sealing member for embedding a semiconductor chip
to improve heat radiation. According to the semiconductor device
disclosed in the Japanese Patent Laid-Open No. 2012-33559, an
appropriate surface area of the heat radiation member can improve
the heat radiation of the semiconductor device, which allows the
thermal resistance thereof to be reduced.
[0005] However, it may cause a problem that the heat sink provided
for improving the heat radiation is peeled off by stress
accompanied with thermal expansion or thermal shrinkage.
SUMMARY
[0006] A semiconductor device according to an embodiment of the
present invention including a substrate whose surface is made of an
insulation material, a semiconductor chip flip-chip connected on
the substrate, and a heat sink bonded to the semiconductor chip via
a thermal interface material and fixed to the substrate outside the
semiconductor chip, wherein the heat sink has a protrusion part
protruding toward the substrate and bonded to the substrate via a
conductive resin between a part bonded to semiconductor chip and a
part fixed to the substrate and the heat sink has a stress
absorbing part.
[0007] The stress absorbing part may has lower rigidity than the
part excluding the stress absorbing part of the heat sink.
[0008] The stress absorbing part may be thinned by a groove
provided on the surface of the heat sink opposing the
substrate.
[0009] The number of the grooves provided thereon may be two or
more.
[0010] The protrusion part may be arranged to surround the
semiconductor chip and the stress absorbing part may be arranged
inside or outside the protrusion part.
[0011] The stress absorbing part may be arranged adjacent to the
protrusion part.
[0012] The stress absorbing part may include a bottomed hole
provided in the surface of the heat sink opposing the substrate or
a through hole.
[0013] The heat sink may be made of Cu, Al, or AlSiCu ceramic.
[0014] The protrusion part may be bonded an electrode arranged on
the substrate via the conductive resin, and the electrode may be
electrivally connected to a ground.
BRIEF DESCRIPTION OF DRAWINGS
[0015] FIG. 1 is a schematic diagram of a semiconductor device
according to a first embodiment of the present invention;
[0016] FIG. 2 is a cross section of the semiconductor device
according to the first embodiment of the present invention;
[0017] FIG. 3A is a top view of a heat sink of the semiconductor
device according to the first embodiment of the present
invention;
[0018] FIG. 3B is a cross section of the heat sink of the
semiconductor device according to the first embodiment of the
present invention;
[0019] FIG. 4A is a top view of a heat sink of a semiconductor
device according to a second embodiment of the present
invention;
[0020] FIG. 4B is a cross section of the heat sink of the
semiconductor device according to the second embodiment of the
present invention;
[0021] FIG. 5A is a top view of a heat sink of a semiconductor
device according to a third embodiment of the present
invention;
[0022] FIG. 5B is a cross section of the heat sink of the
semiconductor device according to the third embodiment of the
present invention;
[0023] FIG. 6A is a top view of a heat sink of a semiconductor
device according to a fourth embodiment of the present
invention;
[0024] FIG. 6B is a cross section of the heat sink of the
semiconductor device according to the fourth embodiment of the
present invention;
[0025] FIG. 7A is a top view of a heat sink of a semiconductor
device according to a fifth embodiment of the present
invention;
[0026] FIG. 7B is a cross section of the heat sink of the
semiconductor device according to the fifth embodiment of the
present invention;
[0027] FIG. 8 is a cross section of a semiconductor device
according to a comparative example;
[0028] FIG. 9 is a cross section of a semiconductor device
according to a comparative example; and
[0029] FIG. 10 is a cross section of the semiconductor device
according to the first embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0030] The present invention provides a highly reliable
semiconductor device which prevents the heat sink from being peeled
off from the substrate by stress accompanied with thermal expansion
and thermal shrinkage.
[0031] The semiconductor device according to the present invention
is described below with reference to the attached drawings. The
semiconductor device according to the present invention can be
implemented in many different embodiments and shall not be
interpreted by limiting to the description of the embodiments shown
below. In the drawings referred in the present embodiments, the
same components or the conponents having similar functions are
given the same reference number and a repetitive description
thereof is omitted.
First Embodiment
[0032] The structure of the semiconductor device according to the
first embodiment is described with reference to FIGS. 1 to 3.
[Structure of Semiconductor Device]
[0033] FIG. 1 is a schematic diagram showing a structure of a
semiconductor device 100 according to a first embodiment of the
present invention. The semiconductor device 100 comprises a
substrate 10, a semiconductor chip 30 is arranged on the substrate
10 and a heat sink 20 is arranged on the substrate 10 and the
semiconductor chip 30. The substrate 10 and the heat sink 20 are
arranged in opposition to each other. Both the substrate 10 and the
heat sink 20 has substantially the same area. The semiconductor
device 100 is nearly cubic.
[Cross Section of Semiconductor Device]
[0034] FIG. 2 is a cross section along the line I-I' in FIG. 1 in
the semiconductor device 100 according to the first embodiment of
the present invention.
[0035] The substrate 10 is a package substrate (a supporting
substrate) and an organic substrate using an organic material such
as polyimide or epoxy resin. The substrate 10 may be a multilayered
buildup substrate. Electrodes electrically connected with the
semiconductor chip 30 and a protrusion part 22 are arranged on a
surface of the substrate 10 opposing the heat sink 20. An electrode
electrically connected with elements except the semiconductor chip
30, an external device, or another substrate may be appropriately
arranged on another surface of the substrate 10. Except for the
electrodes described above, the surfaces of the substrate 10 are
generally composed of insulation materials such as the organic
material forming the substrate 10, an epoxy resin coating material
coated on the substrate 10, thermosetting epoxy insulation film, or
the like.
[0036] The semiconductor chip 30 is arranged on the substrate 10.
The semiconductor chip 30 is flip-chip connected to the substrate
10 via a conductive bump 49. Cupper (Cu), silver (Ag), gold (Au),
and solder may be used as the bump 49. The semiconductor chip 30 is
a semiconductor element such as an IC chip, an LSI chip, or the
like. A semiconductor element using silicon (Si) as a main material
is used as the semiconductor chip 30, however, silicon carbide
(SiC) or gallium nitride (GaN) may be used as main materials of the
semiconductor chip 30. The first embodiment shows an example where
one semiconductor element is arranged on the substrate, however, a
plurality of semiconductor elements may be arranged side by side or
a plurality of semiconductor elements may be stacked one on top of
another on the substrate.
[0037] An underfill 45 for fixing the semiconductor chip 30 is
arranged between the substrate 10 and the semiconductor chip 30.
Epoxy resin, cyanate ester resin, acryl resin, polyimide resin,
silicone resin or the like may be used as the underfill 45.
[0038] The heat sink 20 is arranged on the semiconductor chip 30
via a thermal interface material 47. A known thermal conduction
material (TIM) is used as the thermal interface material 47. A heat
radiation sheet, graphite, thermal conduction greaseor the like,
for example, may be used as the thermal interface material 47. A
material high in thermal conductivity and adhesive property is used
as the thermal interface material 47 to effectively transfer the
heat of the semiconductor chip 30 to the heat sink 20. Cupper (Cu),
aluminum (Al), AlSiCu ceramics or the like may be used as the heat
sink 20.
[0039] A fixing part 28 protruding toward the substrate 10 is
provided near the outer periphery of the heat sink 20. The fixing
part 28 of the heat sink 20 is fixed to the substrate 10 by an
adhesive 41. The adhesive 41 may be insulative or conductive. If
the protrusion part 22 and a stress absorbing part 26 described
later are neglected, the heat sink 20 has a shape of a lid having
the fixing part 28 protruding toward the substrate 10, near the
outer periphery of the heat sink 20. The side face of the substrate
10 and that of the heat sink 20 are arranged on substantially the
same plane, however, the side face of the heat sink 20 may be
positioned nearer the center of the semiconductor device 100 than
the side face of the substrate 10, or contrarily, the side face of
the heat sink 20 may be positioned farther from the center of the
semiconductor device 100 than the side face of the substrate
10.
[0040] The heat sink 20 has the protrusion part 22 protruding
toward the opposing substrate 10 in addition to the fixing part 28
described above. The protrusion part 22 is arranged between a part
bonded to the semiconductor chip 30 and the fixing part 28. The
protrusion part 22 is bonded to the substrate 10 via a conductive
adhesive 43. An electrode electrically connected to the ground of
the substrate 10 is arranged on the part of the substrate 10 bonded
to the protrusion part 22. In other words, the protrusion part 22
is electrically connected with the ground of the substrate 10 via
the electrode and arranged to stabilize the ground of the substrate
10. It is preferable that the protrusion part 22 is arranged in a
position near the semiconductor chip 30 from the viewpoint of the
stabilization of the ground.
[0041] The stress absorbing part 26 is arranged between the part
bonded to the semiconductor chip 30 and the protrusion part 22 on
the heat sink 20 of the semiconductor device 100 according to the
first embodiment of the present invention. More specifically, a
recessed groove 24 is formed between the part bonded to the
semiconductor chip 30 and the protrusion part 22 on the surface of
the heat sink 20 opposing the substrate 10. If the fixing part 28
and the protrusion part 22 on the heat sink 20 are neglected, the
heat sink 20 has a fixed thickness, however, the stress absorbing
part 26 is formed such that the part where the groove 24 is
arranged is thinner than the periphery of the groove 24. The fixing
part 28, the protrusion part 22, and the groove 24 of the heat sink
20 may be formed by etching.
[Planar Configuration of Heat Sink 20]
[0042] FIG. 3A is a top view of the heat sink 20 of the
semiconductor device according to the first embodiment of the
present invention. FIG. 3B is a cross section of the heat sink 20
along the line I-I' in FIG. 3A. A rectangular area 30' surrounded
by a dotted line shows a position where the heat sink 20 is bonded
to the semiconductor chip 30 (not shown). The protrusion part 22 is
arranged in a rectangular shape so as to surround the area 30'
bonded to the semiconductor chip 30. Furthermore, the fixing part
28 bonded and fixed to the substrate 10 (not shown) is arranged on
the outer periphery of the heat sink 20. In the first embodiment,
the groove 24 (the stress absorbing part 26) is arranged between
the area 30' bonded to the semiconductor chip 30 and the protrusion
part 22. Preferably, the groove 24 is arranged in proximity to a
position where the protrusion part 22 is arranged. More preferably,
the groove 24 is arranged adjacent to the position where the
protrusion part 22 is arranged. As is the case with the protrusion
part 22, the groove 24 (the stress absorbing part 26) is also
arranged in a rectangular shape so as to surround the area 30'
bonded to the semiconductor chip 30.
[0043] The substrate 10 and the semiconductor chip 30 included in
the semiconductor device 100 use an organic substrate and silicon
as main materials respectively. The thermal expansion coefficient
of the substrate 10 is about 15 ppm and that of the semiconductor
chip 30 is about 3.4 ppm. Thus, the value of the thermal expansion
coefficient of the substrate 10 is greater than the value of that
of the semiconductor chip 30. For this reason, at a low temperature
(-55.degree. C., for example) in a temperature cyclic test, the
semiconductor device 100 is totally convexly-warped toward the
upper surface (toward the upper side in FIG. 2 and the surface on
which the heat sink 20 is arranged) because the substrate 10 is
greater in shrinkage. The substrate 10 is firmly bonded and fixed
to the heat sink 20 by the adhesive 41 in the neighborhood of the
outer circumference of the semiconductor device 100. The heat sink
20 is firmly bonded and fixed to the semiconductor chip 30 by the
thermal interface material 47. Thus, the heat sink 20 is firmly
bonded and fixed to the substrate 10 and the semiconductor chip 30,
so that the heat sink 20 is subjected to stress in a warping
direction at a low temperature in the temperature cyclic test.
[0044] The heat sink 20 of the semiconductor device 100 according
to the first embodiment of the present invention has the recessed
groove 24 between the part bonded to the semiconductor chip 30 and
the fixing part 28 fixed to the substrate 10. The stress absorbing
part 26 is formed in the heat sink 20 by the groove 24. In other
words, the groove 24 is provided for the heat sink 20 to form the
stress absorbing part 26 in which the heat sink 20 at the part
where the groove 24 is formed is thinner than the heat sink 20 at
the part where the groove 24 is not formed. The stress absorbing
part 26 can reduce the distortion of the heat sink 20 caused by
heat. In other words, the stress absorbing part 26 of the heat sink
20 has lower rigidity than the surroundings thereof. Thus,
arranging the part having low rigidity in the heat sink 20 allows
the thermal stress of the heat sink 20 to be reduced. For example,
the stress absorbing part 26 is arranged in the heat sink 20 to
allow the warp of the semiconductor device 100 to be reduced at a
low temperature in the temperature cyclic test. This can reduce
stress caused by a warp of the semiconductor device 100 at the part
where the protrusion part 22 of the heat sink 20 is bonded to the
substrate 10, which can prevent the protrusion part 22 from being
peeled off from the substrate 10 at the part.
Second Embodiment
[0045] The outline of the semiconductor device according to the
second embodiment of the present invention is described below with
reference to FIGS. 4A and 4B.
[0046] FIG. 4A is a top view of the heat sink 20 of the
semiconductor device according to the second embodiment. FIG. 4B is
a cross section of the heat sink 20 along the line I-I' in FIG. 4A.
The second embodiment is characterized in that two grooves 24a and
24b are arranged in the heat sink 20 to form the stress absorbing
part 26. The grooves 24a and 24b are formed between an area 30'
bonded to the semiconductor chip 30 and the protrusion part 22. As
is the case with the groove 24 in the first embodiment, the groove
24a is preferably arranged in proximity to a position where the
protrusion part 22 is arranged. The groove 24a is more preferably
arranged adjacent to the position where the protrusion part 22 is
arranged. As is the case with the groove 24 in the first
embodiment, the groove 24a is formed in a rectangular shape viewed
from the top so as to surround the area 30'. The grooves 24b is
arranged between the groove 24a and the area 30' bonded to the
semiconductor chip 30. As is the case with the groove 24a, the
groove 24b is formed also in a rectangular shape viewed from the
top so as to surround the area 30'.
[0047] In the second embodiment, the two grooves 24a and 24b are
arranged between the area 30' bonded to the semiconductor chip 30
and the protrusion part 22 to further reduce the rigidity of the
stress absorbing part 26 than that in the first embodiment, which
allows the stress to be further reduced at the part where the
protrusion part 22 of the heat sink 20 is bonded to the substrate
10.
Third Embodiment
[0048] The outline of the semiconductor device according to the
third embodiment of the present invention is described below with
reference to FIGS. 5A and 5B.
[0049] FIG. 5A is a top view of the heat sink 20 of the
semiconductor device according to the third embodiment. FIG. 5B is
a cross section of the heat sink 20 along the line I-I' in FIG. 5A.
The third embodiment is characterized in that a bottomed hole 24c
is arranged in the heat sink 20 to form the stress absorbing part
26. The bottomed hole 24c is arranged between the area 30' bonded
to the semiconductor chip 30 and the protrusion part 22.
Preferably, the bottomed hole 24c is arranged in proximity to the
position where the protrusion part 22 is arranged. More preferably,
the bottomed hole 24c is arranged adjacent to the position where
the protrusion part 22 is arranged. As can be seen from FIG. 5A, a
plurality of the bottomed holes 24c are arranged in the heat sink
20 at regular intervals along the protrusion part 22 so as to
surround the area 30'. Furthermore, a plurality of the bottomed
holes 24c may be further arranged at regular intervals along the
inside of an area where the bottomed holes 24c are arranged so as
to surround the area 30'.
[0050] Thus, in the third embodiment, the groove 24 is not formed
in the heat sink 20 unlike the first embodiment, instead, a
plurality of the bottomed holes 24c are arranged in the heat sink
20 to form the stress absorbing part 26, which can reduce stress
caused by a warp of the semiconductor device 100 at the part where
the protrusion part 22 is bonded to the substrate 10, as is the
case with the first embodiment.
Fourth Embodiment
[0051] The outline of the semiconductor device according to the
fourth embodiment of the present invention is described below with
reference to FIGS. 6A and 6B.
[0052] FIG. 6A is a top view of the heat sink 20 of the
semiconductor device according to the fourth embodiment. FIG. 6B is
a cross section of the heat sink 20 along the line I-I' in FIG. 6A.
The fourth embodiment is characterized in that a through hole 24d,
which serves as the stress absorbing part 26 and passes from the
surface opposing the substrate 10 to the surface being the outside
of the semiconductor device, is arranged in the heat sink 20. The
through hole 24d may be arranged in the same position as that where
the bottomed hole 24c shown in the third embodiment is arranged.
Preferably, the through hole 24d is arranged in proximity to the
position where the protrusion part 22 is arranged. More preferably,
the through hole 24d is arranged adjacent to the position where the
protrusion part 22 is arranged.
[0053] In the fourth embodiment, rigidity is lowered around the
part where a plurality of the through holes 24d (the stress
absorbing parts 26) are arranged in the heat sink 20. This can
reduce stress caused by a warp of the semiconductor device 100 at
the part where the protrusion part 22 is bonded to the substrate
10, as is the case with the first embodiment.
Fifth Embodiment
[0054] The outline of the semiconductor device according to the
fifth embodiment of the present invention is described below with
reference to FIGS. 7A and 7B.
[0055] FIG. 7A is a top view of the heat sink 20 of the
semiconductor device according to the fifth embodiment. FIG. 7B is
a cross section of the heat sink 20 along the line I-I' in FIG. 7A.
The fifth embodiment is characterized in that a groove 24e is
arranged outside the protrusion part 22, that is to say, between
the protrusion part 22 and the fixing part 28 to form the stress
absorbing part 26, unlike the first embodiment. Preferably, the
groove 24e is arranged in proximity to the position where the
protrusion part 22 is arranged. More preferably, the groove 24e is
arranged adjacent to the position where the protrusion part 22 is
arranged. The groove 24e is arranged outside the protrusion part 22
to also allow the stress to be reduced at the part where the
protrusion part 22 is bonded to the substrate 10, as is the case
with the first embodiment in which the groove 24 is arranged inside
the protrusion part 22.
Other Embodiments
[0056] The first to fifth embodiments of the present invention are
described above with reference to FIGS. 1 to 7B. However, the
present invention is not limited to the above embodiments. The
present invention can be implemented by appropriately modifying the
above embodiments within a range not deviated from the gist of the
invention or combining the embodiments with each other.
[0057] The first embodiment, for example, shows an example where
the groove 24 is continuously arranged in a rectangular shape.
However, the groove 24 may be intermittently arranged so as to
surround the area 30'. Alternatively, a groove may be arranged in
parallel to each side of the protrusion part 22 formed in a
rectangular shape and bottomed holes or through holes may be formed
at parts corresponding to the corners thereof. The grooves 24 and
24e may be arranged inside and outside of the position where the
protrusion part 22 is arranged respectively by combining the first
embodiment with the fifth embodiment. Although the example where
the groove 24 is formed in a concave shape is shown above, the
groove 24 may be formed in other different shapes such as a
circular, a triangular shape, and others. The stress absorbing part
26 formed by the groove 24 or the like only has to be arranged
between the part where the heat sink 20 is bonded to the
semiconductor chip 30 and the fixing part 28 where the heat sink 20
is bonded and fixed to the substrate 10. It is preferable that the
stress absorbing part 26 is arranged in a position near the
protrusion part 22 from the viewpoint of the reduction of stress at
the part where the protrusion part 22 is bonded to the substrate
10.
[0058] The first to third and fifth embodiments describe that the
groove 24 or the like are arranged in the surface, opposing the
substrate 10, of the heat sink 20, however the embodiments of the
present invention are not limited to the above. The groove and the
bottomed hole may be arranged in the surface opposite to the
surface opposing the substrate 10, that is to say, in the surface
exposed outside the semiconductor device 100.
[Simulation]
[0059] The following shows the results of a stress simulation for
the semiconductor device according to an embodiment of the present
invention and a comparative example thereof.
STRUCTURE OF COMPARATIVE EXAMPLES
[0060] FIG. 8 is a cross section of a semiconductor device 700
according to the comparative example. The semiconductor device 700
comprises a glass ceramic substrate 710. The glass ceramic
substrate small in transmission loss is often used in a
semiconductor package of a high-speed device. A semiconductor chip
730 is flip-chip connected on the glass ceramic substrate 710 via a
bump 749 and a lid-like heat sink 720 is bonded to the upper
surface of the semiconductor chip 730 via a thermal interface
material 747. The heat sink 720 is bonded and fixed to the glass
ceramic substrate 710 by an adhesive 741 at the outer
circumferential part of the glass ceramic substrate 710. An
underfill 745 is arranged between the substrate 710 and the
semiconductor chip 30.
[0061] The heat sink 720 has a protrusion part 722 protruding
toward the glass ceramic substrate 710 outside the area bonded to
the semiconductor chip 730. The protrusion part 722 is bonded to
the glass ceramic substrate 710 via a conductive adhesive 743 and
electrically connected to the ground of the glass ceramic substrate
710.
[0062] Materials used as the main components of the semiconductor
device 700 are given below. The lid-like heat sink 720 uses copper,
the semiconductor chip 730 uses silicon, and the glass ceramic
substrate 710 uses glass ceramic. The thermal expansion
coefficients of the materials used as the components are given
below. Those of copper, silicon, and glass ceramic are about 15
ppm, about 3.4 ppm, and about 9.5 ppm respectively. For this
reason, at a low temperature (-55.degree. C., for example) in the
temperature cyclic test at the manufacturing process of
semiconductor device 700, the semiconductor device 700 is
convexly-warped upward in FIG. 8 caused by the mismatch among the
thermal expansion coefficients of the components. However, for the
glass ceramic substrate 710, the warp is suppressed comparatively
smaller, which hardly causes a problem that the parts where the
components are boned to each other are peeled off.
[0063] A substrate adaptable to a high-speed device has been
developed in recent years also in an organic substrate such as a
buildup substrate. The organic substrate which is less expensive
than a glass ceramic substrate is often used as the package
substrate for the high-speed device. FIG. 9 shows a cross section
of a semiconductor device 800 according to a comparative example.
The semiconductor device 800 shown in FIG. 9 is the same as the
semiconductor device 700 shown in FIG. 8 in structure, however, the
semiconductor device 800 is different from the semiconductor device
700 in that an organic substrate 810 is used as a package
substrate.
[0064] Materials used as the main components of the semiconductor
device 800 are given below. A lid-like heat sink 820 uses copper, a
semiconductor chip 830 uses silicon, and the organic substrate 810
is a substrate including an organic material. The thermal expansion
coefficients of the materials used as the components are given
below. Those of copper, silicon, and the organic substrate are
about 15 ppm, about 3.4 ppm, and about 15 ppm respectively.
Therefore, the organic substrate 810 shown in FIG. 9 is greater
than the glass ceramic substrate 710 shown in FIG. 8 in the thermal
expansion coefficient. At a low temperature (-55.degree. C., for
example) in the temperature cyclic test, even the semiconductor
device 800 using the organic substrate 810 as the package substrate
is convexly-warped upward in FIG. 9. At this point, the parts where
the components are boned to each other can be peeled off because
the organic substrate 810 is greater than the glass ceramic
substrate 710 shown in FIG. 8 in the warp. The application of
stress to the part where the protrusion part 822 of the heat sink
820 is bonded to the organic substrate 810 can cause release the
protusion part 822 and the organic substrate 810, which may cause a
problem that makes it difficult to keep the stability of a ground
potential.
EXAMPLE
[0065] FIG. 10 shows a cross section of a semiconductor device 100
according to one embodiment of the present invention. The
semiconductor device 100 shown in FIG. 10 is the same as the
semiconductor device 100 described in the first embodiment in
structure. Materials used as the main components of the
semiconductor device 100 are given below. The substrate 10 uses the
organic substrate including an organic material, the heat sink uses
copper, the adhesive 41 uses epoxy resin, the underfill 45 uses
epoxy resin, the conductive adhesive 43 uses Ag paste, and the
thermal interface material 47 uses a metal. The heat sink 20 is in
a square shape, the length "a" of one side thereof is 26.5 mm and
the thickness "b" thereof is 0.5 mm, the width "c" of the groove 24
is 4 mm and the depth "d" thereof is 0.3 mm, the length "e" of the
protrusion part 22 is 0.3 mm and the thickness "f" thereof in the
planar direction is 0.5 mm, the length "g" of the fixing part 28 is
0.7 mm and the thickness "h" thereof in the planar direction is 2
mm, and a distance "i" between the two protrusion parts 22 where
the semiconductor chip 30 is arranged is 16 mm. The semiconductor
chip 30 is in a square shape, the length "j" of one side thereof is
11 mm, and the semiconductor chip 30 is arranged at the center of
the square substrate 10 and the heat sink 20. The length "k" of one
side of the substrate 10 is 27 mm and the thickness "m" thereof is
0.99 mm. The width of the stress absorbing part 26 is 4 mm and the
thickness thereof is 0.3 mm.
[0066] On the other hand, the semiconductor device according to the
comparative example shall not have the groove 24 (the stress
absorbing part 26) in FIG. 10 and others shall be the same in
structure. A table 1 shows temperature and stress at the maximum
stress in the part where the protrusion part 22 is bonded to the
substrate 10 (referred to as a ground connection part) at a
temperature cyclic test (-55.degree. C. to 125.degree. C.).
TABLE-US-00001 TABLE 1 Ground connection part Maximum stress
Structure (Temperature: -55.degree. c.) Groove is not provided 3.75
Mpa (comparative example) Groove is provided 3.52 Mpa (example)
[0067] The maximum stress at the ground connection part in the
semiconductor device without the groove 24 according to the
comparative example was 3.75 Mpa. On the other hand, the maximum
stress at the ground connection part in the semiconductor device
with the groove 24 (i.e., with the stress absorbing part 26)
according to the example was 3.52 Mpa. Therefore, it is clear from
the simulation that the example according to an embodiment of the
present invention could reduce more stress applied to the ground
connection part than the comparative example at a temperature of
-55.degree. C.
[Experimental Results]
[0068] A table 2 shows the experimental results of the temperature
cyclic test (-55.degree. C. to 125.degree. C.) for the
semiconductor devices according to the example and the comparative
example with the dimensions and structure same as those set in the
above simulation. In the table 2, the number of the semiconductor
devices subjected to the temperature cyclic test is taken as a
denominator and the number of the semiconductor devices rejected in
conduction tests applied to the devices is taken as a numerator.
The reason the semiconductor devices are rejected in the conduction
tests seems to be that a part of the protrusion part 22 is peeled
off from the substrate 10 or the protrusion part 22 is wholly
peeled off from the substrate 10 at the part where the protrusion
part 22 of the heat sink 20 is bonded to the substrate 10.
TABLE-US-00002 TABLE 2 Temperature cycle Structure 800 cyc 1000 cyc
1200 cyc 1500 cyc Groove is not provided 0/30 6/30 13/22 4/7
(comparative example) Groove is provided 0/30 0/30 0/28 3/26
(example)
[0069] With reference to the table 2, although all the
semiconductor devices without the groove 24 of the comparative
example were acceptable in the conduction tests at a cycle of 800,
6 of 30 semiconductor devices were rejected at a cycle of 1000, 13
of 22 semiconductor devices were rejected at a cycle of 1200, and 4
of 7 semiconductor devices were rejected at a cycle of 1500. On the
other hand, for the semiconductor device with the groove 24 (with
the stress absorbing part 26) of the example according to an
embodiment of the present invention, 30, 30, and 28 semiconductor
devices were subjected to the tests at cycles of 800, 1000, and
1200 respectively and, as a result, all of the semiconductor
devices were acceptable. 3 of 26 semiconductor devices, however,
were rejected at a cycle of 1500.
[0070] As described above, it was confirmed that the semiconductor
device with the groove 24 (with the stress absorbing part 26) of
the example according to an embodiment of the present invention
could more substantially reduce the ratio in which semiconductor
devices are rejected in the conduction tests carried out after the
temperature cyclic tests than the semiconductor device without the
groove 24 of the comparative example. For this reason, it was
confirmed that the example according to an embodiment of the
present invention was effective for preventing the protrusion part
22 from being peeled off from the substrate at the part where the
protrusion part 22 is bonded to the substrate 10.
[0071] According to the present invention, the stress absorbing
part having low rigidity is provided for the heat sink to allow
reducing stress caused by the warp of the semiconductor device at
the part where the protrusion part of the heat sink is bonded to
the substrate and preventing the protrusion part from being peeled
off from the substrate at the part where the protrusion part is
bonded to the substrate. This can hold a stable electrical
connection between the heat sink and the ground. Consequently, a
highly reliable semiconductor device can be provided.
* * * * *