U.S. patent application number 14/691580 was filed with the patent office on 2016-08-04 for method of manufacturing isolation structure and non-volatile memory with the isolation structure.
The applicant listed for this patent is Powerchip Technology Corporation. Invention is credited to Chun-Yu Chuang, Yi-Lin Hsu, Liang-Chuan Lai.
Application Number | 20160225882 14/691580 |
Document ID | / |
Family ID | 56506718 |
Filed Date | 2016-08-04 |
United States Patent
Application |
20160225882 |
Kind Code |
A1 |
Chuang; Chun-Yu ; et
al. |
August 4, 2016 |
METHOD OF MANUFACTURING ISOLATION STRUCTURE AND NON-VOLATILE MEMORY
WITH THE ISOLATION STRUCTURE
Abstract
A method of manufacturing an isolation structure suitable for a
non-volatile memory is provided. A substrate is provided. A
dielectric layer, a conductive layer, and a hard mask layer are
sequentially formed on the substrate. The hard mask layer and the
conductive layer are patterned to form a first trench which exposes
the dielectric layer. A first liner is formed on the substrate. The
first liner and the dielectric layer that are exposed by the first
trench are removed to expose the substrate. A spacer is formed on
sidewalls of the conductive layer and the hard mask layer. The
substrate is partly removed to form a second trench with use of the
conductive layer and the hard mask layer with the spacer as a mask.
An isolation layer is formed in the second trench. The distance
between the conductive layers is greater than the width of the
second trench.
Inventors: |
Chuang; Chun-Yu; (Taoyuan
City, TW) ; Hsu; Yi-Lin; (Hsinchu County, TW)
; Lai; Liang-Chuan; (Hsinchu County, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Powerchip Technology Corporation |
Hsinchu |
|
TW |
|
|
Family ID: |
56506718 |
Appl. No.: |
14/691580 |
Filed: |
April 21, 2015 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/76224 20130101;
H01L 29/66553 20130101; H01L 27/11524 20130101; H01L 29/66825
20130101; H01L 29/40114 20190801; H01L 29/42324 20130101; H01L
21/283 20130101 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 27/115 20060101 H01L027/115; H01L 21/762 20060101
H01L021/762; H01L 21/28 20060101 H01L021/28; H01L 21/283 20060101
H01L021/283 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 2, 2015 |
TW |
104103413 |
Claims
1. A method of manufacturing an isolation structure, comprising:
providing a substrate; sequentially forming a dielectric layer, a
conductive layer, and a hard mask layer on the substrate;
patterning the hard mask layer and the conductive layer to form a
first trench exposing the dielectric layer; forming a first liner
on the substrate; removing the first liner and the dielectric layer
exposed by the first trench, so as to expose the substrate and form
a spacer on a sidewall of the conductive layer and a sidewall of
the hard mask layer, respectively, wherein the spacer is formed
form the first liner; removing a portion of the substrate to form a
second trench by using the conductive layer and the hard mask layer
having the spacer as a mask; and forming an isolation layer in the
second trench, wherein a distance between the conductive layers is
greater than a width of the second trench, wherein the step of
forming the isolation layer in the second trench comprises: forming
a second liner in the second trench; performing an annealing
process; filling the second trench with an insulation material
layer; and performing a curing process.
2. (canceled)
3. The method of claim 1, wherein a method of forming the first
liner comprises an in-situ steam generation method, a thermal
oxidation method, or an atomic layer deposition method.
4. The method of claim 1, wherein a material of the dielectric
layer comprises silicon oxide.
5. The method of claim 1, wherein a material of the conductive
layer comprises a doped polysilicon layer and a non-doped
polysilicon layer.
6. The method of claim 1, wherein a material of the hard mask layer
comprises silicon nitride or silicon oxide.
7. The method of claim 1, wherein a material of the first liner
comprises silicon oxide.
8. The method of claim 1, wherein a material of the insulation
material layer comprises a spin-on dielectric material.
9. The method of claim 1, wherein a material of the second liner
comprises silicon oxide.
10. A method of manufacturing a non-volatile memory, comprising:
providing a substrate, a dielectric layer, a first conductive
layer, and a hard mask layer being sequentially formed on the
substrate; patterning the hard mask layer and the first conductive
layer to form a first trench exposing the dielectric layer; forming
a first liner on the substrate; removing the first liner and the
dielectric layer exposed by the first trench, so as to expose the
substrate and form a spacer on a sidewall of the first conductive
layer and a sidewall of the hard mask layer, respectively, wherein
the spacer is formed from the first liner; removing a portion of
the substrate to form a second trench by using the first conductive
layer and the hard mask layer having the spacer as a mask; forming
an isolation layer in the second trench, wherein a distance between
the first conductive layers is greater than a width of the second
trench, wherein the step of forming the isolation layer in the
second trench comprises: forming a second liner in the second
trench; performing an annealing process; filling the second trench
with an insulation material layer; and performing a curing process;
removing the hard mask layer; forming an inter-gate dielectric
layer on the substrate; forming a second conductive layer on the
inter-gate dielectric layer; and patterning the second conductive
layer, the inter-gate dielectric layer, and the first conductive
layer to form a control gate and a floating gate.
11. The method of claim 10, wherein the first conductive layer
comprises a doped polysilicon layer and a non-doped polysilicon
layer.
12. The method of claim 10, wherein a method of forming the first
liner comprises an in-situ steam generation method, a thermal
oxidation method, or an atomic layer deposition method.
13. The method of claim 10, wherein a material of the dielectric
layer comprises silicon oxide.
14. The method of claim 10, wherein a material of the hard mask
layer comprises silicon nitride or silicon oxide.
15. The method of claim 10, wherein a material of the first liner
comprises silicon oxide.
16. The method of claim 10, wherein a material of the inter-gate
dielectric layer comprises silicon oxide/silicon nitride/silicon
oxide.
17. The method of claim 10, wherein a material of the second
conductive layer comprises doped polysilicon.
18. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan
application serial no. 104103413, filed on Feb. 2, 2015. The
entirety of the above-mentioned patent application is hereby
incorporated by reference herein and made a part of this
specification.
FIELD OF THE INVENTION
[0002] The invention relates to a method of manufacturing a
semiconductor device; more specifically, the invention relates to a
method of manufacturing an isolation structure and a method of
manufacturing a non-volatile memory with the isolation
structure
DESCRIPTION OF RELATED ART
[0003] A non-volatile memory has been widely used in personal
computers and electronic equipment because data can be stored into,
read from, and erased from the non-volatile memory a number of
times and because the stored data can be retained even after power
supply is cut off.
[0004] In a typical non-volatile memory, floating gates and control
gates are made of doped polysilicon. Generally, the greater the
gate-coupling ratio (GCR) between the floating gates and the
control gates, the lower the floating gate coupling between the
floating gates. In response thereto, the operation speed and the
efficiency of the non-volatile memory are increased. Methods of
enhancing the GCR include an increase in the capacitance of an
inter-gate dielectric layer or a decrease in the capacitance of a
tunneling dielectric layer.
[0005] Along with the rapid progress of science and technologies,
the level of integration of semiconductor devices increases, and
therefore dimensions of various memory devices need be further
reduced. In the event of reducing the dimensions of the memory
devices, however, the excessive electric field of the tunneling
dielectric layer may result in tunnel oxide breakdown, which leads
to the reduction of the reliability of the devices. In order to
further enhance the reliability as well as the stability of the
devices, solutions to said issues are required.
SUMMARY OF THE INVENTION
[0006] The invention is directed to a method of manufacturing an
isolation structure to reduce an electric field of a tunneling
dielectric layer, enhance a gate-coupling ratio (GCR), improve
performance of devices, and increase reliability of the
devices.
[0007] The invention is further directed to a method of
manufacturing a non-volatile memory having said isolation
structure, so as to enhance the GCR as well as a trench-filling
ability of a conductive layer of a control gate; meanwhile,
interference between or among floating gates can be reduced.
[0008] In an embodiment of the invention, a method of manufacturing
an isolation structure includes following steps. A substrate is
provided, and a dielectric layer, a conductive layer, and a hard
mask layer are sequentially formed on the substrate. The hard mask
layer and the conductive layer are patterned to form a first trench
which exposes the dielectric layer. A first liner is formed on the
substrate. The first liner and the dielectric layer that are
exposed by the first trench are removed to expose the substrate and
form a spacer on a sidewall of the conductive layer and a sidewall
of the hard mask layer, respectively. A portion of the substrate is
removed to form a second trench with use of the conductive layer
(having the spacer) and the hard mask layer (having the spacer) as
a mask. An isolation layer is formed in the second trench, and a
distance between the conductive layers is greater than a width of
the second trench.
[0009] According to an embodiment of the invention, the step of
forming the isolation layer in the second trench includes: forming
a second liner in the second trench, performing an annealing
process, filling the second trench with an insulation material
layer, and performing a curing process.
[0010] According to an embodiment of the invention, a method of
forming the first liner includes an in-situ steam generation (ISSG)
method, a thermal oxidation method, or an atomic layer deposition
(ALD) method.
[0011] According to an embodiment of the invention, a material of
the dielectric layer includes silicon oxide.
[0012] According to an embodiment of the invention, the conductive
layer includes a doped polysilicon layer and a non-doped
polysilicon layer.
[0013] According to an embodiment of the invention, a material of
the hard mask layer includes silicon nitride or silicon oxide.
[0014] According to an embodiment of the invention, a material of
the first liner includes silicon oxide.
[0015] According to an embodiment of the invention, a material of
the insulation material layer includes a spin-on dielectric (SOD)
material.
[0016] According to an embodiment of the invention, a material of
the second liner includes silicon oxide.
[0017] In an embodiment of the invention, a method of manufacturing
a non-volatile memory includes following steps. A substrate is
provided, and a dielectric layer, a first conductive layer, and a
hard mask layer are sequentially formed on the substrate. The hard
mask layer and the first conductive layer are patterned to form a
first trench. A spacer is formed on a sidewall of the hard mask
layer and on a sidewall of the first conductive layer,
respectively. A portion of the substrate is removed to form a
second trench with use of the first conductive layer and the hard
mask layer with the spacer as a mask. An isolation layer is formed
in the second trench, and a distance between the first conductive
layers is greater than a width of the second trench. The hard mask
layer is removed, and an inter-gate dielectric layer is formed on
the substrate. A second conductive layer is formed on the
inter-gate dielectric layer. The second conductive layer, the
inter-gate dielectric layer, and the first conductive layer are
patterned to form a control gate and a floating gate.
[0018] According to an embodiment of the invention, the first
conductive layer includes a doped polysilicon layer and a non-doped
polysilicon layer.
[0019] According to an embodiment of the invention, a method of
forming the first liner includes an ISSG method, a thermal
oxidation method, or an ALD method.
[0020] According to an embodiment of the invention, a material of
the dielectric layer includes silicon oxide.
[0021] According to an embodiment of the invention, a material of
the hard mask layer includes silicon nitride or silicon oxide.
[0022] According to an embodiment of the invention, a material of
the first liner includes silicon oxide.
[0023] According to an embodiment of the invention, a material of
the inter-gate dielectric layer includes silicon oxide/silicon
nitride/silicon oxide.
[0024] According to an embodiment of the invention, a material of
the second conductive layer includes doped polysilicon.
[0025] In view of the above, by applying the method of
manufacturing the isolation structure and the method of
manufacturing the non-volatile memory having the isolation
structure, the distance between two adjacent floating gates is
greater than the width of the trench in the isolation structure;
that is, the distance between two adjacent floating gates is
greater than that provided in the related art. As such, the
resultant conductor acting as the control gate is characterized by
favorable trench-filling capabilities, interference between the
floating gates can be reduced, and performance of devices can be
improved. In addition, the fact that the distance between two
adjacent floating gates is greater than the width of the trench in
the isolation structure results in the reduction of the electric
field of the tunneling dielectric layer without incurring the
breakdown of the tunneling dielectric layer, and accordingly the
reliability and the stability of the devices can be enhanced.
[0026] Several exemplary embodiments accompanied with figures are
described in detail below to further describe the invention in
details.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIG. 1A through FIG. 1E are schematic cross-sectional views
illustrating a process flow of manufacturing a non-volatile memory
according to an embodiment of the invention.
DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS
[0028] FIG. 1A through FIG. 1E are schematic cross-sectional views
illustrating a process flow of manufacturing a non-volatile memory
according to an embodiment of the invention. Note that the
cross-sectional views in FIG. 1A to FIG. 1E are taken in a
direction parallel to directions of word lines of memory units or
perpendicular to directions of bit lines of the memory units.
[0029] With reference to FIG. 1A, a substrate 100 is provided. The
substrate 100 is, for instance, a silicon substrate. A dielectric
layer 102, a conductive layer 104, and a hard mask layer 106 are
sequentially formed on the substrate 100.
[0030] A material of the dielectric layer 102 is, for instance,
silicon oxide, and the dielectric layer 102 is formed, for
instance, by thermal oxidation.
[0031] The conductive layer 104, for instance, has a double-layer
structure constituted by conductive layers 104a and 104b. A
material of the conductive layer 104a is, for instance, non-doped
polysilicon, and a method of fabricating the same is, for instance,
chemical vapor deposition (CVD). A material of the conductive layer
104b is, for instance, doped polysilicon, and a method of
fabricating the same includes steps of forming a non-doped
polysilicon layer through CVD and performing ion implantation. The
conductive layer 104b can also be formed by performing a chemical
vapor deposition process with in-situ dopant implantation. The
double-layer structure can expand the surface area of the
conductive layer 104; that is, the surface area of the conductive
layer 104 acting as the floating gate (as shown in FIG. 1E) is
increased, and a coupling ratio between the floating gate and a
subsequently formed control gate can be raised. According to the
present embodiment, the conductive layer 104 has the double-layer
structure, for instance, and the conductive layer 104 can also have
a single-layer structure or a multi-layer structure.
[0032] The hard mask layer 106, for instance, has a double-layer
structure constituted by hard mask layers 106a and 106b. A material
of the hard mask layer 106a is, for instance, silicon nitride, and
a method of forming the hard mask layer 106a is CVD, for instance.
A material of the hard mask layer 106b is, for instance, silicon
oxide, and a method of forming the hard mask layer 106b is CVD, for
instance. According to the present embodiment, the hard mask layer
106 has the double-layer structure, for instance, and the hard mask
layer 106 can also have a single-layer structure or a multi-layer
structure.
[0033] With reference to FIG. 1B, the hard mask layer 106 and the
conductive layer 104 are patterned to form a first trench 108 which
exposes the dielectric layer 102. A method of patterning the hard
mask layer 106 and the conductive layer 104 includes steps of
forming a patterned photoresist layer (not shown) on the substrate
100, etching the hard mask layer 106 and the conductive layer 104
with use of the patterned photoresist layer as a mask, and removing
the photoresist layer, for instance. A first liner 110 is formed on
the substrate 100. A material of the first liner 110 is, for
instance, silicon oxide, and a method of forming the same is
thermal oxide, for instance; however, the method of forming the
first liner 110 may also be in-situ steam generation (ISSG) or
atomic layer deposition (ALD).
[0034] With reference to FIG. 1C, the first liner 110 and the
dielectric layer 102 that are exposed by the first trench 108 are
removed to expose the substrate 100 and form a spacer 110a on a
sidewall of the conductive layer 104 and a sidewall of the hard
mask layer 106, respectively. A method of removing the first liner
110 and the dielectric layer 102 exposed by the first trench 108
is, for instance, anisotropic etching. Through anisotropic etching,
the first liner 110 on the hard mask layer 106 is removed as well.
A portion of the substrate 100 is removed to form a second trench
112 with use of the conductive layer 104 (having the spacer 110a)
and the hard mask layer 106 (having the spacer 110a) collectively
acting as a mask. A method of removing a portion of the substrate
100 is, for instance, etching.
[0035] With reference to FIG. 1D, an isolation layer 122 is formed
in the second trench 112. The isolation layer 122 is constituted by
a second liner 114 and an insulation material layer 116, for
instance.
[0036] A method of forming the isolation layer 122 in the second
trench 112 includes following steps. The second liner 114 is formed
in the second trench 112. A material of the second liner 114 is,
for instance, silicon oxide, and a method for fabricating the same
is, for instance, thermal oxidation; alternatively, the second
liner 114 may also be formed by applying an ISSG method. An
annealing process is then performed in a nitrogen-containing
environment. The second trench 112 is filled with an insulation
material layer 116. A material of the insulation material layer 116
is, for instance, a spin-on dielectric (SOD) material or any other
appropriate insulation material, for instance. A curing process is
performed, and an active area is defined. A method of filling the
second trench 112 with the insulation material layer 116 may be a
spin-coating method, for instance; alternatively, the second trench
112 may be filled with the insulation material layer 116 by forming
an insulation material layer 116 through CVD, performing a
planarization process through chemical-mechanical polishing, and
performing an etch back process to remove at least a portion of the
insulation material layer 116.
[0037] With reference to FIG. 1E, the hard mask layer 106 is
removed. A method of removing the hard mask layer 106 includes a
step of sequentially removing the mask layer 106b and the mask
layer 106a through etching.
[0038] An inter-gate dielectric layer 118 is formed on the
substrate 100. A material of the inter-gate dielectric layer 118
is, for instance, silicon oxide/silicon nitride/silicon oxide
(ONO), and a method of forming the same may include a step of
sequentially forming a silicon oxide layer, a silicon nitride
layer, and a silicon oxide layer through CVD or thermal oxidation,
for instance. The material of the inter-gate dielectric layer 118
can also be silicon oxide, silicon nitride, silicon oxide/silicon
nitride, and so on. Besides, the method of forming the inter-gate
dielectric layer 118 may include CVD with use of different reaction
gases in response to different materials of the inter-gate
dielectric layer 118.
[0039] A conductive layer 120 is formed on the inter-gate
dielectric layer 118. A material of the conductive layer 120 is,
for instance, doped polysilicon, and a method of fabricating the
same includes steps of forming a non-doped polysilicon layer
through CVD and performing ion implantation. The conductive layer
120 can also be formed by performing a chemical vapor deposition
process with in-situ dopant implantation. The conductive layer 120,
the inter-gate dielectric layer 118, and the conductive layer 104
are patterned. The patterned conductive layer 120 constitutes the
control gate, and the patterned conductive layer 104 constitutes
the floating gate 104c. Since the subsequent steps of forming a
non-volatile memory are well known to people having ordinary skill
in the pertinent art, detailed descriptions are omitted
hereinafter.
[0040] As provided herein, by applying the method of manufacturing
the isolation structure and the method of manufacturing the
non-volatile memory having the isolation structure, the distance W1
between two adjacent floating gates 104c is greater than the width
W2 of the second trench 112; by contrast, the distance between two
adjacent floating gates is equal to the width of the second trench
according to the related art. As such, the resultant conductive
layer 120 is characterized by favorable trench-filling
capabilities, interference between the floating gates 104c can be
reduced, and performance of devices can be improved. In addition,
the fact that the distance W1 between two adjacent floating gates
104c is greater than the width W2 of the second trench 112 in the
isolation structure results in the reduction of the electric field
of the tunneling dielectric layer without incurring the breakdown
of the tunneling dielectric layer, and accordingly the reliability
and the stability of the devices can be enhanced.
[0041] Although the invention has been disclosed by the above
embodiments, they are not intended to limit the invention. Persons
skilled in the art may make some modifications and alterations
without departing from the spirit and scope of the invention.
Therefore, the protection range of the invention falls in the
appended claims.
* * * * *