U.S. patent application number 15/043658 was filed with the patent office on 2016-07-07 for semi-conductor device with programmable response.
The applicant listed for this patent is International Business Machines Corporation. Invention is credited to Ali Afzali-Ardakani, Tze-chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari, Young H. Kwark.
Application Number | 20160197296 15/043658 |
Document ID | / |
Family ID | 55700111 |
Filed Date | 2016-07-07 |
United States Patent
Application |
20160197296 |
Kind Code |
A1 |
Afzali-Ardakani; Ali ; et
al. |
July 7, 2016 |
SEMI-CONDUCTOR DEVICE WITH PROGRAMMABLE RESPONSE
Abstract
An apparatus with a programmable response includes a
semiconductor device with a junction formed thereon, the junction
having a built-in potential, a quantum well element proximate to
the junction that provides an energy well within a depletion region
of the junction. The energy well comprises one or more donor energy
states that support electron trapping, and/or one or more acceptor
energy states that support hole trapping; thereby modulating the
built-in potential of the junction. The semiconductor device may be
a diode, a bipolar diode, a transistor, or the like. A
corresponding method is also disclosed herein.
Inventors: |
Afzali-Ardakani; Ali;
(Ossining, NY) ; Chen; Tze-chiang; (Yorktown
Heights, NY) ; Gopalakrishnan; Kailash; (New York,
NY) ; Hekmatshoartabari; Bahman; (White Plains,
NY) ; Kwark; Young H.; (Chappaqua, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Family ID: |
55700111 |
Appl. No.: |
15/043658 |
Filed: |
February 15, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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14588997 |
Jan 5, 2015 |
9318717 |
|
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15043658 |
|
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Current U.S.
Class: |
365/174 ; 257/14;
977/774; 977/943 |
Current CPC
Class: |
H01L 51/0098 20130101;
G11C 11/40 20130101; B82Y 10/00 20130101; G11C 14/00 20130101; Y10S
977/943 20130101; G11C 13/0014 20130101; H01L 51/0587 20130101;
H01L 51/0508 20130101; G11C 2216/08 20130101; G11C 16/0466
20130101; H01L 51/0055 20130101; G11C 11/5664 20130101; Y10S
977/774 20130101; H01L 51/0562 20130101; G11C 7/22 20130101; G11C
11/36 20130101; H01L 51/102 20130101 |
International
Class: |
H01L 51/05 20060101
H01L051/05; G11C 7/22 20060101 G11C007/22; H01L 51/10 20060101
H01L051/10 |
Claims
1. A programmable two-terminal semiconductor diode device,
comprising: a junction in electrical communication with two
terminals, the junction having a built-in potential; a quantum well
element proximate to the junction that provides an energy well
within a depletion region of the junction; the energy well
comprising one or more donor energy states that support electron
trapping and/or one or more acceptor energy states that support
hole trapping; the built-in potential of the junction corresponding
to a net polarity of holes and electrons trapped by the one or more
donor energy states and/or one or more acceptor energy states;
wherein current-voltage characteristics of the two-terminal
semiconductor diode device are programmed by applying an electrical
signal across the two terminals to cause a net polarity of holes
and electrons to be trapped by the one or more donor energy states
and/or one or more acceptor energy states
2. The device of claim 1, wherein the junction is a
hetero-junction.
3. The device of claim 2, wherein the hetero-junction comprises an
interface between a first organic material and an inorganic
material.
4. The device of claim 3, wherein the inorganic material comprises
silicon and the first organic material comprises pentacene.
5. The device of claim 4, further comprising a passivation layer
between the first organic material and the inorganic material that
saturates dangling bonds of the inorganic material.
6. The device of claim 5, wherein the passivation layer comprises a
second organic material.
7. The device of claim 6, wherein the second organic material is
selected from the group consisting of an aromatic organic material,
a monolayer of a long-chain alcohol, and a monolayer of a
long-chain thiol.
8. The device of claim 1, wherein the quantum well element is a
metallic nanoparticle.
9. The device of claim 1, wherein the quantum well element is an
embedded junction having a lower bandgap energy than the
junction.
10. The device of claim 2, wherein the hetero-junction comprises an
interface between two semiconductor materials selected from the
group consisting of a IV material, a III material, and a V
material.
11. The device of claim 10, wherein the interface comprises one of
the following, In0.53Ga0.47As/InP, GaAs0.51Sb0.49/InP,
In0.53Ga0.47As/In0.52A10.48As, GaAs0.51Sb0.49/In0.52A10.48As,
Ge/GaAs, Ge or GaAs/In0.5Ga0.5P or AlxGal-xAs, GaN/AlxGal-xN,
Si/GaN or GaP.
12. The device of claim 10, wherein the two semiconductor materials
are substantially lattice-matched.
13. The device of claim 2, wherein the hetero-junction comprises an
interface between two amorphous, nano-crystalline or
micro-crystalline semiconductor materials.
14. The device of claim 13, wherein the two semiconductor materials
are selected from the group consisting of a-Ge:H, a-SiGe:H,
a-SiC:H, a-Ge:H, a-SiNx:H, and a-SiOx:H.
15. The device of claim 1, wherein the programmed current-voltage
characteristics are non-volatile.
16. A method for obtaining a programmable response, the method
comprising: providing a semiconductor device with: a junction in
electrical communication with two terminals, the junction having a
built-in potential, a quantum well element proximate to the
junction that provides an energy well within a depletion region of
the junction, the energy well comprising one or more donor energy
states that support electron trapping and/or one or more acceptor
energy states that support hole trapping, the built-in potential of
the junction corresponding to a net polarity of holes and electrons
trapped by the one or more donor energy states and/or one or more
acceptor energy states, applying a programming signal to the
semiconductor device to cause a net polarity of holes and electron
to be trapped by the one or more donor energy states and/or one or
more acceptor energy states
17. The method of claim 16, further comprising applying a read
signal to the semiconductor device and detecting a response of the
semiconductor device to a read signal.
18. The method of claim 17, wherein the read signal is a voltage
signal and the response of the semiconductor device is a current
signal.
19. The method of claim 17, wherein the programming signal and the
read signal are voltage signals, and the read signal has a lower
amplitude than the programming signal.
20. The method of claim 16, wherein the programming signal is a
voltage signal.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates generally to the field of
semiconductor devices, and more particularly to programmable
semiconductor devices including memory devices.
[0002] Programmable devices are used for a variety of information
processing and storage applications. Typically, device footprint
and power consumption are key factors in determining which
applications are best served by a specific programmable technology.
A programmable technology with a small footprint and low power
consumption would be usable in a wide variety of applications.
SUMMARY
[0003] As disclosed herein, an apparatus with a programmable
response includes a semiconductor device with a junction formed
thereon, the junction having a built-in potential, a quantum well
element proximate to the junction that provides an energy well
within a depletion region of the junction. The energy well
comprises one or more donor energy states that support electron
trapping, and/or one or more acceptor energy states that support
hole trapping. The built-in potential of the junction is increased
or reduced depending on the net polarity of the trapped charge. The
semiconductor device may be a diode, a bipolar diode, a transistor,
or the like. A corresponding method for obtaining a programmable
response is also disclosed herein that includes providing the above
semiconductor device, applying a programming signal to the
semiconductor device, and detecting a response of the semiconductor
device to a read signal.
[0004] It should be noted that references throughout this
specification to features, advantages, or similar language do not
imply that all of the features and advantages that may be realized
with the present invention should be or are in any single
embodiment of the invention. Rather, language referring to the
features and advantages is understood to mean that a specific
feature, advantage, or characteristic described in connection with
an embodiment is included in at least one embodiment of the present
invention. Thus, discussion of the features, advantages, and
similar language, throughout this specification may, but do not
necessarily, refer to the same embodiment.
[0005] Furthermore, the described features, advantages, and
characteristics of the invention may be combined in any suitable
manner in one or more embodiments. One skilled in the relevant art
will recognize that the invention may be practiced without one or
more of the specific features or advantages of a particular
embodiment. In other instances, additional features and advantages
may be recognized in certain embodiments that may not be present in
all embodiments of the invention.
[0006] These features and advantages will become more fully
apparent from the following description and appended claims, or may
be learned by the practice of the invention as set forth
hereinafter.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIGS. 1a and 1b are cross-sectional illustrations depicting
various embodiments of a semiconductor device with a programmable
response;
[0008] FIGS. 2a, 2b, and 2c are energy band diagrams depicting a
depletion region energy well in accordance with one or more
embodiments disclosed herein;
[0009] FIGS. 3a-3d are perspective view illustrations depicting
various quantum well elements in accordance with one or more
embodiments disclosed herein;
[0010] FIGS. 4a and 4b are chemical bond diagrams depicting a
passivation process for an organic/inorganic hetero-junction in
accordance with one or more embodiments disclosed herein;
[0011] FIG. 5 is a response timing diagram in accordance with one
or more embodiments disclosed herein; and
[0012] FIG. 6 is a graph depicting an example current response in
accordance with one or more embodiments disclosed herein.
DETAILED DESCRIPTION
[0013] The embodiments disclosed herein provide memory and
processing capabilities with a small footprint and low power
consumption and are consequently usable in a wide variety of
applications. For example, neuromorphic computing is an emerging
application that requires high memory density with voltages as low
as 250 mV and currents as little as 10 nA. Resistive memory
elements called "memristors" or "neuristors" are often used to
mimic the memory function of neurons. Unfortunately, a diode
(connected in series with a resistive element) is often required to
use such devices properly, resulting in operating voltages and
footprints above those needed for successful neuromorphic
computing. The embodiments disclosed herein provide the protection
of a diode without requiring the higher operating voltages and
device footprints normally associated with a diode.
[0014] FIGS. 1a and 1b are cross-sectional illustrations depicting
various embodiments of a semiconductor device 100 (e.g., 100a and
100b) with a programmable response. As depicted, the semiconductor
device 100 includes one or more electrodes 110 (e.g., 110a, 110b,
and 110c), a junction 120, and one or more quantum elements 130.
FIG. 1a depicts a diode embodiment 100a, while FIG. 1b depicts a
field effect transistor embodiment 100b. As appreciated by one
skilled in the art, in the field-effect transistor embodiment of
FIG. 1b, the back-gate electrode 110a may be connected to one of
the two electrodes 110b or 110c to operate the device as a
diode-connected transistor, i.e. analogous to the two-terminal
diode device of FIG. 1a. In some embodiments, the back-gate
electrode 110a may be operated independently, i.e. the field-effect
transistor may be operated as a three-terminal device. The voltage
bias applied to the back-gate terminal can modulate the Fermi level
in the channel material 120n, thus modulating the free carrier
concentration in the channel material 120n.
[0015] In some embodiments, the source and drain electrodes 110b
and 110c of the field-effect transistor device of FIG. 1b are
"ambipolar" contacts, i.e., capable of injecting both electrons and
holes into the channel depending on the polarity of the voltage
applied to the back-gate terminal. In these embodiments, the
back-gate electrode can modulate the conductivity type in the
channel material 120n (i.e., n-type or p-type) depending on the
carrier type injected into channel as determined by the polarity of
the gate voltage. As a result, both electrons and holes can be
trapped into the quantum elements 130 from the channel 120n. In
some embodiments, ambipolar operation is advantageous in reducing
the operation voltage by facilitating the trapping of the carriers
of the opposite charge instead of, or in addition to, detrapping
the carriers of the same charge.
[0016] Connecting the back-gate electrode 110a to one of the two
electrodes 110b and 110c of an ambipolar field-effect transistor
results in a two-terminal device operating analogous to that of a
bipolar diode. In some embodiments, a bipolar diode is realized by
connecting two diode devices of the embodiment of FIG. 1a in
parallel to each other with their opposite terminals connected to
each other, i.e. the electrode 110a of the first diode device
connected to the electrode 110b of the second diode device and vice
versa.
[0017] The semiconductor device 100 may be formed from crystalline
or amorphous inorganic semiconductor materials, organic
semiconductor materials, or a combination thereof. The
semiconductor device 100 provides an adjustable (i.e.,
programmable) response, such as a selected voltage or current
response, in response to an input signal applied to the electrodes
110 (e.g., across electrodes 110a and 110b). Consequently, the
semiconductor device 100 can be used in a wide variety of
processing and memory applications.
[0018] The junction 120 may be formed proximate to a boundary
between an `n` region 120n and a `p` region 120p of the
semiconductor device 100. The `n` and `p` regions may be formed by
introducing electron donating impurities within the `n` region 120n
and electron accepting impurities (or molecules) within the `p`
region 120p. In some embodiments, the p and/or n-type conductivity
types may result from the presence of defects or other structural
properties rather than the presence of impurities in the
semiconductor materials. In some embodiments, the junction 120 may
be comprised of a p-i-n junction wherein an additional intrinsic
(i) region is disposed between regions having p-type and n-type
conductivity. In certain embodiments, where the junction 120 is
comprised of a p-i-n junction, the quantum elements 130 are
contained within the i region.
[0019] In some embodiments, the junction 120 is comprised of a
Schottky junction formed between a metal and a semiconductor. In
these embodiments, a high workfunction metal may be used instead of
a p-type semiconductor to form a junction with an n-type
semiconductor; and a low workfunction metal may be used instead of
an n-type semiconductor to form a junction with a p-type
semiconductor. In some embodiments, an additional semiconductor
layer may be disposed between the metal layer and the semiconductor
layer to form a "hybrid" Schottky junction. In some embodiments,
the additional semiconductor material is an organic material which
is substantially free of impurities.
[0020] The proximity of the region 120n to the region 120p creates
a depletion region 122 with a depletion width 124 (only shown in
FIG. 1b) that is essentially depleted of free carrier charges.
[0021] The creation of the depletion region 122 is due to the
formation of a built-in electric field corresponding to a built-in
voltage associated with the junction 120, also known as a `barrier
potential.` As known in the art, the built-in potential may be
dependent on the semiconductor materials used to create the
junction 120 including the doping levels of the n-type and p-type
impurities as well as the structural properties of those
materials.
[0022] Applying a bias voltage to the junction 120 may increase, or
reduce, the electric field across the depletion region and modulate
the depletion width 124 accordingly. The bias voltage is determined
by the voltage (difference) applied to the electrodes 110a and
110b.
[0023] The quantum well elements 130 are proximate to the depletion
region 122, provide an energy well (see FIGS. 2a-2c) within the
depletion region 122, and support charge trapping. In the depicted
embodiment, the quantum well elements 130 are metal nanoparticles.
In some embodiments, the quantum well elements 130 are lattice
defects formed proximate to the depletion region. In some
embodiments, the quantum well elements 130 are interfacial states
formed proximate to the depletion region--for example at the
interface between regions 120n and 120p. In other embodiments, the
quantum well elements 130 are embedded semiconductor elements
(e.g., quantum dots) with a lower band-gap energy than the
semiconductor device 100.
[0024] The amount of charge trapping may be adjusted by applying a
programming signal to the semiconductor device 100 via the
electrodes 110. The amount of charge trapping may change the
barrier potential of the junction, the depletion width 124, and the
resistance of the semiconductor device 100 to current flow.
Consequently, the response of the semiconductor device 100 may be
adjusted (programmed) by a programming signal.
[0025] FIGS. 2a, 2b, and 2c are energy band diagrams depicting a
depletion region energy well in accordance with one or more
embodiments disclosed herein. The energy well may include one or
more donor energy states 220 that support electron trapping and
thereby increase the built-in potential of the junction, and/or one
or more acceptor energy states 230 that support hole trapping and
thereby decrease the built-in potential of the junction.
[0026] As shown in FIG. 2a, an equilibrium Fermi level 240 (EF) for
the semiconductor device 100 may reside above the highest valence
band energy level 242 and below the lowest conduction band energy
level 244. As shown in FIG. 2b, when a positive bias is applied,
the electron quasi-Fermi level (EFN) moves up across and in the
vicinity of the depletion region 122, thus reducing the width of
the depletion region (e.g., the depletion width 124 in FIG. 1b).
The upward movement of the electron quasi-Fermi level (E.sub.FN)
results in electron trapping in the donor level E.sub.e, increasing
the built-in voltage of the junction accordingly. Therefore, when
the bias is removed (not shown), the increased built-in voltage
resulting from the trapped electrons in E.sub.e results in a
depletion region width wider than that shown in FIG. 2a, but
narrower than that shown in FIG. 2b.
[0027] In some embodiments, applying a positive voltage as
illustrated in FIG. 2b may also result in hole trapping in E.sub.h
(equivalent to electron detrapping from E.sub.h). This is due to
the reduction of the energy difference between E.sub.h and the
quasi-Fermi level for holes, E.sub.FP. As appreciated by one
skilled in the art, unless the density of electronics states at
E.sub.h is substantially higher than that at E.sub.e, and/or the
energy level E.sub.e is much shallower than E.sub.h, the electron
trapping in E.sub.e dominates electron detrapping from E.sub.h. The
change in the built-in potential will thus depend on the density of
electrons trapped in E.sub.e, minus the density of electrons
detrapped from E.sub.h (or equivalently the density of holes
trapped in E.sub.h), which may be referred to as the "net" density
of trapped electrons. In contrast, applying a negative bias as
shown in FIG. 2c results in "net" electron detrapping, thus
resulting in the decrease of the built-in potential and therefore a
depletion region width narrower than that shown in FIG. 2a, but
wider than that shown in FIG. 2c (not shown). In some embodiments,
when a negative bias is applied, the detrapping of electrons from
E.sub.e is facilitated via recombination with trapped holes in
E.sub.h, thus reducing the required bias voltage and/or the
required duration of the bias.
[0028] For simplicity, a `p` region quasi-Fermi level 248 is shown
to be substantially equal to the unbiased Fermi level 240, though
in practice they may be unequal. Furthermore, although the
quasi-Fermi level 246a is shown to go above the donor energy state
220 in FIG. 2b and the quasi-Fermi level 246b is shown to go below
the acceptor energy state 230 in FIG. 2c, it is not necessary that
the (electron or hole) quasi-Fermi levels to go above the donor
energy state 220 or below the acceptor energy state 230. In other
words, any change in the quasi-Fermi levels (e.g., 246a and 246b)
from the equilibrium Fermi level 240 may change the response of the
semiconductor device 100.
[0029] The change in the (quasi) Fermi level of the semiconductor
device 100 has a hysteresis effect that is dependent on the
previous state of the device. Consequently, the semiconductor
device 100 may be used for memory applications. In some
embodiments, the trapped electrons and holes escape over time
(e.g., exponentially decay) and the semiconductor device 100 may
return to the original depletion width and built-in voltage. In
other embodiments, the trapping of the electrons and holes is
substantially permanent. Therefore, the semiconductor device 100
may function as a volatile or non-volatile memory depending on the
permanence of the charge trapping. In the case of a Schottky
junction, a metal layer may be used instead of the highly-doped p+
or n+ regions.
[0030] FIGS. 3a-3d are perspective view illustrations depicting
various quantum well elements 300 (i.e., 300a, 300b, 300c and 300d)
in accordance with one or more embodiments disclosed herein. FIG.
3a depicts parallel quantum wells 300a that are inline with current
flow (preferred), FIG. 3b depicts quantum dots 300b, FIG. 3c
depicts parallel quantum wells 300c that are perpendicular with
current flow, and FIG. 3d depicts parallel quantum wells 300d that
are slanted relative to the current flow. While FIGS. 3a to 3d show
specific examples, one of skill in the art will appreciate that a
wide array of quantum well elements are possible (e.g., quantum
dots or metallic nanoparticles) that could be used for charge
trapping in order to change the built-in potential and overall
response of the semiconductor device 100.
[0031] Lattice-matched or nearly lattice-matched single-crystalline
materials may be used to form the quantum well elements with
respect to the channel and/or depletion region of the semiconductor
device 100. Examples of lattice-matched materials systems (as known
in the art, lattice mismatch may be tolerated to some extent)
include In0.53Ga0.47As/InP, GaAs0.51Sb0.49/InP,
In0.53Ga0.47As/In0.52A10.48As, GaAs0.51Sb0.49/In0.52A10.48As,
Ge/GaAs, Ge or GaAs/In0.5Ga0.5P or AlxGal-xAs, GaN/AlxGal-xN,
Si/GaN or GaP. Micro/nano-crystalline forms may be used as well.
Non-crystalline materials may also be used. Examples include:
a-Ge:H, a-SiGe:H, a-SiC:H, a-Ge:H, a-SiNx:H, a-SiOx:H or
combinations thereof. Non-crystalline materials need not be lattice
matched.
[0032] FIGS. 4a and 4b are chemical bond diagrams depicting a
passivation process for an organic/inorganic hetero-junction in
accordance with one or more embodiments disclosed herein. A
crystalline substrate 410 may have dangling bonds 420 that are
initially terminated with hydrogen, for example by dipping in a
dilute hydrofluoric acid solution. A passivation layer 430 may be
formed on the substrate that replaces the hydrogen atoms by an
organic chain 440 to form an organic passivation layer that
saturate the dangling bonds. Examples of an organic passivation
layer include an aromatic organic material, a monolayer of a
long-chain alcohol, and a monolayer of a long-chain thiol.
[0033] An organic material such as pentacene is disposed on the
passivation layer 440 using techniques known in the art, for
example by thermal evaporation, to form an organic/inorganic
hetero-junction (not shown). The use of an organic/inorganic
hetero-junction may eliminate the need for lattice matching and
reduce the complexity of manufacturing the semiconductor device 100
while retaining the benefits associated with inorganic
semiconductors such as their high mobility and good electrical
stability.
[0034] FIG. 5 is a response timing diagram in accordance with one
or more embodiments disclosed herein. As depicted, an initial write
signal 510a may be applied to the electrodes of the semiconductor
device 100 which results in a write current signal 520a and charge
trapping in the semiconductor device 100. Subsequently, a read
signal 510b (which could be identical to the write signal 510a) may
be applied to the input of the semiconductor device 100. The read
signal 510b results in a reduced current signal 520b due to the
change in the built-in voltage of the semiconductor device 100
produced by the write signal 510a. One of skill in the art will
appreciate that the reduced current signal 520b may be monitored to
determine whether a write signal had occurred within a given time
window. (The dashed line in FIG. 5 illustrates the shape of the
signal 520 if no write had occurred or if the standby time were
substantially longer than the retention time of the trapped charge
in the quantum elements). In some embodiments, a read signal with a
lower amplitude and/or shorter duration than the write signal may
be used to facilitate a "non-destructive" read. A non-destructive
read refers to a read operation which does not substantially change
the programmed status of the device.
[0035] FIG. 6 is a graph depicting an example current response in
accordance with one or more embodiments disclosed herein. The data
corresponding to the example current response was generated for a
prototype sample of the embodiment 100a that used Au nanoparticles
as the quantum elements 130, pentacene as layer 120p and Au as a
high workfunction electrode 110b. The response 600a shows the
current associated with an initial write signal. In the depicted
example, the write signal had an amplitude of 1V and duration of 10
.mu.s. Electrical charge trapped in the Au nanoparticles increased
the built-in voltage and reduced the diode current for a subsequent
read signal that was identical to the write signal. The response
600b shows the current associated with the read signal. The read
signal was applied after a standby time of 10 ms from the initial
write signal.
[0036] The charge trapping features of the present invention modify
the response characteristics of a semiconductor device such as the
current response or voltage response. Also, it should be noted that
the apparatuses disclosed herein may be integrated with additional
circuitry within integrated circuit chips. The resulting integrated
circuit chips can be distributed by the fabricator in raw wafer
form (that is, as a single wafer that has multiple unpackaged
chips), as a bare die, or in a packaged form. In the latter case,
the chip is mounted in a single chip package (such as a plastic
carrier, with leads that are affixed to a motherboard or other
higher level carrier) or in a multichip package (such as a ceramic
carrier that has either or both surface interconnections or buried
interconnections). In any case, the chip is then integrated with
other chips, discrete circuit elements, and/or other signal
processing devices as part of either (a) an intermediate product,
such as a motherboard, or (b) an end product. The end product can
be any product that includes integrated circuit chips, ranging from
toys and other low-end applications to advanced computer products
having a display, a keyboard or other input device, and a central
processor.
[0037] It should be noted that this description is not intended to
limit the invention. On the contrary, the embodiments presented are
intended to cover some of the alternatives, modifications, and
equivalents, which are included in the spirit and scope of the
invention as defined by the appended claims. Further, in the
detailed description of the disclosed embodiments, numerous
specific details are set forth in order to provide a comprehensive
understanding of the claimed invention. However, one skilled in the
art would understand that various embodiments may be practiced
without such specific details.
[0038] Although the features and elements of the embodiments
disclosed herein are described in particular combinations, each
feature or element can be used alone without the other features and
elements of the embodiments or in various combinations with or
without other features and elements disclosed herein.
[0039] This written description uses examples of the subject matter
disclosed to enable any person skilled in the art to practice the
same, including making and using any devices or systems and
performing any incorporated methods. The patentable scope of the
subject matter is defined by the claims, and may include other
examples that occur to those skilled in the art. Such other
examples are intended to be within the scope of the claims.
* * * * *