U.S. patent application number 15/067298 was filed with the patent office on 2016-07-07 for solid-state image sensing device and camera system with divided pixels.
The applicant listed for this patent is Sony Corporation. Invention is credited to Eiichi Funatsu, Masashi Nakata.
Application Number | 20160197117 15/067298 |
Document ID | / |
Family ID | 46019298 |
Filed Date | 2016-07-07 |
United States Patent
Application |
20160197117 |
Kind Code |
A1 |
Nakata; Masashi ; et
al. |
July 7, 2016 |
SOLID-STATE IMAGE SENSING DEVICE AND CAMERA SYSTEM WITH DIVIDED
PIXELS
Abstract
A solid-state image sensing device includes: a pixel part in
which pixels are arranged in a matrix; and a pixel signal readout
part including an AD conversion part that analog-digital
(AD)-converts a pixel signal read out from the pixel part. Each of
the adjacent pixels or one of the pixels of the pixel part is
formed as divided pixels divided into regions with different
photosensitivity or amounts of accumulated charge, photosensitivity
or exposure time conditions are set for the divided pixels and the
photosensitivity or exposure time conditions of the divided pixels
provided to be opposed in diagonal directions are set to the same
conditions, the pixel signal readout part reads out divided pixel
signals of the respective divided pixels of the pixel, and the AD
conversion part obtains a pixel signal of one pixel by
AD-converting the respective read out divided pixel signals and
adding the signals.
Inventors: |
Nakata; Masashi; (Kanagawa,
JP) ; Funatsu; Eiichi; (Tokyo, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Sony Corporation |
Tokyo |
|
JP |
|
|
Family ID: |
46019298 |
Appl. No.: |
15/067298 |
Filed: |
March 11, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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14529573 |
Oct 31, 2014 |
9319606 |
|
|
15067298 |
|
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|
13317017 |
Oct 7, 2011 |
8922685 |
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14529573 |
|
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Current U.S.
Class: |
257/225 |
Current CPC
Class: |
H04N 5/378 20130101;
H01L 27/14636 20130101; H01L 27/1461 20130101; H04N 9/045 20130101;
H01L 27/14645 20130101; H04N 5/35563 20130101; H04N 5/369 20130101;
H01L 27/14812 20130101; H04N 5/35554 20130101; H04N 5/37457
20130101; H04N 5/37455 20130101; H01L 27/14607 20130101; H01L
27/14612 20130101; H04N 9/04557 20180801 |
International
Class: |
H01L 27/146 20060101
H01L027/146; H01L 27/148 20060101 H01L027/148 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 8, 2010 |
JP |
2010-250328 |
Claims
1. An imaging device comprising a plurality of pixel groups, at
least one of the pixel groups including: a first floating
diffusion; a second floating diffusion; a third floating diffusion;
a fourth floating diffusion; a first photoelectric conversion
element; a second photoelectric conversion element; a third
photoelectric conversion element; a fourth photoelectric conversion
element; a first transfer transistor connected between the first
photoelectric conversion element and the first floating diffusion;
a second transfer transistor connected between the second
photoelectric conversion element and the second floating diffusion;
a third transfer transistor connected between the third
photoelectric conversion element and the third floating diffusion;
a fourth transfer transistor connected between the fourth
photoelectric conversion element and the fourth floating diffusion;
and an amplifying transistor, wherein a gate of the amplifying
transistor is connected to the first floating diffusion, the second
floating diffusion, the third floating diffusion, and the fourth
floating diffusion.
2. The imaging device according to the claim 1, wherein the one of
the pixel groups further including: a first selection transistor
connected between the gate of the amplifying transistor and the
first floating diffusion; a second selection transistor connected
between the gate of the amplifying transistor and the second
floating diffusion; a third selection transistor connected between
the gate of the amplifying transistor and the third floating
diffusion; and a fourth selection transistor connected between the
ate of the amplifying transistor and the fourth floating
diffusion.
3. The imaging device according to the claim 1, wherein the first
and the fourth photoelectric conversion elements are arranged along
a first direction, and wherein the second and the third
photoelectric conversion elements are arranged along a second
direction,
4. The imaging device according to the claim 1, wherein the first,
the second, the third, and the fourth photoelectric conversion
elements are arranged along a first direction.
5. An imaging device comprising a plurality of pixel groups, at
least one of the pixel groups including: a first floating
diffusion; a second floating diffusion; a first photoelectric
conversion element; a second photoelectric conversion element; a
first transfer transistor connected between the first photoelectric
conversion element and the first floating diffusion; a second
transfer transistor connected between the second photoelectric
conversion element and the second floating diffusion; and an
amplifying transistor, wherein a gate of the amplifying transistor
is connected to the first floating diffusion and the second
floating diffusion different from the first direction.
6. The imaging device according to the claim 5, wherein the one of
the pixel groups further including: a first selection transistor
connected between the gate of the amplifying transistor and the
first floating diffusion; and a second selection transistor
connected between the gate of the amplifying transistor and the
second floating diffusion.
7. An imaging device comprising a plurality of pixel groups, at
least one of the pixel groups including: a first floating
diffusion; a second floating diffusion; a first photoelectric
conversion element; a second photoelectric conversion element; a
third photoelectric conversion element; a fourth photoelectric
conversion element; a first transfer transistor connected between
the first photoelectric conversion element and the first floating
diffusion; a second transfer transistor connected between the
second photoelectric conversion element and the first floating
diffusion; a third transfer transistor connected between the third
photoelectric conversion element and the second floating diffusion;
a fourth transfer transistor connected between the fourth
photoelectric conversion element and the second floating diffusion;
and an amplifying transistor, wherein a gate of the amplifying
transistor is connected to the first floating diffusion and the
second floating diffusion.
8. The imaging device according to the claim 7, wherein the one of
the pixel groups further including: a first selection transistor
connected between the gate of the amplifying transistor and the
first floating diffusion; and a second selection transistor
connected between the gate of the amplifying transistor and the
second floating diffusion.
9. The imaging device according to the claim 7, wherein the first
and the fourth photoelectric conversion elements are arranged along
a first direction, and wherein the second and the third
photoelectric conversion elements are arranged along a second
direction different from the first direction.
10. The imaging device according to the claim 7, wherein the first,
the second, the third, and the fourth photoelectric conversion
elements are arranged along a first direction.
11. The imaging device according to the claim 7, wherein the one of
the pixel groups further including: a first reset transistor
connected to the first floating diffusion; and a second reset
transistor connected to the second floating diffusion.
Description
CROSS REFERENCES TO RELATED APPLICATIONS
[0001] This is a Continuation of application Ser. No. 14/529,573,
filed on Oct. 31, 2014, which is a Continuation of application Ser.
No. 13/317,017, filed on Oct. 7, 2011. The present invention
contains subject matter related to Japanese Patent Application JP
2010-250328, filed in the Japanese Patent Office on Nov. 8, 2010,
the entire contents of which are incorporated herein by
reference.
FIELD
[0002] The present disclosure relates to a solid-state image
sensing device represented by a CCD or CMOS sensor and a camera
system.
BACKGROUND
[0003] It has been desired to realize a solid-state image sensing
device having a wide dynamic range that may enable shooting of
details without losing details of high-brightness information even
in backlit shooting with illumination light of headlights of cars
and ball game grounds or sunlight or bringing an object image in
the low-brightness part too much darker.
[0004] Under the circumstances, technologies of expanding dynamic
ranges with respect to solid-state image sensing device such as
CCDs are disclosed in Patent Document 1 (Japanese Patent No.
2125710), Patent Document 2 (JP-A-03-117281), Patent Document 3
(JP-A-09-205589), Patent Document 4 (JP-A-2004-320119), Patent
Document 5 (JP-A-2005-278135), Patent Document 6
(JP-A-2010-284213), etc.
[0005] Patent Document 1 shows an example of expanding a dynamic
range of a CCD by providing two or more plural regions (cells)
having different sensitivity characteristics within one pixel of
the CCD or the like to provide knee characteristics that
input/output characteristics change in a stepwise fashion.
[0006] The knee characteristics refer to a characteristic curve
shown by a relationship of the output current to the amount of
exposure takes smaller values in a high-input region than those in
a low-input region, and are often referred to as a high-brightness
signal compression technology.
[0007] As methods of changing the photosensitivity of the
photosensitive region (cell), for example, changing the aperture
ratio of the device, providing an optical filter (ND filter),
changing impurity concentration, etc. are described.
[0008] According to Patent Document 1, the example is applicable to
an image sensing device of XY address-type other than the CCD,
however, there is no detailed description.
[0009] Patent Document 2 discloses an example of realizing higher
dynamic range without losing details with highlight of a light
valve or the like using adjacent pixels in a photosensitive pixel
cell of a CCD or cells with different photosensitivity
characteristics as a pair and adding signal charge of the
respective cells within one pixel using it as signal charge of the
pixel.
[0010] In this case, as means for changing photosensitivity, cells
with different pixel areas are paired, for example.
[0011] Patent Document 3 similarly divides one pixel of a
sensitivity pixel cell of a CCD into two different regions, and
mixes signal charge of the regions with different sensitivity of
the same pixel in a vertical register and vertically transfers it.
Further, in the technology, a video signal is formed by sorting the
signal charge with different sensitivity into two horizontal
transfer gates using a sorting gate, and clipping the signal at the
high-sensitivity side using an external signal processing circuit
and adding it to the signal at the low-sensitivity side.
[0012] In this case, the characteristic graph of the video signal
output to the amount of incident light is a line graph, and the
gradient is steep at the high-sensitivity side (low-illuminance
side) and the gradient is mild at the low-sensitivity side
(high-illuminance side).
[0013] Patent Document 4 discloses an improvement method, in an
image sensing device including high-sensitivity imaging cells and
low-sensitivity imaging cells, for a problem that RAW image data
volume (raw data) becomes larger with data of both cells.
[0014] Specifically, whether or not recording of image information
of the high-brightness part is necessary is automatically
determined by analyzing shot image information. If the
determination is "YES", the RAW image data of the high-brightness
part is recorded together with the information of the
low-brightness part. If the determination is "NO", the information
of the high-brightness part is not recorded, but only the RAW image
data of the low-brightness part is recorded.
[0015] One pixel is formed by combining a main photosensitive pixel
cell (with larger area and higher sensitivity: mainly using the
center part of a microlens) and a sub-photosensitive pixel cell
(with smaller area and lower sensitivity: provided at the edge side
of the microlens).
[0016] Patent Document 5 discloses a CMOS image sensor including a
column-parallel ADC having a comparator and an up/down counter. The
CMOS image sensor can execute addition operation of pixel digital
values over plural rows without additional circuits such as an
adder and a line memory device.
[0017] However, compared to the pixel having an area as a total of
all areas of target pixels in the case of the divided pixel
addition, in the case of division, ineffective regions (dead
spaces) that do not directly contribute to photosensitivity are
produced in signal processing.
[0018] Accordingly, the areas of the divided individual cells are
smaller than in the case of simple division into four, the number
of saturated electrons decreases compared to the former case and
the Shot noise relatively increases, and S/N of the divided
individual cells is deteriorated.
[0019] Since the Shot noise is also added at each time of addition,
S/N of the result of the divisional addition is deteriorated.
[0020] Further, addition processing of pixel signals is analog
signal addition and the sensitivity is different with respect to
each pixel, and thus, there are problems that the saturation values
vary and the break point positions vary.
[0021] Furthermore, in the case of digital addition, it is
necessary to provide a memory outside of the sensor.
[0022] That is, in the existing addition method of dividing one
pixel cell into two or more plural pixel cells with different
sensitivity or accumulation times and measuring the sensitivity as
the amount of saturation charge Qs of the pixels, the amount of
saturation charge Qs varies with respect to each pixel.
Accordingly, the addition result varies with respect to each pixel
for the same amount of light.
[0023] In other words, in the sensitivity curves (line graphs) with
the amount of incident light as a horizontal axis and the amount of
saturation charge Qs as a vertical axis, the break point positions
(vertical axis) vary at the divided pixel cell addition points
(horizontal axis).
[0024] Accordingly, Patent Document 6 suggests a method of
realizing a wide dynamic range by applying a technology of
regarding four pixels as one pixel and varying respective
accumulation times of the four pixels. In this technology, four
signals are added.
[0025] FIG. 1 is a diagram for explanation of a method of realizing
a wide dynamic range by varying respective accumulation times of
four pixels.
[0026] In the method, pixels formed by respectively dividing single
colors of R, G, B into four are used.
[0027] Further, as shown by signs A to D in G (green) on the upper
left of FIG. 1 as an example, a structure having four pixels with
different photosensitivity or amounts of exposure is assumed. In
FIG. 1, FD shows a floating diffusion part.
[0028] Furthermore, by summing the outputs of the four pixels, a
wide dynamic range is realized.
[0029] According to the technology, divided pixel addition without
variations in the number of output electrons of pixels may be
realized, and the wide dynamic range in which the sensitivity is
higher in the lower amount of incident light, the sensitivity is
lower with the higher incident light, and the output is not
saturated can be provided.
SUMMARY
[0030] However, the technology disclosed in Patent Document 6 has
the following disadvantages.
[0031] The centers of gravity are different among the respective
pixels and correction of shifts of the centers of gravity may be
necessary.
[0032] As shown in FIG. 2, depending on the computation when the
output signal is returned to be linear as from line X to line Y,
S/N may not be maximized.
[0033] The problem of shifts of the centers of gravity will be
explained further in detail.
[0034] When sensitivity/exposure is varied among four pixels, the
centers of gravity vary among four pixels and the correction of
shifts of the centers of gravity is necessary.
[0035] When the sensitivity/exposure is simply varied between two
pixels, the centers of gravity vary among two pixels and the
correction of shifts of the centers of gravity is also
necessary.
[0036] Due to the difference in the centers of gravity, there may
be the following disadvantages.
[0037] If the centers of gravity are different, the correction of
shifts of the centers of gravity is necessary, and additionally,
for example, when an object in the lateral direction like electric
cables is shot using pixels with sensitivity/accumulation divided
in the vertical direction as shown in FIG. 3, images obtained by
the upper pixels and the lower pixels may be varied.
[0038] This may cause generation of false color or noise.
[0039] Next, the problem of S/N will be further described in
detail.
[0040] When signals are formed from four pixels having different
sensitivity/amounts of exposure, it is necessary that the final
output value is linear relative to the amount of light as shown by
Y in FIG. 2.
[0041] It is necessary that the obtained raw (Raw) signal value is
made linear as shown by the line Y because the line is folded in
the regions RG1 to RG4 in FIG. 2.
[0042] As a computation method in this regard, the following
example is conceivable.
Region "RG1" Expression: y=ax
Region "RG2" Expression: y'=cx+d [0043] (x=obtained signal value,
y=final output)
[0044] In this case, to superimpose the "RG1" Expression on the
"RG2" Expression, the "RG2" Expression may be made linear with
respect to the "RG1" Expression by subtracting intercept d from
"RG2" Expression for setting the intercept to zero, and multiplying
by a/c.
[0045] However, in consideration of S (Signal)/N (Noise), regarding
the interception d subtracted in this case, only S (Signal) is
subtracted and both Signal and Noise are multiplied by a/c for
multiplication (because Subtraction may be impossible for
Noise).
[0046] Accordingly, S/N is largely deteriorated compared to that
before computation.
[0047] Thus, it is desirable to provide a solid-state image sensing
device and a camera system that may prevent shifts of the centers
of gravity, maximize S/N, realize divided pixel addition without
variations in the number of output electrons of pixels with respect
to the amount of incident light, and have a wide dynamic range in
which sensitivity is higher with a lower amount of incident light
and sensitivity is lower with high incident light, and the output
is not saturated.
[0048] A solid-state image sensing device according to one
embodiment of the present disclosure includes a pixel part in which
plural pixels are arranged in a matrix, and a pixel signal readout
part including an AD conversion part that analog-digital
(AD)-converts a pixel signal read out from the pixel part, wherein
each of the plural adjacent pixels or one of the pixels of the
pixel part is formed as plural divided pixels divided into regions
with different photosensitivity or amounts of accumulated charge,
plural photosensitivity or exposure time conditions are set for the
plural divided pixels and the photosensitivity or exposure time
conditions of the divided pixels provided to be opposed in diagonal
directions are set to the same conditions, the pixel signal readout
part reads out divided pixel signals of the respective divided
pixels of the pixel, and the AD conversion part obtains a pixel
signal of one pixel by AD-converting the respective read out
divided pixel signals and adding the signals.
[0049] A solid-state image sensing device according to another
embodiment of the present disclosure includes a pixel part in which
plural pixels are arranged in a matrix, a pixel signal readout part
including an AD conversion part that analog-digital (AD)-converts a
pixel signal read out from the pixel part, and a processing part
that obtains a final output by obtaining an optimal multiplying
factor from an output value of the pixel signal readout part and
multiplying the output value by the obtained multiplying factor,
wherein each of the plural adjacent pixels or one of the pixels of
the pixel part is formed as plural divided pixels divided into
regions with different photosensitivity or amounts of accumulated
charge, the pixel signal readout part reads out divided pixel
signals of the respective divided pixels of the pixel, and the AD
conversion part obtains a pixel signal of one pixel by
AD-converting the respective read out divided pixel signals and
adding the signals.
[0050] A camera system according to still another embodiment of the
present disclosure includes a solid-state image sensing device, and
an optical system that forms an object image on the solid-state
image sensing device, the solid-state image sensing device
including a pixel part in which plural pixels are arranged in a
matrix, and a pixel signal readout part including an AD conversion
part that analog-digital (AD)-converts a pixel signal read out from
the pixel part, wherein each of the plural adjacent pixels or one
of the pixels of the pixel part is formed as plural divided pixels
divided into regions with different photosensitivity or amounts of
accumulated charge, plural photosensitivity or exposure time
conditions are set for the plural divided pixels and the
photosensitivity or exposure time conditions of the divided pixels
provided to be opposed in diagonal directions are set to the same
conditions, the pixel signal readout part reads out divided pixel
signals of the respective divided pixels of the pixel, and the AD
conversion part obtains a pixel signal of one pixel by
AD-converting the respective read out divided pixel signals and
adding the signals.
[0051] A camera system according to yet another embodiment of the
present disclosure includes a solid-state image sensing device, and
an optical system that forms an object image on the solid-state
image sensing device, the solid-state image sensing device
including a pixel part in which plural pixels are arranged in a
matrix, a pixel signal readout part including an AD conversion part
that analog-digital (AD)-converts a pixel signal read out from the
pixel part, and a processing part that obtains a final output by
obtaining an optimal multiplying factor from an output value of the
pixel signal readout part and multiplying the output value by the
obtained multiplying factor, wherein each of the plural adjacent
pixels or one of the pixels of the pixel part is formed as plural
divided pixels divided into regions with different photosensitivity
or amounts of accumulated charge, the pixel signal readout part
reads out divided pixel signals of the respective divided pixels of
the pixel, and the AD conversion part obtains a pixel signal of one
pixel by AD-converting the respective read out divided pixel
signals and adding the signals.
[0052] According to the embodiments of the present disclosure,
shifts of the centers of gravity can be prevented and S/N can be
maximized, and divided pixel addition without variations in the
number of output electrons of the pixels with respect to the amount
of incident light may be realized. As a result, the wide dynamic
range in which the sensitivity is higher in the lower amount of
incident light, the sensitivity is lower with the higher incident
light, and the output is not saturated can be provided.
BRIEF DESCRIPTION OF THE DRAWINGS
[0053] FIG. 1 is a diagram for explanation of a method of realizing
a wide dynamic range by varying respective accumulation times of
four pixels.
[0054] FIG. 2 is a diagram showing relationships between raw (Raw)
output and final output after computation for consideration of a
problem of S/N in the method of realizing a wide dynamic range by
varying respective accumulation times of four pixels.
[0055] FIG. 3 is a diagram for consideration of a problem due to
variations of centers of gravity in the method of realizing a wide
dynamic range by varying respective accumulation times of four
pixels.
[0056] FIG. 4 is a diagram showing a configuration example of a
CMOS image sensor (solid-state image sensing device) according to
an embodiment of the present disclosure.
[0057] FIG. 5 is a diagram showing Bayer arrangement as a pixel
arrangement example.
[0058] FIG. 6 is a conceptual diagram of pixel division according
to the embodiment.
[0059] FIG. 7 is a diagram showing locations where addition
processing is performed in the solid-state image sensing device
(CMOS image sensor) with column-parallel ADC in FIG. 1.
[0060] FIG. 8 is a diagram for explanation of a two-pixel diagonal
method as the first measure for shifts of the centers of gravity
according to the embodiment.
[0061] FIG. 9 is a diagram for explanation of a two-pixel diagonal
Gr/Gb inversion method as the second measure for shifts of the
centers of gravity according to the embodiment.
[0062] FIG. 10 is a diagram for explanation of an application
example of the two-pixel diagonal Gr/Gb inversion method as the
second measure for shifts of the centers of gravity according to
the embodiment.
[0063] FIG. 11 is a diagram for explanation of measures for S/N
according to the embodiment.
[0064] FIG. 12 is a diagram showing an example of a divided pixel
of the CMOS image sensor including four transistors according to
the embodiment.
[0065] FIG. 13 is a circuit diagram showing an example of the
plural divided pixels sharing floating diffusion parts, amplifying
transistors, selection transistors, reset transistors.
[0066] FIG. 14 is a circuit diagram showing an example of the
plural divided pixels individually having floating diffusion parts
and sharing an amplifying transistors.
[0067] FIG. 15 is a circuit diagram showing an example of plural
divided pixels grouped and sharing floating diffusion parts in the
respective groups and sharing an amplifying transistor in the
pixels as a whole.
[0068] FIGS. 16A to 16D are diagrams for explanation of methods of
division into plural regions within a surface of one pixel.
[0069] FIGS. 17A and 17B are diagrams schematically showing
configuration examples of column AD conversion type CMOS image
sensor circuits related to divided pixel addition.
[0070] FIG. 18 is a diagram showing a configuration example of a
solid-state image sensing device corresponding to a CCD sensor
according to the embodiment of the present disclosure.
[0071] FIG. 19 is a diagram showing an example of a configuration
of a camera system to which the solid-state image sensing device
according to the embodiment of the present disclosure is
applied.
DETAILED DESCRIPTION
[0072] As below, embodiments of the present disclosure will be
explained with reference to the drawings.
[0073] The explanation will be made in the following order.
1. Overall Schematic Configuration of Solid-state Image Sensing
Device
2. Measures for Shifts of Centers of Gravity
3. Measures for S/N
4. Configuration Example of Divided Pixel
5. Configuration Example of Camera System
<1. Overall Schematic Configuration of Solid-State Image Sensing
Device>
[0074] FIG. 4 is a block diagram showing a configuration example of
a solid-state image sensing device (CMOS image sensor) with column
parallel ADC according to an embodiment of the present
disclosure.
[0075] The disclosure is applicable not only to the CMOS image
sensor but to a CCD. Here, the CMOS image sensor will be explained
as an example.
[0076] The solid-state image sensing device 100 has a pixel part
110, a vertical scan circuit 120, a horizontal transfer scan
circuit 130, a timing control circuit 140, and an analog digital
converter (ADC) group 150 as shown in FIG. 4.
[0077] The solid-state image sensing device 100 further has a
digital-analog converter (DAC) 160, an amplifier circuit (S/A) 170,
a signal processing circuit 180, and a horizontal transfer line
190.
[0078] The vertical scan circuit 120, the horizontal transfer scan
circuit 130, the timing control circuit 140, the ADC group 150, and
the DAC 160 form a pixel signal readout part.
[0079] The pixel part 110 includes plural pixels arranged in a
matrix.
[0080] The pixel part 110 employs Bayer arrangement as shown in
FIG. 2, for example, as its pixel arrangement.
[0081] In the pixel part 110 of the embodiment, one pixel is
divided into divided pixel cells DPC containing photoelectric
conversion elements formed by photodiodes.
[0082] Specifically, in the solid-state image sensing device (CMOS
image sensor) with column parallel ADC 100, one pixel under color
filters of the same color in the Bayer arrangement is divided into
two or more plural divided pixel cells DPC with different
sensitivity or accumulation times.
[0083] Further, in the embodiment, as will be described later, for
prevention of shifts of the centers of gravity, a structure under
two conditions of exposure time conditions (or photosensitivity)
with pixels opposed to each other in the diagonal direction having
the same exposure time (or photosensitivity) is employed.
[0084] Further, in the embodiment, to maximize S/N, a configuration
in which, when the signal is returned to be linear, the signal is
not directly obtained by computation, but the final output is
obtained by once calculating an optimal multiplying factor from a
raw (Raw) output value and multiplying the raw (Raw) output value
by the multiplying factor is employed.
[0085] Furthermore, when the pixel signal is AD-converted and
output in the column direction, the AD-conversion is performed
after addition of the output divided pixel signal of the divided
pixel. In this regard, the input range to the AD-conversion part is
clipped to be constantly equal to or less than the saturated output
voltage of each pixel so that the output value of each pixel may be
certainly a specific digital value.
[0086] In the following explanation, an example in which one pixel
DPC is divided into four divided pixel cells DPC-A to DPC-D will be
explained.
[0087] FIG. 6 is a conceptual diagram of pixel division according
to the embodiment of the present disclosure.
[0088] FIG. 6 shows the case where a G (green) pixel PCG is divided
into four pixels of DPC-A, DPC-B, DPC-C, DPC-D.
[0089] In FIG. 6, a division method in the case of Bayer
arrangement is shown, and, in the example in which one pixel under
the filters of the same color is divided into four, sensitivity and
accumulation times are different in the divided pixels as
below.
[0090] That is, for prevention of shifts of the centers of gravity,
there are two conditions of exposure time conditions (or
photosensitivity) and pixels opposed to each other in the diagonal
directions have the same exposure times (or photosensitivity).
[0091] For example, in the example of the G pixel in FIG. 6, the
pixels opposed to each other in the diagonal directions DPC-A and
DPC-C, DPC-B and DPC-D have the same exposure times.
[0092] The configurations, division forms, etc. of the pixels and
divided pixels in the pixel part 110 will be described later in
detail.
[0093] Further, for example, the solid-state image sensing device
100 of the embodiment time-sequentially sends out divided pixel
signals amplified within the pixel to the vertical signal line and
executes AD-conversion in the AD-convertor (AD-conversion part) of
the ADC group 150 provided in a column pixel signal readout
part.
[0094] Then, when performing the AD-conversion operation of the
second divided pixel signal, the solid-state image sensing device
100 adds the first AD-converted value and executes the
AD-conversion operation of the second divided pixel signal.
[0095] Then, when performing the AD-conversion operation of the
third divided pixel signal, the solid-state image sensing device
100 adds the second AD-converted value and executes the
AD-conversion operation of the third divided pixel signal.
[0096] Then, when performing AD-conversion operation of the fourth
divided pixel signal, the solid-state image sensing device 100 adds
the third AD-converted value and executes the AD-conversion
operation of the fourth divided pixel signal.
[0097] The solid-state image sensing device of the embodiment
employs a divided pixel addition method of sequentially adding the
pixel signals of the pixels divided into plural parts by the AD
converter provided in the column part in this manner is
employed.
[0098] In the solid-state image sensing device 100, as control
circuits for sequentially reading out the signals of the pixel part
110, the timing control circuit 140 that generates internal clocks,
the vertical scan circuit 120 that controls row addresses and row
scanning, and the horizontal transfer scan circuit 130 that
controls column addresses and column scanning are provided.
[0099] The ADC group 150 has a comparator 151 that compares a
reference voltage Vslop as a ramp waveform in which the reference
voltage generated by the DAC 160 is changed in a stepwise manner
with analog signals (potentials Vsl) obtained from pixels with
respect to each row via the vertical signal line LVS.
[0100] In the ADC group 150, ADCs each having an up-down counter
(hereinafter, simply referred to as "counter") 152 that counts a
comparison time and a latch 153 that holds a count result are
arranged in plural columns.
[0101] The ADC group 150 has an n-bit digital signal conversion
function and is provided with respect to each vertical signal line
(column line), and thereby, a column-parallel AD block is
formed.
[0102] The outputs of the respective latches 153 are connected to
the horizontal transfer line 190 having a 2n-bit width, for
example.
[0103] Further, 2n amplifier circuits 170 corresponding to the
horizontal transfer line 190 and the signal processing circuit 180
are provided.
[0104] In the ADC group 150, the analog signal (potential Vsl) read
out to the vertical signal line LVS is compared with the reference
voltage Vslop (a slope waveform that changes to a linear shape with
a certain gradient) in the comparator (comparator) 151 provided
with respect to each column.
[0105] In this regard, the counter 152 provided with respect to
each column similarly to the comparator 151 operates and the
potential Vslop having the ramp waveform and the counter value
change in one-to-one correspondence, and thereby, the potential
(analog signal) Vsl of the vertical signal line LVS is converted
into the digital signal.
[0106] The change of the reference potential Vslop is conversion of
change in voltage into change in time, and the ADC performs
conversion into a digital value by counting the times in a certain
period (clock).
[0107] Further, when the analog electric signal Vsl and the
reference voltage Vslop intersect, the output of the comparator 151
is inverted, the input clock of the counter 152 is stopped or the
clock with its input having been stopped is input to the counter
152, and thereby, one AD conversion is completed.
[0108] For example, by continuously performing the up and down
count processing of the counter in the number of divided pixel
signals without resetting the counter, the divided pixel addition
as addition by the above described AD convertor is realized.
[0109] FIG. 7 is a diagram showing locations where addition
processing is performed in the solid-state image sensing device
(CMOS image sensor) with column-parallel ADC in FIG. 4.
[0110] In FIG. 7, the locations surrounded by broken lines are
locations where addition processing is actually performed. A thin
broken line is an existing location and a thick broken line is a
region according to the embodiment of the present disclosure.
[0111] The method of addition signal processing of the divided
pixels that has been known is performed in the signal processing
part of DSP or the like.
[0112] On the other hand, in the embodiment, as described above,
addition processing is sequentially performed while AD conversion
of the four divided pixel signal in the counter 152 at AD
conversion.
[0113] That is, the divided pixel signals amplified within the
pixel are time-sequentially sent out to the vertical signal line
VSL, and AD conversion is executed by the AD converter
(AD-conversion part) of the ADC group 150 provided in the column
pixel signal readout part.
[0114] Then, in each ADC of the ADC group 150, when the
AD-conversion operation of the second divided pixel signal is
performed, the first AD-converted value is added and the
AD-conversion operation of the second divided pixel signal is
executed.
[0115] Then, in each ADC of the ADC group 150, when the
AD-conversion operation of the third divided pixel signal is
performed, the second AD-converted value is added and the
AD-conversion operation of the third divided pixel signal is
executed.
[0116] Then, in each ADC of the ADC group 150, when the
AD-conversion operation of the fourth divided pixel signal is
performed, the third AD-converted value is added and the
AD-conversion operation of the fourth divided pixel signal is
executed.
[0117] After the above described AD conversion period is ended, by
the horizontal transfer scan circuit 130, the data held in the
latches 153 are transferred to the horizontal transfer line 190,
input to the signal processing circuit 180 via the amplifier
circuits 170, and thereby, a two-dimensional image is generated by
predetermined signal processing.
[0118] As above, the basic configuration and function in the
embodiment of the present disclosure have been explained.
[0119] As below, the configurations and division forms of the
pixels and divided pixels, the measures for shifts of the centers
of gravity, the measures for S/N, divided pixel addition
processing, etc. as characteristic configurations of the embodiment
will be explained in further detail.
[0120] First, the measures for shifts of the centers of gravity and
the measures for S/N as characteristic configurations of the
embodiment will be described.
[0121] In the case where photosensitivity and amounts of exposure
are different among the four pixels DPC-A to DPC-D of the
respective pixels of RGB, the centers of gravity are different
among the respective pixels, and correction of shifts of the
centers of gravity may be necessary.
[0122] As shown in FIG. 2, depending on the computation when the
output signal is returned to be linear as from line X to line Y,
S/N may not be maximized.
[0123] Accordingly, in the embodiment, the measures for shifts of
the centers of gravity and the measures for S/N described as below
are taken.
<2. Measures for Shifts of Centers of Gravity>
[0124] FIG. 8 is a diagram for explanation of a two-pixel diagonal
method as the first measure for shifts of the centers of gravity
according to the embodiment.
[0125] In the two-pixel diagonal method of FIG. 8, two kinds of
conditions of photosensitivity/amounts of exposure are set so that
the respective diagonal pixels may have the same conditions.
[0126] In the example of FIG. 8, in a Gr pixel, the first condition
is such that the photosensitivity/amounts of exposure of the upper
left pixel DPC-A and the lower right pixel DPC-C opposed to each
other in the diagonal direction are the same. Similarly, the second
condition is such that the photosensitivity/amounts of exposure of
the upper right pixel DPC-B and the lower left pixel DPC-D opposed
to each other in the diagonal direction are the same.
[0127] The conditions are the same with respect to other Gb pixels,
R pixels, and B pixels.
[0128] Regarding these Gr pixel, Gb pixels, R pixels, and B pixels,
all of the centers of gravity of the signals to be finally added in
the FD are collected to the center of the four pixels, and the
correction of shifts of the centers of gravity is unnecessary and
strong for linear objects in the lateral direction and longitudinal
direction.
[0129] FIG. 9 is a diagram for explanation of a two-pixel diagonal
Gr/Gb inversion method as the second measure for shifts of the
centers of gravity according to the embodiment.
[0130] In the two-pixel diagonal Gr/Gb inversion method of FIG. 9,
the direction in which the conditions of photosensitivity/amount of
exposure of G pixels in the B column and the R column vary is
changed.
[0131] In the example of FIG. 9, in the Gr pixel, the first
condition is such that the photosensitivity/amounts of exposure of
the upper left pixel DPC-A and the lower right pixel DPC-C opposed
to each other in the diagonal direction are the same. In the Gr
pixel, the second condition is such that the
photosensitivity/amounts of exposure of the upper right pixel DPC-B
and the lower left pixel DPC-D opposed to each other in the
diagonal direction are the same.
[0132] In this regard, in the R pixel, the second condition is such
that the photosensitivity/amounts of exposure of the upper left
pixel DPC-A and the lower right pixel DPC-C opposed to each other
in the diagonal direction are the same. In the R pixel, the first
condition is such that the photosensitivity/amounts of exposure of
the upper right pixel DPC-B and the lower left pixel DPC-D opposed
to each other in the diagonal direction are the same.
[0133] Further, in the Gb pixel, the second condition is such that
the photosensitivity/amounts of exposure of the upper left pixel
DPC-A and the lower right pixel DPC-C opposed to each other in the
diagonal direction are the same. In the Gb pixel, the first
condition is such that the photosensitivity/amounts of exposure of
the upper right pixel DPC-B and the lower left pixel DPC-D opposed
to each other in the diagonal direction are the same.
[0134] In this regard, in the B pixel, the first condition is such
that the photosensitivity/amounts of exposure of the upper left
pixel DPC-A and the lower right pixel DPC-C opposed to each other
in the diagonal direction are the same. In the B pixel, the second
condition is such that the photosensitivity/amounts of exposure of
the upper right pixel DPC-B and the lower left pixel DPC-D opposed
to each other in the diagonal direction are the same.
[0135] In the two-pixel diagonal method, it is considered that the
possibility of shifts of the centers of gravity may slightly remain
in the linear object in the diagonal direction, however, by
changing the direction in which the conditions of
photosensitivity/amounts of exposure of G pixels in the B column
and the R column vary, a layout having resistance in the diagonal
directions may be realized.
[0136] Note that arrangements strong for false color and noise can
be made with respect to the B signals and R signals by further
applying the two-pixel diagonal Gr/Gb inversion method with a
little ingenuity of arrangement in units of pixels of 8.times.8 as
shown in FIG. 10.
<3. Measures for S/N>
[0137] FIG. 11 is a diagram for explanation of measures for S/N
according to the embodiment.
[0138] In FIG. 11, to facilitate understanding, the signs are the
same as those in FIG. 2 and FIG. 2 may be cited in the
explanation.
[0139] As explained with reference to FIG. 2, subtraction of the
intercept of the expression is subtraction of Signal, and
deterioration of S/N may be caused.
[0140] That is, in the existing method, to obtain the target output
from the Raw sensor output, computation is performed directly from
the equation. Accordingly, S/N may be deteriorated due to the
influence of the subtraction component (only on Signal) and the
multiplication component (also on Noise).
[0141] On the other hand, in the embodiment, to prevent S/N
deterioration, "multiplying factor for obtaining target value" is
once obtained from the obtained signal value and computation is
performed by "obtained signal value.times.multiplying factor", and
thereby, the intercept (Signal) may be left.
[0142] That is, the multiplying factor is calculated from the Raw
sensor output.
[0143] By directly multiplying the Raw sensor output by the
multiplying factor (without subtraction), S/N may be
maintained.
[0144] As described above, "measures for S/N" in the embodiment is
a method of computing the signal value after readout of the pixel
signal, and the multiplying factor is changed depending on the
obtained signal value and output.
[0145] As a computation method, for example, there is a method
having multiplying factor tables with respect to each output value
or a method of mathematical computation.
[0146] These computations are performed in one system after readout
of the pixel signal. For example, the processing may be performed
in the signal processing circuit 180.
<4. Configuration Example of Divided Pixel>
[0147] First, to facilitate understanding, an example of a
configuration of a basic divided pixel of the CMOS image sensor
will be explained.
[0148] FIG. 12 is a diagram showing an example of a divided pixel
of the CMOS image sensor including four transistors according to
the embodiment.
[0149] The divided pixel DPC1 has a photoelectric conversion
element 111 formed by a photodiode, for example.
[0150] The divided pixel DPC in FIG. 12 has four transistors of a
transfer transistor 112, a reset transistor 113, an amplifying
transistor 114 as an amplification part, and a selection transistor
115 as active elements for the one photoelectric conversion element
111.
[0151] The photoelectric conversion element 111 photoelectrically
converts incident light into charge (here, electrons) in an amount
in response to the amount of light.
[0152] The transfer transistor 112 is connected between the
photoelectric conversion element 111 and the floating diffusion
part FD and a control signal Tx is provided to its gate (transfer
gate) through a transfer control line LTx.
[0153] Thereby, the electrons photoelectrically converted by the
photoelectric conversion element 111 are transferred to the
floating diffusion part FD.
[0154] The reset transistor 113 is connected between a power supply
line LVDD and the floating diffusion part FD and a control signal
RST is provided to its gate through a reset control line LRST.
[0155] Thereby, the potential of the floating diffusion part FD is
reset to the potential of the power supply line LVDD.
[0156] To the floating diffusion part FD, the gate of the
amplifying transistor 114 is connected. The amplifying transistor
114 is connected to a vertical signal line 116 via the selection
transistor 115 and forms a source follower with a constant current
source outside of the pixel part.
[0157] Further, a control signal (address signal or select signal)
SEL is provided to the gate of the selection transistor 115 through
a selection control line LSEL and the selection transistor 115 is
turned on.
[0158] When the selection transistor 115 is turned on, the
amplifying transistor 114 amplifies the potential of the floating
diffusion part FD and outputs a voltage in response to the
potential to the vertical signal line 116. The voltages output from
the respective pixels through the vertical signal line 116 are
output to the ADC group 150 as the pixel signal readout
circuit.
[0159] These operations are simultaneously performed with respect
to the respective divided pixels DPC of one row because, for
example, the respective gates of the transfer transistors 112, the
reset transistors 113, and the selection transistors 115 are
connected in units of rows.
[0160] The reset control line LRST, the transfer control line LTx,
and the selection control line LSEL wired in the pixel part 110 are
wired as one set for the respective rows of the pixel
arrangement.
[0161] These reset control line LRST, transfer control line LTx,
and selection control line LSEL are driven by the pixel drive
circuit 102.
[0162] The above described configuration can be applied without
change to the divided pixel cell according to the embodiment.
[0163] Further, as a configuration in which each divided pixel cell
contains the photoelectric conversion element and the transfer
transistor, a configuration in which the divided pixel cells share
the floating diffusion part FD can be employed.
[0164] In this case, the cells can be formed to share the
amplifying transistor as the amplification part, the selection
transistor, and the reset transistor.
[0165] FIG. 13 is a circuit diagram showing an example of the
plural divided pixels sharing floating diffusion parts, amplifying
transistors, selection transistors, reset transistors.
[0166] For the pixel PC containing plural divided pixels DPC-A to
DPC-D in FIG. 13, the photoelectric conversion elements 111-A to
111-D and transfer transistors 112-A to 112-D are provided with
respect to the divided pixels DPC-A to DPC-D.
[0167] Further, one ends (for example, drains) of the transfer
transistors 112-A to 112-D are connected to a shared floating
diffusion part SFD.
[0168] The gate of the transfer transistor 112-A is connected to a
transfer control line LTxA and the gate of the transfer transistor
112-B is connected to a transfer control line LTxB. Similarly, the
gate of the transfer transistor 112-C is connected to a transfer
control line LTxC and the gate of the transfer transistor 112-D is
connected to a transfer control line LTxD.
[0169] The reset transistor 113 is connected between the power
supply potential VDD and the shared floating diffusion part SFD.
The gate of the reset transistor 113 is connected to the reset
control line LRST.
[0170] The amplifying transistor 114 and the selection transistor
115 are connected in series between the power supply potential VDD
and the vertical signal line 116. Further, the gate of the
amplifying transistor 114 is connected to the shared floating
diffusion part SFD and the gate of the selection transistor 115 is
connected to the selection control line LSEL.
[0171] In the configuration, the divided pixel signals
photoelectrically converted by the photoelectric conversion
elements 111-A to 111-D of the respective divided pixels DPC-A to
DPC-D are transferred to the amplifying transistor 114 as the
amplification part through the shared floating diffusion part SFD.
Then, the divided pixel signals are amplified and the amplified
divided pixel signals are time-sequentially sent out to the
vertical signal line 116.
[0172] Further, a configuration in which each divided pixel cell
contains the photoelectric conversion element, the transfer
transistor, and the reset transistor and the divided pixel cell
individually contains the floating diffusion part FD can be
employed.
[0173] In this case, the cells can be formed to share the
amplifying transistor as the amplification part.
[0174] FIG. 14 is a circuit diagram showing an example of the
plural divided pixels individually having floating diffusion parts
and sharing amplifying transistors.
[0175] In the pixel PC containing the plural divided pixels DPC-A
to DPC-D of FIG. 14, the photoelectric conversion elements 111-A to
111-D and transfer transistors 112-A to 112-D are provided with
respect to the divided pixels DPC-A to DPC-D. Further, in the
divided pixels DPC-A to DPC-D, floating diffusion parts FD-A to
FD-D and reset transistors 113-A to 113-D are provided.
[0176] The selection transistor 115-A is connected between the
floating diffusion part FD-A and a node ND1, and the selection
transistor 115-B is connected between the floating diffusion part
FD-B and the node ND1.
[0177] Similarly, the selection transistor 115-C is connected
between the floating diffusion part FD-C and the node ND1, and the
selection transistor 115-D is connected between the floating
diffusion part FD-D and the node ND1.
[0178] The gate of the transfer transistor 112-A is connected to
the transfer control line LTxA and the gate of the transfer
transistor 112-B is connected to the transfer control line LTxB.
Similarly, the gate of the transfer transistor 112-C is connected
to the transfer control line LTxC and the gate of the transfer
transistor 112-D is connected to the transfer control line
LTxD.
[0179] The gate of the reset transistor 113-A is connected to the
reset control line LRSTA and the gate of the reset transistor 113-B
is connected to the reset control line LRSTB. Similarly, the gate
of the reset transistor 113-C is connected to the reset control
line LRSTC and the gate of the reset transistor 113-D is connected
to the reset control line LRSTD.
[0180] The gate of the selection transistor 115-A is connected to
the selection control line LSELA and the gate of the selection
transistor 115-B is connected to the selection control line LSELB.
Similarly, the gate of the selection transistor 115-C is connected
to the selection control line LSELC and the gate of the selection
transistor 115-D is connected to the selection control line
LSELD.
[0181] The amplifying transistor 114 is connected between the power
supply potential VDD and the vertical signal line 116. Further, the
gate of the amplifying transistor 114 is connected to the node
ND1.
[0182] In the configuration, the divided pixel signals
photoelectrically converted by the photoelectric conversion
elements 111-A to 111-D of the respective divided pixels DPC-A to
DPC-D are transferred to the floating diffusion parts FD-A to FD-D.
The divided pixel signals are transferred to the amplifying
transistor 114 as the amplification part through the floating
diffusion parts FD-A to FD-D and further via the selection
transistors 115-A to 115-D. Then, the divided pixel signals are
amplified and the amplified divided pixel signals are
time-sequentially sent out to the vertical signal line 116.
[0183] Further, a configuration in which plural divided pixels
forming one pixel are divided into plural groups and each divided
group shares the floating diffusion part FD can be employed.
[0184] In this case, each divided group can be formed to share the
reset transistor and the selection transistor and the groups can be
formed to share the amplifying transistor as a whole.
[0185] FIG. 15 is a circuit diagram showing an example of plural
divided pixels grouped and sharing floating diffusion parts in the
respective groups and sharing an amplifying transistors in the
pixel as a whole.
[0186] In this example, four divided pixels DPC-A, DPC-B, DPC-C,
DPC-D are segmented into two groups.
[0187] Specifically, the divided pixel DPC-A and the divided pixel
DPC-B are segmented into the first group GRP1 and the divided pixel
DPC-C and the divided pixel DPC-D are segmented into the second
group GRP2.
[0188] For the divided pixels DPC-A and DPC-B of the first group
GRP1 in FIG. 15, the photoelectric conversion elements 111-A and
111-B and the transfer transistors 112-A and 112-B are provided,
respectively.
[0189] Further, one ends (for example, drains) of the transfer
transistors 112-A and 112-B are connected to a shared floating
diffusion part SFD1.
[0190] The gate of the transfer transistor 112-A is connected to
the transfer control line LTxA and the gate of the transfer
transistor 112-B is connected to the transfer control line
LTxB.
[0191] For the divided pixels DPC-C and DPC-D of the second group
GRP2 in FIG. 15, the photoelectric conversion elements 111-C and
111-D and the transfer transistors 112-C and 112-D are provided,
respectively.
[0192] Further, one ends (for example, drains) of the transfer
transistors 112-C and 112-D are connected to a shared floating
diffusion part SFD2.
[0193] The gate of the transfer transistor 112-C is connected to
the transfer control line LTxC and the gate of the transfer
transistor 112-D is connected to the transfer control line
LTxD.
[0194] A reset transistor 113-1 is connected between the power
supply potential VDD and a shared floating diffusion part SFD1. The
gate of the reset transistor 113-1 is connected to the reset
control line LRST1.
[0195] A reset transistor 113-2 is connected between the power
supply potential VDD and the shared floating diffusion part SFD2.
The gate of the reset transistor 113-2 is connected to a reset
control line LRST2.
[0196] A selection transistor 115-1 is connected between the shared
floating diffusion part SFD1 and the node ND2 and a selection
transistor 115-2 is connected between the shared floating diffusion
part SFD2 and the node ND2.
[0197] The gate of the selection transistor 115-1 is connected to a
selection control line LSEL1 and the gate of the selection
transistor 115-2 is connected to a selection control line
LSEL2.
[0198] The amplifying transistor 114 is connected between the power
supply potential VDD and the vertical signal line 116. Further, the
gate of the amplifying transistor 114 is connected to the node
ND2.
[0199] In the configuration, the divided pixel signals
photoelectrically converted by the photoelectric conversion
elements 111-A to 111-D of the respective divided pixels DPC-A to
DPC-D are transferred to the shared floating diffusion parts SFD1
and SFD2. The divided pixel signals are transferred to the
amplifying transistor 114 as the amplification part through the
shared floating diffusion parts SFD1 and SFD2 and further via the
selection transistors 115-1 and 115-2. Then, the divided pixel
signals are amplified and the amplified divided pixel signals are
time-sequentially sent out to the vertical signal line 116.
[0200] As described above, there are various methods of division
into plural regions within a surface of one pixel, and the methods
are roughly classified into a shared floating diffusion (four
pixels shared) method (hereinafter, referred to as "shared FD
method") and an individual floating diffusion method (hereinafter,
referred to as "individual FD method").
[0201] FIGS. 16A to 16D are diagrams for explanation of methods of
division into plural regions within a surface of one pixel.
[0202] FIG. 16A shows an example of division into four in square
shapes by the shared FD method, FIG. 16B shows an example of
division into four in square shapes by the individual FD method,
FIG. 16C shows an example of division into four in reed shapes by
the shared FD method, and FIG. 16D shows an example of division
into four in reed shapes by the individual FD method.
[0203] Although the detailed explanation is omitted, stacking of
photosensitive layers and semiconductor layers (P-N junction) with
different sensitivity in a direction perpendicular to the surface
may be referred to as pixel division in a broad sense.
[0204] To change the sensitivity of the divided pixel may be
realized by methods of changing the aperture ratio of the device,
providing optical filter characteristics to the insulating film on
the photosensitive region, changing impurity concentration of the
substrate, etc.
[0205] FIGS. 16A to 16D show specific examples in which one pixel
is divided into four, and there are ineffective regions (dead
spaces) IVL that does not directly contribute to photosensitivity
in addition to divided photosensitive regions PA, PB, PC, PD.
[0206] The region IVL is a space (channel stop) for electric
isolation so that the pixel charge accumulated in the divided cells
may not leak out or interfere with each other, and wiring for
signal processing is provided therein according to need.
[0207] In the above explanation, the divided pixel addition signal
processing has been explained by taking the solid-state image
sensing device (CMOS image sensor) with column-parallel ADC as an
example.
[0208] For the divided pixel addition signal processing of the
column AD conversion type CMOS image sensor, for example, the
following two methods can be employed.
[0209] FIG. 17A is a diagram schematically showing a configuration
example of a column AD conversion type CMOS image sensor circuit
related to divided pixel addition.
[0210] In FIG. 17A, one pixel under color filters of the same color
is divided into four and photosensitivity and accumulation times
are varied with respect to each of the plural pixels opposed in the
diagonal direction of the respective divided pixels, and pixel
signals are sequentially read out to the same signal line through
the shared floating diffusion part FD. Then, noise processing is
performed by a CDS circuit 200 provided with respect to each column
and A/D conversion is performed on one row at a time outside of the
column.
[0211] FIG. 17B is a diagram schematically showing another
configuration example of the column AD conversion type CMOS image
sensor circuit related to divided pixel addition.
[0212] In FIG. 17B, one pixel under color filters of the same color
is divided into four and photosensitivity and accumulation times
are varied with respect to each of the plural pixels opposed in the
diagonal direction of the respective divided pixels. Then, pixel
signals are sequentially read out to the same signal line through
the shared FD, and the first noise processing is performed by a CDS
circuit 210 provided with respect to each column.
[0213] Then, the analog signal is converted into a digital signal
by an A/D converter 220 similarly provided with respect to each
column, the second noise processing is performed by a CDS circuit
230 similarly provided with respect to each column, and thereby,
the digital noise generated at A/D conversion is removed.
[0214] Further, in the above explanation, the example in which the
embodiment of the present disclosure is applied to the CMOS image
sensor has been explained, however, the embodiment of the present
disclosure may be applied to a CCD sensor.
[0215] FIG. 18 is a diagram showing a configuration example of a
solid-state image sensing device corresponding to a CCD sensor
according to the embodiment of the present disclosure.
[0216] A solid-state image sensing device 300 in FIG. 18 has plural
sensor parts (photoelectric conversion elements) 311 arranged in a
matrix in the row (vertical) direction and the column (horizontal)
direction and convert incident light into signal charge in an
amount of charge in response to its amount of light and accumulates
it.
[0217] The solid-state image sensing device 300 has plural vertical
transfer registers 312 arranged with respect to each vertical
column of the sensor parts 311 and vertically transfer signal
charge read out via a readout gate part (not shown) from the
respective sensor parts 311. The sensor parts and the vertical
transfer registers 312 form an imaging area 313.
[0218] The sensor part 311 employs Bayer arrangement and the
respective pixels are divided into divided pixels DPC as plural
regions with different sensitivity (for example, four, two for
each).
[0219] The vertical transfer register 312 is driven for transfer by
vertical transfer pulses for three or four phases, for example, and
sequentially transfers signal charge as divided pixel signals read
out from the respective sensor parts 311 with respect to each part
corresponding to one scan line (one line) in a part of a horizontal
blanking period.
[0220] A horizontal transfer register 314 is provided on the lower
side of the imaging area 313 in the drawing. The signal charge as
divided pixel signals corresponding to one line is sequentially
transferred from each of the plural vertical transfer registers 312
to the horizontal transfer register 314.
[0221] The horizontal transfer register 314 is driven for transfer
by vertical transfer pulses for three or four phases, for example,
and sequentially transfers the signal charge for one line
transferred from the plural vertical transfer registers 312 in the
horizontal direction in a horizontal scan period after the
horizontal blanking period.
[0222] At the end on the transfer destination side of the
horizontal transfer register 314, for example, a charge detection
part 315 having a floating diffusion amplifier configuration is
provided.
[0223] The charge detection part 315 has a floating diffusion part
FD that accumulates signal charge supplied from the horizontal
transfer register 314 via a horizontal output gate part. Though not
shown, the charge detection part 315 includes a reset drain (RD)
that drains signal charge and a reset gate (RG) provided between
the floating diffusion part FD and the reset drain.
[0224] In the charge detection part 315, a predetermined reset
drain voltage is applied to the reset drain and reset pulses are
applied to the reset gate with a detection period of signal
charge.
[0225] Further, the signal charge accumulated in the floating
diffusion part FD is converted into a signal voltage and led out to
a CSD circuit 320 via an output circuit 316 as a CCD output signal
CCDout. Then, in an ADC 330, AD conversion and addition processing
of the respective divided pixel signals are performed.
[0226] As explained above, according to the embodiment, for
prevention of shifts of the centers of gravity, a structure under
two conditions of exposure time conditions (or photosensitivity)
with pixels opposed to each other in the diagonal direction having
the same exposure time (or photosensitivity) is employed.
[0227] Further, these pixel signals are sent out to the vertical
signal line and added in the AD conversion part provided in the
column part.
[0228] Furthermore, in the embodiment, to maximize S/N, a
configuration in which, when the signal is returned to be linear,
the signal is not directly obtained by computation, but the final
output is obtained by once calculating an optimal multiplying
factor from a raw (Raw) output value and multiplying the raw (Raw)
output value by the multiplying factor is employed.
[0229] Therefore, according to the embodiment, the following
advantages may be obtained.
[0230] Shifts of the centers of gravity can be prevented and S/N
can be maximized.
[0231] Pixels of a solid-state image sensing device that has a wide
dynamic range, higher sensitivity with a low amount of light, and a
high-brightness information compression property may be
realized.
[0232] Further, an external memory is unnecessary compared to
existing digital addition.
[0233] There are no longer variations of the break point at which
one of pixels as addition targets is saturated as in analog
addition.
[0234] S/N is improved at the break point (at which one of pixels
as addition targets is saturated) and S/N nearly equal to or more
than that of a non-divided pixel may be achieved in the middle or
higher brightness range.
[0235] Furthermore, a divided pixel structure may be realized
without much increase in the number of processes.
[0236] In addition, a configuration in which the respective divided
pixels are independently read out according to the specifications
and the readout may be switched to readout for obtaining high
resolution images can be employed.
[0237] The solid-state image sensing device having the above
advantages may be applied as an imaging device for a digital camera
or video camera.
<5. Configuration Example of Camera System>
[0238] FIG. 19 is a diagram showing an example of a configuration
of a camera system to which the solid-state image sensing device
according to the embodiment of the present disclosure is
applied.
[0239] The camera system 400 has an imaging device 410 to which the
CMOS image sensor (solid-state image sensing device) 100, 300
according to the embodiment can be applied as shown in FIG. 19.
[0240] The camera system 400 has an optical system that guides
incident light to a pixel region of the imaging device 410 (forms
an object image) and a lens 420 that images the incident light
(image light) on an imaging surface, for example.
[0241] The camera system 400 has a drive circuit (DRV) 430 that
drives the imaging device 410 and a signal processing circuit (PRC)
440 that processes an output signal of the imaging device 410.
[0242] The drive circuit 430 has a timing generator (not shown)
that generates various timing signals including start pulses and
clock pulses that drive the circuits within the imaging device 410,
and drives the imaging device 410 with predetermined timing
signals.
[0243] Further, the signal processing circuit 440 performs signal
processing such as CDS on the output signal of the imaging device
410.
[0244] The image signal processed in the signal processing circuit
440 is recorded in a recording medium such as a memory. The image
information recorded in the recording medium is hard-copied using a
printer or the like. Alternatively, the image signal processed in
the signal processing circuit 440 is displayed as a moving image on
a monitor of a liquid crystal display or the like.
[0245] As described above, in an imaging apparatus such as a
digital camera, by mounting the above described image sensing
device 100 as the imaging device 410, a camera with low power
consumption and high definition may be realized.
[0246] The present disclosure contains subject matter related to
that disclosed in Japanese Priority Patent Application JP
2010-250328 filed in the Japan Patent Office on Nov. 8, 2010, the
entire content of which is hereby incorporated by reference.
[0247] It should be understood by those skilled in the art that
various modifications, combinations, sub-combinations and
alterations may occur depending on design requirements and other
factors insofar as they are within the scope of the appended claims
or the equivalents thereof.
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