U.S. patent application number 14/903993 was filed with the patent office on 2016-06-09 for data processing device and data processing method.
This patent application is currently assigned to SONY CORPORATION. The applicant listed for this patent is SONY CORPORATION. Invention is credited to Ryoji IKEGAYA, Yuji SHINOHARA, Makiko YAMAMOTO.
Application Number | 20160164540 14/903993 |
Document ID | / |
Family ID | 54553889 |
Filed Date | 2016-06-09 |
United States Patent
Application |
20160164540 |
Kind Code |
A1 |
SHINOHARA; Yuji ; et
al. |
June 9, 2016 |
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
Abstract
A data processing device and a data processing method, which are
capable of securing excellent communication quality in data
transmission using an LDPC code. In group-wise interleave, an LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 6/15, 7/15, 8/15, or 9/15 is interleaved in units of bit groups
of 360 bits. In group-wise deinterleave, a sequence of the LDPC
code that has undergone the group-wise interleave is restored to an
original sequence. For example, the present technology can be
applied to a technique of performing data transmission using an
LDPC code.
Inventors: |
SHINOHARA; Yuji; (Kanagawa,
JP) ; YAMAMOTO; Makiko; (Tokyo, JP) ; IKEGAYA;
Ryoji; (Kanagawa, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SONY CORPORATION |
Tokyo |
|
JP |
|
|
Assignee: |
SONY CORPORATION
Tokyo
JP
|
Family ID: |
54553889 |
Appl. No.: |
14/903993 |
Filed: |
May 8, 2015 |
PCT Filed: |
May 8, 2015 |
PCT NO: |
PCT/JP2015/063254 |
371 Date: |
January 8, 2016 |
Current U.S.
Class: |
714/752 |
Current CPC
Class: |
H03M 13/356 20130101;
H03M 13/2792 20130101; H03M 13/2906 20130101; H03M 13/1102
20130101; H03M 13/152 20130101; H03M 13/1137 20130101; H03M 13/2778
20130101; H03M 13/036 20130101; H03M 13/1165 20130101; H03M 13/255
20130101; H03M 13/271 20130101 |
International
Class: |
H03M 13/27 20060101
H03M013/27; H03M 13/11 20060101 H03M013/11 |
Foreign Application Data
Date |
Code |
Application Number |
May 21, 2014 |
JP |
2014-104810 |
Claims
1. A data processing device comprising: an encoding unit configured
to perform LDPC encoding based on a parity check matrix of an LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 6/15; a group-wise interleaving unit configured to perform
group-wise interleave of interleaving the LDPC code in units of bit
groups of 360 bits; and a mapping unit configured to map the LDPC
code to any of 4096 signal points decided in a modulation scheme in
units of 12 bits, wherein in the group-wise interleave, when an
(i+1)-th bit group from a head of the LDPC code is indicated by a
bit group i, a sequence of bit groups 0 to 179 of the LDPC code of
64800 bits is interleaved into a sequence of bit groups 71, 38, 98,
159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151, 66, 92, 140, 6,
165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110, 128, 73, 148, 14,
5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122, 150, 103, 178,
119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143, 147, 89, 4,
107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153, 90, 152, 124,
7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175, 94, 115, 15,
112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162, 167, 164, 97,
82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105, 134, 173, 84,
9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111, 133, 56, 170,
104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35, 58, 45, 155,
70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69, 158, 129, 139,
62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and 137, the LDPC code
includes an information bit and a parity bit, the parity check
matrix includes an information matrix portion corresponding to the
information bit and a parity matrix portion corresponding to the
parity bit, the information matrix portion is represented by a
parity check matrix initial value table, and the parity check
matrix initial value table is a table in which a position of a 1
element of the information matrix portion is indicated for every
360 columns, and includes 1606 3402 4961 6751 7132 11516 12300
12482 12592 13342 13764 14123 21576 23946 24533 25376 25667 26836
31799 34173 35462 36153 36740 37085 37152 37468 37658 4621 5007
6910 8732 9757 11508 13099 15513 16335 18052 19512 21319 23663
25628 27208 31333 32219 33003 33239 33447 36200 36473 36938 37201
37283 37495 38642 16 1094 2020 3080 4194 5098 5631 6877 7889 8237
9804 10067 11017 11366 13136 13354 15379 18934 20199 24522 26172
28666 30386 32714 36390 37015 37162 700 897 1708 6017 6490 7372
7825 9546 10398 16605 18561 18745 21625 22137 23693 24340 24966
25015 26995 28586 28895 29687 33938 34520 34858 37056 38297 159
2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836 14954 15594
16623 18065 19249 22394 22677 23408 23731 24076 24776 27007 28222
30343 38371 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508
15536 20218 21921 28599 29445 29758 29968 31014 32027 33685 34378
35867 36323 36728 36870 38335 38623 1264 4254 6936 9165 9486 9950
10861 11653 13697 13961 15164 15665 18444 19470 20313 21189 24371
26431 26999 28086 28251 29261 31981 34015 35850 36129 37186 111
1307 1628 2041 2524 5358 7988 8191 10322 11905 12919 14127 15515
15711 17061 19024 21195 22902 23727 24401 24608 25111 25228 27338
35398 37794 38196 961 3035 7174 7948 13355 13607 14971 18189 18339
18665 18875 19142 20615 21136 21309 21758 23366 24745 25849 25982
27583 30006 31118 32106 36469 36583 37920 2990 3549 4273 4808 5707
6021 6509 7456 8240 10044 12262 12660 13085 14750 15680 16049 21587
23997 25803 28343 28693 34393 34860 35490 36021 37737 38296 955
4323 5145 6885 8123 9730 11840 12216 19194 20313 23056 24248 24830
25268 26617 26801 28557 29753 30745 31450 31973 32839 33025 33296
35710 37366 37509 264 605 4181 4483 5156 7238 8863 10939 11251
12964 16254 17511 20017 22395 22818 23261 23422 24064 26329 27723
28186 30434 31956 33971 34372 36764 38123 520 2562 2794 3528 3860
4402 5676 6963 8655 9018 9783 11933 16336 17193 17320 19035 20606
23579 23769 24123 24966 27866 32457 34011 34499 36620 37526 10106
10637 10906 34242 1856 15100 19378 21848 943 11191 27806 29411 4575
6359 13629 19383 4476 4953 18782 24313 5441 6381 21840 35943 9638
9763 12546 30120 9587 10626 11047 25700 4088 15298 28768 35047 2332
6363 8782 28863 4625 4933 28298 30289 3541 4918 18257 31746 1221
25233 26757 34892 8150 16677 27934 30021 8500 25016 33043 38070
7374 10207 16189 35811 611 18480 20064 38261 25416 27352 36089
38469 1667 17614 25839 32776 4118 12481 21912 37945 5573 13222
23619 31271 18271 26251 27182 30587 14690 26430 26799 34355 13688
16040 20716 34558 2740 14957 23436 32540 3491 14365 14681 36858
4796 6238 25203 27854 1731 12816 17344 26025 19182 21662 23742
27872 6502 13641 17509 34713 12246 12372 16746 27452 1589 21528
30621 34003 12328 20515 30651 31432 3415 22656 23427 36395 632 5209
25958 31085 619 3690 19648 37778 9528 13581 26965 36447 2147 26249
26968 28776 15698 18209 30683 1132 19888 34111 4608 25513 38874 475
1729 34100 7348 32277 38587 182 16473 33082 3865 9678 21265 4447
20151 27618 6335 14371 38711 704 9695 28858 4856 9757 30546 1993
19361 30732 756 28000 29138 3821 24076 31813 4611 12326 32291 7628
21515 34995 1246 13294 30068 6466 33233 35865 14484 23274 38150
21269 36411 37450 23129 26195 37653.
2. A data processing method comprising: an encoding step of
performing LDPC encoding based on a parity check matrix of an LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 6/15; a group-wise interleaving step of performing group-wise
interleave of interleaving the LDPC code in units of bit groups of
360 bits; and a mapping step of mapping the LDPC code to any of
4096 signal points decided in a modulation scheme in units of 12
bits, wherein in the group-wise interleave, when an (i+1)-th bit
group from a head of the LDPC code is indicated by a bit group i, a
sequence of bit groups 0 to 179 of the LDPC code of 64800 bits is
interleaved into a sequence of bit groups 71, 38, 98, 159, 1, 32,
28, 177, 125, 102, 83, 17, 121, 151, 66, 92, 140, 6, 165, 23, 75,
91, 87, 108, 163, 50, 77, 39, 110, 128, 73, 148, 14, 5, 68, 37, 53,
93, 149, 26, 166, 48, 79, 10, 122, 150, 103, 178, 119, 101, 61, 34,
8, 86, 36, 138, 146, 72, 179, 143, 147, 89, 4, 107, 33, 144, 141,
40, 100, 29, 118, 63, 46, 20, 153, 90, 152, 124, 7, 30, 31, 43, 78,
120, 85, 25, 52, 47, 64, 81, 175, 94, 115, 15, 112, 99, 13, 21, 42,
169, 76, 19, 168, 16, 27, 162, 167, 164, 97, 82, 44, 106, 12, 109,
132, 145, 161, 174, 95, 0, 105, 134, 173, 84, 9, 65, 88, 54, 67,
116, 154, 80, 22, 172, 60, 111, 133, 56, 170, 104, 131, 123, 24,
49, 113, 136, 55, 3, 157, 156, 35, 58, 45, 155, 70, 59, 57, 171,
176, 74, 117, 18, 127, 114, 11, 69, 158, 129, 139, 62, 135, 96,
142, 41, 130, 160, 2, 126, 51, and 137, the LDPC code includes an
information bit and a parity bit, the parity check matrix includes
an information matrix portion corresponding to the information bit
and a parity matrix portion corresponding to the parity bit, the
information matrix portion is represented by a parity check matrix
initial value table, and the parity check matrix initial value
table is a table in which a position of a 1 element of the
information matrix portion is indicated for every 360 columns, and
includes 1606 3402 4961 6751 7132 11516 12300 12482 12592 13342
13764 14123 21576 23946 24533 25376 25667 26836 31799 34173 35462
36153 36740 37085 37152 37468 37658 4621 5007 6910 8732 9757 11508
13099 15513 16335 18052 19512 21319 23663 25628 27208 31333 32219
33003 33239 33447 36200 36473 36938 37201 37283 37495 38642 16 1094
2020 3080 4194 5098 5631 6877 7889 8237 9804 10067 11017 11366
13136 13354 15379 18934 20199 24522 26172 28666 30386 32714 36390
37015 37162 700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561
18745 21625 22137 23693 24340 24966 25015 26995 28586 28895 29687
33938 34520 34858 37056 38297 159 2010 2573 3617 4452 4958 5556
5832 6481 8227 9924 10836 14954 15594 16623 18065 19249 22394 22677
23408 23731 24076 24776 27007 28222 30343 38371 3118 3545 4768 4992
5227 6732 8170 9397 10522 11508 15536 20218 21921 28599 29445 29758
29968 31014 32027 33685 34378 35867 36323 36728 36870 38335 38623
1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164 15665
18444 19470 20313 21189 24371 26431 26999 28086 28251 29261 31981
34015 35850 36129 37186 111 1307 1628 2041 2524 5358 7988 8191
10322 11905 12919 14127 15515 15711 17061 19024 21195 22902 23727
24401 24608 25111 25228 27338 35398 37794 38196 961 3035 7174 7948
13355 13607 14971 18189 18339 18665 18875 19142 20615 21136 21309
21758 23366 24745 25849 25982 27583 30006 31118 32106 36469 36583
37920 2990 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262
12660 13085 14750 15680 16049 21587 23997 25803 28343 28693 34393
34860 35490 36021 37737 38296 955 4323 5145 6885 8123 9730 11840
12216 19194 20313 23056 24248 24830 25268 26617 26801 28557 29753
30745 31450 31973 32839 33025 33296 35710 37366 37509 264 605 4181
4483 5156 7238 8863 10939 11251 12964 16254 17511 20017 22395 22818
23261 23422 24064 26329 27723 28186 30434 31956 33971 34372 36764
38123 520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783 11933
16336 17193 17320 19035 20606 23579 23769 24123 24966 27866 32457
34011 34499 36620 37526 10106 10637 10906 34242 1856 15100 19378
21848 943 11191 27806 29411 4575 6359 13629 19383 4476 4953 18782
24313 5441 6381 21840 35943 9638 9763 12546 30120 9587 10626 11047
25700 4088 15298 28768 35047 2332 6363 8782 28863 4625 4933 28298
30289 3541 4918 18257 31746 1221 25233 26757 34892 8150 16677 27934
30021 8500 25016 33043 38070 7374 10207 16189 35811 611 18480 20064
38261 25416 27352 36089 38469 1667 17614 25839 32776 4118 12481
21912 37945 5573 13222 23619 31271 18271 26251 27182 30587 14690
26430 26799 34355 13688 16040 20716 34558 2740 14957 23436 32540
3491 14365 14681 36858 4796 6238 25203 27854 1731 12816 17344 26025
19182 21662 23742 27872 6502 13641 17509 34713 12246 12372 16746
27452 1589 21528 30621 34003 12328 20515 30651 31432 3415 22656
23427 36395 632 5209 25958 31085 619 3690 19648 37778 9528 13581
26965 36447 2147 26249 26968 28776 15698 18209 30683 1132 19888
34111 4608 25513 38874 475 1729 34100 7348 32277 38587 182 16473
33082 3865 9678 21265 4447 20151 27618 6335 14371 38711 704 9695
28858 4856 9757 30546 1993 19361 30732 756 28000 29138 3821 24076
31813 4611 12326 32291 7628 21515 34995 1246 13294 30068 6466 33233
35865 14484 23274 38150 21269 36411 37450 23129 26195 37653.
3. A data processing device comprising: a group-wise deinterleaving
unit configured to restore a sequence of an LDPC code that has
undergone group-wise interleave and has been obtained from data
transmitted from a transmitting device to an original sequence, the
transmitting device including an encoding unit configured to
perform LDPC encoding based on a parity check matrix of the LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 6/15, a group-wise interleaving unit configured to perform the
group-wise interleave of interleaving the LDPC code in units of bit
groups of 360 bits, and a mapping unit configured to map the LDPC
code to any of 4096 signal points decided in a modulation scheme in
units of 12 bits, wherein in the group-wise interleave, when an
(i+1)-th bit group from a head of the LDPC code is indicated by a
bit group i, a sequence of bit groups 0 to 179 of the LDPC code of
64800 bits is interleaved into a sequence of bit groups 71, 38, 98,
159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151, 66, 92, 140, 6,
165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110, 128, 73, 148, 14,
5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122, 150, 103, 178,
119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143, 147, 89, 4,
107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153, 90, 152, 124,
7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175, 94, 115, 15,
112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162, 167, 164, 97,
82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105, 134, 173, 84,
9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111, 133, 56, 170,
104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35, 58, 45, 155,
70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69, 158, 129, 139,
62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and 137, the LDPC code
includes an information bit and a parity bit, the parity check
matrix includes an information matrix portion corresponding to the
information bit and a parity matrix portion corresponding to the
parity bit, the information matrix portion is represented by a
parity check matrix initial value table, and the parity check
matrix initial value table is a table in which a position of a 1
element of the information matrix portion is indicated for every
360 columns, and includes 1606 3402 4961 6751 7132 11516 12300
12482 12592 13342 13764 14123 21576 23946 24533 25376 25667 26836
31799 34173 35462 36153 36740 37085 37152 37468 37658 4621 5007
6910 8732 9757 11508 13099 15513 16335 18052 19512 21319 23663
25628 27208 31333 32219 33003 33239 33447 36200 36473 36938 37201
37283 37495 38642 16 1094 2020 3080 4194 5098 5631 6877 7889 8237
9804 10067 11017 11366 13136 13354 15379 18934 20199 24522 26172
28666 30386 32714 36390 37015 37162 700 897 1708 6017 6490 7372
7825 9546 10398 16605 18561 18745 21625 22137 23693 24340 24966
25015 26995 28586 28895 29687 33938 34520 34858 37056 38297 159
2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836 14954 15594
16623 18065 19249 22394 22677 23408 23731 24076 24776 27007 28222
30343 38371 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508
15536 20218 21921 28599 29445 29758 29968 31014 32027 33685 34378
35867 36323 36728 36870 38335 38623 1264 4254 6936 9165 9486 9950
10861 11653 13697 13961 15164 15665 18444 19470 20313 21189 24371
26431 26999 28086 28251 29261 31981 34015 35850 36129 37186 111
1307 1628 2041 2524 5358 7988 8191 10322 11905 12919 14127 15515
15711 17061 19024 21195 22902 23727 24401 24608 25111 25228 27338
35398 37794 38196 961 3035 7174 7948 13355 13607 14971 18189 18339
18665 18875 19142 20615 21136 21309 21758 23366 24745 25849 25982
27583 30006 31118 32106 36469 36583 37920 2990 3549 4273 4808 5707
6021 6509 7456 8240 10044 12262 12660 13085 14750 15680 16049 21587
23997 25803 28343 28693 34393 34860 35490 36021 37737 38296 955
4323 5145 6885 8123 9730 11840 12216 19194 20313 23056 24248 24830
25268 26617 26801 28557 29753 30745 31450 31973 32839 33025 33296
35710 37366 37509 264 605 4181 4483 5156 7238 8863 10939 11251
12964 16254 17511 20017 22395 22818 23261 23422 24064 26329 27723
28186 30434 31956 33971 34372 36764 38123 520 2562 2794 3528 3860
4402 5676 6963 8655 9018 9783 11933 16336 17193 17320 19035 20606
23579 23769 24123 24966 27866 32457 34011 34499 36620 37526 10106
10637 10906 34242 1856 15100 19378 21848 943 11191 27806 29411 4575
6359 13629 19383 4476 4953 18782 24313 5441 6381 21840 35943 9638
9763 12546 30120 9587 10626 11047 25700 4088 15298 28768 35047 2332
6363 8782 28863 4625 4933 28298 30289 3541 4918 18257 31746 1221
25233 26757 34892 8150 16677 27934 30021 8500 25016 33043 38070
7374 10207 16189 35811 611 18480 20064 38261 25416 27352 36089
38469 1667 17614 25839 32776 4118 12481 21912 37945 5573 13222
23619 31271 18271 26251 27182 30587 14690 26430 26799 34355 13688
16040 20716 34558 2740 14957 23436 32540 3491 14365 14681 36858
4796 6238 25203 27854 1731 12816 17344 26025 19182 21662 23742
27872 6502 13641 17509 34713 12246 12372 16746 27452 1589 21528
30621 34003 12328 20515 30651 31432 3415 22656 23427 36395 632 5209
25958 31085 619 3690 19648 37778 9528 13581 26965 36447 2147 26249
26968 28776 15698 18209 30683 1132 19888 34111 4608 25513 38874 475
1729 34100 7348 32277 38587 182 16473 33082 3865 9678 21265 4447
20151 27618 6335 14371 38711 704 9695 28858 4856 9757 30546 1993
19361 30732 756 28000 29138 3821 24076 31813 4611 12326 32291 7628
21515 34995 1246 13294 30068 6466 33233 35865 14484 23274 38150
21269 36411 37450 23129 26195 37653.
4-16. (canceled)
Description
TECHNICAL FIELD
[0001] The present technology relates to a data processing device
and a data processing method, and more particularly, a data
processing device and a data processing method, which are capable
of securing excellent communication quality in data transmission
using an LDPC code, for example.
BACKGROUND ART
[0002] Some of the information disclosed in this specification and
the drawings was provided by Samsung Electronics Co., Ltd.
(hereinafter referred to as Samsung), LG Electronics Inc., NERC,
and CRC/ETRI (indicated in the drawings).
[0003] A low density parity check (LDPC) code has a high error
correction capability, and in recent years, the LDPC code has
widely been employed in transmission schemes of digital
broadcasting such as Digital Video Broadcasting (DVB)-S.2, DVB-T.2,
and DVB-C.2 of Europe and the like, or Advanced Television Systems
Committee (ATSC) 3.0 of the USA and the like (for example, see
Non-Patent Literature 1).
[0004] From a recent study, it is known that performance near a
Shannon limit is obtained from the LDPC code when a code length
increases, similar to a turbo code. Because the LDPC code has a
property that a shortest distance is proportional to the code
length, the LDPC code has advantages of a block error probability
characteristic being superior and a so-called error floor
phenomenon observed in a decoding characteristic of the turbo code
being rarely generated, as characteristics thereof.
CITATION LIST
Non-Patent Literature
[0005] Non-Patent Literature 1: DVB-S.2: ETSI EN 302 307 V1.2.1
(2009-08)
SUMMARY OF INVENTION
Technical Problem
[0006] In data transmission using the LDPC code, for example, the
LDPC code is converted into a symbol of an orthogonal modulation
(digital modulation) such as Quadrature Phase Shift Keying (QPSK),
and the symbol is mapped to a signal point of the orthogonal
modulation and transmitted.
[0007] The data transmission using the LDPC code has spread
worldwide, and there is a demand to secure excellent communication
(transmission) quality.
[0008] The present technology was made in light of the foregoing,
and it is desirable to secure excellent communication quality in
data transmission using the LDPC code.
Solution to Problem
[0009] A first data processing device/method according to the
present technology is a data processing device/method including: an
encoding unit/step configured to perform LDPC encoding based on a
parity check matrix of an LDPC code in which a code length N is
64800 bits and an encoding rate r is 6/15; a group-wise
interleaving unit/step configured to perform group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits;
and a mapping unit/step configured to map the LDPC code to any of
4096 signal points decided in a modulation scheme in units of 12
bits. In the group-wise interleave, when an (i+1)-th bit group from
a head of the LDPC code is indicated by a bit group i, a sequence
of bit groups 0 to 179 of the LDPC code of 64800 bits is
interleaved into a sequence of bit groups
[0010] 71, 38, 98, 159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151,
66, 92, 140, 6, 165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110,
128, 73, 148, 14, 5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122,
150, 103, 178, 119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143,
147, 89, 4, 107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153,
90, 152, 124, 7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175,
94, 115, 15, 112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162,
167, 164, 97, 82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105,
134, 173, 84, 9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111,
133, 56, 170, 104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35,
58, 45, 155, 70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69,
158, 129, 139, 62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and
137.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0011] 1606 3402 4961 6751 7132 11516 12300 12482 12592 13342 13764
14123 21576 23946 24533 25376 25667 26836 31799 34173 35462 36153
36740 37085 37152 37468 37658
[0012] 4621 5007 6910 8732 9757 11508 13099 15513 16335 18052 19512
21319 23663 25628 27208 31333 32219 33003 33239 33447 36200 36473
36938 37201 37283 37495 38642
[0013] 16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067
11017 11366 13136 13354 15379 18934 20199 24522 26172 28666 30386
32714 36390 37015 37162
[0014] 700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561
18745 21625 22137 23693 24340 24966 25015 26995 28586 28895 29687
33938 34520 34858 37056 38297
[0015] 159 2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836
14954 15594 16623 18065 19249 22394 22677 23408 23731 24076 24776
27007 28222 30343 38371
[0016] 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508 15536
20218 21921 28599 29445 29758 29968 31014 32027 33685 34378 35867
36323 36728 36870 38335 38623
[0017] 1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164
15665 18444 19470 20313 21189 24371 26431 26999 28086 28251 29261
31981 34015 35850 36129 37186
[0018] 111 1307 1628 2041 2524 5358 7988 8191 10322 11905 12919
14127 15515 15711 17061 19024 21195 22902 23727 24401 24608 25111
25228 27338 35398 37794 38196
[0019] 961 3035 7174 7948 13355 13607 14971 18189 18339 18665 18875
19142 20615 21136 21309 21758 23366 24745 25849 25982 27583 30006
31118 32106 36469 36583 37920
[0020] 2990 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262
12660 13085 14750 15680 16049 21587 23997 25803 28343 28693 34393
34860 35490 36021 37737 38296
[0021] 955 4323 5145 6885 8123 9730 11840 12216 19194 20313 23056
24248 24830 25268 26617 26801 28557 29753 30745 31450 31973 32839
33025 33296 35710 37366 37509
[0022] 264 605 4181 4483 5156 7238 8863 10939 11251 12964 16254
17511 20017 22395 22818 23261 23422 24064 26329 27723 28186 30434
31956 33971 34372 36764 38123
[0023] 520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783 11933
16336 17193 17320 19035 20606 23579 23769 24123 24966 27866 32457
34011 34499 36620 37526
[0024] 10106 10637 10906 34242
[0025] 1856 15100 19378 21848
[0026] 943 11191 27806 29411
[0027] 4575 6359 13629 19383
[0028] 4476 4953 18782 24313
[0029] 5441 6381 21840 35943
[0030] 9638 9763 12546 30120
[0031] 9587 10626 11047 25700
[0032] 4088 15298 28768 35047
[0033] 2332 6363 8782 28863
[0034] 4625 4933 28298 30289
[0035] 3541 4918 18257 31746
[0036] 1221 25233 26757 34892
[0037] 8150 16677 27934 30021
[0038] 8500 25016 33043 38070
[0039] 7374 10207 16189 35811
[0040] 611 18480 20064 38261
[0041] 25416 27352 36089 38469
[0042] 1667 17614 25839 32776
[0043] 4118 12481 21912 37945
[0044] 5573 13222 23619 31271
[0045] 18271 26251 27182 30587
[0046] 14690 26430 26799 34355
[0047] 13688 16040 20716 34558
[0048] 2740 14957 23436 32540
[0049] 3491 14365 14681 36858
[0050] 4796 6238 25203 27854
[0051] 1731 12816 17344 26025
[0052] 19182 21662 23742 27872
[0053] 6502 13641 17509 34713
[0054] 12246 12372 16746 27452
[0055] 1589 21528 30621 34003
[0056] 12328 20515 30651 31432
[0057] 3415 22656 23427 36395
[0058] 632 5209 25958 31085
[0059] 619 3690 19648 37778
[0060] 9528 13581 26965 36447
[0061] 2147 26249 26968 28776
[0062] 15698 18209 30683
[0063] 1132 19888 34111
[0064] 4608 25513 38874
[0065] 475 1729 34100
[0066] 7348 32277 38587
[0067] 182 16473 33082
[0068] 3865 9678 21265
[0069] 4447 20151 27618
[0070] 6335 14371 38711
[0071] 704 9695 28858
[0072] 4856 9757 30546
[0073] 1993 19361 30732
[0074] 756 28000 29138
[0075] 3821 24076 31813
[0076] 4611 12326 32291
[0077] 7628 21515 34995
[0078] 1246 13294 30068
[0079] 6466 33233 35865
[0080] 14484 23274 38150
[0081] 21269 36411 37450
[0082] 23129 26195 37653.
[0083] In the first data processing device/method according to the
present technology, LDPC encoding is performed based on a parity
check matrix of an LDPC code in which a code length N is 64800 bits
and an encoding rate r is 6/15. Group-wise interleave of
interleaving the LDPC code in units of bit groups of 360 bits is
performed. The LDPC code is mapped to any of 4096 signal points
decided in a modulation scheme in units of 12 bits. In the
group-wise interleave, when an (i+1)-th bit group from a head of
the LDPC code is indicated by a bit group i, a sequence of bit
groups 0 to 179 of the LDPC code of 64800 bits is interleaved into
a sequence of bit groups
[0084] 71, 38, 98, 159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151,
66, 92, 140, 6, 165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110,
128, 73, 148, 14, 5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122,
150, 103, 178, 119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143,
147, 89, 4, 107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153,
90, 152, 124, 7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175,
94, 115, 15, 112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162,
167, 164, 97, 82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105,
134, 173, 84, 9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111,
133, 56, 170, 104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35,
58, 45, 155, 70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69,
158, 129, 139, 62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and
137.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0085] 1606 3402 4961 6751 7132 11516 12300 12482 12592 13342 13764
14123 21576 23946 24533 25376 25667 26836 31799 34173 35462 36153
36740 37085 37152 37468 37658
[0086] 4621 5007 6910 8732 9757 11508 13099 15513 16335 18052 19512
21319 23663 25628 27208 31333 32219 33003 33239 33447 36200 36473
36938 37201 37283 37495 38642
[0087] 16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067
11017 11366 13136 13354 15379 18934 20199 24522 26172 28666 30386
32714 36390 37015 37162
[0088] 700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561
18745 21625 22137 23693 24340 24966 25015 26995 28586 28895 29687
33938 34520 34858 37056 38297
[0089] 159 2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836
14954 15594 16623 18065 19249 22394 22677 23408 23731 24076 24776
27007 28222 30343 38371
[0090] 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508 15536
20218 21921 28599 29445 29758 29968 31014 32027 33685 34378 35867
36323 36728 36870 38335 38623
[0091] 1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164
15665 18444 19470 20313 21189 24371 26431 26999 28086 28251 29261
31981 34015 35850 36129 37186
[0092] 111 1307 1628 2041 2524 5358 7988 8191 10322 11905 12919
14127 15515 15711 17061 19024 21195 22902 23727 24401 24608 25111
25228 27338 35398 37794 38196
[0093] 961 3035 7174 7948 13355 13607 14971 18189 18339 18665 18875
19142 20615 21136 21309 21758 23366 24745 25849 25982 27583 30006
31118 32106 36469 36583 37920
[0094] 2990 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262
12660 13085 14750 15680 16049 21587 23997 25803 28343 28693 34393
34860 35490 36021 37737 38296
[0095] 955 4323 5145 6885 8123 9730 11840 12216 19194 20313 23056
24248 24830 25268 26617 26801 28557 29753 30745 31450 31973 32839
33025 33296 35710 37366 37509
[0096] 264 605 4181 4483 5156 7238 8863 10939 11251 12964 16254
17511 20017 22395 22818 23261 23422 24064 26329 27723 28186 30434
31956 33971 34372 36764 38123
[0097] 520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783 11933
16336 17193 17320 19035 20606 23579 23769 24123 24966 27866 32457
34011 34499 36620 37526
[0098] 10106 10637 10906 34242
[0099] 1856 15100 19378 21848
[0100] 943 11191 27806 29411
[0101] 4575 6359 13629 19383
[0102] 4476 4953 18782 24313
[0103] 5441 6381 21840 35943
[0104] 9638 9763 12546 30120
[0105] 9587 10626 11047 25700
[0106] 4088 15298 28768 35047
[0107] 2332 6363 8782 28863
[0108] 4625 4933 28298 30289
[0109] 3541 4918 18257 31746
[0110] 1221 25233 26757 34892
[0111] 8150 16677 27934 30021
[0112] 8500 25016 33043 38070
[0113] 7374 10207 16189 35811
[0114] 611 18480 20064 38261
[0115] 25416 27352 36089 38469
[0116] 1667 17614 25839 32776
[0117] 4118 12481 21912 37945
[0118] 5573 13222 23619 31271
[0119] 18271 26251 27182 30587
[0120] 14690 26430 26799 34355
[0121] 13688 16040 20716 34558
[0122] 2740 14957 23436 32540
[0123] 3491 14365 14681 36858
[0124] 4796 6238 25203 27854
[0125] 1731 12816 17344 26025
[0126] 19182 21662 23742 27872
[0127] 6502 13641 17509 34713
[0128] 12246 12372 16746 27452
[0129] 1589 21528 30621 34003
[0130] 12328 20515 30651 31432
[0131] 3415 22656 23427 36395
[0132] 632 5209 25958 31085
[0133] 619 3690 19648 37778
[0134] 9528 13581 26965 36447
[0135] 2147 26249 26968 28776
[0136] 15698 18209 30683
[0137] 1132 19888 34111
[0138] 4608 25513 38874
[0139] 475 1729 34100
[0140] 7348 32277 38587
[0141] 182 16473 33082
[0142] 3865 9678 21265
[0143] 4447 20151 27618
[0144] 6335 14371 38711
[0145] 704 9695 28858
[0146] 4856 9757 30546
[0147] 1993 19361 30732
[0148] 756 28000 29138
[0149] 3821 24076 31813
[0150] 4611 12326 32291
[0151] 7628 21515 34995
[0152] 1246 13294 30068
[0153] 6466 33233 35865
[0154] 14484 23274 38150
[0155] 21269 36411 37450
[0156] 23129 26195 37653.
[0157] A second data processing device/method according to the
present technology is a data processing device/method including: a
group-wise deinterleaving unit/step configured to restore a
sequence of an LDPC code that has undergone group-wise interleave
and has been obtained from data transmitted from a transmitting
device to an original sequence, the transmitting device including
an encoding unit configured to perform LDPC encoding based on a
parity check matrix of the LDPC code in which a code length N is
64800 bits and an encoding rate r is 6/15, a group-wise
interleaving unit configured to perform the group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits,
and a mapping unit configured to map the LDPC code to any of 4096
signal points decided in a modulation scheme in units of 12 bits.
In the group-wise interleave, when an (i+1)-th bit group from a
head of the LDPC code is indicated by a bit group i, a sequence of
bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved
into a sequence of bit groups
[0158] 71, 38, 98, 159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151,
66, 92, 140, 6, 165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110,
128, 73, 148, 14, 5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122,
150, 103, 178, 119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143,
147, 89, 4, 107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153,
90, 152, 124, 7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175,
94, 115, 15, 112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162,
167, 164, 97, 82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105,
134, 173, 84, 9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111,
133, 56, 170, 104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35,
58, 45, 155, 70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69,
158, 129, 139, 62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and
137.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0159] 1606 3402 4961 6751 7132 11516 12300 12482 12592 13342 13764
14123 21576 23946 24533 25376 25667 26836 31799 34173 35462 36153
36740 37085 37152 37468 37658
[0160] 4621 5007 6910 8732 9757 11508 13099 15513 16335 18052 19512
21319 23663 25628 27208 31333 32219 33003 33239 33447 36200 36473
36938 37201 37283 37495 38642
[0161] 16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067
11017 11366 13136 13354 15379 18934 20199 24522 26172 28666 30386
32714 36390 37015 37162
[0162] 700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561
18745 21625 22137 23693 24340 24966 25015 26995 28586 28895 29687
33938 34520 34858 37056 38297
[0163] 159 2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836
14954 15594 16623 18065 19249 22394 22677 23408 23731 24076 24776
27007 28222 30343 38371
[0164] 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508 15536
20218 21921 28599 29445 29758 29968 31014 32027 33685 34378 35867
36323 36728 36870 38335 38623
[0165] 1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164
15665 18444 19470 20313 21189 24371 26431 26999 28086 28251 29261
31981 34015 35850 36129 37186
[0166] 111 1307 1628 2041 2524 5358 7988 8191 10322 11905 12919
14127 15515 15711 17061 19024 21195 22902 23727 24401 24608 25111
25228 27338 35398 37794 38196
[0167] 961 3035 7174 7948 13355 13607 14971 18189 18339 18665 18875
19142 20615 21136 21309 21758 23366 24745 25849 25982 27583 30006
31118 32106 36469 36583 37920
[0168] 2990 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262
12660 13085 14750 15680 16049 21587 23997 25803 28343 28693 34393
34860 35490 36021 37737 38296
[0169] 955 4323 5145 6885 8123 9730 11840 12216 19194 20313 23056
24248 24830 25268 26617 26801 28557 29753 30745 31450 31973 32839
33025 33296 35710 37366 37509
[0170] 264 605 4181 4483 5156 7238 8863 10939 11251 12964 16254
17511 20017 22395 22818 23261 23422 24064 26329 27723 28186 30434
31956 33971 34372 36764 38123
[0171] 520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783 11933
16336 17193 17320 19035 20606 23579 23769 24123 24966 27866 32457
34011 34499 36620 37526
[0172] 10106 10637 10906 34242
[0173] 1856 15100 19378 21848
[0174] 943 11191 27806 29411
[0175] 4575 6359 13629 19383
[0176] 4476 4953 18782 24313
[0177] 5441 6381 21840 35943
[0178] 9638 9763 12546 30120
[0179] 9587 10626 11047 25700
[0180] 4088 15298 28768 35047
[0181] 2332 6363 8782 28863
[0182] 4625 4933 28298 30289
[0183] 3541 491 8 18257 31746
[0184] 1221 25233 26757 34892
[0185] 8150 16677 27934 30021
[0186] 8500 25016 33043 38070
[0187] 7374 10207 16189 35811
[0188] 611 18480 20064 38261
[0189] 25416 27352 36089 38469
[0190] 1667 17614 25839 32776
[0191] 4118 12481 21912 37945
[0192] 5573 13222 23619 31271
[0193] 18271 26251 27182 30587
[0194] 14690 26430 26799 34355
[0195] 13688 16040 20716 34558
[0196] 2740 14957 23436 32540
[0197] 3491 14365 14681 36858
[0198] 4796 6238 25203 27854
[0199] 1731 12816 17344 26025
[0200] 19182 21662 23742 27872
[0201] 6502 13641 17509 34713
[0202] 12246 12372 16746 27452
[0203] 1589 21528 30621 34003
[0204] 12328 20515 30651 31432
[0205] 3415 22656 23427 36395
[0206] 632 5209 25958 31085
[0207] 619 3690 19648 37778
[0208] 9528 13581 26965 36447
[0209] 2147 26249 26968 28776
[0210] 15698 18209 30683
[0211] 1132 19888 34111
[0212] 4608 25513 38874
[0213] 475 1729 34100
[0214] 7348 32277 38587
[0215] 182 16473 33082
[0216] 3865 9678 21265
[0217] 4447 20151 27618
[0218] 6335 14371 38711
[0219] 704 9695 28858
[0220] 4856 9757 30546
[0221] 1993 19361 30732
[0222] 756 28000 29138
[0223] 3821 24076 31813
[0224] 4611 12326 32291
[0225] 7628 21515 34995
[0226] 1246 13294 30068
[0227] 6466 33233 35865
[0228] 14484 23274 38150
[0229] 21269 36411 37450
[0230] 23129 26195 37653.
[0231] In the second data processing device/method according to the
present technology, a sequence of an LDPC code that has undergone
group-wise interleave and has been obtained from data transmitted
from a transmitting device is restored to an original sequence, the
transmitting device including an encoding unit configured to
perform LDPC encoding based on a parity check matrix of the LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 6/15, a group-wise interleaving unit configured to perform the
group-wise interleave of interleaving the LDPC code in units of bit
groups of 360 bits, and a mapping unit configured to map the LDPC
code to any of 4096 signal points decided in a modulation scheme in
units of 12 bits. In the group-wise interleave, when an (i+1)-th
bit group from a head of the LDPC code is indicated by a bit group
i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits
is interleaved into a sequence of bit groups
[0232] 71, 38, 98, 159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151,
66, 92, 140, 6, 165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110,
128, 73, 148, 14, 5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122,
150, 103, 178, 119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143,
147, 89, 4, 107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153,
90, 152, 124, 7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175,
94, 115, 15, 112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162,
167, 164, 97, 82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105,
134, 173, 84, 9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111,
133, 56, 170, 104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35,
58, 45, 155, 70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69,
158, 129, 139, 62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and
137.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0233] 1606 3402 4961 6751 7132 11516 12300 12482 12592 13342 13764
14123 21576 23946 24533 25376 25667 26836 31799 34173 35462 36153
36740 37085 37152 37468 37658
[0234] 4621 5007 6910 8732 9757 11508 13099 15513 16335 18052 19512
21319 23663 25628 27208 31333 32219 33003 33239 33447 36200 36473
36938 37201 37283 37495 38642
[0235] 16 1094 2020 3080 4194 5098 5631 6877 7889 8237 9804 10067
11017 11366 13136 13354 15379 18934 20199 24522 26172 28666 30386
32714 36390 37015 37162
[0236] 700 897 1708 6017 6490 7372 7825 9546 10398 16605 18561
18745 21625 22137 23693 24340 24966 25015 26995 28586 28895 29687
33938 34520 34858 37056 38297
[0237] 159 2010 2573 3617 4452 4958 5556 5832 6481 8227 9924 10836
14954 15594 16623 18065 19249 22394 22677 23408 23731 24076 24776
27007 28222 30343 38371
[0238] 3118 3545 4768 4992 5227 6732 8170 9397 10522 11508 15536
20218 21921 28599 29445 29758 29968 31014 32027 33685 34378 35867
36323 36728 36870 38335 38623
[0239] 1264 4254 6936 9165 9486 9950 10861 11653 13697 13961 15164
15665 18444 19470 20313 21189 24371 26431 26999 28086 28251 29261
31981 34015 35850 36129 37186
[0240] 111 1307 1628 2041 2524 5358 7988 8191 10322 11905 12919
14127 15515 15711 17061 19024 21195 22902 23727 24401 24608 25111
25228 27338 35398 37794 38196
[0241] 961 3035 7174 7948 13355 13607 14971 18189 18339 18665 18875
19142 20615 21136 21309 21758 23366 24745 25849 25982 27583 30006
31118 32106 36469 36583 37920
[0242] 2990 3549 4273 4808 5707 6021 6509 7456 8240 10044 12262
12660 13085 14750 15680 16049 21587 23997 25803 28343 28693 34393
34860 35490 36021 37737 38296
[0243] 955 4323 5145 6885 8123 9730 11840 12216 19194 20313 23056
24248 24830 25268 26617 26801 28557 29753 30745 31450 31973 32839
33025 33296 35710 37366 37509
[0244] 264 605 4181 4483 5156 7238 8863 10939 11251 12964 16254
17511 20017 22395 22818 23261 23422 24064 26329 27723 28186 30434
31956 33971 34372 36764 38123
[0245] 520 2562 2794 3528 3860 4402 5676 6963 8655 9018 9783 11933
16336 17193 17320 19035 20606 23579 23769 24123 24966 27866 32457
34011 34499 36620 37526
[0246] 10106 10637 10906 34242
[0247] 1856 15100 19378 21848
[0248] 943 11191 27806 29411
[0249] 4575 6359 13629 19383
[0250] 4476 4953 18782 24313
[0251] 5441 6381 21840 35943
[0252] 9638 9763 12546 30120
[0253] 9587 10626 11047 25700
[0254] 4088 15298 28768 35047
[0255] 2332 6363 8782 28863
[0256] 4625 4933 28298 30289
[0257] 3541 4918 18257 31746
[0258] 1221 25233 26757 34892
[0259] 8150 16677 27934 30021
[0260] 8500 25016 33043 38070
[0261] 7374 10207 16189 35811
[0262] 611 18480 20064 38261
[0263] 25416 27352 36089 38469
[0264] 1667 17614 25839 32776
[0265] 4118 12481 21912 37945
[0266] 5573 13222 23619 31271
[0267] 18271 26251 27182 30587
[0268] 14690 26430 26799 34355
[0269] 13688 16040 20716 34558
[0270] 2740 14957 23436 32540
[0271] 3491 14365 14681 36858
[0272] 4796 6238 25203 27854
[0273] 1731 12816 17344 26025
[0274] 19182 21662 23742 27872
[0275] 6502 13641 17509 34713
[0276] 12246 12372 16746 27452
[0277] 1589 21528 30621 34003
[0278] 12328 20515 30651 31432
[0279] 3415 22656 23427 36395
[0280] 632 5209 25958 31085
[0281] 619 3690 19648 37778
[0282] 9528 13581 26965 36447
[0283] 2147 26249 26968 28776
[0284] 15698 18209 30683
[0285] 1132 19888 34111
[0286] 4608 25513 38874
[0287] 475 1729 34100
[0288] 7348 32277 38587
[0289] 182 16473 33082
[0290] 3865 9678 21265
[0291] 4447 20151 27618
[0292] 6335 14371 38711
[0293] 704 9695 28858
[0294] 4856 9757 30546
[0295] 1993 19361 30732
[0296] 756 28000 29138
[0297] 3821 24076 31813
[0298] 4611 12326 32291
[0299] 7628 21515 34995
[0300] 1246 13294 30068
[0301] 6466 33233 35865
[0302] 14484 23274 38150
[0303] 21269 36411 37450
[0304] 23129 26195 37653.
[0305] A third data processing device/method according to the
present technology is a data processing device/method including: an
encoding unit/step configured to perform LDPC encoding based on a
parity check matrix of an LDPC code in which a code length N is
64800 bits and an encoding rate r is 7/15; a group-wise
interleaving unit/step configured to perform group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits;
and a mapping unit/step configured to map the LDPC code to any of
4096 signal points decided in a modulation scheme in units of 12
bits. In the group-wise interleave, when an (i+1)-th bit group from
a head of the LDPC code is indicated by a bit group i, a sequence
of bit groups 0 to 179 of the LDPC code of 64800 bits is
interleaved into a sequence of bit groups
[0306] 66, 61, 150, 157, 63, 42, 78, 44, 23, 154, 133, 101, 82, 26,
84, 123, 89, 31, 45, 102, 36, 134, 83, 117, 170, 27, 73, 137, 25,
32, 62, 91, 4, 20, 144, 145, 21, 74, 113, 148, 24, 135, 5, 19, 2,
34, 43, 168, 14, 64, 142, 115, 87, 38, 147, 39, 51, 152, 56, 86,
122, 76, 57, 129, 172, 6, 126, 10, 97, 85, 164, 3, 80, 90, 79, 124,
138, 120, 17, 103, 99, 116, 46, 98, 162, 151, 143, 11, 175, 160,
96, 132, 81, 171, 94, 65, 118, 161, 125, 178, 95, 112, 88, 174, 13,
35, 1, 167, 0, 128, 12, 58, 29, 169, 67, 28, 119, 166, 60, 55, 54,
130, 92, 146, 177, 149, 111, 9, 173, 179, 176, 75, 77, 114, 48,
159, 8, 141, 107, 139, 52, 100, 136, 105, 127, 47, 18, 69, 109, 16,
121, 59, 163, 165, 108, 106, 70, 22, 93, 41, 33, 110, 53, 140, 153,
158, 50, 15, 37, 72, 156, 7, 131, 49, 71, 68, 104, 30, 40, and
155.
The parity check matrix includes a g.times.K A matrix arranged on
an upper left of the parity check matrix, the A matrix being
indicated by a predetermined value g and an information length
K=N.times.r of the LDPC code, a g.times.g B matrix having a
staircase structure, the B matrix being adjacent to the right of
the A matrix, a g.times.(N-K-g) Z matrix serving as a zero matrix
adjacent to the right of the B matrix, an (N-K-g).times.(K+g) C
matrix adjacently below the A matrix and the B matrix, and an
(N-K-g).times.(N-K-g) D matrix serving as a unit matrix adjacent to
the right of the C matrix. The predetermined value g is 1080. The A
matrix and the C matrix are represented by a parity check matrix
initial value table. The parity check matrix initial value table is
a table in which positions of 1 elements of the A matrix and the C
matrix are indicated for every 360 columns, and includes
[0307] 460 792 1007 4580 11452 13130 26882 27020 32439
[0308] 35 472 1056 7154 12700 13326 13414 16828 19102
[0309] 45 440 772 4854 7863 26945 27684 28651 31875
[0310] 744 812 892 1509 9018 12925 14140 21357 25106
[0311] 271 474 761 4268 6706 9609 19701 19707 24870
[0312] 223 477 662 1987 9247 18376 22148 24948 27694
[0313] 44 379 786 8823 12322 14666 16377 28688 29924
[0314] 104 219 562 5832 19665 20615 21043 22759 32180
[0315] 41 43 870 7963 13718 14136 17216 30470 33428
[0316] 592 744 887 4513 6192 18116 19482 25032 34095
[0317] 456 821 1078 7162 7443 8774 15567 17243 33085
[0318] 151 666 977 6946 10358 11172 18129 19777 32234
[0319] 236 793 870 2001 6805 9047 13877 30131 34252
[0320] 297 698 772 3449 4204 11608 22950 26071 27512
[0321] 202 428 474 3205 3726 6223 7708 20214 25283
[0322] 139 719 915 1447 2938 11864 15932 21748 28598
[0323] 135 853 902 3239 18590 20579 30578 33374 34045
[0324] 9 13 971 11834 13642 17628 21669 24741 30965
[0325] 344 531 730 1880 16895 17587 21901 28620 31957
[0326] 7 192 380 3168 3729 5518 6827 20372 34168
[0327] 28 521 681 4313 7465 14209 21501 23364 25980
[0328] 269 393 898 3561 11066 11985 17311 26127 30309
[0329] 42 82 707 4880 4890 9818 23340 25959 31695
[0330] 189 262 707 6573 14082 22259 24230 24390 24664
[0331] 383 568 573 5498 13449 13990 16904 22629 34203
[0332] 585 596 820 2440 2488 21956 28261 28703 29591
[0333] 755 763 795 5636 16433 21714 23452 31150 34545
[0334] 23 343 669 1159 3507 13096 17978 24241 34321
[0335] 316 384 944 4872 8491 18913 21085 23198 24798
[0336] 64 314 765 3706 7136 8634 14227 17127 23437
[0337] 220 693 899 8791 12417 13487 18335 22126 27428
[0338] 285 794 1045 8624 8801 9547 19167 21894 32657
[0339] 386 621 1045 1634 1882 3172 13686 16027 22448
[0340] 95 622 693 2827 7098 11452 14112 18831 31308
[0341] 446 813 928 7976 8935 13146 27117 27766 33111
[0342] 89 138 241 3218 9283 20458 31484 31538 34216
[0343] 277 420 704 9281 12576 12788 14496 15357 20585
[0344] 141 643 758 4894 10264 15144 16357 22478 26461
[0345] 17 108 160 13183 15424 17939 19276 23714 26655
[0346] 109 285 608 1682 20223 21791 24615 29622 31983
[0347] 123 515 622 7037 13946 15292 15606 16262 23742
[0348] 264 565 923 6460 13622 13934 23181 25475 26134
[0349] 202 548 789 8003 10993 12478 16051 25114 27579
[0350] 121 450 575 5972 10062 18693 21852 23874 28031
[0351] 507 560 889 12064 13316 19629 21547 25461 28732
[0352] 664 786 1043 9137 9294 10163 23389 31436 34297
[0353] 45 830 907 10730 16541 21232 30354 30605 31847
[0354] 203 507 1060 6971 12216 13321 17861 22671 29825
[0355] 369 881 952 3035 12279 12775 17682 17805 34281
[0356] 683 709 1032 3787 17623 24138 26775 31432 33626
[0357] 524 792 1042 12249 14765 18601 25811 32422 33163
[0358] 137 639 688 7182 8169 10443 22530 24597 29039
[0359] 159 643 749 16386 17401 24135 28429 33468 33469
[0360] 107 481 555 7322 13234 19344 23498 26581 31378
[0361] 249 389 523 3421 10150 17616 19085 20545 32069
[0362] 395 738 1045 2415 3005 3820 19541 23543 31068
[0363] 27 293 703 1717 3460 8326 8501 10290 32625
[0364] 126 247 515 6031 9549 10643 22067 29490 34450
[0365] 331 471 1007 3020 3922 7580 23358 28620 30946
[0366] 222 542 1021 3291 3652 13130 16349 33009 34348
[0367] 532 719 1038 5891 7528 23252 25472 31395 31774
[0368] 145 398 774 7816 13887 14936 23708 31712 33160
[0369] 88 536 600 1239 1887 12195 13782 16726 27998
[0370] 151 269 585 1445 3178 3970 15568 20358 21051
[0371] 650 819 865 15567 18546 25571 32038 33350 33620
[0372] 93 469 800 6059 10405 12296 17515 21354 22231
[0373] 97 206 951 6161 16376 27022 29192 30190 30665
[0374] 412 549 986 5833 10583 10766 24946 28878 31937
[0375] 72 604 659 5267 12227 21714 32120 33472 33974
[0376] 25 902 912 1137 2975 9642 11598 25919 28278
[0377] 420 976 1055 8473 11512 20198 21662 25443 30119
[0378] 1 24 932 6426 11899 13217 13935 16548 29737
[0379] 53 618 988 6280 7267 11676 13575 15532 25787
[0380] 111 739 809 8133 12717 12741 20253 20608 27850
[0381] 120 683 943 14496 15162 15440 18660 27543 32404
[0382] 600 754 1055 7873 9679 17351 27268 33508
[0383] 344 756 1054 7102 7193 22903 24720 27883
[0384] 582 1003 1046 11344 23756 27497 27977 32853
[0385] 28 429 509 11106 11767 12729 13100 31792
[0386] 131 555 907 5113 10259 10300 20580 23029
[0387] 406 915 977 12244 20259 26616 27899 32228
[0388] 46 195 224 1229 4116 10263 13608 17830
[0389] 19 819 953 7965 9998 13959 30580 30754
[0390] 164 1003 1032 12920 15975 16582 22624 27357
[0391] 8433 11894 13531 17675 25889 31384
[0392] 3166 3813 8596 10368 25104 29584
[0393] 2466 8241 12424 13376 24837 32711.
[0394] In the third data processing device/method according to the
present technology, LDPC encoding is performed based on a parity
check matrix of an LDPC code in which a code length N is 64800 bits
and an encoding rate r is 7/15. Group-wise interleave of
interleaving the LDPC code in units of bit groups of 360 bits is
performed. The LDPC code is mapped to any of 4096 signal points
decided in a modulation scheme in units of 12 bits. In the
group-wise interleave, when an (i+1)-th bit group from a head of
the LDPC code is indicated by a bit group i, a sequence of bit
groups 0 to 179 of the LDPC code of 64800 bits is interleaved into
a sequence of bit groups
[0395] 66, 61, 150, 157, 63, 42, 78, 44, 23, 154, 133, 101, 82, 26,
84, 123, 89, 31, 45, 102, 36, 134, 83, 117, 170, 27, 73, 137, 25,
32, 62, 91, 4, 20, 144, 145, 21, 74, 113, 148, 24, 135, 5, 19, 2,
34, 43, 168, 14, 64, 142, 115, 87, 38, 147, 39, 51, 152, 56, 86,
122, 76, 57, 129, 172, 6, 126, 10, 97, 85, 164, 3, 80, 90, 79, 124,
138, 120, 17, 103, 99, 116, 46, 98, 162, 151, 143, 11, 175, 160,
96, 132, 81, 171, 94, 65, 118, 161, 125, 178, 95, 112, 88, 174, 13,
35, 1, 167, 0, 128, 12, 58, 29, 169, 67, 28, 119, 166, 60, 55, 54,
130, 92, 146, 177, 149, 111, 9, 173, 179, 176, 75, 77, 114, 48,
159, 8, 141, 107, 139, 52, 100, 136, 105, 127, 47, 18, 69, 109, 16,
121, 59, 163, 165, 108, 106, 70, 22, 93, 41, 33, 110, 53, 140, 153,
158, 50, 15, 37, 72, 156, 7, 131, 49, 71, 68, 104, 30, 40, and
155.
The parity check matrix includes a g.times.K A matrix arranged on
an upper left of the parity check matrix, the A matrix being
indicated by a predetermined value g and an information length
K=N.times.r of the LDPC code, a g.times.g B matrix having a
staircase structure, the B matrix being adjacent to the right of
the A matrix, a g.times.(N-K-g) Z matrix serving as a zero matrix
adjacent to the right of the B matrix, an (N-K-g).times.(K+g) C
matrix adjacently below the A matrix and the B matrix, and an
(N-K-g).times.(N-K-g) D matrix serving as a unit matrix adjacent to
the right of the C matrix. The predetermined value g is 1080. The A
matrix and the C matrix are represented by a parity check matrix
initial value table. The parity check matrix initial value table is
a table in which positions of 1 elements of the A matrix and the C
matrix are indicated for every 360 columns, and includes
[0396] 460 792 1007 4580 11452 13130 26882 27020 32439
[0397] 35 472 1056 7154 12700 13326 13414 16828 19102
[0398] 45 440 772 4854 7863 26945 27684 28651 31875
[0399] 744 812 892 1509 9018 12925 14140 21357 25106
[0400] 271 474 761 4268 6706 9609 19701 19707 24870
[0401] 223 477 662 1987 9247 18376 22148 24948 27694
[0402] 44 379 786 8823 12322 14666 16377 28688 29924
[0403] 104 219 562 5832 19665 20615 21043 22759 32180
[0404] 41 43 870 7963 13718 14136 17216 30470 33428
[0405] 592 744 887 4513 6192 18116 19482 25032 34095
[0406] 456 821 1078 7162 7443 8774 15567 17243 33085
[0407] 151 666 977 6946 10358 11172 18129 19777 32234
[0408] 236 793 870 2001 6805 9047 13877 30131 34252
[0409] 297 698 772 3449 4204 11608 22950 26071 27512
[0410] 202 428 474 3205 3726 6223 7708 20214 25283
[0411] 139 719 915 1447 2938 11864 15932 21748 28598
[0412] 135 853 902 3239 18590 20579 30578 33374 34045
[0413] 9 13 971 11834 13642 17628 21669 24741 30965
[0414] 344 531 730 1880 16895 17587 21901 28620 31957
[0415] 7 192 380 3168 3729 5518 6827 20372 34168
[0416] 28 521 681 4313 7465 14209 21501 23364 25980
[0417] 269 393 898 3561 11066 11985 17311 26127 30309
[0418] 42 82 707 4880 4890 9818 23340 25959 31695
[0419] 189 262 707 6573 14082 22259 24230 24390 24664
[0420] 383 568 573 5498 13449 13990 16904 22629 34203
[0421] 585 596 820 2440 2488 21956 28261 28703 29591
[0422] 755 763 795 5636 16433 21714 23452 3 1150 34545
[0423] 23 343 669 1159 3507 13096 17978 24241 34321
[0424] 316 384 944 4872 8491 18913 21085 23198 24798
[0425] 64 314 765 3706 7136 8634 14227 17127 23437
[0426] 220 693 899 8791 12417 13487 18335 22126 27428
[0427] 285 794 1045 8624 8801 9547 19167 21894 32657
[0428] 386 621 1045 1634 1882 3172 13686 16027 22448
[0429] 95 622 693 2827 7098 11452 14112 18831 31308
[0430] 446 813 928 7976 8935 13146 27117 27766 33111
[0431] 89 138 241 3218 9283 20458 31484 31538 34216
[0432] 277 420 704 9281 12576 12788 14496 15357 20585
[0433] 141 643 758 4894 10264 15144 16357 22478 26461
[0434] 17 108 160 13183 15424 17939 19276 23714 26655
[0435] 109 285 608 1682 20223 21791 24615 29622 31983
[0436] 123 515 622 7037 13946 15292 15606 16262 23742
[0437] 264 565 923 6460 13622 13934 23181 25475 26134
[0438] 202 548 789 8003 10993 12478 16051 25114 27579
[0439] 121 450 575 5972 10062 18693 21852 23874 28031
[0440] 507 560 889 12064 13316 19629 21547 25461 28732
[0441] 664 786 1043 9137 9294 10163 23389 31436 34297
[0442] 45 830 907 10730 16541 21232 30354 30605 31847
[0443] 203 507 1060 6971 12216 13321 17861 22671 29825
[0444] 369 881 952 3035 12279 12775 17682 17805 34281
[0445] 683 709 1032 3787 17623 24138 26775 31432 33626
[0446] 524 792 1042 12249 14765 18601 25811 32422 33163
[0447] 137 639 688 7182 8169 10443 22530 24597 29039
[0448] 159 643 749 16386 17401 24135 28429 33468 33469
[0449] 107 481 555 7322 13234 19344 23498 26581 31378
[0450] 249 389 523 3421 10150 17616 19085 20545 32069
[0451] 395 738 1045 2415 3005 3820 19541 23543 31068
[0452] 27 293 703 1717 3460 8326 8501 10290 32625
[0453] 126 247 515 6031 9549 10643 22067 29490 34450
[0454] 331 471 1007 3020 3922 7580 23358 28620 30946
[0455] 222 542 1021 3291 3652 13130 16349 33009 34348
[0456] 532 719 1038 5891 7528 23252 25472 31395 31774
[0457] 145 398 774 7816 13887 14936 23708 31712 33160
[0458] 88 536 600 1239 1887 12195 13782 16726 27998
[0459] 151 269 585 1445 3178 3970 15568 20358 21051
[0460] 650 819 865 15567 18546 25571 32038 33350 33620
[0461] 93 469 800 6059 10405 12296 17515 21354 22231
[0462] 97 206 951 6161 16376 27022 29192 30190 30665
[0463] 412 549 986 5833 10583 10766 24946 28878 31937
[0464] 72 604 659 5267 12227 21714 32120 33472 33974
[0465] 25 902 912 1137 2975 9642 11598 25919 28278
[0466] 420 976 1055 8473 11512 20198 21662 25443 30119
[0467] 1 24 932 6426 11899 13217 13935 16548 29737
[0468] 53 618 988 6280 7267 11676 13575 15532 25787
[0469] 111 739 809 8133 12717 12741 20253 20608 27850
[0470] 120 683 943 14496 15162 15440 18660 27543 32404
[0471] 600 754 1055 7873 9679 17351 27268 33508
[0472] 344 756 1054 7102 7193 22903 24720 27883
[0473] 582 1003 1046 11344 23756 27497 27977 32853
[0474] 28 429 509 11106 11767 12729 13100 31792
[0475] 131 555 907 5113 10259 10300 20580 23029
[0476] 406 915 977 12244 20259 26616 27899 32228
[0477] 46 195 224 1229 4116 10263 13608 17830
[0478] 19 819 953 7965 9998 13959 30580 30754
[0479] 164 1003 1032 12920 15975 16582 22624 27357
[0480] 8433 11894 13531 17675 25889 31384
[0481] 3166 3813 8596 10368 25104 29584
[0482] 2466 8241 12424 13376 24837 32711.
[0483] A fourth data processing device/method according to the
present technology is a data processing device/method including: a
group-wise deinterleaving unit/step configured to restore a
sequence of an LDPC code that has undergone group-wise interleave
and has been obtained from data transmitted from a transmitting
device to an original sequence, the transmitting device including
an encoding unit configured to perform LDPC encoding based on a
parity check matrix of the LDPC code in which a code length N is
64800 bits and an encoding rate r is 7/15, a group-wise
interleaving unit configured to perform the group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits,
and a mapping unit configured to map the LDPC code to any of 4096
signal points decided in a modulation scheme in units of 12 bits.
In the group-wise interleave, when an (i+1)-th bit group from a
head of the LDPC code is indicated by a bit group i, a sequence of
bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved
into a sequence of bit groups
[0484] 66, 61, 150, 157, 63, 42, 78, 44, 23, 154, 133, 101, 82, 26,
84, 123, 89, 31, 45, 102, 36, 134, 83, 117, 170, 27, 73, 137, 25,
32, 62, 91, 4, 20, 144, 145, 21, 74, 113, 148, 24, 135, 5, 19, 2,
34, 43, 168, 14, 64, 142, 115, 87, 38, 147, 39, 51, 152, 56, 86,
122, 76, 57, 129, 172, 6, 126, 10, 97, 85, 164, 3, 80, 90, 79, 124,
138, 120, 17, 103, 99, 116, 46, 98, 162, 151, 143, 11, 175, 160,
96, 132, 81, 171, 94, 65, 118, 161, 125, 178, 95, 112, 88, 174, 13,
35, 1, 167, 0, 128, 12, 58, 29, 169, 67, 28, 119, 166, 60, 55, 54,
130, 92, 146, 177, 149, 111, 9, 173, 179, 176, 75, 77, 114, 48,
159, 8, 141, 107, 139, 52, 100, 136, 105, 127, 47, 18, 69, 109, 16,
121, 59, 163, 165, 108, 106, 70, 22, 93, 41, 33, 110, 53, 140, 153,
158, 50, 15, 37, 72, 156, 7, 131, 49, 71, 68, 104, 30, 40, and
155.
The parity check matrix includes a g.times.K A matrix arranged on
an upper left of the parity check matrix, the A matrix being
indicated by a predetermined value g and an information length
K=N.times.r of the LDPC code, a g.times.g B matrix having a
staircase structure, the B matrix being adjacent to the right of
the A matrix, a g.times.(N-K-g) Z matrix serving as a zero matrix
adjacent to the right of the B matrix, an (N-K-g).times.(K+g) C
matrix adjacently below the A matrix and the B matrix, and an
(N-K-g).times.(N-K-g) D matrix serving as a unit matrix adjacent to
the right of the C matrix. The predetermined value g is 1080. The A
matrix and the C matrix are represented by a parity check matrix
initial value table. The parity check matrix initial value table is
a table in which positions of 1 elements of the A matrix and the C
matrix are indicated for every 360 columns, and includes
[0485] 460 792 1007 4580 11452 13130 26882 27020 32439
[0486] 35 472 1056 7154 12700 13326 13414 16828 19102
[0487] 45 440 772 4854 7863 26945 27684 28651 31875
[0488] 744 812 892 1509 9018 12925 14140 21357 25106
[0489] 271 474 761 4268 6706 9609 19701 19707 24870
[0490] 223 477 662 1987 9247 18376 22148 24948 27694
[0491] 44 379 786 8823 12322 14666 16377 28688 29924
[0492] 104 219 562 5832 19665 20615 21043 22759 32180
[0493] 41 43 870 7963 13718 14136 17216 30470 33428
[0494] 592 744 887 4513 6192 18116 19482 25032 34095
[0495] 456 821 1078 7162 7443 8774 15567 17243 33085
[0496] 151 666 977 6946 10358 11172 18129 19777 32234
[0497] 236 793 870 2001 6805 9047 13877 30131 34252
[0498] 297 698 772 3449 4204 11608 22950 26071 27512
[0499] 202 428 474 3205 3726 6223 7708 20214 25283
[0500] 139 719 915 1447 2938 11864 15932 21748 28598
[0501] 135 853 902 3239 18590 20579 30578 33374 34045
[0502] 9 13 971 11834 13642 17628 21669 24741 30965
[0503] 344 531 730 1880 16895 17587 21901 28620 31957
[0504] 7 192 380 3168 3729 5518 6827 20372 34168
[0505] 28 521 681 4313 7465 14209 21501 23364 25980
[0506] 269 393 898 3561 11066 11985 17311 26127 30309
[0507] 42 82 707 4880 4890 9818 23340 25959 31695
[0508] 189 262 707 6573 14082 22259 24230 24390 24664
[0509] 383 568 573 5498 13449 13990 16904 22629 34203
[0510] 585 596 820 2440 2488 21956 28261 28703 29591
[0511] 755 763 795 5636 16433 21714 23452 31150 34545
[0512] 23 343 669 1159 3507 13096 17978 24241 34321
[0513] 316 384 944 4872 8491 18913 21085 23198 24798
[0514] 64 314 765 3706 7136 8634 14227 17127 23437
[0515] 220 693 899 8791 12417 13487 18335 22126 27428
[0516] 285 794 1045 8624 8801 9547 19167 21894 32657
[0517] 386 621 1045 1634 1882 3172 13686 16027 22448
[0518] 95 622 693 2827 7098 11452 14112 18831 31308
[0519] 446 813 928 7976 893 5 13146 27117 27766 33111
[0520] 89 138 241 3218 9283 20458 31484 31538 34216
[0521] 277 420 704 9281 12576 12788 14496 15357 20585
[0522] 141 643 758 4894 10264 15144 16357 22478 26461
[0523] 17 108 160 13183 15424 17939 19276 23714 26655
[0524] 109 285 608 1682 20223 21791 24615 29622 31983
[0525] 123 515 622 7037 13946 15292 15606 16262 23742
[0526] 264 565 923 6460 13622 13934 23181 25475 26134
[0527] 202 548 789 8003 10993 12478 16051 25114 27579
[0528] 121 450 575 5972 10062 18693 21852 23874 28031
[0529] 507 560 889 12064 13316 19629 21547 25461 28732
[0530] 664 786 1043 9137 9294 10163 23389 31436 34297
[0531] 45 830 907 10730 16541 21232 30354 30605 31847
[0532] 203 507 1060 6971 12216 13321 17861 22671 29825
[0533] 369 881 952 3035 12279 12775 17682 17805 34281
[0534] 683 709 1032 3787 17623 24138 26775 31432 33626
[0535] 524 792 1042 12249 14765 18601 25811 32422 33163
[0536] 137 639 688 7182 8169 10443 22530 24597 29039
[0537] 159 643 749 16386 17401 24135 28429 33468 33469
[0538] 107 481 555 7322 13234 19344 23498 26581 31378
[0539] 249 389 523 3421 10150 17616 19085 20545 32069
[0540] 395 738 1045 2415 3005 3820 19541 23543 31068
[0541] 27 293 703 1717 3460 8326 8501 10290 32625
[0542] 126 247 515 6031 9549 10643 22067 29490 34450
[0543] 331 471 1007 3020 3922 7580 23358 28620 30946
[0544] 222 542 1021 3291 3652 13130 16349 33009 34348
[0545] 532 719 1038 5891 7528 23252 25472 31395 31774
[0546] 145 398 774 7816 13887 14936 23708 31712 33160
[0547] 88 536 600 1239 1887 12195 13782 16726 27998
[0548] 151 269 585 1445 3178 3970 15568 20358 21051
[0549] 650 819 865 15567 18546 25571 32038 33350 33620
[0550] 93 469 800 6059 10405 12296 17515 21354 22231
[0551] 97 206 951 6161 16376 27022 29192 30190 30665
[0552] 412 549 986 5833 10583 10766 24946 28878 31937
[0553] 72 604 659 5267 12227 21714 32120 33472 33974
[0554] 25 902 912 1137 2975 9642 11598 25919 28278
[0555] 420 976 1055 8473 11512 20198 21662 25443 30119
[0556] 1 24 932 6426 11899 13217 13935 16548 29737
[0557] 53 618 988 6280 7267 11676 13575 15532 25787
[0558] 111 739 809 8133 12717 12741 20253 20608 27850
[0559] 120 683 943 14496 15162 15440 18660 27543 32404
[0560] 600 754 1055 7873 9679 17351 27268 33508
[0561] 344 756 1054 7102 7193 22903 24720 27883
[0562] 582 1003 1046 11344 23756 27497 27977 32853
[0563] 28 429 509 11106 11767 12729 13100 31792
[0564] 131 555 907 5113 10259 10300 20580 23029
[0565] 406 915 977 12244 20259 26616 27899 32228
[0566] 46 195 224 1229 4116 10263 13608 17830
[0567] 19 819 953 7965 9998 13959 30580 30754
[0568] 164 1003 1032 12920 15975 16582 22624 27357
[0569] 8433 11894 13531 17675 25889 31384
[0570] 3166 3813 8596 10368 25104 29584
[0571] 2466 8241 12424 13376 24837 32711.
[0572] In the fourth data processing device/method according to the
present technology, a sequence of an LDPC code that has undergone
group-wise interleave and has been obtained from data transmitted
from a transmitting device is restored to an original sequence, the
transmitting device including an encoding unit configured to
perform LDPC encoding based on a parity check matrix of the LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 7/15, a group-wise interleaving unit configured to perform the
group-wise interleave of interleaving the LDPC code in units of bit
groups of 360 bits, and a mapping unit configured to map the LDPC
code to any of 4096 signal points decided in a modulation scheme in
units of 12 bits. In the group-wise interleave, when an (i+1)-th
bit group from a head of the LDPC code is indicated by a bit group
i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits
is interleaved into a sequence of bit groups
[0573] 66, 61, 150, 157, 63, 42, 78, 44, 23, 154, 133, 101, 82, 26,
84, 123, 89, 31, 45, 102, 36, 134, 83, 117, 170, 27, 73, 137, 25,
32, 62, 91, 4, 20, 144, 145, 21, 74, 113, 148, 24, 135, 5, 19, 2,
34, 43, 168, 14, 64, 142, 115, 87, 38, 147, 39, 51, 152, 56, 86,
122, 76, 57, 129, 172, 6, 126, 10, 97, 85, 164, 3, 80, 90, 79, 124,
138, 120, 17, 103, 99, 116, 46, 98, 162, 151, 143, 11, 175, 160,
96, 132, 81, 171, 94, 65, 118, 161, 125, 178, 95, 112, 88, 174, 13,
35, 1, 167, 0, 128, 12, 58, 29, 169, 67, 28, 119, 166, 60, 55, 54,
130, 92, 146, 177, 149, 111, 9, 173, 179, 176, 75, 77, 114, 48,
159, 8, 141, 107, 139, 52, 100, 136, 105, 127, 47, 18, 69, 109, 16,
121, 59, 163, 165, 108, 106, 70, 22, 93, 41, 33, 110, 53, 140, 153,
158, 50, 15, 37, 72, 156, 7, 131, 49, 71, 68, 104, 30, 40, and
155.
The parity check matrix includes a g.times.K A matrix arranged on
an upper left of the parity check matrix, the A matrix being
indicated by a predetermined value g and an information length
K=N.times.r of the LDPC code, a g.times.g B matrix having a
staircase structure, the B matrix being adjacent to the right of
the A matrix, a g.times.(N-K-g) Z matrix serving as a zero matrix
adjacent to the right of the B matrix, an (N-K-g).times.(K+g) C
matrix adjacently below the A matrix and the B matrix, and an
(N-K-g).times.(N-K-g) D matrix serving as a unit matrix adjacent to
the right of the C matrix. The predetermined value g is 1080. The A
matrix and the C matrix are represented by a parity check matrix
initial value table. The parity check matrix initial value table is
a table in which positions of 1 elements of the A matrix and the C
matrix are indicated for every 360 columns, and includes
[0574] 460 792 1007 4580 11452 13130 26882 27020 32439
[0575] 35 472 1056 7154 12700 13326 13414 16828 19102
[0576] 45 440 772 4854 7863 26945 27684 28651 31875
[0577] 744 812 892 1509 9018 12925 14140 21357 25106
[0578] 271 474 761 4268 6706 9609 19701 19707 24870
[0579] 223 477 662 1987 9247 18376 22148 24948 27694
[0580] 44 379 786 8823 12322 14666 16377 28688 29924
[0581] 104 219 562 5832 19665 20615 21043 22759 32180
[0582] 41 43 870 7963 13718 14136 17216 30470 33428
[0583] 592 744 887 4513 6192 18116 19482 25032 34095
[0584] 456 821 1078 7162 7443 8774 15567 17243 33085
[0585] 151 666 977 6946 10358 11172 18129 19777 32234
[0586] 236 793 870 2001 6805 9047 13877 30131 34252
[0587] 297 698 772 3449 4204 11608 22950 26071 27512
[0588] 202 428 474 3205 3726 6223 7708 20214 25283
[0589] 139 719 915 1447 2938 11864 15932 21748 28598
[0590] 135 853 902 3239 18590 20579 30578 33374 34045
[0591] 9 13 971 11834 13642 17628 21669 24741 30965
[0592] 344 531 730 1880 16895 17587 21901 28620 31957
[0593] 7 192 380 3168 3729 5518 6827 20372 34168
[0594] 28 521 681 4313 7465 14209 21501 23364 25980
[0595] 269 393 898 3561 11066 11985 17311 26127 30309
[0596] 42 82 707 4880 4890 9818 23340 25959 31695
[0597] 189 262 707 6573 14082 22259 24230 24390 24664
[0598] 383 568 573 5498 13449 13990 16904 22629 34203
[0599] 585 596 820 2440 2488 21956 28261 28703 29591
[0600] 755 763 795 5636 16433 21714 23452 31150 34545
[0601] 23 343 669 1159 3507 13096 17978 24241 34321
[0602] 316 384 944 4872 8491 18913 21085 23198 24798
[0603] 64 314 765 3706 7136 8634 14227 17127 23437
[0604] 220 693 899 8791 12417 13487 18335 22126 27428
[0605] 285 794 1045 8624 8801 9547 19167 21894 32657
[0606] 386 621 1045 1634 1882 3172 13686 16027 22448
[0607] 95 622 693 2827 7098 11452 14112 18831 31308
[0608] 446 813 928 7976 8935 13146 27117 27766 33111
[0609] 89 138 241 3218 9283 20458 31484 31538 34216
[0610] 277 420 704 9281 12576 12788 14496 15357 20585
[0611] 141 643 758 4894 10264 15144 16357 22478 26461
[0612] 17 108 160 13183 15424 17939 19276 23714 26655
[0613] 109 285 608 1682 20223 21791 24615 29622 31983
[0614] 123 515 622 7037 13946 15292 15606 16262 23742
[0615] 264 565 923 6460 13622 13934 23181 25475 26134
[0616] 202 548 789 8003 10993 12478 16051 25114 27579
[0617] 121 450 575 5972 10062 18693 21852 23874 28031
[0618] 507 560 889 12064 13316 19629 21547 25461 28732
[0619] 664 786 1043 9137 9294 10163 23389 31436 34297
[0620] 45 830 907 10730 16541 21232 30354 30605 31847
[0621] 203 507 1060 6971 12216 13321 17861 22671 29825
[0622] 369 881 952 3035 12279 12775 17682 17805 34281
[0623] 683 709 1032 3787 17623 24138 26775 31432 33626
[0624] 524 792 1042 12249 14765 18601 25811 32422 33163
[0625] 137 639 688 7182 8169 10443 22530 24597 29039
[0626] 159 643 749 16386 17401 24135 28429 33468 33469
[0627] 107 481 555 7322 13234 19344 23498 26581 31378
[0628] 249 389 523 3421 10150 17616 19085 20545 32069
[0629] 395 738 1045 2415 3005 3820 19541 23543 31068
[0630] 27 293 703 1717 3460 8326 8501 10290 32625
[0631] 126 247 515 6031 9549 10643 22067 29490 34450
[0632] 331 471 1007 3020 3922 7580 23358 28620 30946
[0633] 222 542 1021 3291 3652 13130 16349 33009 34348
[0634] 532 719 1038 5891 7528 23252 25472 31395 31774
[0635] 145 398 774 7816 13887 14936 23708 31712 33160
[0636] 88 536 600 1239 1887 12195 13782 16726 27998
[0637] 151 269 585 1445 3178 3970 15568 20358 21051
[0638] 650 819 865 15567 18546 25571 32038 33350 33620
[0639] 93 469 800 6059 10405 12296 17515 21354 22231
[0640] 97 206 951 6161 16376 27022 29192 30190 30665
[0641] 412 549 986 5833 10583 10766 24946 28878 31937
[0642] 72 604 659 5267 12227 21714 32120 33472 33974
[0643] 25 902 912 1137 2975 9642 11598 25919 28278
[0644] 420 976 1055 8473 11512 20198 21662 25443 30119
[0645] 1 24 932 6426 11899 13217 13935 16548 29737
[0646] 53 618 988 6280 7267 11676 13575 15532 25787
[0647] 111 739 809 8133 12717 12741 20253 20608 27850
[0648] 120 683 943 14496 15162 15440 18660 27543 32404
[0649] 600 754 1055 7873 9679 17351 27268 33508
[0650] 344 756 1054 7102 7193 22903 24720 27883
[0651] 582 1003 1046 11344 23756 27497 27977 32853
[0652] 28 429 509 11106 11767 12729 13100 31792
[0653] 131 555 907 5113 10259 10300 20580 23029
[0654] 406 915 977 12244 20259 26616 27899 32228
[0655] 46 195 224 1229 4116 10263 13608 17830
[0656] 19 819 953 7965 9998 13959 30580 30754
[0657] 164 1003 1032 12920 15975 16582 22624 27357
[0658] 8433 11894 13531 17675 25889 31384
[0659] 3166 3813 8596 10368 25104 29584
[0660] 2466 8241 12424 13376 24837 32711.
[0661] A fifth data processing device/method according to the
present technology is a data processing device/method including: an
encoding unit/step configured to perform LDPC encoding based on a
parity check matrix of an LDPC code in which a code length N is
64800 bits and an encoding rate r is 8/15; a group-wise
interleaving unit/step configured to perform group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits;
and a mapping unit/step configured to map the LDPC code to any of
4096 signal points decided in a modulation scheme in units of 12
bits. In the group-wise interleave, when an (i+1)-th bit group from
a head of the LDPC code is indicated by a bit group i, a sequence
of bit groups 0 to 179 of the LDPC code of 64800 bits is
interleaved into a sequence of bit groups
[0662] 75, 83, 11, 24, 86, 104, 156, 76, 37, 173, 127, 61, 43, 139,
106, 69, 49, 2, 128, 140, 68, 14, 100, 8, 36, 73, 148, 65, 16, 47,
177, 6, 132, 45, 5, 30, 13, 22, 29, 27, 101, 150, 23, 90, 41, 93,
89, 92, 135, 4, 71, 87, 44, 124, 26, 64, 1, 129, 157, 130, 107, 18,
91, 118, 3, 82, 144, 113, 121, 54, 84, 97, 122, 120, 7, 154, 56,
134, 57, 161, 33, 116, 28, 96, 72, 172, 12, 115, 38, 164, 32, 167,
145, 17, 88, 39, 151, 80, 0, 136, 169, 142, 74, 147, 126, 166, 163,
40, 110, 171, 50, 160, 131, 70, 175, 103, 125, 77, 162, 31, 85, 66,
67, 52, 108, 159, 133, 42, 153, 21, 51, 119, 123, 98, 35, 48, 111,
149, 25, 58, 60, 158, 102, 59, 117, 20, 141, 143, 46, 53, 155, 15,
165, 152, 112, 176, 105, 178, 99, 174, 168, 114, 179, 78, 10, 19,
62, 63, 170, 138, 34, 109, 9, 146, 95, 94, 55, 137, 81, and 79.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0663] 2768 3039 4059 5856 6245 7013 8157 9341 9802 10470 11521
12083 16610 18361 20321 24601 27420 28206 29788
[0664] 2739 8244 8891 9157 12624 12973 15534 16622 16919 18402
18780 19854 20220 20543 22306 25540 27478 27678 28053
[0665] 1727 2268 6246 7815 9010 9556 10134 10472 11389 14599 15719
16204 17342 17666 18850 22058 25579 25860 29207
[0666] 28 1346 3721 5565 7019 9240 12355 13109 14800 16040 16839
17369 17631 19357 19473 19891 20381 23911 29683
[0667] 869 2450 4386 5316 6160 7107 10362 11132 11271 13149 16397
16532 17113 19894 22043 22784 27383 28615 28804
[0668] 508 4292 5831 8559 10044 10412 11283 14810 15888 17243 17538
19903 20528 22090 22652 27235 27384 28208 28485
[0669] 389 2248 5840 6043 7000 9054 11075 11760 12217 12565 13587
15403 19422 19528 21493 25142 27777 28566 28702
[0670] 1015 2002 5764 6777 9346 9629 11039 11153 12690 13068 13990
16841 17702 20021 24106 26300 29332 30081 30196
[0671] 1480 3084 3467 4401 4798 5187 7851 11368 12323 14325 14546
16360 17158 18010 21333 25612 26556 26906 27005
[0672] 6925 8876 12392 14529 15253 15437 19226 19950 20321 23021
23651 24393 24653 26668 27205 28269 28529 29041 29292
[0673] 2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881
17410 18971 19609 19717 22150 24941 27908 29018
[0674] 888 1581 2311 5511 7218 9107 10454 12252 13662 15714 15894
17025 18671 24304 25316 25556 28489 28977 29212
[0675] 1047 1494 1718 4645 5030 6811 7868 8146 10611 15767 17682
18391 22614 23021 23763 25478 26491 29088 29757
[0676] 59 1781 1900 3814 4121 8044 8906 9175 11156 14841 15789
16033 16755 17292 18550 19310 22505 29567 29850
[0677] 1952 3057 4399 9476 10171 10769 11335 11569 15002 19501
20621 22642 23452 24360 25109 25290 25828 28505 29122
[0678] 2895 3070 3437 4764 4905 6670 9244 11845 13352 13573 13975
14600 15871 17996 19672 20079 20579 25327 27958
[0679] 612 1528 2004 4244 4599 4926 5843 7684 10122 10443 12267
14368 18413 19058 22985 24257 26202 26596 27899
[0680] 1361 2195 4146 6708 7158 7538 9138 9998 14862 15359 16076
18925 21401 21573 22503 24146 24247 27778 29312
[0681] 5229 6235 7134 7655 9139 13527 15408 16058 16705 18320 19909
20901 22238 22437 23654 25131 27550 28247 29903
[0682] 697 2035 4887 5275 6909 9166 11805 15338 16381 18403 20425
20688 21547 24590 25171 26726 28848 29224 29412
[0683] 5379 17329 22659 23062
[0684] 11814 14759 22329 22936
[0685] 2423 2811 10296 12727
[0686] 8460 15260 16769 17290
[0687] 14191 14608 29536 30187
[0688] 7103 10069 20111 22850
[0689] 4285 15413 26448 29069
[0690] 548 2137 9189 10928
[0691] 4581 7077 23382 23949
[0692] 3942 17248 19486 27922
[0693] 8668 10230 16922 26678
[0694] 6158 9980 13788 28198
[0695] 12422 16076 24206 29887
[0696] 8778 10649 18747 22111
[0697] 21029 22677 27150 28980
[0698] 7918 15423 27672 27803
[0699] 5927 18086 23525
[0700] 3397 15058 30224
[0701] 24016 25880 26268
[0702] 1096 4775 7912
[0703] 3259 17301 20802
[0704] 129 8396 15132
[0705] 17825 28119 28676
[0706] 2343 8382 28840
[0707] 3907 18374 20939
[0708] 1132 1290 8786
[0709] 1481 4710 28846
[0710] 2185 3705 26834
[0711] 5496 15681 21854
[0712] 12697 13407 22178
[0713] 12788 21227 22894
[0714] 629 2854 6232
[0715] 2289 18227 27458
[0716] 7593 21935 23001
[0717] 3836 7081 12282
[0718] 7925 18440 23135
[0719] 497 6342 9717
[0720] 11199 22046 30067
[0721] 12572 28045 28990
[0722] 1240 2023 10933
[0723] 19566 20629 25186
[0724] 6442 13303 28813
[0725] 4765 10572 16180
[0726] 552 19301 24286
[0727] 6782 18480 21383
[0728] 11267 12288 15758
[0729] 771 5652 15531
[0730] 16131 20047 25649
[0731] 13227 23035 24450
[0732] 4839 13467 27488
[0733] 2852 4677 22993
[0734] 2504 28116 29524
[0735] 12518 17374 24267
[0736] 1222 11859 27922
[0737] 9660 17286 18261
[0738] 232 11296 29978
[0739] 9750 11165 16295
[0740] 4894 9505 23622
[0741] 10861 11980 14110
[0742] 2128 15883 22836
[0743] 6274 17243 21989
[0744] 10866 13202 22517
[0745] 11159 16111 21608
[0746] 3719 18787 22100
[0747] 1756 2020 23901
[0748] 20913 29473 30103
[0749] 2729 15091 26976
[0750] 4410 8217 12963
[0751] 5395 24564 28235
[0752] 3859 17909 23051
[0753] 5733 26005 29797
[0754] 1935 3492 29773
[0755] 11903 21380 29914
[0756] 6091 10469 29997
[0757] 2895 8930 15594
[0758] 1827 10028 20070
[0759] In the fifth data processing device/method according to the
present technology, LDPC encoding is performed based on a parity
check matrix of an LDPC code in which a code length N is 64800 bits
and an encoding rate r is 8/15. Group-wise interleave of
interleaving the LDPC code in units of bit groups of 360 bits is
performed. The LDPC code is mapped to any of 4096 signal points
decided in a modulation scheme in units of 12 bits. In the
group-wise interleave, when an (i+1)-th bit group from a head of
the LDPC code is indicated by a bit group i, a sequence of bit
groups 0 to 179 of the LDPC code of 64800 bits is interleaved into
a sequence of bit groups
[0760] 75, 83, 11, 24, 86, 104, 156, 76, 37, 173, 127, 61, 43, 139,
106, 69, 49, 2, 128, 140, 68, 14, 100, 8, 36, 73, 148, 65, 16, 47,
177, 6, 132, 45, 5, 30, 13, 22, 29, 27, 101, 150, 23, 90, 41, 93,
89, 92, 135, 4, 71, 87, 44, 124, 26, 64, 1, 129, 157, 130, 107, 18,
91, 118, 3, 82, 144, 113, 121, 54, 84, 97, 122, 120, 7, 154, 56,
134, 57, 161, 33, 116, 28, 96, 72, 172, 12, 115, 38, 164, 32, 167,
145, 17, 88, 39, 151, 80, 0, 136, 169, 142, 74, 147, 126, 166, 163,
40, 110, 171, 50, 160, 131, 70, 175, 103, 125, 77, 162, 31, 85, 66,
67, 52, 108, 159, 133, 42, 153, 21, 51, 119, 123, 98, 35, 48, 111,
149, 25, 58, 60, 158, 102, 59, 117, 20, 141, 143, 46, 53, 155, 15,
165, 152, 112, 176, 105, 178, 99, 174, 168, 114, 179, 78, 10, 19,
62, 63, 170, 138, 34, 109, 9, 146, 95, 94, 55, 137, 81, and 79.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0761] 2768 3039 4059 5856 6245 7013 8157 9341 9802 10470 11521
12083 16610 18361 20321 24601 27420 28206 29788
[0762] 2739 8244 8891 9157 12624 12973 15534 16622 16919 18402
18780 19854 20220 20543 22306 25540 27478 27678 28053
[0763] 1727 2268 6246 7815 9010 9556 10134 10472 11389 14599 15719
16204 17342 17666 18850 22058 25579 25860 29207
[0764] 28 1346 3721 5565 7019 9240 12355 13109 14800 16040 16839
17369 17631 19357 19473 19891 20381 23911 29683
[0765] 869 2450 4386 5316 6160 7107 10362 11132 11271 13149 16397
16532 17113 19894 22043 22784 27383 28615 28804
[0766] 508 4292 5831 8559 10044 10412 11283 14810 15888 17243 17538
19903 20528 22090 22652 27235 27384 28208 28485
[0767] 389 2248 5840 6043 7000 9054 11075 11760 12217 12565 13587
15403 19422 19528 21493 25142 27777 28566 28702
[0768] 1015 2002 5764 6777 9346 9629 11039 11153 12690 13068 13990
16841 17702 20021 24106 26300 29332 30081 30196
[0769] 1480 3084 3467 4401 4798 5187 7851 11368 12323 14325 14546
16360 17158 18010 21333 25612 26556 26906 27005
[0770] 6925 8876 12392 14529 15253 15437 19226 19950 20321 23021
23651 24393 24653 26668 27205 28269 28529 29041 29292
[0771] 2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881
17410 18971 19609 19717 22150 24941 27908 29018
[0772] 888 1581 2311 5511 7218 9107 10454 12252 13662 15714 15894
17025 18671 24304 25316 25556 28489 28977 29212
[0773] 1047 1494 1718 4645 5030 6811 7868 8146 10611 15767 17682
18391 22614 23021 23763 25478 26491 29088 29757
[0774] 59 1781 1900 3814 4121 8044 8906 9175 11156 14841 15789
16033 16755 17292 18550 19310 22505 29567 29850
[0775] 1952 3057 4399 9476 10171 10769 11335 11569 15002 19501
20621 22642 23452 24360 25109 25290 25828 28505 29122
[0776] 2895 3070 3437 4764 4905 6670 9244 11845 13352 13573 13975
14600 15871 17996 19672 20079 20579 25327 27958
[0777] 612 1528 2004 4244 4599 4926 5843 7684 10122 10443 12267
14368 18413 19058 22985 24257 26202 26596 27899
[0778] 1361 2195 4146 6708 7158 7538 9138 9998 14862 15359 16076
18925 21401 21573 22503 24146 24247 27778 29312
[0779] 5229 6235 7134 7655 9139 13527 15408 16058 16705 18320 19909
20901 22238 22437 23654 25131 27550 28247 29903
[0780] 697 2035 4887 5275 6909 9166 11805 15338 16381 18403 20425
20688 21547 24590 25171 26726 28848 29224 29412
[0781] 5379 17329 22659 23062
[0782] 11814 14759 22329 22936
[0783] 2423 2811 10296 12727
[0784] 8460 15260 16769 17290
[0785] 14191 14608 29536 30187
[0786] 7103 10069 20111 22850
[0787] 4285 15413 26448 29069
[0788] 548 2137 9189 10928
[0789] 4581 7077 23382 23949
[0790] 3942 17248 19486 27922
[0791] 8668 10230 16922 26678
[0792] 6158 9980 13788 28198
[0793] 12422 16076 24206 29887
[0794] 8778 10649 18747 22111
[0795] 21029 22677 27150 28980
[0796] 7918 15423 27672 27803
[0797] 5927 18086 23525
[0798] 3397 15058 30224
[0799] 24016 25880 26268
[0800] 1096 4775 7912
[0801] 3259 17301 20802
[0802] 129 8396 15132
[0803] 17825 28119 28676
[0804] 2343 8382 28840
[0805] 3907 18374 20939
[0806] 1132 1290 8786
[0807] 1481 4710 28846
[0808] 2185 3705 26834
[0809] 5496 15681 21854
[0810] 12697 13407 22178
[0811] 12788 21227 22894
[0812] 629 2854 6232
[0813] 2289 18227 27458
[0814] 7593 21935 23001
[0815] 3836 7081 12282
[0816] 7925 18440 23135
[0817] 497 6342 9717
[0818] 11199 22046 30067
[0819] 12572 28045 28990
[0820] 1240 2023 10933
[0821] 19566 20629 25186
[0822] 6442 13303 28813
[0823] 4765 10572 16180
[0824] 552 19301 24286
[0825] 6782 18480 21383
[0826] 11267 12288 15758
[0827] 771 5652 15531
[0828] 16131 20047 25649
[0829] 13227 23035 24450
[0830] 4839 13467 27488
[0831] 2852 4677 22993
[0832] 2504 28116 29524
[0833] 12518 17374 24267
[0834] 1222 11859 27922
[0835] 9660 17286 18261
[0836] 232 11296 29978
[0837] 9750 11165 16295
[0838] 4894 9505 23622
[0839] 10861 11980 14110
[0840] 2128 15883 22836
[0841] 6274 17243 21989
[0842] 10866 13202 22517
[0843] 11159 16111 21608
[0844] 3719 18787 22100
[0845] 1756 2020 23901
[0846] 20913 29473 30103
[0847] 2729 15091 26976
[0848] 4410 8217 12963
[0849] 5395 24564 28235
[0850] 3859 17909 23051
[0851] 5733 26005 29797
[0852] 1935 3492 29773
[0853] 11903 21380 29914
[0854] 6091 10469 29997
[0855] 2895 8930 15594
[0856] 1827 10028 20070
[0857] A sixth data processing device/method according to the
present technology is a data processing device/method including: a
group-wise deinterleaving unit/step configured to restore a
sequence of an LDPC code that has undergone group-wise interleave
and has been obtained from data transmitted from a transmitting
device to an original sequence, the transmitting device including
an encoding unit configured to perform LDPC encoding based on a
parity check matrix of the LDPC code in which a code length N is
64800 bits and an encoding rate r is 8/15, a group-wise
interleaving unit configured to perform the group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits,
and a mapping unit configured to map the LDPC code to any of 4096
signal points decided in a modulation scheme in units of 12 bits.
In the group-wise interleave, when an (i+1)-th bit group from a
head of the LDPC code is indicated by a bit group i, a sequence of
bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved
into a sequence of bit groups
[0858] 75, 83, 11, 24, 86, 104, 156, 76, 37, 173, 127, 61, 43, 139,
106, 69, 49, 2, 128, 140, 68, 14, 100, 8, 36, 73, 148, 65, 16, 47,
177, 6, 132, 45, 5, 30, 13, 22, 29, 27, 101, 150, 23, 90, 41, 93,
89, 92, 135, 4, 71, 87, 44, 124, 26, 64, 1, 129, 157, 130, 107, 18,
91, 118, 3, 82, 144, 113, 121, 54, 84, 97, 122, 120, 7, 154, 56,
134, 57, 161, 33, 116, 28, 96, 72, 172, 12, 115, 38, 164, 32, 167,
145, 17, 88, 39, 151, 80, 0, 136, 169, 142, 74, 147, 126, 166, 163,
40, 110, 171, 50, 160, 131, 70, 175, 103, 125, 77, 162, 31, 85, 66,
67, 52, 108, 159, 133, 42, 153, 21, 51, 119, 123, 98, 35, 48, 111,
149, 25, 58, 60, 158, 102, 59, 117, 20, 141, 143, 46, 53, 155, 15,
165, 152, 112, 176, 105, 178, 99, 174, 168, 114, 179, 78, 10, 19,
62, 63, 170, 138, 34, 109, 9, 146, 95, 94, 55, 137, 81, and 79,
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0859] 2768 3039 4059 5856 6245 7013 8157 9341 9802 10470 11521
12083 16610 18361 20321 24601 27420 28206 29788
[0860] 2739 8244 8891 9157 12624 12973 15534 16622 16919 18402
18780 19854 20220 20543 22306 25540 27478 27678 28053
[0861] 1727 2268 6246 7815 9010 9556 10134 10472 11389 14599 15719
16204 17342 17666 18850 22058 25579 25860 29207
[0862] 28 1346 3721 5565 7019 9240 12355 13109 14800 16040 16839
17369 17631 19357 19473 19891 20381 23911 29683
[0863] 869 2450 4386 5316 6160 7107 10362 11132 11271 13149 16397
16532 17113 19894 22043 22784 27383 28615 28804
[0864] 508 4292 5831 8559 10044 10412 11283 14810 15888 17243 17538
19903 20528 22090 22652 27235 27384 28208 28485
[0865] 389 2248 5840 6043 7000 9054 11075 11760 12217 12565 13587
15403 19422 19528 21493 25142 27777 28566 28702
[0866] 1015 2002 5764 6777 9346 9629 11039 11153 12690 13068 13990
16841 17702 20021 24106 26300 29332 30081 30196
[0867] 1480 3084 3467 4401 4798 5187 7851 11368 12323 14325 14546
16360 17158 18010 21333 25612 26556 26906 27005
[0868] 6925 8876 12392 14529 15253 15437 19226 19950 20321 23021
23651 24393 24653 26668 27205 28269 28529 29041 29292
[0869] 2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881
17410 18971 19609 19717 22150 24941 27908 29018
[0870] 888 1581 2311 5511 7218 9107 10454 12252 13662 15714 15894
17025 18671 24304 25316 25556 28489 28977 29212
[0871] 1047 1494 1718 4645 5030 6811 7868 8146 10611 15767 17682
18391 22614 23021 23763 25478 26491 29088 29757
[0872] 59 1781 1900 3814 4121 8044 8906 9175 11156 14841 15789
16033 16755 17292 18550 19310 22505 29567 29850
[0873] 1952 3057 4399 9476 10171 10769 11335 11569 15002 19501
20621 22642 23452 24360 25109 25290 25828 28505 29122
[0874] 2895 3070 3437 4764 4905 6670 9244 11845 13352 13573 13975
14600 15871 17996 19672 20079 20579 25327 27958
[0875] 612 1528 2004 4244 4599 4926 5843 7684 10122 10443 12267
14368 18413 19058 22985 24257 26202 26596 27899
[0876] 1361 2195 4146 6708 7158 7538 9138 9998 14862 15359 16076
18925 21401 21573 22503 24146 24247 27778 29312
[0877] 5229 6235 7134 7655 9139 13527 15408 16058 16705 18320 19909
20901 22238 22437 23654 25131 27550 28247 29903
[0878] 697 2035 4887 5275 6909 9166 11805 15338 16381 18403 20425
20688 21547 24590 25171 26726 28848 29224 29412
[0879] 5379 17329 22659 23062
[0880] 11814 14759 22329 22936
[0881] 2423 2811 10296 12727
[0882] 8460 15260 16769 17290
[0883] 14191 14608 29536 30187
[0884] 7103 10069 20111 22850
[0885] 4285 15413 26448 29069
[0886] 548 2137 9189 10928
[0887] 4581 7077 23382 23949
[0888] 3942 17248 19486 27922
[0889] 8668 10230 16922 26678
[0890] 6158 9980 13788 28198
[0891] 12422 16076 24206 29887
[0892] 8778 10649 18747 22111
[0893] 21029 22677 27150 28980
[0894] 7918 15423 27672 27803
[0895] 5927 18086 23525
[0896] 3397 15058 30224
[0897] 24016 25880 26268
[0898] 1096 4775 7912
[0899] 3259 17301 20802
[0900] 129 8396 15132
[0901] 17825 28119 28676
[0902] 2343 8382 28840
[0903] 3907 18374 20939
[0904] 1132 1290 8786
[0905] 1481 4710 28846
[0906] 2185 3705 26834
[0907] 5496 15681 21854
[0908] 12697 13407 22178
[0909] 12788 21227 22894
[0910] 629 2854 6232
[0911] 2289 18227 27458
[0912] 7593 21935 23001
[0913] 3836 7081 12282
[0914] 7925 18440 23135
[0915] 497 6342 9717
[0916] 11199 22046 30067
[0917] 12572 28045 28990
[0918] 1240 2023 10933
[0919] 19566 20629 25186
[0920] 6442 13303 28813
[0921] 4765 10572 16180
[0922] 552 19301 24286
[0923] 6782 18480 213 83
[0924] 11267 12288 15758
[0925] 771 5652 15531
[0926] 16131 20047 25649
[0927] 13227 23035 24450
[0928] 4839 13467 27488
[0929] 2852 4677 22993
[0930] 2504 28116 29524
[0931] 12518 17374 24267
[0932] 1222 11859 27922
[0933] 9660 17286 18261
[0934] 232 11296 29978
[0935] 9750 11165 16295
[0936] 4894 9505 23622
[0937] 10861 11980 14110
[0938] 2128 15883 22836
[0939] 6274 17243 21989
[0940] 10866 13202 22517
[0941] 11159 16111 21608
[0942] 3719 18787 22100
[0943] 1756 2020 23901
[0944] 20913 29473 30103
[0945] 2729 15091 26976
[0946] 4410 8217 12963
[0947] 5395 24564 28235
[0948] 3859 17909 23051
[0949] 5733 26005 29797
[0950] 1935 3492 29773
[0951] 11903 21380 29914
[0952] 6091 10469 29997
[0953] 2895 8930 15594
[0954] 1827 10028 20070
[0955] In the sixth data processing device/method according to the
present technology, a sequence of an LDPC code that has undergone
group-wise interleave and has been obtained from data transmitted
from a transmitting device is restored to an original sequence, the
transmitting device including an encoding unit configured to
perform LDPC encoding based on a parity check matrix of the LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 8/15, a group-wise interleaving unit configured to perform the
group-wise interleave of interleaving the LDPC code in units of bit
groups of 360 bits, and a mapping unit configured to map the LDPC
code to any of 4096 signal points decided in a modulation scheme in
units of 12 bits. In the group-wise interleave, when an (i+1)-th
bit group from a head of the LDPC code is indicated by a bit group
i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits
is interleaved into a sequence of bit groups
[0956] 75, 83, 11, 24, 86, 104, 156, 76, 37, 173, 127, 61, 43, 139,
106, 69, 49, 2, 128, 140, 68, 14, 100, 8, 36, 73, 148, 65, 16, 47,
177, 6, 132, 45, 5, 30, 13, 22, 29, 27, 101, 150, 23, 90, 41, 93,
89, 92, 135, 4, 71, 87, 44, 124, 26, 64, 1, 129, 157, 130, 107, 18,
91, 118, 3, 82, 144, 113, 121, 54, 84, 97, 122, 120, 7, 154, 56,
134, 57, 161, 33, 116, 28, 96, 72, 172, 12, 115, 38, 164, 32, 167,
145, 17, 88, 39, 151, 80, 0, 136, 169, 142, 74, 147, 126, 166, 163,
40, 110, 171, 50, 160, 131, 70, 175, 103, 125, 77, 162, 31, 85, 66,
67, 52, 108, 159, 133, 42, 153, 21, 51, 119, 123, 98, 35, 48, 111,
149, 25, 58, 60, 158, 102, 59, 117, 20, 141, 143, 46, 53, 155, 15,
165, 152, 112, 176, 105, 178, 99, 174, 168, 114, 179, 78, 10, 19,
62, 63, 170, 138, 34, 109, 9, 146, 95, 94, 55, 137, 81, and 79,
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[0957] 2768 3039 4059 5856 6245 7013 8157 9341 9802 10470 11521
12083 16610 18361 20321 24601 27420 28206 29788
[0958] 2739 8244 8891 9157 12624 12973 15534 16622 16919 18402
18780 19854 20220 20543 22306 25540 27478 27678 28053
[0959] 1727 2268 6246 7815 9010 9556 10134 10472 11389 14599 15719
16204 17342 17666 18850 22058 25579 25860 29207
[0960] 28 1346 3721 5565 7019 9240 12355 13109 14800 16040 16839
17369 17631 19357 19473 19891 20381 23911 29683
[0961] 869 2450 4386 5316 6160 7107 10362 11132 11271 13149 16397
16532 17113 19894 22043 22784 27383 28615 28804
[0962] 508 4292 5831 8559 10044 10412 11283 14810 15888 17243 17538
19903 20528 22090 22652 27235 27384 28208 28485
[0963] 389 2248 5840 6043 7000 9054 11075 11760 12217 12565 13587
15403 19422 19528 21493 25142 27777 28566 28702
[0964] 1015 2002 5764 6777 9346 9629 11039 11153 12690 13068 13990
16841 17702 20021 24106 26300 29332 30081 30196
[0965] 1480 3084 3467 4401 4798 5187 7851 11368 12323 14325 14546
16360 17158 18010 21333 25612 26556 26906 27005
[0966] 6925 8876 12392 14529 15253 15437 19226 19950 20321 23021
23651 24393 24653 26668 27205 28269 28529 29041 29292
[0967] 2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881
17410 18971 19609 19717 22150 24941 27908 29018
[0968] 888 1581 2311 5511 7218 9107 10454 12252 13662 15714 15894
17025 18671 24304 25316 25556 28489 28977 29212
[0969] 1047 1494 1718 4645 5030 6811 7868 8146 10611 15767 17682
18391 22614 23021 23763 25478 26491 29088 29757
[0970] 59 1781 1900 3814 4121 8044 8906 9175 11156 14841 15789
16033 16755 17292 18550 19310 22505 29567 29850
[0971] 1952 3057 4399 9476 10171 10769 11335 11569 15002 19501
20621 22642 23452 24360 25109 25290 25828 28505 29122
[0972] 2895 3070 3437 4764 4905 6670 9244 11845 13352 13573 13975
14600 15871 17996 19672 20079 20579 25327 27958
[0973] 612 1528 2004 4244 4599 4926 5843 7684 10122 10443 12267
14368 18413 19058 22985 24257 26202 26596 27899
[0974] 1361 2195 4146 6708 7158 7538 9138 9998 14862 15359 16076
18925 21401 21573 22503 24146 24247 27778 29312
[0975] 5229 6235 7134 7655 9139 13527 15408 16058 16705 18320 19909
20901 22238 22437 23654 25131 27550 28247 29903
[0976] 697 2035 4887 5275 6909 9166 11805 15338 16381 18403 20425
20688 21547 24590 25171 26726 28848 29224 29412
[0977] 5379 17329 22659 23062
[0978] 11814 14759 22329 22936
[0979] 2423 2811 10296 12727
[0980] 8460 15260 16769 17290
[0981] 14191 14608 29536 30187
[0982] 7103 10069 20111 22850
[0983] 4285 15413 26448 29069
[0984] 548 2137 9189 10928
[0985] 4581 7077 23382 23949
[0986] 3942 17248 19486 27922
[0987] 8668 10230 16922 26678
[0988] 6158 9980 13788 28198
[0989] 12422 16076 24206 29887
[0990] 8778 10649 18747 22111
[0991] 21029 22677 27150 28980
[0992] 7918 15423 27672 27803
[0993] 5927 18086 23525
[0994] 3397 15058 30224
[0995] 24016 25880 26268
[0996] 1096 4775 7912
[0997] 3259 17301 20802
[0998] 129 8396 15132
[0999] 17825 28119 28676
[1000] 2343 8382 28840
[1001] 3907 18374 20939
[1002] 1132 1290 8786
[1003] 1481 4710 28846
[1004] 2185 3705 26834
[1005] 5496 15681 21854
[1006] 12697 13407 22178
[1007] 12788 21227 22894
[1008] 629 2854 6232
[1009] 2289 18227 27458
[1010] 7593 21935 23001
[1011] 3836 7081 12282
[1012] 7925 18440 23135
[1013] 497 6342 9717
[1014] 11199 22046 30067
[1015] 12572 28045 28990
[1016] 1240 2023 10933
[1017] 19566 20629 25186
[1018] 6442 13303 28813
[1019] 4765 10572 16180
[1020] 552 19301 24286
[1021] 6782 18480 21383
[1022] 11267 12288 15758
[1023] 771 5652 15531
[1024] 16131 20047 25649
[1025] 13227 23035 24450
[1026] 4839 13467 27488
[1027] 2852 4677 22993
[1028] 2504 28116 29524
[1029] 12518 17374 24267
[1030] 1222 11859 27922
[1031] 9660 17286 18261
[1032] 232 11296 29978
[1033] 9750 11165 16295
[1034] 4894 9505 23622
[1035] 10861 11980 14110
[1036] 2128 15883 22836
[1037] 6274 17243 21989
[1038] 10866 13202 22517
[1039] 11159 16111 21608
[1040] 3719 18787 22100
[1041] 1756 2020 23901
[1042] 20913 29473 30103
[1043] 2729 15091 26976
[1044] 4410 8217 12963
[1045] 5395 24564 28235
[1046] 3859 17909 23051
[1047] 5733 26005 29797
[1048] 1935 3492 29773
[1049] 11903 21380 29914
[1050] 6091 10469 29997
[1051] 2895 8930 15594
[1052] 1827 10028 20070
[1053] A seventh data processing device/method according to the
present technology is a data processing device/method including: an
encoding unit/step configured to perform LDPC encoding based on a
parity check matrix of an LDPC code in which a code length N is
64800 bits and an encoding rate r is 9/15; a group-wise
interleaving unit/step configured to perform group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits;
and a mapping unit/step configured to map the LDPC code to any of
4096 signal points decided in a modulation scheme in units of 12
bits. In the group-wise interleave, when an (i+1)-th bit group from
a head of the LDPC code is indicated by a bit group i, a sequence
of bit groups 0 to 179 of the LDPC code of 64800 bits is
interleaved into a sequence of bit groups
[1054] 98, 159, 59, 125, 163, 89, 26, 4, 102, 70, 92, 36, 37, 142,
176, 95, 71, 19, 87, 45, 81, 47, 65, 170, 103, 48, 67, 61, 64, 35,
76, 80, 140, 77, 10, 167, 178, 155, 120, 156, 151, 12, 58, 5, 83,
137, 41, 109, 2, 66, 133, 62, 135, 28, 93, 128, 86, 57, 153, 161,
110, 52, 147, 141, 31, 79, 32, 88, 160, 84, 150, 6, 100, 73, 126,
164, 17, 42, 101, 7, 55, 105, 91, 22, 130, 154, 1, 82, 14, 0, 9,
21, 50, 165, 72, 138, 175, 106, 108, 3, 169, 30, 157, 54, 18, 20,
44, 34, 134, 107, 56, 53, 15, 162, 38, 166, 24, 33, 60, 85, 145,
115, 43, 39, 40, 124, 149, 144, 132, 96, 11, 146, 90, 129, 119,
111, 171, 8, 152, 121, 173, 131, 49, 27, 118, 16, 148, 68, 177, 94,
179, 13, 114, 75, 51, 117, 25, 46, 136, 143, 139, 113, 127, 174,
74, 29, 122, 158, 69, 97, 78, 63, 99, 112, 104, 116, 172, 168, 23,
and 123.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[1055] 113 1557 3316 5680 6241 10407 13404 13947 14040 14353 15522
15698 16079 17363 19374 19543 20530 22833 24339
[1056] 271 1361 6236 7006 7307 7333 12768 15441 15568 17923 18341
20321 21502 22023 23938 25351 25590 25876 25910
[1057] 73 605 872 4008 6279 7653 10346 10799 12482 12935 13604
15909 16526 19782 20506 22804 23629 24859 25600
[1058] 1445 1690 4304 4851 8919 9176 9252 13783 16076 16675 17274
18806 18882 20819 21958 22451 23869 23999 24177
[1059] 1290 2337 5661 6371 8996 10102 10941 11360 12242 14918 16808
20571 23374 24046 25045 25060 25662 25783 25913
[1060] 28 42 1926 3421 3503 8558 9453 10168 15820 17473 19571 19685
22790 23336 23367 23890 24061 25657 25680
[1061] 0 1709 4041 4932 5968 7123 8430 9564 10596 11026 14761 19484
20762 20858 23803 24016 24795 25853 25863
[1062] 29 1625 6500 6609 16831 18517 18568 18738 19387 20159 20544
21603 21941 24137 24269 24416 24803 25154 25395
[1063] 55 66 871 3700 11426 13221 15001 16367 17601 18380 22796
23488 23938 25476 25635 25678 25807 25857 25872
[1064] 1 19 5958 8548 8860 11489 16845 18450 18469 19496 20190
23173 25262 25566 25668 25679 25858 25888 25915
[1065] 7520 7690 8855 9183 14654 16695 17121 17854 18083 18428
19633 20470 20736 21720 22335 23273 25083 25293 25403
[1066] 48 58 410 1299 3786 10668 18523 18963 20864 22106 22308
23033 23107 23128 23990 24286 24409 24595 25802
[1067] 12 51 3894 6539 8276 10885 11644 12777 13427 14039 15954
17078 19053 20537 22863 24521 25087 25463 25838
[1068] 3509 8748 9581 11509 15884 16230 17583 19264 20900 21001
21310 22547 22756 22959 24768 24814 25594 25626 25880
[1069] 21 29 69 1448 2386 4601 6626 6667 10242 13141 13852 14137
18640 19951 22449 23454 24431 25512 25814
[1070] 18 53 7890 9934 10063 16728 19040 19809 20825 21522 21800
23582 24556 25031 25547 25562 25733 25789 25906
[1071] 4096 4582 5766 5894 6517 10027 12182 13247 15207 17041 18958
20133 20503 22228 24332 24613 25689 25855 25883
[1072] 0 25 819 5539 7076 7536 7695 9532 13668 15051 17683 19665
20253 21996 24136 24890 25758 25784 25807
[1073] 34 40 44 4215 6076 7427 7965 8777 11017 15593 19542 22202
22973 23397 23423 24418 24873 25107 25644
[1074] 1595 6216 22850 25439
[1075] 1562 15172 19517 22362
[1076] 7508 12879 24324 24496
[1077] 6298 15819 16757 18721
[1078] 11173 15175 19966 21195
[1079] 59 13505 16941 23 793
[1080] 2267 4830 12023 20587
[1081] 8827 9278 13072 16664
[1082] 14419 17463 23398 25348
[1083] 6112 16534 20423 22698
[1084] 493 8914 21103 24799
[1085] 6896 12761 13206 25873
[1086] 2 1380 12322 21701
[1087] 11600 21306 25753 25790
[1088] 8421 13076 14271 15401
[1089] 9630 14112 19017 20955
[1090] 212 13932 21781 25824
[1091] 5961 9110 16654 19636
[1092] 58 5434 9936 12770
[1093] 6575 11433 19798
[1094] 2731 7338 20926
[1095] 14253 18463 25404
[1096] 21791 24805 25869
[1097] 2 11646 15850
[1098] 6075 8586 23819
[1099] 18435 22093 24852
[1100] 2103 2368 11704
[1101] 10925 17402 18232
[1102] 9062 25061 25674
[1103] 18497 20853 23404
[1104] 18606 19364 19551
[1105] 7 1022 25543
[1106] 6744 15481 25868
[1107] 9081 17305 25164
[1108] 8 23701 25883
[1109] 9680 19955 22848
[1110] 56 4564 19121
[1111] 5595 15086 25892
[1112] 3174 17127 23183
[1113] 19397 19817 20275
[1114] 12561 24571 25825
[1115] 7111 9889 25865
[1116] 19104 20189 21851
[1117] 549 9686 25548
[1118] 6586 20325 25906
[1119] 3224 20710 21637
[1120] 641 15215 25754
[1121] 13484 23729 25818
[1122] 2043 7493 24246
[1123] 16860 25230 25768
[1124] 22047 24200 24902
[1125] 9391 18040 19499
[1126] 7855 24336 25069
[1127] 23834 25570 25852
[1128] 1977 8800 25756
[1129] 6671 21772 25859
[1130] 3279 6710 24444
[1131] 24099 25117 25820
[1132] 5553 12306 25915
[1133] 48 11107 23907
[1134] 10832 11974 25773
[1135] 2223 17905 25484
[1136] 16782 17135 20446
[1137] 475 2861 3457
[1138] 16218 22449 24362
[1139] 11716 22200 25897
[1140] 8315 15009 22633
[1141] 13 20480 25852
[1142] 12352 18658 25687
[1143] 3681 14794 23703
[1144] 30 24531 25846
[1145] 4103 22077 24107
[1146] 23837 25622 25812
[1147] 3627 13387 25839
[1148] 908 5367 19388
[1149] 0 6894 25795
[1150] 20322 23546 25181
[1151] 8178 25260 25437
[1152] 2449 13244 22565
[1153] 31 18928 22741
[1154] 1312 5134 14838
[1155] 6085 13937 24220
[1156] 66 14633 25670
[1157] 47 22512 25472
[1158] 8867 24704 25279
[1159] 6742 21623 22745
[1160] 147 9948 24178
[1161] 8522 24261 24307
[1162] 19202 22406 24609.
[1163] In the seventh data processing device/method according to
the present technology, LDPC encoding is performed based on a
parity check matrix of an LDPC code in which a code length N is
64800 bits and an encoding rate r is 9/15. Group-wise interleave of
interleaving the LDPC code in units of bit groups of 360 bits is
performed. The LDPC code is mapped to any of 4096 signal points
decided in a modulation scheme in units of 12 bits. In the
group-wise interleave, when an (i+1)-th bit group from a head of
the LDPC code is indicated by a bit group i, a sequence of bit
groups 0 to 179 of the LDPC code of 64800 bits is interleaved into
a sequence of bit groups
[1164] 98, 159, 59, 125, 163, 89, 26, 4, 102, 70, 92, 36, 37, 142,
176, 95, 71, 19, 87, 45, 81, 47, 65, 170, 103, 48, 67, 61, 64, 35,
76, 80, 140, 77, 10, 167, 178, 155, 120, 156, 151, 12, 58, 5, 83,
137, 41, 109, 2, 66, 133, 62, 135, 28, 93, 128, 86, 57, 153, 161,
110, 52, 147, 141, 31, 79, 32, 88, 160, 84, 150, 6, 100, 73, 126,
164, 17, 42, 101, 7, 55, 105, 91, 22, 130, 154, 1, 82, 14, 0, 9,
21, 50, 165, 72, 138, 175, 106, 108, 3, 169, 30, 157, 54, 18, 20,
44, 34, 134, 107, 56, 53, 15, 162, 38, 166, 24, 33, 60, 85, 145,
115, 43, 39, 40, 124, 149, 144, 132, 96, 11, 146, 90, 129, 119,
111, 171, 8, 152, 121, 173, 131, 49, 27, 118, 16, 148, 68, 177, 94,
179, 13, 114, 75, 51, 117, 25, 46, 136, 143, 139, 113, 127, 174,
74, 29, 122, 158, 69, 97, 78, 63, 99, 112, 104, 116, 172, 168, 23,
and 123.
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[1165] 113 1557 3316 5680 6241 10407 13404 13947 14040 14353 15522
15698 16079 17363 19374 19543 20530 22833 24339
[1166] 271 1361 6236 7006 7307 7333 12768 15441 15568 17923 18341
20321 21502 22023 23938 25351 25590 25876 25910
[1167] 73 605 872 4008 6279 7653 10346 10799 12482 12935 13604
15909 16526 19782 20506 22804 23629 24859 25600
[1168] 1445 1690 4304 4851 8919 9176 9252 13783 16076 16675 17274
18806 18882 20819 21958 22451 23869 23999 24177
[1169] 1290 2337 5661 6371 8996 10102 10941 11360 12242 14918 16808
20571 23374 24046 25045 25060 25662 25783 25913
[1170] 28 42 1926 3421 3503 8558 9453 10168 15820 17473 19571 19685
22790 23336 23367 23890 24061 25657 25680
[1171] 0 1709 4041 4932 5968 7123 8430 9564 10596 11026 14761 19484
20762 20858 23803 24016 24795 25853 25863
[1172] 29 1625 6500 6609 16831 18517 18568 18738 19387 20159 20544
21603 21941 24137 24269 24416 24803 25154 25395
[1173] 55 66 871 3700 11426 13221 15001 16367 17601 18380 22796
23488 23938 25476 25635 25678 25807 25857 25872
[1174] 1 19 5958 8548 8860 11489 16845 18450 18469 19496 20190
23173 25262 25566 25668 25679 25858 25888 25915
[1175] 7520 7690 8855 9183 14654 16695 17121 17854 18083 18428
19633 20470 20736 21720 22335 23273 25083 25293 25403
[1176] 48 58 410 1299 3786 10668 18523 18963 20864 22106 22308
23033 23107 23128 23990 24286 24409 24595 25802
[1177] 12 51 3894 6539 8276 10885 11644 12777 13427 14039 15954
17078 19053 20537 22863 24521 25087 25463 25838
[1178] 3509 8748 9581 11509 15884 16230 17583 19264 20900 21001
21310 22547 22756 22959 24768 24814 25594 25626 25880
[1179] 21 29 69 1448 2386 4601 6626 6667 10242 13141 13852 14137
18640 19951 22449 23454 24431 25512 25814
[1180] 18 53 7890 9934 10063 16728 19040 19809 20825 21522 21800
23582 24556 25031 25547 25562 25733 25789 25906
[1181] 4096 4582 5766 5894 6517 10027 12182 13247 15207 17041 18958
20133 20503 22228 24332 24613 25689 25855 25883
[1182] 0 25 819 5539 7076 7536 7695 9532 13668 15051 17683 19665
20253 21996 24136 24890 25758 25784 25807
[1183] 34 40 44 4215 6076 7427 7965 8777 11017 15593 19542 22202
22973 23397 23423 24418 24873 25107 25644
[1184] 1595 6216 22850 25439
[1185] 1562 15172 19517 22362
[1186] 7508 12879 24324 24496
[1187] 6298 15819 16757 18721
[1188] 11173 15175 19966 21195
[1189] 59 13505 16941 23793
[1190] 2267 4830 12023 20587
[1191] 8827 9278 13072 16664
[1192] 14419 17463 23398 25348
[1193] 6112 16534 20423 22698
[1194] 493 8914 21103 24799
[1195] 6896 12761 13206 25873
[1196] 2 1380 12322 21701
[1197] 11600 21306 25753 25790
[1198] 8421 13076 14271 15401
[1199] 9630 14112 19017 20955
[1200] 212 13932 21781 25824
[1201] 5961 9110 16654 19636
[1202] 58 5434 9936 12770
[1203] 6575 11433 19798
[1204] 2731 7338 20926
[1205] 14253 18463 25404
[1206] 21791 24805 25869
[1207] 2 11646 15850
[1208] 6075 8586 23819
[1209] 18435 22093 24852
[1210] 2103 2368 11704
[1211] 10925 17402 18232
[1212] 9062 25061 25674
[1213] 18497 20853 23404
[1214] 18606 19364 19551
[1215] 7 1022 25543
[1216] 6744 15481 25868
[1217] 9081 17305 25164
[1218] 8 23701 25883
[1219] 9680 19955 22848
[1220] 56 4564 19121
[1221] 5595 15086 25892
[1222] 3174 17127 23183
[1223] 19397 19817 20275
[1224] 12561 24571 25825
[1225] 7111 9889 25865
[1226] 19104 20189 21851
[1227] 549 9686 25548
[1228] 6586 20325 25906
[1229] 3224 20710 21637
[1230] 641 15215 25754
[1231] 13484 23729 25818
[1232] 2043 7493 24246
[1233] 16860 25230 25768
[1234] 22047 24200 24902
[1235] 9391 18040 19499
[1236] 7855 24336 25069
[1237] 23834 25570 25852
[1238] 1977 8800 25756
[1239] 6671 21772 25859
[1240] 3279 6710 24444
[1241] 24099 25117 25820
[1242] 5553 12306 25915
[1243] 48 11107 23907
[1244] 10832 11974 25773
[1245] 2223 17905 25484
[1246] 16782 17135 20446
[1247] 475 2861 3457
[1248] 16218 22449 24362
[1249] 11716 22200 25897
[1250] 8315 15009 22633
[1251] 13 20480 25852
[1252] 12352 18658 25687
[1253] 3681 14794 23703
[1254] 30 24531 25846
[1255] 4103 22077 24107
[1256] 23837 25622 25812
[1257] 3627 13387 25839
[1258] 908 5367 19388
[1259] 0 6894 25795
[1260] 20322 23546 25181
[1261] 8178 25260 25437
[1262] 2449 13244 22565
[1263] 31 18928 22741
[1264] 1312 5134 14838
[1265] 6085 13937 24220
[1266] 66 14633 25670
[1267] 47 22512 25472
[1268] 8867 24704 25279
[1269] 6742 21623 22745
[1270] 147 9948 24178
[1271] 8522 24261 24307
[1272] 19202 22406 24609.
[1273] An eighth data processing device/method according to the
present technology is a data processing device/method including: a
group-wise deinterleaving unit/step configured to restore a
sequence of an LDPC code that has undergone group-wise interleave
and has been obtained from data transmitted from a transmitting
device to an original sequence, the transmitting device including
an encoding unit configured to perform LDPC encoding based on a
parity check matrix of the LDPC code in which a code length N is
64800 bits and an encoding rate r is 9/15, a group-wise
interleaving unit configured to perform the group-wise interleave
of interleaving the LDPC code in units of bit groups of 360 bits,
and a mapping unit configured to map the LDPC code to any of 4096
signal points decided in a modulation scheme in units of 12 bits.
In the group-wise interleave, when an (i+1)-th bit group from a
head of the LDPC code is indicated by a bit group i, a sequence of
bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved
into a sequence of bit groups
[1274] 98, 159, 59, 125, 163, 89, 26, 4, 102, 70, 92, 36, 37, 142,
176, 95, 71, 19, 87, 45, 81, 47, 65, 170, 103, 48, 67, 61, 64, 35,
76, 80, 140, 77, 10, 167, 178, 155, 120, 156, 151, 12, 58, 5, 83,
137, 41, 109, 2, 66, 133, 62, 135, 28, 93, 128, 86, 57, 153, 161,
110, 52, 147, 141, 31, 79, 32, 88, 160, 84, 150, 6, 100, 73, 126,
164, 17, 42, 101, 7, 55, 105, 91, 22, 130, 154, 1, 82, 14, 0, 9,
21, 50, 165, 72, 138, 175, 106, 108, 3, 169, 30, 157, 54, 18, 20,
44, 34, 134, 107, 56, 53, 15, 162, 38, 166, 24, 33, 60, 85, 145,
115, 43, 39, 40, 124, 149, 144, 132, 96, 11, 146, 90, 129, 119,
111, 171, 8, 152, 121, 173, 131, 49, 27, 118, 16, 148, 68, 177, 94,
179, 13, 114, 75, 51, 117, 25, 46, 136, 143, 139, 113, 127, 174,
74, 29, 122, 158, 69, 97, 78, 63, 99, 112, 104, 116, 172, 168, 23,
and 123,
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[1275] 113 1557 3316 5680 6241 10407 13404 13947 14040 14353 15522
15698 16079 17363 19374 19543 20530 22833 24339
[1276] 271 1361 6236 7006 7307 7333 12768 15441 15568 17923 18341
20321 21502 22023 23938 25351 25590 25876 25910
[1277] 73 605 872 4008 6279 7653 10346 10799 12482 12935 13604
15909 16526 19782 20506 22804 23629 24859 25600
[1278] 1445 1690 4304 4851 8919 9176 9252 13783 16076 16675 17274
18806 18882 20819 21958 22451 23869 23999 24177
[1279] 1290 2337 5661 6371 8996 10102 10941 11360 12242 14918 16808
20571 23374 24046 25045 25060 25662 25783 25913
[1280] 28 42 1926 3421 3503 8558 9453 10168 15820 17473 19571 19685
22790 23336 23367 23890 24061 25657 25680
[1281] 0 1709 4041 4932 5968 7123 8430 9564 10596 11026 14761 19484
20762 20858 23803 24016 24795 25853 25863
[1282] 29 1625 6500 6609 16831 18517 18568 18738 19387 20159 20544
21603 21941 24137 24269 24416 24803 25154 25395
[1283] 55 66 871 3700 11426 13221 15001 16367 17601 18380 22796
23488 23938 25476 25635 25678 25807 25857 25872
[1284] 1 19 5958 8548 8860 11489 16845 18450 18469 19496 20190
23173 25262 25566 25668 25679 25858 25888 25915
[1285] 7520 7690 8855 9183 14654 16695 17121 17854 18083 18428
19633 20470 20736 21720 22335 23273 25083 25293 25403
[1286] 48 58 410 1299 3786 10668 18523 18963 20864 22106 22308
23033 23107 23128 23990 24286 24409 24595 25802
[1287] 12 51 3894 6539 8276 10885 11644 12777 13427 14039 15954
17078 19053 20537 22863 24521 25087 25463 25838
[1288] 3509 8748 9581 11509 15884 16230 17583 19264 20900 21001
21310 22547 22756 22959 24768 24814 25594 25626 25880
[1289] 21 29 69 1448 2386 4601 6626 6667 10242 13141 13852 14137
18640 19951 22449 23454 24431 25512 25814
[1290] 18 53 7890 9934 10063 16728 19040 19809 20825 21522 21800
23582 24556 25031 25547 25562 25733 25789 25906
[1291] 4096 4582 5766 5894 6517 10027 12182 13247 15207 17041 18958
20133 20503 22228 24332 24613 25689 25855 25883
[1292] 0 25 819 5539 7076 7536 7695 9532 13668 15051 17683 19665
20253 21996 24136 24890 25758 25784 25807
[1293] 34 40 44 4215 6076 7427 7965 8777 11017 15593 19542 22202
22973 23397 23423 24418 24873 25107 25644
[1294] 1595 6216 22850 25439
[1295] 1562 15172 19517 22362
[1296] 7508 12879 24324 24496
[1297] 6298 15819 16757 18721
[1298] 11173 15175 19966 21195
[1299] 59 13505 16941 23793
[1300] 2267 4830 12023 20587
[1301] 8827 9278 13072 16664
[1302] 14419 17463 23398 25348
[1303] 6112 16534 20423 22698
[1304] 493 8914 21103 24799
[1305] 6896 12761 13206 25873
[1306] 2 1380 12322 21701
[1307] 11600 21306 25753 25790
[1308] 8421 13076 14271 15401
[1309] 9630 14112 19017 20955
[1310] 212 13932 21781 25824
[1311] 5961 9110 16654 19636
[1312] 58 5434 9936 12770
[1313] 6575 11433 19798
[1314] 2731 7338 20926
[1315] 14253 18463 25404
[1316] 21791 24805 25869
[1317] 2 11646 15850
[1318] 6075 8586 23819
[1319] 18435 22093 24852
[1320] 2103 2368 11704
[1321] 10925 17402 18232
[1322] 9062 25061 25674
[1323] 18497 20853 23404
[1324] 18606 19364 19551
[1325] 7 1022 25543
[1326] 6744 15481 25868
[1327] 9081 17305 25164
[1328] 8 23701 25883
[1329] 9680 19955 22848
[1330] 56 4564 19121
[1331] 5595 15086 25892
[1332] 3174 17127 23183
[1333] 19397 19817 20275
[1334] 12561 24571 25825
[1335] 7111 9889 25865
[1336] 19104 20189 21851
[1337] 549 9686 25548
[1338] 6586 20325 25906
[1339] 3224 20710 21637
[1340] 641 15215 25754
[1341] 13484 23729 25818
[1342] 2043 7493 24246
[1343] 16860 25230 25768
[1344] 22047 24200 24902
[1345] 9391 18040 19499
[1346] 7855 24336 25069
[1347] 23834 25570 25852
[1348] 1977 8800 25756
[1349] 6671 21772 25859
[1350] 3279 6710 24444
[1351] 24099 25117 25820
[1352] 5553 12306 25915
[1353] 48 11107 23907
[1354] 10832 11974 25773
[1355] 2223 17905 25484
[1356] 16782 17135 20446
[1357] 475 2861 3457
[1358] 16218 22449 24362
[1359] 11716 22200 25897
[1360] 8315 15009 22633
[1361] 13 20480 25852
[1362] 12352 18658 25687
[1363] 3681 14794 23703
[1364] 30 24531 25846
[1365] 4103 22077 24107
[1366] 23837 25622 25812
[1367] 3627 13387 25839
[1368] 908 5367 19388
[1369] 0 6894 25795
[1370] 20322 23546 25181
[1371] 8178 25260 25437
[1372] 2449 13244 22565
[1373] 31 18928 22741
[1374] 1312 5134 14838
[1375] 6085 13937 24220
[1376] 66 14633 25670
[1377] 47 22512 25472
[1378] 8867 24704 25279
[1379] 6742 21623 22745
[1380] 147 9948 24178
[1381] 8522 24261 24307
[1382] 19202 22406 24609.
[1383] In the eighth data processing device/method according to the
present technology, a sequence of an LDPC code that has undergone
group-wise interleave and has been obtained from data transmitted
from a transmitting device is restored to an original sequence, the
transmitting device including an encoding unit configured to
perform LDPC encoding based on a parity check matrix of the LDPC
code in which a code length N is 64800 bits and an encoding rate r
is 9/15, a group-wise interleaving unit configured to perform the
group-wise interleave of interleaving the LDPC code in units of bit
groups of 360 bits, and a mapping unit configured to map the LDPC
code to any of 4096 signal points decided in a modulation scheme in
units of 12 bits. In the group-wise interleave, when an (i+1)-th
bit group from a head of the LDPC code is indicated by a bit group
i, a sequence of bit groups 0 to 179 of the LDPC code of 64800 bits
is interleaved into a sequence of bit groups
[1384] 98, 159, 59, 125, 163, 89, 26, 4, 102, 70, 92, 36, 37, 142,
176, 95, 71, 19, 87, 45, 81, 47, 65, 170, 103, 48, 67, 61, 64, 35,
76, 80, 140, 77, 10, 167, 178, 155, 120, 156, 151, 12, 58, 5, 83,
137, 41, 109, 2, 66, 133, 62, 135, 28, 93, 128, 86, 57, 153, 161,
110, 52, 147, 141, 31, 79, 32, 88, 160, 84, 150, 6, 100, 73, 126,
164, 17, 42, 101, 7, 55, 105, 91, 22, 130, 154, 1, 82, 14, 0, 9,
21, 50, 165, 72, 138, 175, 106, 108, 3, 169, 30, 157, 54, 18, 20,
44, 34, 134, 107, 56, 53, 15, 162, 38, 166, 24, 33, 60, 85, 145,
115, 43, 39, 40, 124, 149, 144, 132, 96, 11, 146, 90, 129, 119,
111, 171, 8, 152, 121, 173, 131, 49, 27, 118, 16, 148, 68, 177, 94,
179, 13, 114, 75, 51, 117, 25, 46, 136, 143, 139, 113, 127, 174,
74, 29, 122, 158, 69, 97, 78, 63, 99, 112, 104, 116, 172, 168, 23,
and 123,
The LDPC code includes an information bit and a parity bit. The
parity check matrix includes an information matrix portion
corresponding to the information bit and a parity matrix portion
corresponding to the parity bit. The information matrix portion is
represented by a parity check matrix initial value table. The
parity check matrix initial value table is a table in which a
position of a 1 element of the information matrix portion is
indicated for every 360 columns, and includes
[1385] 113 1557 3316 5680 6241 10407 13404 13947 14040 14353 15522
15698 16079 17363 19374 19543 20530 22833 24339
[1386] 271 1361 6236 7006 7307 7333 12768 15441 15568 17923 18341
20321 21502 22023 23938 25351 25590 25876 25910
[1387] 73 605 872 4008 6279 7653 10346 10799 12482 12935 13604
15909 16526 19782 20506 22804 23629 24859 25600
[1388] 1445 1690 4304 4851 8919 9176 9252 13783 16076 16675 17274
18806 18882 20819 21958 22451 23869 23999 24177
[1389] 1290 2337 5661 6371 8996 10102 10941 11360 12242 14918 16808
20571 23374 24046 25045 25060 25662 25783 25913
[1390] 28 42 1926 3421 3503 8558 9453 10168 15820 17473 19571 19685
22790 23336 23367 23890 24061 25657 25680
[1391] 0 1709 4041 4932 5968 7123 8430 9564 10596 11026 14761 19484
20762 20858 23803 24016 24795 25853 25863
[1392] 29 1625 6500 6609 16831 18517 18568 18738 19387 20159 20544
21603 21941 24137 24269 24416 24803 25154 25395
[1393] 55 66 871 3700 11426 13221 15001 16367 17601 18380 22796
23488 23938 25476 25635 25678 25807 25857 25872
[1394] 1 19 5958 8548 8860 11489 16845 18450 18469 19496 20190
23173 25262 25566 25668 25679 25858 25888 25915
[1395] 7520 7690 8855 9183 14654 16695 17121 17854 18083 18428
19633 20470 20736 21720 22335 23273 25083 25293 25403
[1396] 48 58 410 1299 3786 10668 18523 18963 20864 22106 22308
23033 23107 23128 23990 24286 24409 24595 25802
[1397] 12 51 3894 6539 8276 10885 11644 12777 13427 14039 15954
17078 19053 20537 22863 24521 25087 25463 25838
[1398] 3509 8748 9581 11509 15884 16230 17583 19264 20900 21001
21310 22547 22756 22959 24768 24814 25594 25626 25880
[1399] 21 29 69 1448 2386 4601 6626 6667 10242 13141 13852 14137
18640 19951 22449 23454 24431 25512 25814
[1400] 18 53 7890 9934 10063 16728 19040 19809 20825 21522 21800
23582 24556 25031 25547 25562 25733 25789 25906
[1401] 4096 4582 5766 5894 6517 10027 12182 13247 15207 17041 18958
20133 20503 22228 24332 24613 25689 25855 25883
[1402] 0 25 819 5539 7076 7536 7695 9532 13668 15051 17683 19665
20253 21996 24136 24890 25758 25784 25807
[1403] 34 40 44 4215 6076 7427 7965 8777 11017 15593 19542 22202
22973 23397 23423 24418 24873 25107 25644
[1404] 1595 6216 22850 25439
[1405] 1562 15172 19517 22362
[1406] 7508 12879 24324 24496
[1407] 6298 15819 16757 18721
[1408] 11173 15175 19966 21195
[1409] 59 13505 16941 23793
[1410] 2267 4830 12023 20587
[1411] 8827 9278 13072 16664
[1412] 14419 17463 23398 25348
[1413] 6112 16534 20423 22698
[1414] 493 8914 21103 24799
[1415] 6896 12761 13206 25873
[1416] 2 1380 12322 21701
[1417] 11600 21306 25753 25790
[1418] 8421 13076 14271 15401
[1419] 9630 14112 19017 20955
[1420] 212 13932 21781 25824
[1421] 5961 9110 16654 19636
[1422] 58 5434 9936 12770
[1423] 6575 11433 19798
[1424] 2731 7338 20926
[1425] 14253 18463 25404
[1426] 21791 24805 25869
[1427] 2 11646 15850
[1428] 6075 8586 23819
[1429] 18435 22093 24852
[1430] 2103 2368 11704
[1431] 10925 17402 18232
[1432] 9062 25061 25674
[1433] 18497 20853 23404
[1434] 18606 19364 19551
[1435] 7 1022 25543
[1436] 6744 15481 25868
[1437] 9081 17305 25164
[1438] 8 23701 25883
[1439] 9680 19955 22848
[1440] 56 4564 19121
[1441] 5595 15086 25892
[1442] 3174 17127 23183
[1443] 19397 19817 20275
[1444] 12561 24571 25825
[1445] 7111 9889 25865
[1446] 19104 20189 21851
[1447] 549 9686 25548
[1448] 6586 20325 25906
[1449] 3224 20710 21637
[1450] 641 15215 25754
[1451] 13484 23729 25818
[1452] 2043 7493 24246
[1453] 16860 25230 25768
[1454] 22047 24200 24902
[1455] 9391 18040 19499
[1456] 7855 24336 25069
[1457] 23834 25570 25852
[1458] 1977 8800 25756
[1459] 6671 21772 25859
[1460] 3279 6710 24444
[1461] 24099 25117 25820
[1462] 5553 12306 25915
[1463] 48 11107 23907
[1464] 10832 11974 25773
[1465] 2223 17905 25484
[1466] 16782 17135 20446
[1467] 475 2861 3457
[1468] 16218 22449 24362
[1469] 11716 22200 25897
[1470] 8315 15009 22633
[1471] 13 20480 25852
[1472] 12352 18658 25687
[1473] 3681 14794 23703
[1474] 30 24531 25846
[1475] 4103 22077 24107
[1476] 23837 25622 25812
[1477] 3627 13387 25839
[1478] 908 5367 19388
[1479] 0 6894 25795
[1480] 20322 23546 25181
[1481] 8178 25260 25437
[1482] 2449 13244 22565
[1483] 31 18928 22741
[1484] 1312 5134 14838
[1485] 6085 13937 24220
[1486] 66 14633 25670
[1487] 47 22512 25472
[1488] 8867 24704 25279
[1489] 6742 21623 22745
[1490] 147 9948 24178
[1491] 8522 24261 24307
[1492] 19202 22406 24609.
[1493] The data processing device may be an independent device and
may be an internal block constituting one device.
Advantageous Effects of Invention
[1494] According to the present technology, it is possible to
secure excellent communication quality in data transmission using
the LDPC code.
[1495] The effects described herein are not necessarily limited and
may include any effect described in the present disclosure.
BRIEF DESCRIPTION OF DRAWINGS
[1496] FIG. 1 is an illustration of a parity check matrix H of an
LDPC code.
[1497] FIG. 2 is a flowchart illustrating a decoding sequence of an
LDPC code.
[1498] FIG. 3 is an illustration of an example of a parity check
matrix of an LDPC code.
[1499] FIG. 4 is an illustration of an example of a Tanner graph of
a parity check matrix.
[1500] FIG. 5 is an illustration of an example of a variable
node.
[1501] FIG. 6 is an illustration of an example of a check node.
[1502] FIG. 7 is an illustration of a configuration example of an
embodiment of a transmission system to which the present invention
is applied.
[1503] FIG. 8 is a block diagram illustrating a configuration
example of a transmitting device 11.
[1504] FIG. 9 is a block diagram illustrating a configuration
example of a bit interleaver 116.
[1505] FIG. 10 is an illustration of an example of a parity check
matrix.
[1506] FIG. 11 is an illustration of an example of a parity
matrix.
[1507] FIG. 12 is an illustration of the parity check matrix of the
LDPC code that is defined in the standard of the DVB-T.2.
[1508] FIG. 13 is an illustration of the parity check matrix of the
LDPC code that is defined in the standard of the DVB-T.2.
[1509] FIG. 14 is an illustration of an example of a Tanner graph
for decoding of an LDPC code.
[1510] FIG. 15 is an illustration of an example of a parity matrix
H.sub.T becoming a staircase structure and a Tanner graph
corresponding to the parity matrix H.sub.T.
[1511] FIG. 16 is an illustration of an example of a parity matrix
H.sub.T of a parity check matrix H corresponding to an LDPC code
after parity interleave.
[1512] FIG. 17 is a flowchart illustrating an example of a process
performed by a bit interleaver 116 and a mapper 117.
[1513] FIG. 18 is a block diagram illustrating a configuration
example of an LDPC encoder 115.
[1514] FIG. 19 is a flowchart illustrating processing of an example
of an LDPC encoder 115.
[1515] FIG. 20 is an illustration of an example of a parity check
matrix initial value table in which an encoding rate is 1/4 and a
code length is 16200.
[1516] FIG. 21 is an illustration of a method of calculating a
parity check matrix H from a parity check matrix initial value
table.
[1517] FIG. 22 is an illustration of a structure of a parity check
matrix.
[1518] FIG. 23 is an illustration of an example of the parity check
matrix initial value table.
[1519] FIG. 24 is an illustration of an A matrix generated from a
parity check matrix initial value table.
[1520] FIG. 25 is an illustration of parity interleave of a B
matrix.
[1521] FIG. 26 is an illustration of a C matrix generated from a
parity check matrix initial value table.
[1522] FIG. 27 is an illustration of parity interleave of a D
matrix.
[1523] FIG. 28 is an illustration of a parity check matrix obtained
by performing a column permutation serving as parity deinterleave
for restoring parity interleave to an original state on a parity
check matrix.
[1524] FIG. 29 is an illustration of a transformed parity check
matrix obtained by performing a row permutation on a parity check
matrix.
[1525] FIG. 30 is an illustration of an example of the parity check
matrix initial value table.
[1526] FIG. 31 is an illustration of an example of the parity check
matrix initial value table.
[1527] FIG. 32 is an illustration of an example of the parity check
matrix initial value table.
[1528] FIG. 33 is an illustration of an example of the parity check
matrix initial value table.
[1529] FIG. 34 is an illustration of an example of the parity check
matrix initial value table.
[1530] FIG. 35 is an illustration of an example of the parity check
matrix initial value table.
[1531] FIG. 36 is an illustration of an example of the parity check
matrix initial value table.
[1532] FIG. 37 is an illustration of an example of the parity check
matrix initial value table.
[1533] FIG. 38 is an illustration of an example of the parity check
matrix initial value table.
[1534] FIG. 39 is an illustration of an example of the parity check
matrix initial value table.
[1535] FIG. 40 is an illustration of an example of the parity check
matrix initial value table.
[1536] FIG. 41 is an illustration of an example of the parity check
matrix initial value table.
[1537] FIG. 42 is an illustration of an example of the parity check
matrix initial value table.
[1538] FIG. 43 is an illustration of an example of the parity check
matrix initial value table.
[1539] FIG. 44 is an illustration of an example of the parity check
matrix initial value table.
[1540] FIG. 45 is an illustration of an example of the parity check
matrix initial value table.
[1541] FIG. 46 is an illustration of an example of the parity check
matrix initial value table.
[1542] FIG. 47 is an illustration of an example of the parity check
matrix initial value table.
[1543] FIG. 48 is an illustration of an example of the parity check
matrix initial value table.
[1544] FIG. 49 is an illustration of an example of the parity check
matrix initial value table.
[1545] FIG. 50 is an illustration of an example of the parity check
matrix initial value table.
[1546] FIG. 51 is an illustration of an example of the parity check
matrix initial value table.
[1547] FIG. 52 is an illustration of an example of the parity check
matrix initial value table.
[1548] FIG. 53 is an illustration of an example of the parity check
matrix initial value table.
[1549] FIG. 54 is an illustration of an example of the parity check
matrix initial value table.
[1550] FIG. 55 is an illustration of an example of the parity check
matrix initial value table.
[1551] FIG. 56 is an illustration of an example of the parity check
matrix initial value table.
[1552] FIG. 57 is an illustration of an example of the parity check
matrix initial value table.
[1553] FIG. 58 is an illustration of an example of the parity check
matrix initial value table.
[1554] FIG. 59 is an illustration of an example of the parity check
matrix initial value table.
[1555] FIG. 60 is an illustration of an example of the parity check
matrix initial value table.
[1556] FIG. 61 is an illustration of an example of the parity check
matrix initial value table.
[1557] FIG. 62 is an illustration of an example of the parity check
matrix initial value table.
[1558] FIG. 63 is an illustration of an example of the parity check
matrix initial value table.
[1559] FIG. 64 is an illustration of an example of the parity check
matrix initial value table.
[1560] FIG. 65 is an illustration of an example of the parity check
matrix initial value table.
[1561] FIG. 66 is an illustration of an example of the parity check
matrix initial value table.
[1562] FIG. 67 is an illustration of an example of the parity check
matrix initial value table.
[1563] FIG. 68 is an illustration of an example of the parity check
matrix initial value table.
[1564] FIG. 69 is an illustration of an example of the parity check
matrix initial value table.
[1565] FIG. 70 is an illustration of an example of the parity check
matrix initial value table.
[1566] FIG. 71 is an illustration of an example of the parity check
matrix initial value table.
[1567] FIG. 72 is an illustration of an example of the parity check
matrix initial value table.
[1568] FIG. 73 is an illustration of an example of a tanner graph
of an ensemble of a degree sequence in which a column weight is 3,
and a row weight is 6.
[1569] FIG. 74 is an illustration of an example of a tanner graph
of an ensemble of a multi-edge type.
[1570] FIG. 75 is an illustration of a parity check matrix.
[1571] FIG. 76 is an illustration of a parity check matrix.
[1572] FIG. 77 is an illustration of a parity check matrix.
[1573] FIG. 78 is an illustration of a parity check matrix.
[1574] FIG. 79 is an illustration of a parity check matrix.
[1575] FIG. 80 is an illustration of a parity check matrix.
[1576] FIG. 81 is an illustration of a parity check matrix.
[1577] FIG. 82 is an illustration of a parity check matrix.
[1578] FIG. 83 is an illustration of an example of a constellation
when a modulation scheme is 16QAM.
[1579] FIG. 84 is an illustration of an example of a constellation
when a modulation scheme is 64QAM.
[1580] FIG. 85 is an illustration of an example of a constellation
when a modulation scheme is 256QAM.
[1581] FIG. 86 is an illustration of an example of a constellation
when a modulation scheme is 1024QAM.
[1582] FIG. 87 is an illustration of an example of a constellation
when a modulation scheme is 4096QAM.
[1583] FIG. 88 is an illustration of an example of a constellation
when a modulation scheme is 4096QAM.
[1584] FIG. 89 is an illustration of an example of coordinates of a
signal point of a UC when a modulation scheme is QPSK.
[1585] FIG. 90 is an illustration of an example of coordinates of a
signal point of a 2D NUC when a modulation scheme is 16QAM.
[1586] FIG. 91 is an illustration of an example of coordinates of a
signal point of a 2D NUC when a modulation scheme is 64QAM.
[1587] FIG. 92 is an illustration of an example of coordinates of a
signal point of a 2D NUC when a modulation scheme is 256QAM.
[1588] FIG. 93 is an illustration of an example of coordinates of a
signal point of a 2D NUC when a modulation scheme is 256QAM.
[1589] FIG. 94 is an illustration of an example of coordinates of a
signal point of a 1D NUC when a modulation scheme is 1024QAM.
[1590] FIG. 95 is an illustration of relations of a symbol y of
1024QAM with a real part Re (z.sub.q) and an imaginary part Im
(z.sub.q) of a complex number serving as coordinates of a signal
point z.sub.q of a 1D NUC corresponding to the symbol y.
[1591] FIG. 96 is an illustration of an example of coordinates of a
signal point of a 1D NUC when a modulation scheme is 4096QAM.
[1592] FIG. 97 is an illustration of relations of a symbol y of
4096QAM with a real part Re (z.sub.q) and an imaginary part Im
(z.sub.q) of a complex number serving as coordinates of a signal
point z.sub.q of a 1 D NUC corresponding to the symbol y.
[1593] FIG. 98 is an illustration of another example of a
constellation when a modulation scheme is 16QAM
[1594] FIG. 99 is an illustration of another example of a
constellation when a modulation scheme is 64QAM
[1595] FIG. 100 is an illustration of another example of a
constellation when a modulation scheme is 256QAM
[1596] FIG. 101 is an illustration of another example of
coordinates of a signal point of a 2D NUC when a modulation scheme
is 16QAM.
[1597] FIG. 102 is an illustration of another example of
coordinates of a signal point of a 2D NUC when a modulation scheme
is 64QAM.
[1598] FIG. 103 is an illustration of another example of
coordinates of a signal point of a 2D NUC when a modulation scheme
is 256QAM.
[1599] FIG. 104 is an illustration of another example of
coordinates of a signal point of a 2D NUC when a modulation scheme
is 256QAM.
[1600] FIG. 105 is a block diagram illustrating a configuration
example of a block interleaver 25.
[1601] FIG. 106 is an illustration of an example of the number C of
columns of parts 1 and 2 and part column lengths R1 and R2 for a
combination of a code length N and a modulation scheme.
[1602] FIG. 107 is an illustration of block interleave performed by
a block interleaver 25.
[1603] FIG. 108 is an illustration of group-wise interleave
performed by a group-wise interleaver 24.
[1604] FIG. 109 is an illustration of a 1st example of a GW pattern
for an LDPC code in which a code length N is 64 k bits.
[1605] FIG. 110 is an illustration of a 2nd example of a GW pattern
for an LDPC code in which a code length N is 64 k bits.
[1606] FIG. 111 is an illustration of a 3rd example of a GW pattern
for an LDPC code in which a code length N is 64 k bits.
[1607] FIG. 112 is an illustration of a 4th example of a GW pattern
for an LDPC code in which a code length IN is 64 k bits.
[1608] FIG. 113 is an illustration of a 5th example of a GW pattern
for an LDPC code in which a code length N is 64 k bits.
[1609] FIG. 114 is an illustration of a 6th example of a GW pattern
for an LDPC code in which a code length N is 64 k bits.
[1610] FIG. 115 is an illustration of a 7th example of a GW pattern
for an LDPC code in which a code length N is 64 k bits.
[1611] FIG. 116 is an illustration of an 8th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1612] FIG. 117 is an illustration of a 9th example of a GW pattern
for an LDPC code in which a code length N is 64 k bits.
[1613] FIG. 118 is an illustration of a 10th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1614] FIG. 119 is an illustration of an 11th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1615] FIG. 120 is an illustration of a 12th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1616] FIG. 121 is an illustration of a 13th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1617] FIG. 122 is an illustration of a 14th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1618] FIG. 123 is an illustration of a 15th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1619] FIG. 124 is an illustration of a 16th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1620] FIG. 125 is an illustration of a 17th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1621] FIG. 126 is an illustration of an 18th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1622] FIG. 127 is an illustration of a 19th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1623] FIG. 128 is an illustration of a 20th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1624] FIG. 129 is an illustration of a 21st example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1625] FIG. 130 is an illustration of a 22nd example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1626] FIG. 131 is an illustration of a 23rd example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1627] FIG. 132 is an illustration of a 24th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1628] FIG. 133 is an illustration of a 25th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1629] FIG. 134 is an illustration of a 26th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1630] FIG. 135 is an illustration of a 27th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1631] FIG. 136 is an illustration of a 28th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1632] FIG. 137 is an illustration of a 29th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1633] FIG. 138 is an illustration of a 30th example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1634] FIG. 139 is an illustration of a 31st example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1635] FIG. 140 is an illustration of a 32nd example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1636] FIG. 141 is an illustration of a 33rd example of a GW
pattern for an LDPC code in which a code length N is 64 k bits.
[1637] FIG. 142 is an illustration of a 1st example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[1638] FIG. 143 is an illustration of a 2nd example of a GW pattern
for an LDPC code in which a code length IN is 16 k bits.
[1639] FIG. 144 is an illustration of a 3rd example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[1640] FIG. 145 is an illustration of a 4th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[1641] FIG. 146 is an illustration of a 5th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[1642] FIG. 147 is an illustration of a 6th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[1643] FIG. 148 is an illustration of a 7th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[1644] FIG. 149 is an illustration of an 8th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1645] FIG. 150 is an illustration of a 9th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[1646] FIG. 151 is an illustration of a 10th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1647] FIG. 152 is an illustration of an 11th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1648] FIG. 153 is an illustration of a 12th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1649] FIG. 154 is an illustration of a 13th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1650] FIG. 155 is an illustration of a 14th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1651] FIG. 156 is an illustration of a 15th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1652] FIG. 157 is an illustration of a 16th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[1653] FIG. 158 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1654] FIG. 159 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1655] FIG. 160 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1656] FIG. 161 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1657] FIG. 162 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1658] FIG. 163 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1659] FIG. 164 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1660] FIG. 165 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1661] FIG. 166 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1662] FIG. 167 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1663] FIG. 168 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1664] FIG. 169 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1665] FIG. 170 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1666] FIG. 171 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1667] FIG. 172 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1668] FIG. 173 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1669] FIG. 174 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1670] FIG. 175 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1671] FIG. 176 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1672] FIG. 177 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1673] FIG. 178 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1674] FIG. 179 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1675] FIG. 180 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1676] FIG. 181 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1677] FIG. 182 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1678] FIG. 183 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1679] FIG. 184 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1680] FIG. 185 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1681] FIG. 186 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1682] FIG. 187 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1683] FIG. 188 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1684] FIG. 189 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1685] FIG. 190 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1686] FIG. 191 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1687] FIG. 192 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1688] FIG. 193 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1689] FIG. 194 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1690] FIG. 195 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1691] FIG. 196 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1692] FIG. 197 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1693] FIG. 198 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1694] FIG. 199 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1695] FIG. 200 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1696] FIG. 201 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1697] FIG. 202 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1698] FIG. 203 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1699] FIG. 204 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1700] FIG. 205 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1701] FIG. 206 is an illustration of a simulation result of a
simulation of measuring an error rate.
[1702] FIG. 207 is a block diagram illustrating a configuration
example of a receiving device 12.
[1703] FIG. 208 is a block diagram illustrating a configuration
example of a bit deinterleaver 165.
[1704] FIG. 209 is a flowchart illustrating an example of a process
performed by a demapper 164, a bit deinterleaver 165, and an LDPC
decoder 166.
[1705] FIG. 210 is an illustration of an example of a parity check
matrix of an LDPC code.
[1706] FIG. 211 is an illustration of an example of a matrix (a
transformed parity check matrix) obtained by performing a row
permutation and a column permutation on a parity check matrix.
[1707] FIG. 212 is an illustration of an example of a transformed
parity check matrix divided into 5.times.5 units.
[1708] FIG. 213 is a block diagram illustrating a configuration
example of a decoding device that collectively performs P node
operations.
[1709] FIG. 214 is a block diagram illustrating a configuration
example of an LDPC decoder 166.
[1710] FIG. 215 is a block diagram illustrating a configuration
example of a block deinterleaver 54.
[1711] FIG. 216 is a block diagram illustrating another
configuration example of a bit deinterleaver 165.
[1712] FIG. 217 is a block diagram illustrating a first
configuration example of a reception system that can be applied to
the receiving device 12.
[1713] FIG. 218 is a block diagram illustrating a second
configuration example of a reception system that can be applied to
the receiving device 12.
[1714] FIG. 219 is a block diagram illustrating a third
configuration example of a reception system that can be applied to
the receiving device 12.
[1715] FIG. 220 is a block diagram illustrating a configuration
example of an embodiment of a computer to which the present
technology is applied.
DESCRIPTION OF EMBODIMENTS
[1716] Hereinafter, exemplary embodiments of the present technology
will be described, but before the description of the exemplary
embodiments of the present technology, an LDPC code will be
described.
[1717] <LDPC Code>
[1718] The LDPC code is a linear code and it is not necessary for
the LDPC code to be a binary code. However, in this case, it is
assumed that the LDPC code is the binary code.
[1719] A maximum characteristic of the LDPC code is that a parity
check matrix defining the LDPC code is sparse. In this case, the
sparse matrix is a matrix in which the number of "1" of elements of
the matrix is very small (a matrix in which most elements are
0).
[1720] FIG. 1 is an illustration of an example of a parity check
matrix H of the LDPC code.
[1721] In the parity check matrix H of FIG. 1, a weight of each
column (the column weight) (the number of "1") becomes "3" and a
weight of each row (the row weight) becomes "6".
[1722] In encoding using the LDPC code (LDPC encoding), for
example, a generation matrix G is generated on the basis of the
parity check matrix H and the generation matrix G is multiplied by
binary information bits, so that a code word (LDPC code) is
generated.
[1723] Specifically, an encoding device that performs the LDPC
encoding first calculates the generation matrix G in which an
expression GH.sup.T=0 is realized, between a transposed matrix
H.sup.T of the parity check matrix H and the generation matrix G.
In this case, when the generation matrix G is a K.times.N matrix,
the encoding device multiplies the generation matrix G with a bit
string (vector u) of information bits including K bits and
generates a code word c (=uG) including N bits. The code word (LDPC
code) that is generated by the encoding device is received at a
reception side through a predetermined communication path.
[1724] The LDPC code can be decoded by an algorithm called
probabilistic decoding suggested by Gallager, that is, a message
passing algorithm using belief propagation on a so-called Tanner
graph, including a variable node (also referred to as a message
node) and a check node. Hereinafter, the variable node and the
check node are appropriately referred to as nodes simply.
[1725] FIG. 2 is a flowchart illustrating a decoding sequence of an
LDPC code.
[1726] Hereinafter, a real value (a reception LLR) that is obtained
by representing the likelihood of "0" of a value of an i-th code
bit of the LDPC code (one code word) received by the reception side
by a log likelihood ratio is appropriately referred to as a
reception value u.sub.0i. In addition, a message output from the
check node is referred to as u.sub.j and a message output from the
variable node is referred to as v.sub.i.
[1727] First, in decoding of the LDPC code, as illustrated in FIG.
2, in step S11, the LDPC code is received, the message (check node
message) u.sub.j is initialized to "0", and a variable k taking an
integer as a counter of repetition processing is initialized to
"0", and the processing proceeds to step S12. In step S12, the
message (variable node message) v.sub.i is calculated by performing
an operation (variable node operation) represented by an expression
(1), on the basis of the reception value u.sub.0i obtained by
receiving the LDPC code, and the message u.sub.j is calculated by
performing an operation (check node operation) represented by an
expression (2), on the basis of the message v.sub.i.
[ Math . 1 ] v i = u 0 i + j = 1 d v - 1 u j ( 1 ) [ Math . 2 ] tan
h ( u j 2 ) = i = 1 d c - 1 tan h ( v i 2 ) ( 2 ) ##EQU00001##
[1728] Here, d.sub.v and d.sub.c in an expression (1) and
expression (2) are respectively parameters which can be arbitrarily
selected and illustrates the number of "1" in the longitudinal
direction (column) and transverse direction (row) of the parity
check matrix H. For example, in the case of an LDPC code ((3, 6)
LDPC code) with respect to the parity check matrix H with a column
weight of 3 and a row weight of 6 as illustrated in FIGS. 1,
d.sub.v=3 and d.sub.c=6 are established.
[1729] In the variable node operation of the expression (1) and the
check node operation of the expression (2), because a message input
from an edge (line coupling the variable node and the check node)
for outputting the message is not an operation target, an operation
range becomes 1 to -1 or 1 to d.sub.c-1. The check node operation
of the expression (2) is performed actually by previously making a
table of a function R (v.sub.1, v.sub.2) represented by an
expression (3) defined by one output with respect to two inputs
v.sub.1 and v.sub.2 and using the table consecutively
(recursively), as represented by an expression (4).
[Math. 3]
x=2 tan h.sup.-1{tan h(v.sub.1/2)tan
h(v.sub.2/2)}=R(v.sub.1,v.sub.2) (3)
[Math. 4]
u.sub.j=R(v.sub.1,R(v.sub.2,R(v.sub.3, . . .
R(v.sub.d.sub.c.sub.-2,v.sub.d.sub.c.sub.-1)))) (4)
[1730] In step S12, the variable k is incremented by "1" and the
processing proceeds to step S13. In step S13, it is determined
whether the variable k is more than the predetermined repetition
decoding number of times C. When it is determined in step S13 that
the variable k is not more than C, the processing returns to step
S12 and the same processing is repeated hereinafter.
[1731] When it is determined in step S13 that the variable k is
more than C, the processing proceeds to step S14, the message
v.sub.i that corresponds to a decoding result to be finally output
is calculated by performing an operation represented by an
expression (5) and is output, and the decoding processing of the
LDPC code ends.
[ Math . 5 ] v i = u 0 i + j = 1 d v u j ( 5 ) ##EQU00002##
[1732] In this case, the operation of the expression (5) is
performed using messages u.sub.j from all edges connected to the
variable node, different from the variable node operation of the
expression (1).
[1733] FIG. 3 illustrates an example of the parity check matrix H
of the (3, 6) LDPC code (an encoding rate of 1/2 and a code length
of 12).
[1734] In the parity check matrix H of FIG. 3, a weight of a column
is set to 3 and a weight of a row is set to 6, similar to FIG.
1.
[1735] FIG. 4 illustrates a Tanner graph of the parity check matrix
H of FIG. 3.
[1736] In FIG. 4, the check node is represented by "+" (plus) and
the variable node is represented by "=" (equal). The check node and
the variable node correspond to the row and the column of the
parity check matrix H. A line that couples the check node and the
variable node is the edge and corresponds to "1" of elements of the
parity check matrix.
[1737] That is, when an element of a j-th row and an i-th column of
the parity check matrix is 1, in FIG. 4, an i-th variable node
(node of "=") from the upper side and a j-th check node (node of
"+") from the upper side are connected by the edge. The edge shows
that a code bit corresponding to the variable node has a
restriction condition corresponding to the check node.
[1738] In a sum product algorithm that is a decoding method of the
LDPC code, the variable node operation and the check node operation
are repetitively performed.
[1739] FIG. 5 illustrates the variable node operation that is
performed by the variable node.
[1740] In the variable node, the message v.sub.i that corresponds
to the edge for calculation is calculated by the variable node
operation of the expression (1) using messages u.sub.1 and u.sub.2
from the remaining edges connected to the variable node and the
reception value u.sub.0i. The messages that correspond to the other
edges are also calculated by the same method.
[1741] FIG. 6 illustrates the check node operation that is
performed by the check node.
[1742] In this case, the check node operation of the expression (2)
can be rewritten by an expression (6) using a relation of an
expression
a.times.b=exp{(ln(|a|)+ln(|b|)}.times.sign(a).times.sign(b).
However, sign(x) is 1 in the case of x.gtoreq.0 and is -1 in the
case of x<0.
[ Math . 6 ] u j = 2 tan h - 1 ( i = 1 d c - 1 tan h ( v i 2 ) ) =
2 tan h - 1 [ exp { i = 1 d c - 1 ln ( tan h ( v i 2 ) ) } .times.
i = 1 d c - 1 sign ( tan h ( v i 2 ) ) ] = 2 tan h - 1 [ exp { - (
i = 1 d c - 1 - ln ( tan h ( v i 2 ) ) ) } ] .times. i = 1 d c - 1
sign ( v i ) ( 6 ) ##EQU00003##
[1743] In x.gtoreq.0, if a function .phi.(x) is defined as an
expression .phi.(x)=ln(tan h(x/2)), an expression .phi..sup.-1(x)=2
tan h.sup.-1(e.sup.-x) is realized. For this reason, the expression
(6) can be changed to an expression (7).
[ Math . 7 ] u j = .phi. - 1 ( i = 1 d c - 1 .phi. ( v i ) )
.times. i = 1 d c - 1 sign ( v i ) ( 7 ) ##EQU00004##
[1744] In the check node, the check node operation of the
expression (2) is performed according to the expression (7).
[1745] That is, in the check node, as illustrated in FIG. 6, the
message u.sub.j that corresponds to the edge for calculation is
calculated by the check node operation of the expression (7) using
messages v.sub.1, v.sub.2, v.sub.3, v.sub.4, and v.sub.5 from the
remaining edges connected to the check node. The messages that
correspond to the other edges are also calculated by the same
method.
[1746] The function .phi.(x) of the expression (7) can be
represented as .phi.(x)=ln((e.sup.x+1)/(e.sup.x-1)) and
.phi.(x)=.phi..sup.-1(x) is satisfied in x>0. When the functions
.phi.(x) and .phi..sup.-1(x) are mounted to hardware, the functions
.phi.(x) and .phi..sup.-1(x) may be mounted using an LUT (Look Up
Table). However, both the functions .phi.(x) and .phi..sup.-1(x)
become the same LUT.
[1747] <Configuration Example of Transmission System to which
Present Disclosure is Applied>
[1748] FIG. 7 illustrates a configuration example of an embodiment
of a transmission system (a system means a logical gathering of a
plurality of devices and a device of each configuration may be
arranged or may not be arranged in the same casing) to which the
present invention is applied.
[1749] In FIG. 7, the transmission system includes a transmitting
device 11 and a receiving device 12.
[1750] For example, the transmitting device 11 transmits
(broadcasts) (transfers) a program of television broadcasting, and
so on. That is, for example, the transmitting device 11 encodes
target data that is a transmission target such as image data and
audio data as a program into LDPC codes, and, for example,
transmits them through a communication path 13 such as a satellite
circuit, a ground wave and a cable (wire circuit).
[1751] The receiving device 12 receives the LDPC code transmitted
from the transmitting device 11 through the communication path 13,
decodes the LDPC code to obtain the target data, and outputs the
target data.
[1752] In this case, it is known that the LDPC code used by the
transmission system of FIG. 7 shows the very high capability in an
AWGN (Additive White Gaussian Noise) communication path.
[1753] Meanwhile, in the communication path 13, burst error or
erasure may be generated. Especially in the case where the
communication path 13 is the ground wave, for example, in an OFDM
(Orthogonal Frequency Division Multiplexing) system, power of a
specific symbol may become 0 (erasure) according to delay of an
echo (paths other than a main path), under a multi-path environment
in which D/U (Desired to Undesired Ratio) is 0 dB (power of
Undesired=echo is equal to power of Desired=main path).
[1754] In the flutter (communication path in which delay is 0 and
an echo having a Doppler frequency is added), when D/U is 0 dB,
entire power of an OFDM symbol at a specific time may become 0
(erasure) by the Doppler frequency.
[1755] In addition, the burst error may be generated due to a
situation of a wiring line from a receiving unit (not illustrated
in the drawings) of the side of the receiving device 12 such as an
antenna receiving a signal from the transmitting device 11 to the
receiving device 12 or instability of a power supply of the
receiving device 12.
[1756] Meanwhile, in decoding of the LDPC code, in the variable
node corresponding to the column of the parity check matrix H and
the code bit of the LDPC code, as illustrated in FIG. 5, the
variable node operation of the expression (1) with the addition of
(the reception value u0i of) the code bit of the LDPC code is
performed. For this reason, if error is generated in the code bits
used for the variable node operation, precision of the calculated
message is deteriorated.
[1757] In the decoding of the LDPC code, in the check node, the
check node operation of the expression (7) is performed using the
message calculated by the variable node connected to the check
node. For this reason, if the number of check nodes in which error
(including erasure) is generated simultaneously in (the code bits
of the LDPC codes corresponding to) the plurality of connected
variable nodes increases, decoding performance is deteriorated.
[1758] That is, if the two or more variable nodes of the variable
nodes connected to the check node become simultaneously erasure,
the check node returns a message in which the probability of a
value being 0 and the probability of a value being 1 are equal to
each other, to all the variable nodes. In this case, the check node
that returns the message of the equal probabilities does not
contribute to one decoding processing (one set of the variable node
operation and the check node operation). As a result, it is
necessary to increase the repetition number of times of the
decoding processing, the decoding performance is deteriorated, and
consumption power of the receiving device 12 that performs decoding
of the LDPC code increases.
[1759] Therefore, in the transmission system of FIG. 7, tolerance
against the burst error or the erasure can be improved while
performance in the AWGN communication path (AWGN channel) is
maintained.
[1760] <Configuration Example of Transmitting Device 11>
[1761] FIG. 8 is a block diagram illustrating a configuration
example of the transmitting device 11 of FIG. 7.
[1762] In the transmitting device 11, one or more input streams
corresponding to target data are supplied to a mode
adaptation/multiplexer 111.
[1763] The mode adaptation/multiplexer 111 performs mode selection
and processes such as multiplexing of one or more input streams
supplied thereto, as needed, and supplies data obtained as a result
to a padder 112.
[1764] The padder 112 performs necessary zero padding (insertion of
Null) with respect to the data supplied from the mode
adaptation/multiplexer 111 and supplies data obtained as a result
to a BB scrambler 113.
[1765] The BB scrambler 113 performs base-band scrambling (BB
scrambling) with respect to the data supplied from the padder 112
and supplies data obtained as a result to a BCH encoder 114.
[1766] The BCH encoder 114 performs BCH encoding with respect to
the data supplied from the BB scrambler 113 and supplies data
obtained as a result as LDPC target data to be an LDPC encoding
target to an LDPC encoder 115.
[1767] The LDPC encoder 115 performs LDPC encoding according to a
parity check matrix or the like in which a parity matrix to be a
portion corresponding to a parity bit of an LDPC code becomes a
staircase (dual diagonal) structure with respect to the LDPC target
data supplied from the BCH encoder 114, for example, and outputs an
LDPC code in which the LDPC target data is information bits.
[1768] That is, the LDPC encoder 115 performs the LDPC encoding to
encode the LDPC target data with an LDPC such as the LDPC code
(corresponding to the parity check matrix) defined in the
predetermined standard of the DVB-S.2, the DVB-T.2, the DVB-C.2 or
the like, and the LDPC code (corresponding to the parity check
matrix) or the like that is to be employed in ATSC 3.0, and outputs
the LDPC code obtained as a result.
[1769] The LDPC code defined in the standard of the DVB-T.2 and the
LDPC code that is to be employed in ATSC 3.0 are an IRA (Irregular
Repeat Accumulate) code and a parity matrix of the parity check
matrix of the LDPC code becomes a staircase structure. The parity
matrix and the staircase structure will be described later. The IRA
code is described in "Irregular Repeat-Accumulate Codes", H. Jin,
A. Khandekar, and R. J. McEliece, in Proceedings of 2nd
International Symposium on Turbo codes and Related Topics, pp. 1-8,
September 2000, for example.
[1770] The LDPC code that is output by the LDPC encoder 115 is
supplied to the bit interleaver 116.
[1771] The bit interleaver 116 performs bit interleave to be
described later with respect to the LDPC code supplied from the
LDPC encoder 115 and supplies the LDPC code after the bit
interleave to an mapper 117.
[1772] The mapper 117 maps the LDPC code supplied from the bit
interleaver 116 to a signal point representing one symbol of
orthogonal modulation in a unit (symbol unit) of code bits of one
or more bits of the LDPC code and performs the orthogonal
modulation (multilevel modulation).
[1773] That is, the mapper 117 performs maps the LDPC code supplied
from the bit interleaver 116 to a signal point determined by a
modulation scheme performing the orthogonal modulation of the LDPC
code, on an IQ plane (IQ constellation) defined by an I axis
representing an I component of the same phase as a carrier and a Q
axis representing a Q component orthogonal to the carrier, and
performs the orthogonal modulation.
[1774] When the number of signal points decided in the modulation
scheme of the orthogonal modulation performed by the mapper 117 is
2.sup.m, m-bit code bits of the LDPC code are used as a symbol (one
symbol), and the mapper 117 maps the LDPC code supplied from the
bit interleaver 116 to a signal point indicating a symbol among the
2.sup.m signal points in units of symbols.
[1775] Here, examples of the modulation scheme of the orthogonal
modulation performed by the mapper 117 include a modulation scheme
specified in a standard such as DVB-T.2, a modulation scheme that
is scheduled to be employed in ATSC 3.0, and other modulation
schemes, that is, includes Binary Phase Shift Keying (BPSK),
Quadrature Phase Shift Keying (QPSK), 8 Phase-Shift Keying (8PSK),
16 Amplitude Phase-Shift Keying (APSK), 32APSK, 16 Quadrature
Amplitude Modulation (QAM), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM,
and 4 Pulse Amplitude Modulation (PAM). A modulation scheme by
which the orthogonal modulation is performed in the mapper 117 is
set in advance, for example, according to an operation of an
operator of the transmitting device 11.
[1776] The data (a mapping result of mapping the symbol to the
signal point) obtained by the process of the mapper 117 is supplied
to a time interleaver 118.
[1777] The time interleaver 118 performs time interleave
(interleave in a time direction) in a unit of symbol with respect
to the data supplied from the mapper 117 and supplies data obtained
as a result to an single input single output/multiple input single
output encoder (SISO/MISO encoder) 119.
[1778] The SISO/MISO encoder 119 performs spatiotemporal encoding
with respect to the data supplied from the time interleaver 118 and
supplies the data to the frequency interleaver 120.
[1779] The frequency interleaver 120 performs frequency interleave
(interleave in a frequency direction) in a unit of symbol with
respect to the data supplied from the SISO/MISO encoder 119 and
supplies the data to a frame builder/resource allocation unit
131.
[1780] On the other hand, for example, control data (signalling)
for transfer control such as BB signaling (Base Band Signalling)
(BB Header) is supplied to the BCH encoder 121.
[1781] The BCH encoder 121 performs the BCH encoding with respect
to the signaling supplied thereto and supplies data obtained as a
result to an LDPC encoder 122, similar to the BCH encoder 114.
[1782] The LDPC encoder 122 sets the data supplied from the BCH
encoder 121 as LDPC target data, performs the LDPC encoding with
respect to the data, and supplies an LDPC code obtained as a result
to a mapper 123, similar to the LDPC encoder 115.
[1783] The mapper 123 maps the LDPC code supplied from the LDPC
encoder 122 to a signal point representing one symbol of orthogonal
modulation in a unit (symbol unit) of code bits of one or more bits
of the LDPC code, performs the orthogonal modulation, and supplies
data obtained as a result to the frequency interleaver 124, similar
to the mapper 117.
[1784] The frequency interleaver 124 performs the frequency
interleave in a unit of symbol with respect to the data supplied
from the mapper 123 and supplies the data to the frame
builder/resource allocation unit 131, similar to the frequency
interleaver 120.
[1785] The frame builder/resource allocation unit 131 inserts
symbols of pilots into necessary positions of the data (symbols)
supplied from the frequency interleavers 120 and 124, configures a
frame (for example, a physical layer (PL) frame, a T2 frame, a C2
frame, and so on) including symbols of a predetermined number from
data (symbols) obtained as a result, and supplies the frame to an
OFDM generating unit 132.
[1786] The OFDM generating unit 132 generates an OFDM signal
corresponding to the frame from the frame supplied from the frame
builder/resource allocation unit 131 and transmits the OFDM signal
through the communication path 13 (FIG. 7).
[1787] Here, for example, the transmitting device 11 can be
configured without including part of the blocks illustrated in FIG.
8 such as the time interleaver 118, the SISO/MISO encoder 119, the
frequency interleaver 120 and the frequency interleaver 124.
[1788] <Configuration Example of Bit Interleaver 116>
[1789] FIG. 9 illustrates a configuration example of the bit
interleaver 116 of FIG. 8.
[1790] The bit interleaver 116 has a function of interleaving data,
and includes a parity interleaver 23, a group-wise interleaver 24,
and a block interleaver 25.
[1791] The parity interleaver 23 performs parity interleave for
interleaving the parity bits of the LDPC code supplied from the
LDPC encoder 115 into positions of other parity bits and supplies
the LDPC code after the parity interleave to the group-wise
interleaver 24.
[1792] The group-wise interleaver 24 performs the group-wise
interleave with respect to the LDPC code supplied from the parity
interleaver 23 and supplies the LDPC code after the group-wise
interleave to the block interleaver 25.
[1793] Here, in the group-wise interleave, 360 bits of one segment
are used as a bit group, where the LDPC code of one code is divided
into segments in units of 360 bits equal to the unit size P which
will be described later, and the LDPC code supplied from the parity
interleaver 23 is interleaved in units of bit groups, starting from
the head.
[1794] When the group-wise interleave is performed, the error rate
can be improved to be better than when the group-wise interleave is
not performed, and as a result, it is possible to secure the
excellent communication quality in the data transmission.
[1795] The block interleaver 25 performs block interleave for
demultiplexing the LDPC code supplied from the group-wise
interleaver 24, converts, for example, the LDPC code corresponding
to one code into an m-bit symbol serving as a unit of mapping, and
supplies the m-bit symbol to the mapper 117 (FIG. 8).
[1796] Here, in the block interleave, for example, the LDPC code
corresponding to one code is converted into the m-bit symbol such
that the LDPC code supplied from the group-wise interleaver 24 is
written in a storage region in which columns serving as a storage
region storing a predetermined number of bits in a column
(vertical) direction are arranged in a row (horizontal) direction
by the number m of bits of the symbol in the column direction and
read from the storage region in the row direction.
[1797] <Parity Check Matrix H of the LDPC Code>
[1798] Next, FIG. 10 illustrates an example of the parity check
matrix H that is used for LDPC encoding by the LDPC encoder 115 of
FIG. 8.
[1799] The parity check matrix H becomes an LDGM (Low-Density
Generation Matrix) structure and can be represented by an
expression H=[H.sub.A|H.sub.T] (a matrix in which elements of the
information matrix H.sub.A are set to left elements and elements of
the parity matrix H.sub.T are set to right elements), using an
information matrix H.sub.A of a portion corresponding to
information bits among the code bits of the LDPC code and a parity
matrix H.sub.T corresponding to the parity bits.
[1800] In this case, a bit number of the information bits among the
code bits of one code of LDPC code (one code word) and a bit number
of the parity bits are referred to as an information length K and a
parity length M, respectively, and a bit number of the code bits of
one code (one code word) of LDPC code is referred to as a code
length N (=K+M).
[1801] The information length K and the parity length M of the LDPC
code having the certain code length N are determined by an encoding
rate. The parity check matrix H becomes a matrix in which
row.times.column is M.times.N (a matrix of M.times.N). The
information matrix H.sub.A becomes a matrix of M.times.K and the
parity matrix H.sub.T becomes a matrix of M.times.M.
[1802] FIG. 11 is an illustration of an example of the parity
matrix H.sub.T of the parity check matrix H used for LDPC encoding
in the LDPC encoder 115 of FIG. 8.
[1803] The parity matrix H.sub.T of the parity check matrix H used
for LDPC encoding in the LDPC encoder 115 is identical to, for
example, the parity matrix H.sub.T of the parity check matrix H of
the LDPC code specified in a standard such as DVB-T.2.
[1804] The parity matrix H.sub.T of the parity check matrix H of
the LDPC code that is defined in the standard of the DVB-T.2 or the
like becomes a staircase structure matrix (lower bidiagonal matrix)
in which elements of 1 are arranged in a staircase shape, as
illustrated in FIG. 11. The row weight of the parity matrix H.sub.T
becomes 1 with respect to the first row and becomes 2 with respect
to the remaining rows. The column weight becomes 1 with respect to
the final column and becomes 2 with respect to the remaining
columns.
[1805] As described above, the LDPC code of the parity check matrix
H in which the parity matrix H.sub.T becomes the staircase
structure can be easily generated using the parity check matrix
H.
[1806] That is, the LDPC code (one code word) is represented by a
row vector c and a column vector obtained by transposing the row
vector is represented by C.sup.T. In addition, a portion of
information bits of the row vector c to be the LDPC code is
represented by a row vector A and a portion of the parity bits is
represented by a row vector T.
[1807] The row vector c can be represented by an expression c=[A|T]
(a row vector in which elements of the row vector A are set to left
elements and elements of the row vector T are set to right
elements), using the row vector A corresponding to the information
bits and the row vector T corresponding to the parity bits.
[1808] In the parity check matrix H and the row vector c=[A|T]
corresponding to the LDPC code, it is necessary to satisfy an
expression Hc.sup.T=0. The row vector T that corresponds to the
parity bits constituting the row vector c=[A|T] satisfying the
expression Hc.sup.T=0 can be sequentially calculated by setting
elements of each row to 0, sequentially (in order) from elements of
a first row of the column vector Hc.sup.T in the expression
Hc.sup.T=0, when the parity matrix H.sub.T of the parity check
matrix H=[H.sub.A|H.sub.T] becomes the staircase structure
illustrated in FIG. 11.
[1809] FIG. 12 is an illustration of the parity check matrix H of
the LDPC code that is defined in the standard of the DVB-T.2 or the
like.
[1810] The column weight becomes X with respect KX columns from a
first column of the parity check matrix H of the LDPC code defined
in the standard of the DVB-T.2 or the like, becomes 3 with respect
to the following K3 columns, becomes 2 with respect to the
following (M-1) columns, and becomes 1 with respect to a final
column.
[1811] In this case, KX+K3+M-1+1 is equal to the code length N.
[1812] FIG. 13 is an illustration of column numbers KX, K3, and M
and a column weight X, with respect to each encoding rate r of the
LDPC code defined in the standard of the DVB-T.2 or the like.
[1813] In the standard of the DVB-T.2 or the like, LDPC codes that
have code lengths N of 64800 bits and 16200 bits are defined.
[1814] With respect to the LDPC code having the code length N of
64800 bits, 11 encoding rates (nominal rates) of 1/4, 1/3, 2/5,
1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined. With
respect to the LDPC code having the code length N of 16200 bits, 10
encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and
8/9 are defined.
[1815] Hereinafter, the code length N of the 64800 bits is referred
to as 64 kbits and the code length N of the 16200 is referred to as
16 kbits.
[1816] With respect to the LDPC code, an error rate tends to be
lower in a code bit corresponding to a column of which a column
weight of the parity check matrix H is large.
[1817] In the parity check matrix H that is illustrated in FIGS. 12
and 13 and is defined in the standard of the DVB-T.2 or the like, a
column weight of a column of a head side (left side) tends to be
large. Therefore, with respect to the LDPC code corresponding to
the parity check matrix H, a code bit of a head side tends to be
robust to error (there is tolerance against the error) and a code
bit of an ending side tends to be weak for the error.
[1818] <Parity Interleave>
[1819] Next, the parity interleave by the parity interleaver 23 of
FIG. 9 will be described with reference to FIGS. 14 to 16.
[1820] FIG. 24 illustrates an example of (a part of) a Tanner graph
of the parity check matrix of the LDPC code.
[1821] As illustrated in FIG. 14, if a plurality of, for example,
two variable nodes among (the code bits corresponding to) the
variable nodes connected to the check node simultaneously become
the error such as the erasure, the check node returns a message in
which the probability of a value being 0 and the probability of a
value being 1 are equal to each other, to all the variable nodes
connected to the check node. For this reason, if the plurality of
variable nodes connected to the same check node simultaneously
become the erasure, decoding performance is deteriorated.
[1822] Meanwhile, the LDPC code that is output by the LDPC encoder
115 of FIG. 8 is an IRA code, same as the LDPC code that is defined
in the standard of the DVB-T.2 or the like, and the parity matrix
H.sub.T of the parity check matrix H becomes a staircase structure,
as illustrated in FIG. 11.
[1823] FIG. 15 illustrates the parity matrix HT becoming the
staircase structure as illustrated in FIG. 11, and an example of a
Tanner graph corresponding to the parity matrix HT.
[1824] That is, A of FIG. 15 illustrates an example of the parity
matrix HT becoming the staircase structure and B of FIG. 15
illustrates the Tanner graph corresponding to the parity matrix HT
of A of FIG. 15.
[1825] In the parity matrix H.sub.T with a staircase structure,
elements of 1 are adjacent in each row (excluding the first row).
Therefore, in the Tanner graph of the parity matrix H.sub.T, two
adjacent variable nodes corresponding to a column of two adjacent
elements in which the value of the parity matrix H.sub.T is 1 are
connected with the same check node.
[1826] Therefore, when parity bits corresponding to two
above-mentioned adjacent variable nodes become errors at the same
time by burst error and erasure, and so on, the check node
connected with two variable nodes (variable nodes to find a message
by the use of parity bits) corresponding to those two parity bits
that became errors returns message that the probability with a
value of 0 and the probability with a value of 1 are equal
probability, to the variable nodes connected with the check node,
and therefore the performance of decoding is deteriorated. Further,
when the burst length (bit number of parity bits that continuously
become errors) becomes large, the number of check nodes that return
the message of equal probability increases and the performance of
decoding is further deteriorated.
[1827] Therefore, the parity interleaver 23 (FIG. 9) performs the
parity interleave for interleaving the parity bits of the LDPC code
from the LDPC encoder 115 into positions of other parity bits, to
prevent the decoding performance from being deteriorated.
[1828] FIG. 16 is an illustration of the parity matrix H.sub.T of
the parity check matrix H corresponding to the LDPC code that has
undergone the parity interleave performed by the parity interleaver
23 of FIG. 9.
[1829] Here, the information matrix H.sub.A of the parity check
matrix H corresponding to the LDPC code output by the LDPC encoder
115 has a cyclic structure, similarly to the information matrix of
the parity check matrix H corresponding to the LDPC code specified
in a standard such as DVB-T.2.
[1830] The cyclic structure refers to a structure in which a
certain column matches one obtained by cyclically shifting another
column, and includes, for example, a structure in which a position
of 1 of each row of P columns becomes a position obtained by
cyclically shifting a first column of the P columns in the column
direction by a predetermined value such as a value that is
proportional to a value q obtained by dividing a parity length M
for every P columns. Hereinafter, the P columns in the cyclic
structure are referred to appropriately as a unit size.
[1831] As an LDPC code defined in a standard such as DVB-T.2, as
described in FIG. 12 and FIG. 13, there are two kinds of LDPC codes
whose code length N is 64800 bits and 16200 bits, and, for both of
those two kinds of LDPC codes, the unit size P is defined as 360
which is one of divisors excluding 1 and M among the divisors of
the parity length M.
[1832] The parity length M becomes a value other than primes
represented by an expression M=q.times.P=q.times.360, using a value
q different according to the encoding rate. Therefore, similar to
the unit size P, the value q is one other than 1 and M among the
divisors of the parity length M and is obtained by dividing the
parity length M by the unit size P (the product of P and q to be
the divisors of the parity length M becomes the parity length
M).
[1833] As described above, when information length is assumed to be
K, an integer equal to or greater than 0 and less than P is assumed
to be x and an integer equal to or greater than 0 and less than q
is assumed to be y, the parity interleaver 23 interleaves the
K+qx+y+l-th code bit among code bits of an LDPC code of N bits to
the position of the K+Py+x+1-th code bit as parity interleave.
[1834] Since both of the K+qx+y+1-th code bit and the K+Py+x+1-th
code bit are code bits after the K+1-th one, they are parity bits,
and therefore the positions of the parity bits of the LDPC code are
moved according to the parity interleave.
[1835] According to the parity interleave, (the parity bits
corresponding to) the variable nodes connected to the same check
node are separated by the unit size P, that is, 360 bits in this
case. For this reason, when the burst length is less than 360 bits,
the plurality of variable nodes connected to the same check node
can be prevented from simultaneously becoming the error. As a
result, tolerance against the burst error can be improved.
[1836] The LDPC code after the interleave for interleaving the
(K+qx+y+1)-th code bit into the position of the (K+Py+x+1)-th code
bit is matched with an LDPC code of a parity check matrix
(hereinafter, referred to as a transformed parity check matrix)
obtained by performing column replacement for replacing the
(K+qx+y+1)-th column of the original parity check matrix H with the
(K+Py+x+1)-th column.
[1837] In the parity matrix of the transformed parity check matrix,
as illustrated in FIG. 16, a pseudo cyclic structure that uses the
P columns (in FIG. 16, 360 columns) as a unit appears.
[1838] Here, the pseudo cyclic structure is a structure in which
the remaining portion excluding a part has the cyclic
structure.
[1839] The transformed parity check matrix obtained by performing
the column permutation corresponding to the parity interleave on
the parity check matrix of the LDPC code specified in the standard
such as DVB-T.2 has the pseudo cyclic structure rather than the
(perfect) cyclic structure since it is one 1 element short (it is a
0 element) in a portion (a shift matrix which will be described
later) of a 360.times.360 matrix of a right top corner portion of
the transformed parity check matrix.
[1840] The transformed parity check matrix for the parity check
matrix of the LDPC code output by the LDPC encoder 115 has the
pseudo cyclic structure, for example, similarly to the transformed
parity check matrix for the parity check matrix of the LDPC code
specified in the standard such as DVB-T.2.
[1841] The transformed parity check matrix of FIG. 16 becomes a
matrix that is obtained by performing the column replacement
corresponding to the parity interleave and replacement (row
replacement) of a row to configure the transformed parity check
matrix with a constitutive matrix to be described later, with
respect to the original parity check matrix H.
[1842] FIG. 17 is a flowchart illustrating processing executed by
the LDPC encoder 115, the bit interleaver 116, and the mapper 117
of FIG. 8.
[1843] The LDPC encoder 115 awaits supply of the LDPC target data
from the BCH encoder 114. In step S101, the LDPC encoder 115
encodes the LDPC target data with the LDPC code and supplies the
LDPC code to the bit interleaver 116. The processing proceeds to
step S102.
[1844] In step S102, the bit interleaver 116 performs the bit
interleave on the LDPC code supplied from the LDPC encoder 115, and
supplies the symbol obtained by the bit interleave to the mapper
117, and the process proceeds to step S103.
[1845] That is, in step S102, in the bit interleaver 116 (FIG. 9),
the parity interleaver 23 performs parity interleave with respect
to the LDPC code supplied from the LDPC encoder 115 and supplies
the LDPC code after the parity interleave to the group-wise
interleaver 24.
[1846] The group-wise interleaver 24 performs the group-wise
interleave on the LDPC code supplied from the parity interleaver
23, and supplies the resulting LDPC code to the block interleaver
25.
[1847] The block interleaver 25 performs the block interleave on
the LDPC code that has undergone the group-wise interleave
performed by the group-wise interleaver 24, and supplies the m-bit
symbol obtained as a result to the mapper 117.
[1848] In step S103, the mapper 117 maps the symbol supplied from
the block interleaver 25 to any of the 2.sup.m signal points
decided in the modulation scheme of the orthogonal modulation
performed by the mapper 117, performs the orthogonal modulation,
and supplies data obtained as a result to the time interleaver
118.
[1849] As described above, by performing the parity interleave and
the group-wise interleave, it is possible to improve the error rate
when transmission is performed using a plurality of code bits of
the LDPC code as one symbol.
[1850] Here, in FIG. 9, for the sake of convenience of description,
the parity interleaver 23 serving as the block performing the
parity interleave and the group-wise interleaver 24 serving as the
block performing the group-wise interleave are configured
individually, but the parity interleaver 23 and the group-wise
interleaver 24 may be configured integrally.
[1851] That is, both the parity interleave and the group-wise
interleave can be performed by writing and reading of the code bits
with respect to the memory and can be represented by a matrix to
convert an address (write address) to perform writing of the code
bits into an address (read address) to perform reading of the code
bits.
[1852] Therefore, if a matrix obtained by multiplying a matrix
representing the parity interleave and a matrix representing the
group-wise interleave is calculated, the code bits are converted by
the matrixes, the parity interleave is performed, and a group-wise
interleave result of the LDPC code after the parity interleave can
be obtained.
[1853] In addition to the parity interleaver 23 and the group-wise
interleaver 24, the block interleaver 25 can be integrally
configured.
[1854] That is, the block interleave executed by the block
interleaver 25 can be represented by the matrix to convert the
write address of the memory storing the LDPC code into the read
address.
[1855] Therefore, if a matrix obtained by multiplying the matrix
representing the parity interleave, the matrix representing the
group-wise interleave, and the matrix representing the block
interleave is calculated, the parity interleave, the group-wise
interleave, and the block interleave can be collectively executed
by the matrixes.
[1856] <Configuration Example of LDPC Encoder 115>
[1857] FIG. 18 is a block diagram illustrating a configuration
example of the LDPC encoder 115 of FIG. 8.
[1858] The LDPC encoder 122 of FIG. 8 is also configured in the
same manner.
[1859] As described in FIGS. 12 and 13, in the standard of the
DVB-T.2 or the like, the LDPC codes that have the two code lengths
N of 64800 bits and 16200 bits are defined.
[1860] With respect to the LDPC code having the code length N of
64800 bits, 11 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4,
4/5, 5/6, 8/9, and 9/10 are defined. With respect to the LDPC code
having the code length N of 16200 bits, 10 encoding rates of 1/4,
1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (FIGS.
12 and 13).
[1861] For example, the LDPC encoder 115 can perform encoding
(error correction encoding) using the LDPC code of each encoding
rate having the code length N of 64800 bits or 16200 bits,
according to the parity check matrix H prepared for each code
length N and each encoding rate.
[1862] The LDPC encoder 115 includes an encoding processing unit
601 and a storage unit 602.
[1863] The encoding processing unit 601 includes an encoding rate
setting unit 611, an initial value table reading unit 612, a parity
check matrix generating unit 613, an information bit reading unit
614, an encoding parity operation unit 615, an a control unit 616.
The encoding processing unit 601 performs the LDPC encoding of LDPC
target data supplied to the LDPC encoder 115 and supplies an LDPC
code obtained as a result to the bit interleaver 116 (FIG. 8).
[1864] That is, the encoding rate setting unit 611 sets the code
length N and the encoding rate of the LDPC code, according to an
operation of an operator.
[1865] The initial value table reading unit 612 reads a parity
check matrix initial value table to be described later, which
corresponds to the code length N and the encoding rate set by the
encoding rate setting unit 611, from the storage unit 602.
[1866] The parity check matrix generating unit 613 generates a
parity check matrix H by arranging elements of 1 of an information
matrix H.sub.A corresponding to an information length K
(=information length N-parity length M) according to the code
length N and the encoding rate set by the encoding rate setting
unit 611 in the column direction with a period of 360 columns (unit
size P), on the basis of the parity check matrix initial value
table read by the initial value table reading unit 612, and stores
the parity check matrix H in the storage unit 602.
[1867] The information bit reading unit 614 reads (extracts)
information bits corresponding to the information length K, from
the LDPC target data supplied to the LDPC encoder 115.
[1868] The encoding parity operation unit 615 reads the parity
check matrix H generated by the parity check matrix generating unit
613 from the storage unit 602, and generates a code word (LDPC
code) by calculating parity bits for the information bits read by
the information bit reading unit 614 on the basis of a
predetermined expression using the parity check matrix H.
[1869] The control unit 616 controls each block constituting the
encoding processing unit 601.
[1870] In the storage unit 602, a plurality of parity check matrix
initial value tables that correspond to the plurality of encoding
rates illustrated in FIGS. 12 and 13, with respect to the code
lengths N such as the 64800 bits and 16200 bits, are stored. In
addition, the storage unit 602 temporarily stores data that is
necessary for processing of the encoding processing unit 601.
[1871] FIG. 19 is a flowchart illustrating an example of processing
of the LDPC encoder 115 of FIG. 18.
[1872] In step S201, the encoding rate setting unit 611 determines
(sets) the code length N and the encoding rate r to perform the
LDPC encoding.
[1873] In step S202, the initial value table reading unit 612 reads
the previously determined parity check matrix initial value table
corresponding to the code length N and the encoding rate r
determined by the encoding rate setting unit 611, from the storage
unit 602.
[1874] In step S203, the parity check matrix generating unit 613
calculates (generates) the parity check matrix H of the LDPC code
of the code length N and the encoding rate r determined by the
encoding rate setting unit 611, using the parity check matrix
initial value table read from the storage unit 602 by the initial
value table reading unit 612, supplies the parity check matrix to
the storage unit 602, and stores the parity check matrix in the
storage unit.
[1875] In step S204, the information bit reading unit 614 reads the
information bits of the information length K (=N.times.r)
corresponding to the code length N and the encoding rate r
determined by the encoding rate setting unit 611, from the LDPC
target data supplied to the LDPC encoder 115, reads the parity
check matrix H calculated by the parity check matrix generating
unit 613 from the storage unit 602, and supplies the information
bits and the parity check matrix to the encoding parity operation
unit 615.
[1876] In step S205, the encoding parity operation unit 615
sequentially operates parity bits of a code word c that satisfies
an expression (8) using the information bits and the parity check
matrix H that have been read from the information bit reading unit
614.
Hc.sup.T=0 (8)
[1877] In the expression (8), c represents a row vector as the code
word (LDPC code) and c.sup.T represents transposition of the row
vector c.
[1878] As described above, when a portion of the information bits
of the row vector c as the LDPC code (one code word) is represented
by a row vector A and a portion of the parity bits is represented
by a row vector T, the row vector c can be represented by an
expression c=[A/T], using the row vector A as the information bits
and the row vector T as the parity bits.
[1879] In the parity check matrix H and the row vector c=[A|T]
corresponding to the LDPC code, it is necessary to satisfy an
expression Hc.sup.T=0. The row vector T that corresponds to the
parity bits constituting the row vector c=[A|T] satisfying the
expression Hc.sup.T=0 can be sequentially calculated by setting
elements of each row to 0, sequentially from elements of a first
row of the column vector Hc.sup.T in the expression Hc.sup.T=0,
when the parity matrix H.sub.T of the parity check matrix
H=[H.sub.A|H.sub.T] becomes the staircase structure illustrated in
FIG. 11.
[1880] If the encoding parity operation unit 615 calculates the
parity bits T with respect to the information bits A from the
information bit reading unit 614, the encoding parity operation
unit 615 outputs the code word c=[A/T] represented by the
information bits A and the parity bits T as an LDPC encoding result
of the information bits A.
[1881] Then, in step S206, the control unit 616 determines whether
the LDPC encoding ends. When it is determined in step S206 that the
LDPC encoding does not end, that is, when there is LDPC target data
to perform the LDPC encoding, the processing returns to step S201
(or step S204). Hereinafter, the processing of steps S201 (or step
S204) to S206 is repeated.
[1882] When it is determined in step S206 that the LDPC encoding
ends, that is, there is no LDPC target data to perform the LDPC
encoding, the LDPC encoder 115 ends the processing.
[1883] As described above, the parity check matrix initial value
table corresponding to each code length N and each encoding rate r
is prepared and the LDPC encoder 115 performs the LDPC encoding of
the predetermined code length N and the predetermined encoding rate
r, using the parity check matrix H generated from the parity check
matrix initial value table corresponding to the predetermined code
length N and the predetermined encoding rate r.
[1884] <Example of the Parity Check Matrix Initial Value
Table>
[1885] The parity check matrix initial value table is a table that
represents positions of elements of 1 of the information matrix
H.sub.A (FIG. 10) of the parity check matrix H corresponding to the
information length K according to the code length N and the
encoding rate r of the LDPC code (LDPC code defined by the parity
check matrix H) for every 360 columns (unit size P) and is
previously made for each parity check matrix H of each code length
N and each encoding rate r.
[1886] That is, the parity check matrix initial value table
represents at least positions of elements of 1 of the information
matrix H.sub.A for every 360 columns (unit size P).
[1887] Examples of the parity check matrix H include a parity check
matrix in which the (whole) parity matrix H.sub.T has the staircase
structure, which is specified in DVB-T.2 or the like and a parity
check matrix in which a part of the parity matrix H.sub.T has the
staircase structure, and the remaining portion is a diagonal matrix
(a unit matrix), which is proposed by CRC/ETRI.
[1888] Hereinafter, an expression scheme of a parity check matrix
initial value table indicating the parity check matrix in which the
parity matrix H.sub.T has the staircase structure, which is
specified in DVB-T.2 or the like, is referred to as a DVB scheme,
and an expression scheme of a parity check matrix initial value
table indicating the parity check matrix proposed by CRC/ETRI is
referred to as an ETRI scheme.
[1889] FIG. 20 is an illustration of an example of the parity check
matrix initial value table in the DVB method.
[1890] That is, FIG. 20 illustrates a parity check matrix initial
value table with respect to the parity check matrix H that is
defined in the standard of the DVB-T.2 and has the code length N of
16200 bits and the encoding rate (an encoding rate of notation of
the DVB-T.2) r of 1/4.
[1891] The parity check matrix generating unit 613 (FIG. 18)
calculates the parity check matrix H using the parity check matrix
initial value table in the DVB method, as follows.
[1892] FIG. 21 is an illustration of a method of calculating a
parity check matrix H from a parity check matrix initial value
table in the DVB method.
[1893] That I, FIG. 21 illustrates a parity check matrix initial
value table with respect to the parity check matrix H that is
defined in the standard of the DVB-T.2 and has the code length N of
16200 bits and the encoding rate r of 2/3.
[1894] The parity check matrix initial value table in the DVB
method is the table that represents the positions of the elements
of 1 of the whole information matrix H.sub.A corresponding to the
information length K according to the code length N and the
encoding rate r of the LDPC code for every 360 columns (unit size
P). In the i-th row thereof, row numbers (row numbers when a row
number of a first row of the parity check matrix H is set to 0) of
elements of 1 of a (1+360.times.(i-1)-th column of the parity check
matrix H are arranged by a number of column weights of the
(1+360.times.(i-1)-th column.
[1895] Here, since the parity matrix H.sub.T (FIG. 10)
corresponding to the parity length M in the parity check matrix H
of the DVB scheme is fixed to the staircase structure illustrated
in FIG. 15, it is possible to obtain the parity check matrix H if
it is possible to obtain the information matrix H.sub.A (FIG. 10)
corresponding to the information length K through the parity check
matrix initial value table.
[1896] A row number k+1 of the parity check matrix initial value
table in the DVB method is different according to the information
length K.
[1897] A relation of an expression (9) is realized between the
information length K and the row number k+1 of the parity check
matrix initial value table.
K=(k+1).times.360 (9)
[1898] In this case, 360 of the expression (9) is the unit size P
described in FIG. 16.
[1899] In the parity check matrix initial value table of FIG. 21,
13 numerical values are arranged from the first row to the third
row and 3 numerical values are arranged from the fourth row to the
(k+1)-th row (in FIG. 21, the 30th row).
[1900] Therefore, the column weights of the parity check matrix H
that are calculated from the parity check matrix initial value
table of FIG. 21 are 13 from the first column to the
(1+360.times.(3-1)-1)-th column and are 3 from the
(1+360.times.(3-1))-th column to the K-th column.
[1901] The first row of the parity check matrix initial value table
of FIG. 21 becomes 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297,
2481, 3369, 3451, 4620, and 2622, which shows that elements of rows
having row numbers of 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297,
2481, 3369, 3451, 4620, and 2622 are 1 (and the other elements are
0), in the first column of the parity check matrix H.
[1902] The second row of the parity check matrix initial value
table of FIG. 21 becomes 1, 122, 1516, 3448, 2880, 1407, 1847,
3799, 3529, 373, 971, 4358, and 3108, which shows that elements of
rows having row numbers of 1, 122, 1516, 3448, 2880, 1407, 1847,
3799, 3529, 373, 971, 4358, and 3108 are 1, in the 361
(=1+360.times.(2-1))-th column of the parity check matrix H.
[1903] As described above, the parity check matrix initial value
table represents positions of elements of 1 of the information
matrix H.sub.A of the parity check matrix H for every 360
columns.
[1904] The columns other than the (1+360.times.(i-1))-th column of
the parity check matrix H, that is, the individual columns from the
(2+360.times.(i-1))-th column to the (360.times.i)-th column are
arranged by cyclically shifting elements of 1 of the
(1+360.times.(i-1))-th column determined by the parity check matrix
initial value table periodically in a downward direction (downward
direction of the columns) according to the parity length M.
[1905] That is, the (2+360.times.(i-1))-th column is obtained by
cyclically shifting (1+360.times.(i-1))-th column in the downward
direction by M/360 (=q) and the next (3+360.times.(i-1))-th column
is obtained by cyclically shifting (1+360.times.(i-1))-th column in
the downward direction by 2.times.M/360 (=2.times.q) (obtained by
cyclically shifting (2+360.times.(i-1))-th column in the downward
direction by M/360 (=q)).
[1906] If a numerical value of a j-th column (j-th column from the
left side) of an i-th row (i-th row from the upper side) of the
parity check matrix initial value table is represented as h.sub.i,j
and a row number of the j-th element of 1 of the w-th column of the
parity check matrix H is represented as H.sub.w-j, the row number
H.sub.w-j of the element of 1 of the w-th column to be a column
other than the (1+360.times.(i-1))-th column of the parity check
matrix H can be calculated by an expression (10).
H.sub.w-j=mod{h.sub.i,j+mod((w-1),P).times.q,M) (10)
[1907] In this case, mod(x, y) means a remainder that is obtained
by dividing x by y.
[1908] In addition, P is a unit size described above. In the
present embodiment, for example, same as the standard of the
DVB-S.2, the DVB-T.2, and the DVB-C.2, P is 360. In addition, q is
a value M/360 that is obtained by dividing the parity length M by
the unit size P (=360).
[1909] The parity check matrix generating unit 613 (FIG. 18)
specifies the row numbers of the elements of 1 of the
(1+360.times.(i-1))-th column of the parity check matrix H by the
parity check matrix initial value table.
[1910] The parity check matrix generating unit 613 (FIG. 18)
calculates the row number H.sub.w-j of the element of 1 of the w-th
column to be the column other than the (1+360.times.(i-1))-th
column of the parity check matrix H, according to the expression
(10), and generates the parity check matrix H in which the element
of the obtained row number is set to 1.
[1911] FIG. 22 is an illustration of a structure of the parity
check matrix of the ETRI scheme.
[1912] The parity check matrix of the ETRI scheme is configured
with an A matrix, a B matrix, a C matrix, a D matrix, and a Z
matrix.
[1913] The A matrix is a g.times.K upper left matrix of the parity
check matrix expressed by a predetermined value g and the
information length K of the LDPC code (=the code length N.times.the
encoding rate r).
[1914] The B matrix is a g.times.g matrix having the staircase
structure adjacent to the right of the A matrix.
[1915] The C matrix is an (N-K-g).times.(K+g) matrix adjacently
below the A matrix and the B matrix.
[1916] The D matrix is an (N-K-g).times.(N-K-g) unit matrix
adjacent to the right of the C matrix.
[1917] The Z matrix is a g.times.(N-K-g) zero matrix (zero matrix)
adjacent to the right of the B matrix.
[1918] In the parity check matrix of the ETRI scheme configured
with the A to D matrices and the Z matrix, the A matrix and a
portion of the C matrix configure an information matrix, and the B
matrix, the remaining portion of the C matrix, the D matrix, and
the Z matrix configure a parity matrix.
[1919] Further, since the B matrix is the matrix having the
staircase structure, and the D matrix is the unit matrix, a portion
(a portion of the B matrix) of the parity matrix of the parity
check matrix of the ETRI scheme has the staircase structure, and
the remaining portion (the portion of the D matrix) is the diagonal
matrix (the unit matrix).
[1920] Similarly to the information matrix of the parity check
matrix of the DVB scheme, the A matrix and the C matrix have the
cyclic structure for every 360 columns (the unit size P), and the
parity check matrix initial value table of the ETRI scheme
indicates positions of 1 elements of the A matrix and the C matrix
in units of 360 columns.
[1921] Here, as described above, since the A matrix, and a portion
of the C matrix configure the information matrix, it can be said
that the parity check matrix initial value table of the ETRI scheme
that indicates positions of 1 elements of the A matrix and the C
matrix in units of 360 columns indicates at least positions of 1
elements of the information matrix in units of 360 columns.
[1922] FIG. 23 is an illustration of an example of the parity check
matrix initial value table of the ETRI scheme.
[1923] In other words, FIG. 23 illustrates an example of a parity
check matrix initial value table for a parity check matrix in which
the code length N is 50 bits, and the encoding rate r is 1/2.
[1924] The parity check matrix initial value table of the ETRI
scheme is a table in which positions of 1 elements of the A matrix
and the C matrix are indicated for each unit size P, and row
numbers (row numbers when a row number of a first row of the parity
check matrix is 0) of 1 elements of a (1+P.times.(i-1))-th column
of the parity check matrix that correspond in number to the column
weight of the (1+P.times.(i-1))-th column are arranged in an i-th
row.
[1925] Here, in order to simplify the description, the unit size P
is assumed to be, for example, 5.
[1926] Further, parameters for the parity check matrix of the ETRI
scheme include g=M.sub.1, M.sub.2, Q.sub.1, and Q.sub.2.
[1927] g=M.sub.1 is a parameter for deciding the size of the B
matrix and has a value that is a multiple of the unit size P. The
performance of the LDPC code is changed by adjusting g=M.sub.1, and
g=M.sub.1 is adjusted to a predetermined value when the parity
check matrix is decided. Here, 15, which is three times the unit
size P (=5), is assumed to be employed as g=M.sub.1.
[1928] M.sub.2 has a value M-M.sub.1 obtained by subtracting
M.sub.1 from the parity length M.
[1929] Here, since the information length K is
N.times.r=50.times.1/2=25, and the parity length M is N-K=50-25=25,
M.sub.2 is M-M.sub.1=25-15=10.
[1930] Q.sub.1 is obtained from the formula Q.sub.1=M.sub.1/P, and
indicates the number of shifts (the number of rows) of the cyclic
shift in the A matrix.
[1931] In other words, in each column other than the
(1+P.times.(i-1))-th column of the A matrix of the parity check
matrix of the ETRI scheme, that is, in each of a
(2+P.times.(i-1))-th column to a (P.times.i)-th column, 1 elements
of a (1+360.times.(i-1))-th column decided by the parity check
matrix initial value table have periodically been cyclically
shifted downward (downward in the column) and arranged, and Q.sub.1
indicates the number of shifts the cyclic shift in the A
matrix.
[1932] Q.sub.2 is obtained from the formula Q.sub.2=M.sub.2/P, and
indicates the number of shifts (the number of rows) of the cyclic
shift in the C matrix.
[1933] In other words, in each column other than the
(1+P.times.(i-1))-th column of the C matrix of the parity check
matrix of the ETRI scheme, that is, in each of a
(2+P.times.(i-1))-th column to a (P.times.i)-th column, 1 elements
of a (1+360.times.(i-1))-th column decided by the parity check
matrix initial value table have periodically been cyclically
shifted downward (downward in the column) and arranged, and Q.sub.2
indicates the number of shifts the cyclic shift in the C
matrix.
[1934] Here, Q.sub.1 is M.sub.1/P=15/5=3, and Q.sub.2 is
M.sub.2/P=10/5=2.
[1935] In the parity check matrix initial value table of FIG. 23, 3
numerical values are arranged in 1st and 2nd rows, and one
numerical value is arranged in 3rd to 5th rows, and according to a
sequence of the numerical values, the column weight of the parity
check matrix obtained from the parity check matrix initial value
table of FIG. 23 is 3 in the 1st column to a (1+5.times.(2-1)-1)-th
column and 1 in a (1+5.times.(2-1))-th column to a 5th column.
[1936] In other words, 2, 6, and 18 are arranged in the 1st row of
the parity check matrix initial value table of FIG. 23, which
indicates that elements of rows having the row numbers of 2, 6, and
18 are 1 (and the other elements are 0) in the 1st column of the
parity check matrix.
[1937] Here, in this case, the A matrix is a 15.times.25
(g.times.K) matrix, the C matrix is a 10.times.40
((N-K-g).times.(K+g)) matrix, rows having the row numbers of 0 to
14 in the parity check matrix are rows of the A matrix, and rows
having the row numbers of 15 to 24 in the parity check matrix are
rows of the C matrix.
[1938] Thus, among the rows having the row numbers of 2, 6, and 18
(hereinafter referred to as rows #2, #6, and #18), the rows #2 and
#6 are the rows of the A matrix, and the row #18 is the row of the
C matrix.
[1939] 2, 10, and 19 are arranged in the 2nd row of the parity
check matrix initial value table of FIG. 23, which indicates that
elements of the rows #2, #10, and #19 are 1 in a 6
(=1+5.times.(2-1))-th column of the parity check matrix.
[1940] Here, in the 6 (=1+5.times.(2-1))-th column of the parity
check matrix, among the rows #2, #10, and #19, the rows #2 and #10
are the rows of the A matrix, and the row #19 is the row of the C
matrix.
[1941] 22 is arranged in the 3rd row of the parity check matrix
initial value table of FIG. 23, which indicates that an element of
the row #22 is 1 in an 11 (=1+5.times.(3-1))-th column of the
parity check matrix.
[1942] Here, in the 11 (=1+5.times.(3-1))-th column of the parity
check matrix, the row #22 is the row of the C matrix.
[1943] Similarly, 19 in the 4th column of the parity check matrix
initial value table of FIG. 23 indicates that an element of the row
#19 is 1 in a 16 (=1+5.times.(4-1))-th column of the parity check
matrix, and 15 in the 5th row of the parity check matrix initial
value table of FIG. 23 indicates that an element of the row #15 is
1 in a 21(=1+5.times.(5-1))-st column of the parity check
matrix.
[1944] As described above, the parity check matrix initial value
table indicates the positions of the 1 elements of the A matrix and
the C matrix of the parity check matrix for each unit size P (=5
columns).
[1945] In each column other than a (1+5 (i-1))-th column of the A
matrix and the C matrix of the parity check matrix, that is, in
each of a (2+5.times.(i-1))-th column to a (5.times.i)-th column,
the 1 elements of the (1+5.times.(i-1))-th column decided by the
parity check matrix initial value table have periodically been
cyclically shifted downward (downward in the column) and arranged
according to the parameters Q.sub.1 and Q.sub.2.
[1946] In other words, for example, in the (2+5.times.(i-1))-th
column of the A matrix, the (1+5.times.(i-1))-th column has been
cyclically shifted downward by Q.sub.1 (=3), and in a
(3+5.times.(i-1))-th column, the (1+5.times.(i-1))-th column has
been cyclically shifted downward by 2.times.Q.sub.1 (=2.times.3)
(the (2+5.times.(i-1))-th column has been cyclically shifted
downward by Q.sub.1).
[1947] Further, for example, in the (2+5.times.(i-1))-th column of
the C matrix, the (1+5.times.(i-1))-th column has been cyclically
shifted downward by Q.sub.2 (=2), and in a (3+5.times.(i-1))-th
column, the (1+5.times.(i-1))-th column has been cyclically shifted
downward by 2.times.Q.sub.2 (=2.times.2) (the (2+5.times.(i-1))-th
column has been cyclically shifted downward by Q.sub.2).
[1948] FIG. 24 is an illustration of the A matrix generated from
the parity check matrix initial value table of FIG. 23.
[1949] In the A matrix of FIG. 24, according to the 1st row of the
parity check matrix initial value table of FIG. 23, elements of
rows #2 and #6 of a 1 (=1+5.times.(1-1))-st column are 1.
[1950] Further, in each of a 2 (=2+5.times.(1-1))-nd column to a 5
(=5+5.times.(1-1))-th column, an immediately previous column has
been cyclically shifted downward by Q.sub.1=3.
[1951] Further, in the A matrix of FIG. 24, according to the 2nd
row of the parity check matrix initial value table of FIG. 23,
elements of rows #2 and #10 of a 6 (=1+5.times.(2-1))-th column are
1.
[1952] Further, in each of a 7 (=2+5.times.(2-1))-th column to a 10
(=5+5.times.(2-1))-th column, an immediately previous column has
been cyclically shifted downward by Q.sub.1=3.
[1953] FIG. 25 is an illustration of the parity interleave of the B
matrix.
[1954] The parity check matrix generating unit 613 (FIG. 18)
generates the A matrix using the parity check matrix initial value
table, and arranges the B matrix having the staircase structure at
the right of the A matrix. Further, the parity check matrix
generating unit 613 regards the B matrix as the parity matrix, and
performs the parity interleave so that the adjacent 1 elements of
the B matrix having the staircase structure are away from each
other in the row direction by the unit size P=5.
[1955] FIG. 25 illustrates the A matrix and the B matrix after the
B matrix has undergone the parity interleave.
[1956] FIG. 26 is an illustration of the C matrix generated from
the parity check matrix initial value table of FIG. 23.
[1957] In the C matrix of FIG. 26, according to the 1st row of the
parity check matrix initial value table of FIG. 23, element of a
row #18 of a 1 (=1+5.times.(1-1))-st column of the parity check
matrix is 1.
[1958] Further, each of a 2 (=2+5.times.(1-1))-nd column to a 5
(=5+5.times.(1-1))-th column is one in which an immediately
previous column has been cyclically shifted downward by
Q.sub.2=2.
[1959] Further, in the C matrix of FIG. 26, according to the 2nd to
5th columns of the parity check matrix initial value table of FIG.
23, elements of a row #19 of a 6 (=1+5.times.(2-1))-th column of
the parity check matrix, a row #22 of an 11 (=1+5.times.(3-1))-th
column, a row #19 of a 16 (=1+5.times.(4-1))-th column, and a row
#15 of a 21 (=1+5.times.(5-1))-th column are 1.
[1960] Further, in each of the 7 (=2+5.times.(2-1))-th column to
the 10 (=5+5.times.(2-1))-th column, each of a 12
(=2+5.times.(3-1))-th column to a 15 (=5+5.times.(3-1))-th column,
each of a 17 (=2+5.times.(4-1))-th column to a 20
(=5+5.times.(4-1))-th column, and each of a 22
(=2+5.times.(5-1))-nd column to a 25 (=5+5.times.(5-1))-th column,
an immediately previous column has been cyclically shifted downward
by Q.sub.2=2.
[1961] The parity check matrix generating unit 613 (FIG. 18)
generates the C matrix using the parity check matrix initial value
table, and arranges the C matrix below the A matrix and the B
matrix (that has undergone the parity interleave).
[1962] Further, the parity check matrix generating unit 613
arranges the Z matrix at the right of the B matrix, arranges the D
matrix at the right of the C matrix, and generates the parity check
matrix illustrated in FIG. 26.
[1963] FIG. 27 is an illustration of the parity interleave of the D
matrix.
[1964] After generating the parity check matrix of FIG. 26, the
parity check matrix generating unit 613 regards the D matrix as the
parity matrix, and performs the parity interleave (only for the D
matrix) so that the 1 elements of the odd-numbered rows and the
next even-numbered rows of the D matrix of the unit matrix are away
from each other in the row direction by the unit size P (=5).
[1965] FIG. 27 illustrates the parity check matrix after the parity
interleave of the D matrix is performed on the parity check matrix
of FIG. 26.
[1966] (The encoding parity operation unit 615 (FIG. 18) of) The
LDPC encoder 115 performs LDPC encoding (generation of the LDPC
code), for example, using the parity check matrix of FIG. 27.
[1967] Here, the LDPC code generated using the parity check matrix
of FIG. 27 is the LDPC code that has undergone the parity
interleave, and thus it is unnecessary to perform the parity
interleave on the LDPC code generated using the parity check matrix
of FIG. 27 in the parity interleaver 23 (FIG. 9).
[1968] FIG. 28 is an illustration of the parity check matrix
obtained by performing the column permutation serving as the parity
deinterleave for restoring the parity interleave to an original
state on the B matrix, the portion of the C matrix (the portion of
the C matrix arranged below the B matrix), and the D matrix of the
parity check matrix of FIG. 27.
[1969] The LDPC encoder 115 can perform LDPC encoding (generation
of the LDPC code) using the parity check matrix of FIG. 28.
[1970] When the LDPC encoding is performed using the parity check
matrix of FIG. 28, the LDPC code that does not undergo the parity
interleave is obtained according to the LDPC encoding. Thus, when
the LDPC encoding is performed using the parity check matrix of
FIG. 28, the parity interleaver 23 (FIG. 9) performs the parity
interleave.
[1971] FIG. 29 is an illustration of the transformed parity check
matrix obtained by performing the row permutation on the parity
check matrix of FIG. 27.
[1972] As will be described later, the transformed parity check
matrix is a matrix represented by a combination of a P.times.P unit
matrix, a quasi unit matrix obtained by setting one or more is of
the unit matrix to zero (0), a shift matrix obtained by cyclically
shifting the unit matrix or the quasi unit matrix, a sum matrix
serving as a sum of two or more matrices of the unit matrix, the
quasi unit matrix, and the shifted matrix, and a P.times.P zero
matrix.
[1973] As the transformed parity check matrix is used for decoding
of the LDPC code, an architecture of performing P check node
operations and P variable node operations at the same time can be
employed for decoding the LDPC code as will be described later.
[1974] <New LDPC Code>
[1975] Incidentally, a terrestrial digital television broadcasting
standard called ATSC 3.0 is currently pending.
[1976] In this regard, a novel LDPC code which can be used in ATSC
3.0 and other data transmission (hereinafter referred to as a new
LDPC code) will be described.
[1977] For example, the LDPC code of the DVB scheme or the LDPC
code of the ETRI scheme having the unit size P of 360, similarly to
DVB-T.2 or the like, and corresponding to the parity check matrix
having the cyclic structure can be employed as the new LDPC
code.
[1978] The LDPC encoder 115 (FIGS. 8 and 18) can perform LDPC
encoding for generating a new LDPC code using the parity check
matrix obtained from the parity check matrix initial value table of
the new LDPC code in which the code length N is 16 kbits or 64
kbits, and the encoding rate r is any of 5/15, 6, 15, 7/15, 8/15,
9/15, 10/15, 11/15, 12/15, and 13/15.
[1979] In this case, the storage unit 602 of the LDPC encoder 115
(FIG. 8) stores the parity check matrix initial value of the new
LDPC code.
[1980] FIG. 30 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 8/15 (hereinafter, also referred to as
Sony symbol (16 k, 8/15)), proposed by the applicant of the present
application.
[1981] FIG. 31 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 10/15 (hereinafter, also referred to as
Sony symbol (16 k, 10/15)), proposed by the applicant of the
present application.
[1982] FIG. 32 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 12/15 (hereinafter, also referred to as
Sony symbol (16 k, 12/15)), proposed by the applicant of the
present application.
[1983] FIGS. 33, 34, and 35 are illustrations of an example of a
parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 7/15 (hereinafter, also
referred to as Sony symbol (64 k, 7/15)), proposed by the applicant
of the present application.
[1984] FIG. 34 is an illustration subsequent to FIG. 33, and FIG.
35 is an illustration subsequent to FIG. 34.
[1985] FIGS. 36, 37, and 38 are illustrations of an example of a
parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 9/15 (hereinafter, also
referred to as Sony symbol (64 k, 9/15)), proposed by the applicant
of the present application.
[1986] FIG. 37 is an illustration subsequent to FIG. 36, and FIG.
38 is an illustration subsequent to FIG. 37.
[1987] FIGS. 39, 40, 41, and 42 are illustrations of an example of
a parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 11/15 (hereinafter, also
referred to as Sony symbol (64 k, 11/15)), proposed by the
applicant of the present application.
[1988] FIG. 40 is an illustration subsequent to FIG. 39, and FIG.
41 is an illustration subsequent to FIG. 40.
[1989] FIGS. 43, 44, 45, and 46 are illustrations of an example of
a parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 13/15 (hereinafter, also
referred to as Sony symbol (64 k, 13/15)), proposed by the
applicant of the present application.
[1990] FIG. 44 is an illustration subsequent to FIG. 43, and FIG.
45 is an illustration subsequent to FIG. 44.
[1991] FIGS. 47 and 48 are illustrations of an example of a parity
check matrix initial value table of the DVB scheme for a parity
check matrix of a new LDPC code in which the code length N is 64
kbits, and the encoding rate r is 6/15 (hereinafter, also referred
to as Samsung symbol (64 k, 6/15)), proposed by Samsung.
[1992] FIG. 48 is an illustration subsequent to FIG. 47.
[1993] FIGS. 49, 50, and 51 are illustrations of an example of a
parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 8/15 (hereinafter, also
referred to as Samsung symbol (64 k, 8/15)), proposed by
Samsung.
[1994] FIG. 50 is an illustration subsequent to FIG. 49, and FIG.
51 is an illustration subsequent to FIG. 50.
[1995] FIGS. 52, 53, and 54 are illustrations of an example of a
parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 12/15 (hereinafter, also
referred to as Samsung symbol (64 k, 12/15)), proposed by
Samsung.
[1996] FIG. 53 is an illustration subsequent to FIG. 52, and FIG.
54 is an illustration subsequent to FIG. 53.
[1997] FIG. 55 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 6/15 (hereinafter, also referred to as
LGE symbol (16 k, 6/15)), proposed by LG Electronics Inc.
[1998] FIG. 56 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 7/15 (hereinafter, also referred to as
LGE symbol (16 k, 7/15)), proposed by LG Electronics Inc.
[1999] FIG. 57 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 9/15 (hereinafter, also referred to as
LGE symbol (16 k, 9/15)), proposed by LG Electronics Inc.
[2000] FIG. 58 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 11/15 (hereinafter, also referred to as
LGE symbol (16 k, 11/15)), proposed by LG Electronics Inc.
[2001] FIG. 59 is an illustration of an example of a parity check
matrix initial value table of the DVB scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 13/15 (hereinafter, also referred to as
LGE symbol (16 k, 13/15)), proposed by LG Electronics Inc
[2002] FIGS. 60, 61, and 62 are an illustrations of an example of a
parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 10/15 (hereinafter, also
referred to as LGE symbol (64 k, 10/15)), proposed by LG
Electronics Inc.
[2003] FIG. 61 is an illustration subsequent to FIG. 60, and FIG.
62 is an illustration subsequent to FIG. 61.
[2004] FIGS. 63, 64, and 65 are illustrations of an example of a
parity check matrix initial value table of the DVB scheme for a
parity check matrix of a new LDPC code in which the code length N
is 64 kbits, and the encoding rate r is 9/15 (hereinafter, also
referred to as NERC symbol (64 k, 9/15)), proposed by NERC.
[2005] FIG. 64 is an illustration subsequent to FIG. 63, and FIG.
65 is an illustration subsequent to FIG. 64.
[2006] FIG. 66 is an illustration of an example of a parity check
matrix initial value table of the ETRI scheme for a parity check
matrix of a new LDPC code in which the code length N is 16 kbits,
and the encoding rate r is 5/15 (hereinafter, also referred to as
ETRI symbol (16 k, 5/15)), proposed by CRC/ETRI.
[2007] FIGS. 67 and 68 are illustrations of an example of a parity
check matrix initial value table of the ETRI scheme for a parity
check matrix of a new LDPC code in which the code length N is 64
kbits, and the encoding rate r is 5/15 (hereinafter, also referred
to as ETRI symbol (64 k, 5/15)), proposed by CRC/ETRI.
[2008] FIG. 68 is an illustration subsequent to FIG. 67.
[2009] FIGS. 69 and 70 are illustrations of an example of a parity
check matrix initial value table of the ETRI scheme for a parity
check matrix of a new LDPC code in which the code length N is 64
kbits, and the encoding rate r is 6/15 (hereinafter, also referred
to as ETRI symbol (64 k, 6/15)), proposed by CRC/ETRI.
[2010] FIG. 70 is an illustration subsequent to FIG. 69.
[2011] FIGS. 71 and 72 are illustrations of an example of a parity
check matrix initial value table of the ETRI scheme for a parity
check matrix of a new LDPC code in which the code length N is 64
kbits, and the encoding rate r is 7/15 (hereinafter, also referred
to as ETRI symbol (64 k, 7/15)), proposed by CRC/ETRI.
[2012] FIG. 72 is an illustration subsequent to FIG. 71.
[2013] Among the new LDPC codes, the Sony symbol is an LDPC code
having particularly excellent performance.
[2014] Here, the LDPC code of good performance is an LDPC code
obtained from an appropriate parity check matrix H.
[2015] The appropriate parity check matrix H is, for example, a
parity check matrix that satisfies a predetermined condition to
make BER (and FER) smaller when an LDPC code obtained from the
parity check matrix H is transmitted at low E.sub.s/N.sub.0 or
E.sub.b/N.sub.o (signal-to-noise power ratio per bit).
[2016] For example, the appropriate parity check matrix H can be
found by performing simulation to measure BER when LDPC codes
obtained from various parity check matrices that satisfy a
predetermined condition are transmitted at low E.sub.s/N.sub.o.
[2017] As a predetermined condition to be satisfied by the
appropriate parity check matrix H, for example, an analysis result
obtained by a code performance analysis method called density
evolution (Density Evolution) is excellent, and a loop of elements
of 1 does not exist, which is called cycle 4, and so on.
[2018] Here, in the information matrix H.sub.A, it is known that
the decoding performance of LDPC code is deteriorated when elements
of 1 are dense like cycle 4, and therefore it is requested that
cycle 4 does not exist, as a predetermined condition to be
satisfied by the appropriate parity check matrix H.
[2019] Here, the predetermined condition to be satisfied by the
appropriate parity check matrix H can be arbitrarily determined
from the viewpoint of the improvement in the decoding performance
of LDPC code and the facilitation (simplification) of decoding
processing of LDPC code, and so on.
[2020] FIG. 73 and FIG. 74 are diagrams to describe the density
evolution that can obtain an analytical result as a predetermined
condition to be satisfied by the appropriate parity check matrix
H.
[2021] The density evolution is a code analysis method that
calculates the expectation value of the error probability of the
entire LDPC code (ensemble) with a code length N of .infin.
characterized by a degree sequence described later.
[2022] For example, when the dispersion value of noise is gradually
increased from 0 on the AWGN channel, the expectation value of the
error probability of a certain ensemble is 0 first, but, when the
dispersion value of noise becomes equal to or greater than a
certain threshold, it is not 0.
[2023] According to the density evolution, by comparison of the
threshold of the dispersion value of noise (which may also be
called a performance threshold) in which the expectation value of
the error probability is not 0, it is possible to decide the
quality of ensemble performance (appropriateness of the parity
check matrix).
[2024] Here, as for a specific LDPC code, when an ensemble to which
the LDPC code belongs is decided and density evolution is performed
for the ensemble, rough performance of the LDPC code can be
expected.
[2025] Therefore, if an ensemble of good performance is found, an
LDPC code of good performance can be found from LDPC codes
belonging to the ensemble.
[2026] Here, the above-mentioned degree sequence shows at what
percentage a variable node or check node having the weight of each
value exists with respect to the code length N of an LDPC code.
[2027] For example, a regular (3,6) LDPC code with an encoding rate
of 1/2 belongs to an ensemble characterized by a degree sequence in
which the weight (column weight) of all variable nodes is 3 and the
weight (row weight) of all check nodes is 6.
[2028] FIG. 73 illustrates a Tanner graph of such an ensemble.
[2029] In the Tanner graph of FIG. 73, there are variable nodes
shown by circles (sign O) in the diagram only by N pieces equal to
the code length N, and there are check nodes shown by quadrangles
(sign .quadrature.) only by N/2 pieces equal to a multiplication
value multiplying encoding rate 1/2 by the code length N.
[2030] Three branches (edge) equal to the column weight are
connected with each variable node, and therefore there are totally
3N branches connected with N variable nodes.
[2031] Moreover, six branches (edge) equal to the row weight are
connected with each check node, and therefore there are totally 3N
branches connected with N/2 check nodes.
[2032] In addition, there is one interleaver in the Tanner graph in
FIG. 73.
[2033] The interleaver randomly rearranges 3N branches connected
with N variable nodes and connects each rearranged branch with any
of 3N branches connected with N/2 check nodes.
[2034] There are (3N)! (=(3N).times.(3N-1).times. . . . .times.1)
rearrangement patterns to rearrange 3N branches connected with N
variable nodes in the interleaver. Therefore, an ensemble
characterized by the degree sequence in which the weight of all
variable nodes is 3 and the weight of all check nodes is 6, becomes
aggregation of (3N)! LDPC codes.
[2035] In simulation to find an LDPC code of good performance
(appropriate parity check matrix), an ensemble of a multi-edge type
is used in the density evolution.
[2036] In the multi edge type, an interleaver through which the
branches connected with the variable nodes and the branches
connected with the check nodes pass, is divided into plural (multi
edge), and, by this means, the ensemble is characterized more
strictly.
[2037] FIG. 74 illustrates an example of a Tanner graph of an
ensemble of the multi-edge type.
[2038] In the Tanner graph of FIG. 74, there are two interleavers
of the first interleaver and the second interleaver.
[2039] Moreover, in the Tanner graph chart of FIG. 74, v1 variable
nodes with one branch connected with the first interleaver and no
branch connected with the second interleaver exist, v2 variable
nodes with one branch connected with the first interleaver and two
branches connected with the second interleaver exist, and v3
variable nodes with no branch connected with the first interleaver
and two branches connected with the second interleaver exist,
respectively.
[2040] Furthermore, in the Tanner graph chart of FIG. 74, c1 check
nodes with two branches connected with the first interleaver and no
branch connected with the second interleaver exist, c2 check nodes
with two branches connected with the first interleaver and two
branches connected with the second interleaver exist, and c3 check
nodes with no branch connected with the first interleaver and three
branches connected with the second interleaver exist,
respectively.
[2041] Here, for example, the density evolution and the mounting
thereof are described in "On the Design of Low-Density Parity-Check
Codes within 0.0045 dB of the Shannon Limit", S. Y. Chung, G. D.
Forney, T. J. Richardson, R. Urbanke, IEEE Communications Leggers,
VOL. 5, NO. 2, February 2001.
[2042] In simulation to find (a parity check matrix initial value
table of) a Sony code, by the density evaluation of the multi-edge
type, an ensemble in which a performance threshold that is
E.sub.b/N.sub.0 (signal-to-noise power ratio per bit) with
deteriorating (decreasing) BER is equal to or less than a
predetermined value is found, and an LDPC code that decreases BER
in a case using one or more orthogonal modulations such as QPSK is
selected from LDPC codes belonging to the ensemble as an LDPC code
of good performance.
[2043] The parity check matrix initial value table of the Sony code
is found from the above-mentioned simulation.
[2044] Thus, according to the Sony symbol obtained from the parity
check matrix initial value table, it is possible to secure the
excellent communication quality in the data transmission.
[2045] FIG. 75 is an illustration of parity check matrices H
(hereinafter, also referred to as "parity check matrices H of Sony
symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15)") obtained
from the parity check matrix initial value table of the Sony
symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15).
[2046] Every minimum cycle length of the parity check matrices H of
the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) has
a value exceeding cycle 4, and thus there is no cycle 4 (a loop of
1 elements in which a loop length is 4). Here, the minimum cycle
length (girth) is a minimum value of a length (a loop length) of a
loop configured with 1 elements in the parity check matrix H.
[2047] A performance threshold value of the Sony symbol (16 k,
8/15) is set to 0.805765, a performance threshold value of the Sony
symbol (16 k, 10/15) is set to 2.471011, and a performance
threshold value of the Sony symbol (16 k, 12/15) is set to
4.269922.
[2048] The column weight is set to X1 for KX1 columns of the parity
check matrices H of the Sony symbols (16 k, 8/15), (16 k, 10/15),
and (16 k, 12/15) starting from the 1st column, the column weight
is set to X2 for KX2 columns subsequent thereto, the column weight
is set to Y1 for KY1 columns subsequent thereto, the column weight
is set to Y2 for KY2 columns subsequent thereto, the column weight
is set to 2 for M-1 columns subsequent thereto, and the column
weight is set to 1 for the last column.
[2049] Here, KX1+KX2+KY1+KY2+M-1+1 is equal to the code length N
(=16200 bits) of the Sony symbols (16 k, 8/15), (16 k, 10/15), and
(16 k, 12/15).
[2050] In the parity check matrices H of the Sony symbols (16 k,
8/15), (16 k, 10/15), and (16 k, 12/15), the numbers KX1, KX2, KY1,
KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set
as illustrated in FIG. 75.
[2051] In the parity check matrices H of the Sony symbols (16 k,
8/15), (16 k, 10/15), and (16 k, 12/15), similarly to the parity
check matrix described above with reference to FIGS. 12 and 13,
columns closer to the head side (the left side) have higher column
weights, and thus a code bit at the head of the Sony symbol tends
to be robust to error (have error tolerance).
[2052] According to the simulation conducted by the applicant of
the present application, an excellent BER/FER is obtained for the
Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), and
thus it is possible to secure the excellent communication quality
in the data transmission using the Sony symbols (16 k, 8/15), (16
k, 10/15), and (16 k, 12/15).
[2053] FIG. 76 is an illustration of parity check matrices H of the
Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k,
13/15).
[2054] Every minimum cycle length of the parity check matrices H of
the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64
k, 13/15) has a value exceeding a cycle 4, and thus there is no
cycle 4.
[2055] A performance threshold value of the Sony symbol (64 k,
7/15) is set to -0.093751, a performance threshold value of the
Sony symbol (64 k, 9/15) is set to 1.658523, a performance
threshold value of the Sony symbol (64 k, 11/15) is set to
3.351930, and a performance threshold value of the Sony symbol (64
k, 13/15) is set to 5.301749.
[2056] The column weight is set to X1 for KX1 columns of the parity
check matrices H of the Sony symbols (64 k, 7/15), (64 k, 9/15),
(64 k, 11/15), and (64 k, 13/15) starting from the 1st column, the
column weight is set to X2 for KX2 columns subsequent thereto, the
column weight is set to Y1 for KY1 columns subsequent thereto, the
column weight is set to Y2 for KY2 columns subsequent thereto, the
column weight is set to 2 for M-1 columns subsequent thereto, and
the column weight is set to 1 for the last column.
[2057] Here, KX1+KX2+KY1+KY2+M-1+1 is equal to the code length N
(=64800 bits) of the Sony symbols (64 k, 7/15), (64 k, 9/15), (64
k, 11/15), and (64 k, 13/15).
[2058] In the parity check matrices H of the Sony symbols (64 k,
7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), the numbers
KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1,
and Y2 are set as illustrated in FIG. 76.
[2059] In the parity check matrices H of the Sony symbols (64 k,
7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), similarly to
the parity check matrix described above with reference to FIGS. 12
and 13, columns closer to the head side (the left side) have higher
column weights, and thus a code bit at the head of the Sony symbol
tends to be robust to error (have error tolerance).
[2060] According to the simulation conducted by the applicant of
the present application, an excellent BER/FER is obtained for the
Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k,
13/15), and thus it is possible to secure the excellent
communication quality in the data transmission using the Sony
symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k,
13/15).
[2061] FIG. 77 is an illustration of parity check matrices H of
Samsung symbols (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15).
[2062] The column weight is set to X1 for KX1 columns of the parity
check matrices H of the Samsung symbols (64 k, 6/15), (64 k, 8/15),
and (64 k, 12/15) starting from the 1st column, the column weight
is set to X2 for KX2 columns subsequent thereto, the column weight
is set to Y1 for KY1 columns subsequent thereto, the column weight
is set to Y2 for KY2 columns subsequent thereto, the column weight
is set to 2 for M-1 columns subsequent thereto, and the column
weight is set to 1 for the last column.
[2063] Here, KX1+KX2+KY1+KY2+M-1+1 is equal to the code length N
(=64800 bits) of the Samsung symbols (64 k, 6/15), (64 k, 8/15),
and (64 k, 12/15)
[2064] In the parity check matrices H of the Samsung symbols (64 k,
6/15), (64 k, 8/15), and (64 k, 12/15), the numbers KX1, KX2, KY1,
KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set
as illustrated in FIG. 77.
[2065] FIG. 78 is an illustration of parity check matrices H of the
LGE symbols (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k,
11/15), and (16 k, 13/15).
[2066] The column weight is set to X1 for KX1 columns of the parity
check matrices H of the LGE symbols (16 k, 6/15), (16 k, 7/15), (16
k, 9/15), (16 k, 11/15), and (16 k, 13/15) starting from the 1st
column, the column weight is set to X2 for KX2 columns subsequent
thereto, the column weight is set to Y1 for KY1 columns subsequent
thereto, the column weight is set to Y2 for KY2 columns subsequent
thereto, the column weight is set to 2 for M-1 columns subsequent
thereto, and the column weight is set to 1 for the last column.
[2067] Here, KX1+KX2+KY1+KY2+M-1+1 is equal to the code length N
(=16200 bits) of the LGE symbols (16 k, 6/15), (16 k, 7/15), (16 k,
9/15), (16 k, 11/15), and (16 k, 13/15).
[2068] In the parity check matrices H of the LGE symbols (16 k,
6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k,
13/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column
weights X1, X2, Y1, and Y2 are set as illustrated in FIG. 78.
[2069] FIG. 79 is an illustration of parity check matrices H of the
LGE symbols (64 k, 10/15).
[2070] The column weight is set to X1 for KX1 columns of the parity
check matrices H of the LGE symbols (64 k, 10/15) starting from the
1st column, the column weight is set to X2 for KX2 columns
subsequent thereto, the column weight is set to Y1 for KY1 columns
subsequent thereto, the column weight is set to Y2 for KY2 columns
subsequent thereto, the column weight is set to 2 for M-1 columns
subsequent thereto, and the column weight is set to 1 for the last
column.
[2071] Here, KX1+KX2+KY1+KY2+M-1+1 is equal to the code length N
(=64800 bits) of the LGE symbols (64 k, 10/15).
[2072] In the parity check matrices H of the LGE symbols (64 k,
10/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column
weights X1, X2, Y1, and Y2 are set as illustrated in FIG. 79.
[2073] FIG. 80 is an illustration of parity check matrices H of the
NERC symbols (64 k, 9/15).
[2074] The column weight is set to X1 for KX1 columns of the parity
check matrices H of the NERC symbols (64 k, 9/15) starting from the
1st column, the column weight is set to X2 for KX2 columns
subsequent thereto, the column weight is set to Y1 for KY1 columns
subsequent thereto, the column weight is set to Y2 for KY2 columns
subsequent thereto, the column weight is set to 2 for M-1 columns
subsequent thereto, and the column weight is set to 1 for the last
column.
[2075] Here, KX1+KX2+KY1+KY2+M-1+1 is equal to the code length N
(=64800 bits) of the NERC symbols (64 k, 9/15).
[2076] In the parity check matrices H of the NERC symbol s (64 k,
9/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column
weights X1, X2, Y1, and Y2 are set as illustrated in FIG. 80.
[2077] FIG. 81 is an illustration of a parity check matrix H of an
ETRI symbol (16 k, 5/15).
[2078] For the parity check matrix H of the ETRI symbol (16 k,
5/15), the parameter g=M.sub.1 is 720.
[2079] Further, for the ETRI symbol (16 k, 5/15), since the code
length N is 16200 and the encoding rate r is 5/15, the information
length K=N.times.r is 16200.times.5/15=5400 and the parity length
M=N-K is 16200-5400=10800.
[2080] Further, the parameter M.sub.2=M-M.sub.1=N-K-g is
10800-720=10080.
[2081] Thus, the parameter Q.sub.1=M.sub.1/P is 720/360=2, and the
parameter Q.sub.2=M.sub.2/P is 10080/360=28.
[2082] FIG. 82 is an illustration of parity check matrices H of
ETRI symbols of (64 k, 5/15), (64 k, 6/15), and (64 k, 7/15).
[2083] For the parity check matrices H of the ETRI symbols of (64
k, 5/15), (64 k, 6/15), and (64 k, 7/15), the parameters g=M.sub.1,
M.sub.2, Q.sub.1, and Q.sub.2 are set as illustrated in FIG.
82.
[2084] <Constellation>
[2085] FIGS. 83 to 104 are illustrations of examples of
constellation types employed in the transmission system of FIG.
7.
[2086] In the transmission system of FIG. 7, for example, a
constellation used in MODCOD can be set to MODCOD serving as a
combination of a modulation scheme and an LDPC code.
[2087] In other words, in the transmission system of FIG. 7, for
example, the LDPC codes can be classified into 9 types of LDPC
codes in which the encoding rate r is 5/15, 6/15, 7/15, 8/15, 9/15,
10/15, 11/15, 12, 15, and 13/15 according to the encoding rate r
(regardless of the code length N), and a combination of the 9 types
of LDPC codes (each of the LDPC codes in which the encoding rate r
is 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15)
and each modulation scheme can be employed as MODCOD.
[2088] Further, in the transmission system of FIG. 7, one or more
of constellations can be set to MODCOD of 1 using the modulation
scheme of MODCOD.
[2089] The constellations include uniform constellations (UCs) in
which an arrangement of signal points is uniform, and non uniform
constellations (NUCs) in which an arrangement of signal points is
not uniform.
[2090] Examples of NUCs include a constellation called a
1-dimensional M.sup.2-QAM non-uniform constellation (1D NUC) and a
constellation called a 2-dimensional QQAM non-uniform constellation
(2D NUC).
[2091] Commonly, the 1D NUC is better in the BER than the UC, and
the 2D NUC is better in the BER than the 1D NUC
[2092] A constellation in which the modulation scheme is QPSK is
the UC. For example, the 2D NUC can be employed as the
constellation in which the modulation scheme is 16QAM, 64QAM,
256QAM, or the like, and for example, the 1D NUC can be employed as
the constellation in which the modulation scheme is 1024QAM,
4096QAM, or the like.
[2093] Hereinafter, a constellation of an NUC used in MODCOD in
which the modulation scheme is a modulation scheme in which an
m-bit symbol is mapped to any of 2.sup.m signal points, and an
encoding rate of an LDPC is r is also referred to as
NUC_2.sup.m_r.
[2094] For example, "NUC_16_6/15" indicates a constellation of an
NUC used in MODCOD in which the modulation scheme is 16QAM (or the
modulation scheme in which a symbol is mapped to any of 16 signal
points), and the encoding rate r of the LDPC code is 6/15.
[2095] In the transmission system of FIG. 7, when the modulation
scheme is QPSK, the same constellation is used for each encoding
rate r of the LDPC code.
[2096] Further, in the transmission system of FIG. 7, when the
modulation scheme is 16QAM, 64QAM, or 256QAM, a different
constellation of a 2D NUC is used according to each encoding rate r
of the LDPC code.
[2097] Further, in the transmission system of FIG. 7, when the
modulation scheme is 1024QAM or 4096QAM, a different constellation
of a 1D NUC is used according to each encoding rate r of the LDPC
code.
[2098] Thus, as described above, when the LDPC codes are classified
into the 9 types of LDPC codes of r=5/15, 6/15, 7/15, 8/15, 9/15,
10/15, 11/15, 12, 15, 13/15 according to the encoding rate r, one
type of constellation is prepared for QPSK, 9 types of
constellations of a 2D NUC are prepared for each of 16QAM, 64QAM,
and 256QAM, and 9 types of constellations of a 1D NUC are prepared
for each of 1024QAM and 4096QAM.
[2099] FIG. 83 is an illustration of an example of a constellation
of a 2D NUC for each of 9 types of encoding rates r (=5/15, 6/15,
7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15) of LDPC codes
when the modulation scheme is 16QAM
[2100] FIG. 84 is an illustration of an example of a constellation
of a 2D NUC for each of 9 types of encoding rates r (=5/15, 6/15,
7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15) of LDPC codes
when the modulation scheme is 64QAM.
[2101] FIG. 85 is an illustration of an example of a constellation
of a 2D NUC for each of 9 types of encoding rates r (=5/15, 6/15,
7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15) of LDPC codes
when the modulation scheme is 256QAM
[2102] FIG. 86 is an illustration of an example of a constellation
of a 1D NUC for each of 9 types of encoding rates r (=5/15, 6/15,
7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15) of LDPC codes
when the modulation scheme is 1024QAM.
[2103] FIG. 87 and FIG. 88 are illustrations of examples of a
constellation of a 1D NUC for each of 9 types of encoding rates r
(=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and 13/15) of
LDPC codes when the modulation scheme is 4096QAM.
[2104] In FIGS. 83 to 88, a horizontal axis and a vertical axis are
an I axis and a Q axis, and Re{x.sub.1} and Im{x.sub.1} indicate a
real part and an imaginary part of a signal point x.sub.1 serving
as coordinates of the signal point x.sub.1.
[2105] In FIGS. 83 to 88, a numerical value written after "for CR"
indicates the encoding rate r of the LDPC code.
[2106] FIG. 89 is an illustration of an example of coordinates of a
signal point of a UC that is used in common to 9 types of encoding
rates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and
13/15) of LDPC codes when the modulation scheme is QPSK
[2107] In FIG. 89, "Input cell word y" indicates a 2-bit symbol
that is mapped to a UC of QPSK, and "Constellation point z.sub.q"
indicates coordinates a signal point z.sub.q. An index q of the
signal point z.sub.q indicates a discrete time (a time interval
between a certain symbol and a next symbol) of a symbol.
[2108] In FIG. 89, coordinates of the signal point z.sub.q are
indicated in the form of a complex number, in which i indicates an
imaginary unit ( (-1)).
[2109] FIG. 90 is an illustration of an example of coordinates of
the signal point of the 2D NUC of FIG. 83 used for the 9 types of
encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,
15, and 13/15) of the LDPC codes when the modulation scheme is
16QAM.
[2110] FIG. 91 is an illustration of an example of coordinates of
the signal point of the 2D NUC of FIG. 84 used for the 9 types of
encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12,
15, and 13/15) of the LDPC codes when the modulation scheme is
64QAM.
[2111] FIGS. 92 and 93 are illustrations of an example of
coordinates of the signal point of the 2D NUC of FIG. 85 used for
the 9 types of encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15,
10/15, 11/15, 12, 15, and 13/15) of the LDPC codes when the
modulation scheme is 256QAM
[2112] In FIGS. 90 to 93, NUC_2.sup.m_r indicates coordinates of a
signal point of a 2D NUC used when the modulation scheme is
2.sup.mQAM, and the encoding rate of the LDPC code is r.
[2113] In FIGS. 90 to 93, similarly to FIG. 89, coordinates of the
signal point z.sub.q are indicated in the form of a complex number,
in which i indicates an imaginary unit.
[2114] In FIGS. 90 to 93, w#k indicates coordinates of a signal
point of a first quadrant of the constellation.
[2115] In the 2D NUC, a signal point of a second quadrant of the
constellation is arranged at a position to which the signal point
of the first quadrant has moved symmetrically to the Q axis, and a
signal point of a third quadrant of the constellation is arranged
at a position to which the signal point of the first quadrant has
moved symmetrically to an origin. Further, a signal point of a
fourth quadrant of the constellation is arranged at a position to
which the signal point of the first quadrant has moved
symmetrically to the I axis.
[2116] Here, when the modulation scheme is 2.sup.mQAM, m bits are
used as one symbol, and one symbol is mapped to a signal point
corresponding to the symbol.
[2117] The m-bit symbol is expressed by, for example, an integer
value of 0 to 2.sup.m-1, but if b=2.sup.m/4 is assumed, symbols
y(0), y(1), . . . , and y(2.sup.m-1) expressed by the integer value
of 0 to 2.sup.m-1 can be classified into four symbols y(0) to
y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to
y(4b-1).
[2118] In FIGS. 90 to 93, a suffix k of w#k has an integer value
within a range of 0 to b-1, and w#k indicates coordinates of a
signal point corresponding to the symbol y(k) within the range of
the symbols y(0) to y(b-1).
[2119] Further, coordinates of a signal point corresponding to the
symbol y(k+b) within the range of the symbols y(b) to y(2b-1) are
indicated by -conj(w#k), and coordinates of a signal point
corresponding to the symbol y(k+2b) within the range of the symbols
y(2b) to y(3b-1) are indicated by conj(w#k). Further, coordinates
of a signal point corresponding to the symbol y(k+3b) within the
range of the symbols y(3b) to y(4b-1) are indicated by -w#k.
[2120] Here, conj(w#k) indicates a complex conjugate of w#k.
[2121] For example, when the modulation scheme is 16QAM, the
symbols y(0), y(1), . . . , and y(15) of m=4 bits are classified
into four symbols y(0) to y(3), y(4) to y(7), y(8) to y(11), and
y(12) to y(15) if b=2.sup.4/4=4.
[2122] Among the symbols y(0) to y(15), for example, the symbol
y(12) is the symbol y(k+3b)=y(0+3.times.4) within the symbols y(3b)
to y(4b-1), and k is zero (0), and thus the coordinates of the
signal point corresponding to the symbol y(12) are -w#k=-w0.
[2123] Now, for example, if the encoding rate r of the LDPC code is
9/15, according to FIG. 90, when the modulation scheme is 16QAM,
and the encoding rate r is 9/15, w0 of (NUC_16_9/15) is
0.4967+1.1932i, and thus the coordinates-w0 of the signal point
corresponding to the symbol y(12) are -(0.4967+1.1932i).
[2124] FIG. 94 is an illustration of an example of the coordinates
of the signal point of the 1D NUC of FIG. 86 used for the 9 types
of encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15,
12, 15, and 13/15) of the LDPC codes when the modulation scheme is
1024QAM.
[2125] In FIG. 94, a column of NUC_1k_r indicates a value of u#k
indicating the coordinates of the signal point of the 1D NUC used
when the modulation scheme is 1024QAM, and the encoding rate of the
LDPC code is r.
[2126] u#k indicates the real part Re(z.sub.q) and the imaginary
part Im(z.sub.q) of the complex number serving as the coordinates
of the signal point z.sub.q of the 1D NUC.
[2127] FIG. 95 is an illustration of a relation between the symbol
y of 1024QAM and u#k serving as each of the real part Re(z.sub.q)
and the imaginary part Im(z.sub.q) of the complex number indicating
the coordinates of the signal point z.sub.q of the 1D NUC
corresponding to the symbol y.
[2128] Now, the 10-bit symbol y of 1024QAM is assumed to be
indicated by y.sub.0,q, y.sub.1,q, y.sub.2,q, y.sub.3,q, y.sub.4,q,
y.sub.5,q, y.sub.6,q, y.sub.7,q, y.sub.8,q, and y.sub.9,q from the
first bit (the most significant bit).
[2129] A of FIG. 95 illustrates a correspondence relation between 5
odd-numbered bits y.sub.0,q, y.sub.2,q, y.sub.4,q, y.sub.6,q,
y.sub.8,q of the symbol y and u#k indicating the real part
Re(z.sub.q) (of the coordinates) of the signal point z.sub.q
corresponding to the symbol y.
[2130] B of FIG. 95 is a correspondence relation between 5
even-numbered bits y.sub.1,q, y.sub.3,q, y.sub.5,q, y.sub.7,q, and
y.sub.9,q of the symbol y and u#k indicating the imaginary part
Im(z.sub.q) (of the coordinates) of the signal point z.sub.q
corresponding to the symbol y.
[2131] For example, when the 10-bit symbol y=(y.sub.0,q, y.sub.1,q,
y.sub.2,q, y.sub.3,q, y.sub.4,q, y.sub.5,q, y.sub.6,q, y.sub.7,q,
y.sub.8,q, y.sub.9,q) of 1024QAM is (0, 0, 1, 0, 0, 1, 1, 1, 0, 0),
the 5 odd-numbered bits (y.sub.0,q, y.sub.2,q, y.sub.4,q,
y.sub.6,q, y.sub.8,q) are (0, 1, 0, 1, 0), and the 5 even-numbered
bits (y.sub.1,q, y.sub.3,q, y.sub.5,q, y.sub.7,q, and y.sub.9,q)
are (0, 0, 1, 1, 0).
[2132] In A of FIG. 95, the 5 odd-numbered bits (0, 1, 0, 1, 0) are
associated with u3, and thus the real part Re(z.sub.q) of the
signal point z.sub.q corresponding to the symbol y=(0, 0, 1, 0, 0,
1, 1, 1, 0, 0) is u3.
[2133] In B of FIG. 95, the 5 even-numbered bits (0, 0, 1, 1, 0)
are associated with u11, and thus the imaginary part Im(z.sub.q) of
the signal point z.sub.q corresponding to the symbol y=(0, 0, 1, 0,
0, 1, 1, 1, 0, 0) is u11.
[2134] Meanwhile, for example, if the encoding rate r of the LDPC
code is 7/15, according to FIG. 94, for the 1D NUC (NUC_1k_7/15)
used when the modulation scheme is 1024QAM and the encoding rate r
of the LDPC code is 7/15, u3 is 1.1963, and u11 is 6.9391.
[2135] Thus, the real part Re(z.sub.q) of the signal point z.sub.q
corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3
(=1.1963), and Im(z.sub.q) is u11 (=6.9391). As a result, the
coordinates of the signal point z.sub.q corresponding to the symbol
y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) are indicated by
1.1963+6.9391i.
[2136] FIG. 96 is an illustration of an example of the coordinates
of the signal point of the 1D NUC of FIGS. 87 and 88 used for the 9
types of encoding rates r (=5/15, 6/15, 7/15, 8/15, 9/15, 10/15,
11/15, 12, 15, and 13/15) of the LDPC codes when the modulation
scheme is 4096QAM.
[2137] In FIG. 96, each column indicates a value of u#k indicating
the coordinates of the signal point of the 1D NUC used when the
modulation scheme is 4096QAM and the encoding rates r of the LDPC
codes are 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, and
13/15.
[2138] u#k indicates the real part Re(z.sub.q) and the imaginary
part Im(z.sub.q) of the complex number serving as the coordinates
of the signal point z.sub.q of the 1D NUC.
[2139] FIG. 97 is an illustration of a relation between the symbol
y of 4096QAM and u#k serving as each of the real part Re(z.sub.q)
and the imaginary part Im(z.sub.q) of the complex number indicating
the coordinates of the signal point z.sub.q of the 1D NUC
corresponding to the symbol y.
[2140] A method of obtaining the coordinates of the signal point of
the 1D NUC of 4096QAM using FIGS. 96 and 97 is the same as the
method of obtaining the coordinates of the signal point of the 1D
NUC of 1024QAM using FIGS. 94 and 95, and thus a description
thereof is omitted.
[2141] FIG. 98 is an illustration of another example of the
constellation of the 2D NUC for each of the 9 types of encoding
rates r of the LDPC codes when the modulation scheme is 16QAM.
[2142] FIG. 99 is an illustration of another example of the
constellation of the 2D NUC for each of the 9 types of encoding
rates r of the LDPC codes when the modulation scheme is 64QAM.
[2143] FIG. 100 is an illustration of another example of the
constellation of the 2D NUC for each of the 9 types of encoding
rates r of the LDPC codes when the modulation scheme is 256QAM.
[2144] In FIGS. 98 to 100, similarly to FIGS. 83 to 88, a
horizontal axis and a vertical axis are the I axis and the Q axis,
and Re{x.sub.1} and Im{x.sub.1} indicate the real part and the
imaginary part of the signal point x.sub.1 serving as the
coordinates of the signal point x.sub.1. Further, in FIGS. 98 to
100, a numerical value written after "for CR" indicates the
encoding rate r of the LDPC code.
[2145] FIG. 101 is an illustration of another example of the
coordinates of the signal point of the 2D NUC of FIG. 98 used for
each of the 9 types of encoding rates r of the LDPC codes when the
modulation scheme is 16QAM.
[2146] FIG. 102 is an illustration of another example of the
coordinates of the signal point of the 2D NUC of FIG. 99 used for
each of the 9 types of encoding rates r of the LDPC codes when the
modulation scheme is 64QAM.
[2147] FIGS. 103 and 104 are illustrations of another example of
the coordinates of the signal point of the 2D NUC of FIG. 100 used
for each of the 9 types of encoding rates r of the LDPC codes when
the modulation scheme is 256QAM.
[2148] In FIGS. 101 to 104, NUC_2.sup.m_r indicates the coordinates
of the signal point of the 2D NUC used when the modulation scheme
is 2.sup.mQAM, and the encoding rate of the LDPC code is r,
similarly to FIGS. 90 to 93.
[2149] The signal points of the 1D NUC are arranged in a grid form
on a straight line parallel to the I axis or a straight line
parallel to the Q axis. However, an interval between the signal
points is not constant. Further, when the signal point (the mapped
data) is transmitted, average power of the signal points on the
constellation is normalized. The normalization is performed by
multiplying each signal point z.sub.q on the constellation by a
reciprocal 1/( P.sub.ave) of a square root P.sub.ave of a root mean
square value P.sub.ave when a root mean square value of an absolute
value for (coordinates of) all signal points on the constellation
is indicated by P.sub.ave.
[2150] According to the constellations described above with
reference to FIGS. 83 to 104, it is confirmed that the excellent
error rate is obtained.
[2151] <Block Interleaver 25>
[2152] FIG. 105 is a block diagram illustrating a configuration
example of the block interleaver 25 of FIG. 9.
[2153] The block interleaver 25 includes a storage region called a
part 1 and a storage region called a part 2.
[2154] Each of the parts 1 and 2 is configured such that a number C
of columns equal in number to the number m of bits of the symbol
and serving as storage regions that store one bit in the row
(horizontal) direction and store a predetermined number of bits in
the column (vertical) direction are arranged.
[2155] If the number of bits (hereinafter, also referred to as a
part column length) that are stored in the column direction by the
column of the part 1 is indicated by R1, and the part column length
of the column of the part 2 is indicated by R2, (R1+R2).times.C is
equal to the code length N (64800 bits or 16200 bits in the present
embodiment) of the LDPC code of the block interleave target.
[2156] Further, the part column length R1 is equal to a multiple of
360 bits serving as the unit size P, and the part column length R2
is equal to a remainder when a sum (hereinafter, also referred to
as a column length) R1+R2 of the part column length R1 of the part
1 and the part column length R2 of the part 2 is divided by 360
bits serving as the unit size P.
[2157] Here, the column length R1+R2 is equal to a value obtained
by dividing the code length N of the LDPC code of the block
interleave target by the number m of bits of the symbol.
[2158] For example, when 16QAM is employed as the modulation scheme
for the LDPC code in which the code length N is 16200 bits, the
number m of bits of the symbol is 4 bits, and thus the column
length R1+R2 is 4050 (=16200/4) bits.
[2159] Further, since the remainder when the column length
R1+R2=4050 is divided by 360 bits serving as the unit size P is 90,
the part column length R2 of the part 2 is 90 bits.
[2160] Further, the part column length R1 of the part 1 is
R1+R2-R2=4050-90=3960 bits.
[2161] FIG. 106 is an illustration of the number C of columns of
the parts 1 and 2 and the part column lengths (the number of rows)
R1 and R2 for a combination of the code length N and the modulation
scheme.
[2162] FIG. 106 illustrates the number C of columns of the parts 1
and 2 and the part column lengths R1 and R2 for combinations of the
LDPC code in which the code length N is 16200 bits and the LDPC
code in which the code length N is 64800 bits and the modulation
schemes of QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.
[2163] FIG. 107 is an illustration of the block interleave
performed by the block interleaver 25 of FIG. 105.
[2164] The block interleaver 25 performs the block interleave by
writing the LDPC code in the parts 1 and 2 and reading the LDPC
code from the parts 1 and 2.
[2165] In other words, in the block interleave, writing of the code
bits of the LDPC code of one code word downward (in the column
direction) in the column of the part 1 is performed from the column
at the left side to the column at the right side as illustrated in
A of FIG. 107.
[2166] Then, when the writing of the code bits is completed to the
bottom of the rightmost column (a C-th column) of the columns of
the part 1, writing of the remaining code bits downward (in the
column direction) in the column of the part 2 is performed from the
column at the left side to the column at the right side.
[2167] Thereafter, when the writing of the code bits is completed
to the bottom of the rightmost column (the C-th column) of the
columns of the part 2, the code bits are read from the 1st rows of
all the C columns of the part 1 in the row direction in units of
C=m bits.
[2168] Then, the reading of the code bits from all the C columns of
the part 1 is sequentially performed toward a row therebelow, and
when the reading is completed up to an R1-th row serving as the
last row, the code bits are read from the 1st rows of all the C
columns of the part 2 in the row direction in units of C=m
bits.
[2169] The reading of the code bits from all the C columns of the
part 2 is sequentially performed toward a row therebelow and the
reading is performed up to an R2 row serving as the last row.
[2170] As a result, the code bits read from the parts 1 and 2 in
units of m bits are supplied to the mapper 117 (FIG. 8) as the
symbol.
[2171] <Group-Wise Interleave>
[2172] FIG. 108 is an illustration of the group-wise interleave
performed by the group-wise interleaver 24 of FIG. 9.
[2173] In the group-wise interleave, 360 bits of one segment are
used as the bit group, where the LDPC code of one code word is
divided into segments in units of 360 bits equal to the unit size
P, and the LDPC code of one code word is interleaved according to a
predetermined pattern (hereinafter, also referred to as a GW
pattern), starting from the head.
[2174] Here, when the LDPC code of one code word is segmented into
the bit groups, an (i+1)-th bit group from the head is also
referred to as a bit group i.
[2175] When the unit size P is 360, for example, the LDPC code in
which the code length N is 1800 bits is segmented into bit groups
0, 1, 2, 3, and 4, that is, 5 (=1800/360) bit groups. Further, for
example, the LDPC code in which the code length N is 16200 bits is
segmented into bit groups 0, 1, . . . , and 44, that is, 45
(=16200/360) bit groups, and the LDPC code in which the code length
N is 64800 bits is segmented into bit groups 0, 1, . . . , and 179,
that is, 180 (=64800/360) bit groups.
[2176] Hereinafter, the GW pattern is assumed to be indicated by a
sequence of numbers indicating a bit group. For example, for the
LDPC code in which the code length N is 1800 bits, for example, the
GW pattern 4, 2, 0, 3, 1 indicates that a sequence of bit groups 0,
1, 2, 3, and 4 is interleaved (rearranged) into a sequence of bit
groups 4, 2, 0, 3, and 1.
[2177] The GW pattern can be set at least for each code length N of
the LDPC code.
[2178] <Example of GW Pattern for LDPC Code of 64 kbits>
[2179] FIG. 109 is an illustration of a 1st example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2180] According to the GW pattern of FIG. 109, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2181] 39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46,
10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25,
77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151,
84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5,
31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160,
71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139,
172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162,
153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21,
149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155,
99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174,
34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144,
135, 20, 62, 81, 169, 124, 6, 19, 30, 163, 61, 179, 136, 97, 16,
and 88.
[2182] FIG. 110 is an illustration of a 2nd example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2183] According to the GW pattern of FIG. 110, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2184] 6, 14, 1, 127, 161, 177, 75, 123, 62, 103, 17, 18, 167, 88,
27, 34, 8, 110, 7, 78, 94, 44, 45, 166, 149, 61, 163, 145, 155,
157, 82, 130, 70, 92, 151, 139, 160, 133, 26, 2, 79, 15, 95, 122,
126, 178, 101, 24, 138, 146, 179, 30, 86, 58, 11, 121, 159, 49, 84,
132, 117, 119, 50, 52, 4, 51, 48, 74, 114, 59, 40, 131, 33, 89, 66,
136, 72, 16, 134, 37, 164, 77, 99, 173, 20, 158, 156, 90, 41, 176,
81, 42, 60, 109, 22, 150, 105, 120, 12, 64, 56, 68, 111, 21, 148,
53, 169, 97, 108, 35, 140, 91, 115, 152, 36, 106, 154, 0, 25, 54,
63, 172, 80, 168, 142, 118, 162, 135, 73, 83, 153, 141, 9, 28, 55,
31, 112, 107, 85, 100, 175, 23, 57, 47, 38, 170, 137, 76, 147, 93,
19, 98, 124, 39, 87, 174, 144, 46, 10, 129, 69, 71, 125, 96, 116,
171, 128, 65, 102, 5, 43, 143, 104, 13, 67, 29, 3, 113, 32, and
165.
[2185] FIG. 111 is an illustration of a 3rd example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2186] According to the GW pattern of FIG. 111, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2187] 103, 116, 158, 0, 27, 73, 140, 30, 148, 36, 153, 154, 10,
174, 122, 178, 6, 106, 162, 59, 142, 112, 7, 74, 11, 51, 49, 72,
31, 65, 156, 95, 171, 105, 173, 168, 1, 155, 125, 82, 86, 161, 57,
165, 54, 26, 121, 25, 157, 93, 22, 34, 33, 39, 19, 46, 150, 141,
12, 9, 79, 118, 24, 17, 85, 117, 67, 58, 129, 160, 89, 61, 146, 77,
130, 102, 101, 137, 94, 69, 14, 133, 60, 149, 136, 16, 108, 41, 90,
28, 144, 13, 175, 114, 2, 18, 63, 68, 21, 109, 53, 123, 75, 81,
143, 169, 42, 119, 138, 104, 4, 131, 145, 8, 5, 76, 15, 88, 177,
124, 45, 97, 64, 100, 37, 132, 38, 44, 107, 35, 43, 80, 50, 91,
152, 78, 166, 55, 115, 170, 159, 147, 167, 87, 83, 29, 96, 172, 48,
98, 62, 139, 70, 164, 84, 47, 151, 134, 126, 113, 179, 110, 111,
128, 32, 52, 66, 40, 135, 176, 99, 127, 163, 3, 120, 71, 56, 92,
23, and 20.
[2188] FIG. 112 is an illustration of a 4th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2189] According to the GW pattern of FIG. 112, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2190] 139, 106, 125, 81, 88, 104, 3, 66, 60, 65, 2, 95, 155, 24,
151, 5, 51, 53, 29, 75, 52, 85, 8, 22, 98, 93, 168, 15, 86, 126,
173, 100, 130, 176, 20, 10, 87, 92, 175, 36, 143, 110, 67, 146,
149, 127, 133, 42, 84, 64, 78, 1, 48, 159, 79, 138, 46, 112, 164,
31, 152, 57, 144, 69, 27, 136, 122, 170, 132, 171, 129, 115, 107,
134, 89, 157, 113, 119, 135, 45, 148, 83, 114, 71, 128, 161, 140,
26, 13, 59, 38, 35, 96, 28, 0, 80, 174, 137, 49, 16, 101, 74, 179,
91, 44, 55, 169, 131, 163, 123, 145, 162, 108, 178, 12, 77, 167,
21, 154, 82, 54, 90, 177, 17, 41, 39, 7, 102, 156, 62, 109, 14, 37,
23, 153, 6, 147, 50, 47, 63, 18, 70, 68, 124, 72, 33, 158, 32, 118,
99, 105, 94, 25, 121, 166, 120, 160, 141, 165, 111, 19, 150, 97,
76, 73, 142, 117, 4, 172, 58, 11, 30, 9, 103, 40, 61, 43, 34, 56,
and 116
[2191] FIG. 113 is an illustration of a 5th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2192] According to the GW pattern of FIG. 113, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2193] 72, 59, 65, 61, 80, 2, 66, 23, 69, 101, 19, 16, 53, 109, 74,
106, 113, 56, 97, 30, 164, 15, 25, 20, 117, 76, 50, 82, 178, 13,
169, 36, 107, 40, 122, 138, 42, 96, 27, 163, 46, 64, 124, 57, 87,
120, 168, 166, 39, 177, 22, 67, 134, 9, 102, 28, 148, 91, 83, 88,
167, 32, 99, 140, 60, 152, 1, 123, 29, 154, 26, 70, 149, 171, 12,
6, 55, 100, 62, 86, 114, 174, 132, 139, 7, 45, 103, 130, 31, 49,
151, 119, 79, 41, 118, 126, 3, 179, 110, 111, 51, 93, 145, 73, 133,
54, 104, 161, 37, 129, 63, 38, 95, 159, 89, 112, 115, 136, 33, 68,
17, 35, 137, 173, 143, 78, 77, 141, 150, 58, 158, 125, 156, 24,
105, 98, 43, 84, 92, 128, 165, 153, 108, 0, 121, 170, 131, 144, 47,
157, 11, 155, 176, 48, 135, 4, 116, 146, 127, 52, 162, 142, 8, 5,
34, 85, 90, 44, 172, 94, 160, 175, 75, 71, 18, 147, 10, 21, 14, and
81.
[2194] FIG. 114 is an illustration of a 6th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2195] According to the GW pattern of FIG. 114, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2196] 8, 27, 7, 70, 75, 84, 50, 131, 146, 99, 96, 141, 155, 157,
82, 57, 120, 38, 137, 13, 83, 23, 40, 9, 56, 171, 124, 172, 39,
142, 20, 128, 133, 2, 89, 153, 103, 112, 129, 151, 162, 106, 14,
62, 107, 110, 73, 71, 177, 154, 80, 176, 24, 91, 32, 173, 25, 16,
17, 159, 21, 92, 6, 67, 81, 37, 15, 136, 100, 64, 102, 163, 168,
18, 78, 76, 45, 140, 123, 118, 58, 122, 11, 19, 86, 98, 119, 111,
26, 138, 125, 74, 97, 63, 10, 152, 161, 175, 87, 52, 60, 22, 79,
104, 30, 158, 54, 145, 49, 34, 166, 109, 179, 174, 93, 41, 116, 48,
3, 29, 134, 167, 105, 132, 114, 169, 147, 144, 77, 61, 170, 90,
178, 0, 43, 149, 130, 117, 47, 44, 36, 115, 88, 101, 148, 69, 46,
94, 143, 164, 139, 126, 160, 156, 33, 113, 65, 121, 53, 42, 66,
165, 85, 127, 135, 5, 55, 150, 72, 35, 31, 51, 4, 1, 68, 12, 28,
95, 59, and 108.
[2197] FIG. 115 is an illustration of a 7th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2198] According to the GW pattern of FIG. 115, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2199] 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98,
100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124,
126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150,
152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176,
178, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33,
35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67,
69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99,
101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125,
127, 129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151,
153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177,
and 179.
[2200] FIG. 116 is an illustration of an 8th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2201] According to the GW pattern of FIG. 116, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2202] 11, 5, 8, 18, 1, 25, 32, 31, 19, 21, 50, 102, 65, 85, 45,
86, 98, 104, 64, 78, 72, 53, 103, 79, 93, 41, 82, 108, 112, 116,
120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168,
172, 176, 4, 12, 15, 3, 10, 20, 26, 34, 23, 33, 68, 63, 69, 92, 44,
90, 75, 56, 100, 47, 106, 42, 39, 97, 99, 89, 52, 109, 113, 117,
121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169,
173, 177, 6, 16, 14, 7, 13, 36, 28, 29, 37, 73, 70, 54, 76, 91, 66,
80, 88, 51, 96, 81, 95, 38, 57, 105, 107, 59, 61, 110, 114, 118,
122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170,
174, 178, 0, 9, 17, 2, 27, 30, 24, 22, 35, 77, 74, 46, 94, 62, 87,
83, 101, 49, 43, 84, 48, 60, 67, 71, 58, 40, 55, 111, 115, 119,
123, 127, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171,
175, and 179.
[2203] FIG. 117 is an illustration of a 9th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2204] According to the GW pattern of FIG. 117, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2205] 9, 18, 15, 13, 35, 26, 28, 99, 40, 68, 85, 58, 63, 104, 50,
52, 94, 69, 108, 114, 120, 126, 132, 138, 144, 150, 156, 162, 168,
174, 8, 16, 17, 24, 37, 23, 22, 103, 64, 43, 47, 56, 92, 59, 70,
42, 106, 60, 109, 115, 121, 127, 133, 139, 145, 151, 157, 163, 169,
175, 4, 1, 10, 19, 30, 31, 89, 86, 77, 81, 51, 79, 83, 48, 45, 62,
67, 65, 110, 116, 122, 128, 134, 140, 146, 152, 158, 164, 170, 176,
6, 2, 0, 25, 20, 34, 98, 105, 82, 96, 90, 107, 53, 74, 73, 93, 55,
102, 111, 117, 123, 129, 135, 141, 147, 153, 159, 165, 171, 177,
14, 7, 3, 27, 21, 33, 44, 97, 38, 75, 72, 41, 84, 80, 100, 87, 76,
57, 112, 118, 124, 130, 136, 142, 148, 154, 160, 166, 172, 178, 5,
11, 12, 32, 29, 36, 88, 71, 78, 95, 49, 54, 61, 66, 46, 39, 101,
91, 113, 119, 125, 131, 137, 143, 149, 155, 161, 167, 173, and
179.
[2206] FIG. 118 is an illustration of a 10th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2207] According to the GW pattern of FIG. 118, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2208] 0, 14, 19, 21, 2, 11, 22, 9, 8, 7, 16, 3, 26, 24, 27, 80,
100, 121, 107, 31, 36, 42, 46, 49, 75, 93, 127, 95, 119, 73, 61,
63, 117, 89, 99, 129, 52, 111, 124, 48, 122, 82, 106, 91, 92, 71,
103, 102, 81, 113, 101, 97, 33, 115, 59, 112, 90, 51, 126, 85, 123,
40, 83, 53, 69, 70, 132, 134, 136, 138, 140, 142, 144, 146, 148,
150, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174,
176, 178, 4, 5, 10, 12, 20, 6, 18, 13, 17, 15, 1, 29, 28, 23, 25,
67, 116, 66, 104, 44, 50, 47, 84, 76, 65, 130, 56, 128, 77, 39, 94,
87, 120, 62, 88, 74, 35, 110, 131, 98, 60, 37, 45, 78, 125, 41, 34,
118, 38, 72, 108, 58, 43, 109, 57, 105, 68, 86, 79, 96, 32, 114,
64, 55, 30, 54, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151,
153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177,
and 179.
[2209] FIG. 119 is an illustration of an 11th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2210] According to the GW pattern of FIG. 119, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2211] 21, 11, 12, 9, 0, 6, 24, 25, 85, 103, 118, 122, 71, 101, 41,
93, 55, 73, 100, 40, 106, 119, 45, 80, 128, 68, 129, 61, 124, 36,
126, 117, 114, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168,
172, 176, 20, 18, 10, 13, 16, 8, 26, 27, 54, 111, 52, 44, 87, 113,
115, 58, 116, 49, 77, 95, 86, 30, 78, 81, 56, 125, 53, 89, 94, 50,
123, 65, 83, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173,
177, 2, 17, 1, 4, 7, 15, 29, 82, 32, 102, 76, 121, 92, 130, 127,
62, 107, 38, 46, 43, 110, 75, 104, 70, 91, 69, 96, 120, 42, 34, 79,
35, 105, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174,
178, 19, 5, 3, 14, 22, 28, 23, 109, 51, 108, 131, 33, 84, 88, 64,
63, 59, 57, 97, 98, 48, 31, 99, 37, 72, 39, 74, 66, 60, 67, 47,
112, 90, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, and
179.
[2212] FIG. 120 is an illustration of a 12th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2213] According to the GW pattern of FIG. 120, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2214] 12, 15, 2, 16, 27, 50, 35, 74, 38, 70, 108, 32, 112, 54, 30,
122, 72, 116, 36, 90, 49, 85, 132, 138, 144, 150, 156, 162, 168,
174, 0, 14, 9, 5, 23, 66, 68, 52, 96, 117, 84, 128, 100, 63, 60,
127, 81, 99, 53, 55, 103, 95, 133, 139, 145, 151, 157, 163, 169,
175, 10, 22, 13, 11, 28, 104, 37, 57, 115, 46, 65, 129, 107, 75,
119, 110, 31, 43, 97, 78, 125, 58, 134, 140, 146, 152, 158, 164,
170, 176, 4, 19, 6, 8, 24, 44, 101, 94, 118, 130, 69, 71, 83, 34,
86, 124, 48, 106, 89, 40, 102, 91, 135, 141, 147, 153, 159, 165,
171, 177, 3, 20, 7, 17, 25, 87, 41, 120, 47, 80, 59, 62, 88, 45,
56, 131, 61, 126, 113, 92, 51, 98, 136, 142, 148, 154, 160, 166,
172, 178, 21, 18, 1, 26, 29, 39, 73, 121, 105, 77, 42, 114, 93, 82,
111, 109, 67, 79, 123, 64, 76, 33, 137, 143, 149, 155, 161, 167,
173, and 179.
[2215] FIG. 121 is an illustration of a 13th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2216] According to the GW pattern of FIG. 121, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2217] 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98,
100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124,
126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150,
152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176,
178, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33,
35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67,
69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99,
101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125,
127, 129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151,
153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177,
and 179.
[2218] FIG. 122 is an illustration of a 14th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2219] According to the GW pattern of FIG. 122, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2220] 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120,
124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172,
176, 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61,
65, 69, 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121,
125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173,
177, 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62,
66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122,
126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174,
178, 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63,
67, 71, 75, 79, 83, 87, 91, 95, 99, 103, 107, 111, 115, 119, 123,
127, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175,
and 179.
[2221] FIG. 123 is an illustration of a 15th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2222] According to the GW pattern of FIG. 123, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2223] 8, 112, 92, 165, 12, 55, 5, 126, 87, 70, 69, 94, 103, 78,
137, 148, 9, 60, 13, 7, 178, 79, 43, 136, 34, 68, 118, 152, 49, 15,
99, 61, 66, 28, 109, 125, 33, 167, 81, 93, 97, 26, 35, 30, 153,
131, 122, 71, 107, 130, 76, 4, 95, 42, 58, 134, 0, 89, 75, 40, 129,
31, 80, 101, 52, 16, 142, 44, 138, 46, 116, 27, 82, 88, 143, 128,
72, 29, 83, 117, 172, 14, 51, 159, 48, 160, 100, 1, 102, 90, 22, 3,
114, 19, 108, 113, 39, 73, 111, 155, 106, 105, 91, 150, 54, 25,
135, 139, 147, 36, 56, 123, 6, 67, 104, 96, 157, 10, 62, 164, 86,
74, 133, 120, 174, 53, 140, 156, 171, 149, 127, 85, 59, 124, 84,
11, 21, 132, 41, 145, 158, 32, 17, 23, 50, 169, 170, 38, 18, 151,
24, 166, 175, 2, 47, 57, 98, 20, 177, 161, 154, 176, 163, 37, 110,
168, 141, 64, 65, 173, 162, 121, 45, 77, 115, 179, 63, 119, 146,
and 144.
[2224] FIG. 124 is an illustration of a 16th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2225] According to the GW pattern of FIG. 124 a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2226] 103, 138, 168, 82, 116, 45, 178, 28, 160, 2, 129, 148, 150,
23, 54, 106, 24, 78, 49, 87, 145, 179, 26, 112, 119, 12, 18, 174,
21, 48, 134, 137, 102, 147, 152, 72, 68, 3, 22, 169, 30, 64, 108,
142, 131, 13, 113, 115, 121, 37, 133, 136, 101, 59, 73, 161, 38,
164, 43, 167, 42, 144, 41, 85, 91, 58, 128, 154, 172, 57, 75, 17,
157, 19, 4, 86, 15, 25, 35, 9, 105, 123, 14, 34, 56, 111, 60, 90,
74, 149, 146, 62, 163, 31, 16, 141, 88, 6, 155, 130, 89, 107, 135,
79, 8, 10, 124, 171, 114, 162, 33, 66, 126, 71, 44, 158, 51, 84,
165, 173, 120, 7, 11, 170, 176, 1, 156, 96, 175, 153, 36, 47, 110,
63, 132, 29, 95, 143, 98, 70, 20, 122, 53, 100, 93, 140, 109, 139,
76, 151, 52, 61, 46, 125, 94, 50, 67, 81, 69, 65, 40, 127, 77, 32,
39, 27, 99, 97, 159, 166, 80, 117, 55, 92, 118, 0, 5, 83, 177, and
104.
[2227] FIG. 125 is an illustration of a 17th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2228] According to the GW pattern of FIG. 125, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2229] 104, 120, 47, 136, 116, 109, 22, 20, 117, 61, 52, 108, 86,
99, 76, 90, 37, 58, 36, 138, 95, 130, 177, 93, 56, 33, 24, 82, 0,
67, 83, 46, 79, 70, 154, 18, 75, 43, 49, 63, 162, 16, 167, 80, 125,
1, 123, 107, 9, 45, 53, 15, 38, 23, 57, 141, 4, 178, 165, 113, 21,
105, 11, 124, 126, 77, 146, 29, 131, 27, 176, 40, 74, 91, 140, 64,
73, 44, 129, 157, 172, 51, 10, 128, 119, 163, 103, 28, 85, 156, 78,
6, 8, 173, 160, 106, 31, 54, 122, 25, 139, 68, 150, 164, 87, 135,
97, 166, 42, 169, 161, 137, 26, 39, 133, 5, 94, 69, 2, 30, 171,
149, 115, 96, 145, 101, 92, 143, 12, 88, 81, 71, 19, 147, 50, 152,
159, 155, 151, 174, 60, 32, 3, 142, 72, 14, 170, 112, 65, 89, 175,
158, 17, 114, 62, 144, 13, 98, 66, 59, 7, 118, 48, 153, 100, 134,
84, 111, 132, 127, 41, 168, 110, 102, 34, 121, 179, 148, 55, and
35.
[2230] FIG. 126 is an illustration of a 18th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2231] According to the GW pattern of FIG. 126, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2232] 37, 98, 160, 63, 18, 6, 94, 136, 8, 50, 0, 75, 65, 32, 107,
60, 108, 17, 21, 156, 157, 5, 73, 66, 38, 177, 162, 130, 171, 76,
57, 126, 103, 62, 120, 134, 154, 101, 143, 29, 13, 149, 16, 33, 55,
56, 159, 128, 23, 146, 153, 141, 169, 49, 46, 152, 89, 155, 111,
127, 48, 14, 93, 41, 7, 78, 135, 69, 123, 179, 36, 87, 27, 58, 88,
170, 125, 110, 15, 97, 178, 90, 121, 173, 30, 102, 10, 80, 104,
166, 64, 4, 147, 1, 52, 45, 148, 68, 158, 31, 140, 100, 85, 115,
151, 70, 39, 82, 122, 79, 12, 91, 133, 132, 22, 163, 47, 19, 119,
144, 35, 25, 42, 83, 92, 26, 72, 138, 54, 124, 24, 74, 118, 117,
168, 71, 109, 112, 106, 176, 175, 44, 145, 11, 9, 161, 96, 77, 174,
137, 34, 84, 2, 164, 129, 43, 150, 61, 53, 20, 165, 113, 142, 116,
95, 3, 28, 40, 81, 99, 139, 114, 59, 67, 172, 131, 105, 167, 51,
and 86.
[2233] FIG. 127 is an illustration of a 19th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2234] According to the GW pattern of FIG. 127, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2235] 58, 70, 23, 32, 26, 63, 55, 48, 35, 41, 53, 20, 38, 51, 61,
65, 44, 29, 7, 2, 113, 68, 96, 104, 106, 89, 27, 0, 119, 21, 4, 49,
46, 100, 13, 36, 57, 98, 102, 9, 42, 39, 33, 62, 22, 95, 101, 15,
91, 25, 93, 132, 69, 87, 47, 59, 67, 124, 17, 11, 31, 43, 40, 37,
85, 50, 97, 140, 45, 92, 56, 30, 34, 60, 107, 24, 52, 94, 64, 5,
71, 90, 66, 103, 88, 86, 84, 19, 169, 159, 147, 126, 28, 130, 14,
162, 144, 166, 108, 153, 115, 135, 120, 122, 112, 139, 151, 156,
16, 172, 164, 123, 99, 54, 136, 81, 105, 128, 116, 150, 155, 76,
18, 142, 170, 175, 83, 146, 78, 109, 73, 131, 127, 82, 167, 77,
110, 79, 137, 152, 3, 173, 148, 72, 158, 117, 1, 6, 12, 8, 161, 74,
143, 133, 168, 171, 134, 163, 138, 121, 141, 160, 111, 10, 149, 80,
75, 165, 157, 174, 129, 145, 114, 125, 154, 118, 176, 177, 178, and
179.
[2236] FIG. 128 is an illustration of a 20th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2237] According to the GW pattern of FIG. 128, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2238] 40, 159, 100, 14, 88, 75, 53, 24, 157, 84, 23, 77, 140, 145,
32, 28, 112, 39, 76, 50, 93, 27, 107, 25, 152, 101, 127, 5, 129,
71, 9, 21, 96, 73, 35, 106, 158, 49, 136, 30, 137, 115, 139, 48,
167, 85, 74, 72, 7, 110, 161, 41, 170, 147, 82, 128, 149, 33, 8,
120, 47, 68, 58, 67, 87, 155, 11, 18, 103, 151, 29, 36, 83, 135,
79, 150, 97, 54, 70, 138, 156, 31, 121, 34, 20, 130, 61, 57, 2,
166, 117, 15, 6, 165, 118, 98, 116, 131, 109, 62, 126, 175, 22,
111, 164, 16, 133, 102, 55, 105, 64, 177, 78, 37, 162, 124, 119,
19, 4, 69, 132, 65, 123, 160, 17, 52, 38, 1, 80, 90, 42, 81, 104,
13, 144, 51, 114, 3, 43, 146, 163, 59, 45, 89, 122, 169, 44, 94,
86, 99, 66, 171, 173, 0, 141, 148, 176, 26, 143, 178, 60, 153, 142,
91, 179, 12, 168, 113, 95, 174, 56, 134, 92, 46, 108, 125, 10, 172,
154, and 63.
[2239] FIG. 129 is an illustration of a 21st example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2240] According to the GW pattern of FIG. 129, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2241] 143, 57, 67, 26, 134, 112, 136, 103, 13, 94, 16, 116, 169,
95, 98, 6, 174, 173, 102, 15, 114, 39, 127, 78, 18, 123, 121, 4,
89, 115, 24, 108, 74, 63, 175, 82, 48, 20, 104, 92, 27, 3, 33, 106,
62, 148, 154, 25, 129, 69, 178, 156, 87, 83, 100, 122, 70, 93, 50,
140, 43, 125, 166, 41, 128, 85, 157, 49, 86, 66, 79, 130, 133, 171,
21, 165, 126, 51, 153, 38, 142, 109, 10, 65, 23, 91, 90, 73, 61,
42, 47, 131, 77, 9, 58, 96, 101, 37, 7, 159, 44, 2, 170, 160, 162,
0, 137, 31, 45, 110, 144, 88, 8, 11, 40, 81, 168, 135, 56, 151,
107, 105, 32, 120, 132, 1, 84, 161, 179, 72, 176, 71, 145, 139, 75,
141, 97, 17, 149, 124, 80, 60, 36, 52, 164, 53, 158, 113, 34, 76,
5, 111, 155, 138, 19, 35, 167, 172, 14, 147, 55, 152, 59, 64, 54,
117, 146, 118, 119, 150, 29, 163, 68, 99, 46, 177, 28, 22, 30, and
12.
[2242] FIG. 130 is an illustration of a 22nd example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2243] According to the GW pattern of FIG. 130, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2244] 116, 47, 155, 89, 109, 137, 103, 60, 114, 14, 148, 100, 28,
132, 129, 105, 154, 7, 167, 140, 160, 30, 57, 32, 81, 3, 86, 45,
69, 147, 125, 52, 20, 22, 156, 168, 17, 5, 93, 53, 61, 149, 56, 62,
112, 48, 11, 21, 166, 73, 158, 104, 79, 128, 135, 126, 63, 26, 44,
97, 13, 151, 123, 41, 118, 35, 131, 8, 90, 58, 134, 6, 78, 130, 82,
106, 99, 178, 102, 29, 108, 120, 107, 139, 23, 85, 36, 172, 174,
138, 95, 145, 170, 122, 50, 19, 91, 67, 101, 92, 179, 27, 94, 66,
171, 39, 68, 9, 59, 146, 15, 31, 38, 49, 37, 64, 77, 152, 144, 72,
165, 163, 24, 1, 2, 111, 80, 124, 43, 136, 127, 153, 75, 42, 113,
18, 164, 133, 142, 98, 96, 4, 51, 150, 46, 121, 76, 10, 25, 176,
34, 110, 115, 143, 173, 169, 40, 65, 157, 175, 70, 33, 141, 71,
119, 16, 162, 177, 12, 84, 87, 117, 0, 88, 161, 55, 54, 83, 74, and
159.
[2245] FIG. 131 is an illustration of a 23rd example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2246] According to the GW pattern of FIG. 131, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2247] 62, 17, 10, 25, 174, 13, 159, 14, 108, 0, 42, 57, 78, 67,
41, 132, 110, 87, 77, 27, 88, 56, 8, 161, 7, 164, 171, 44, 75, 176,
145, 165, 157, 34, 142, 98, 103, 52, 11, 82, 141, 116, 15, 158,
139, 120, 36, 61, 20, 112, 144, 53, 128, 24, 96, 122, 114, 104,
150, 50, 51, 80, 109, 33, 5, 95, 59, 16, 134, 105, 111, 21, 40,
146, 18, 133, 60, 23, 160, 106, 32, 79, 55, 6, 1, 154, 117, 19,
152, 167, 166, 30, 35, 100, 74, 131, 99, 156, 39, 76, 86, 43, 178,
155, 179, 177, 136, 175, 81, 64, 124, 153, 84, 163, 135, 115, 125,
47, 45, 143, 72, 48, 172, 97, 85, 107, 126, 91, 129, 137, 83, 118,
54, 2, 9, 58, 169, 73, 123, 4, 92, 168, 162, 94, 138, 119, 22, 31,
63, 89, 90, 69, 49, 173, 28, 127, 26, 29, 101, 170, 93, 140, 147,
149, 148, 66, 65, 121, 12, 71, 37, 70, 102, 46, 38, 68, 130, 3,
113, and 151.
[2248] FIG. 132 is an illustration of a 24th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2249] According to the GW pattern of FIG. 132, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2250] 168, 18, 46, 131, 88, 90, 11, 89, 111, 174, 172, 38, 78,
153, 9, 80, 53, 27, 44, 79, 35, 83, 171, 51, 37, 99, 95, 119, 117,
127, 112, 166, 28, 123, 33, 160, 29, 6, 135, 10, 66, 69, 74, 92,
15, 109, 106, 178, 65, 141, 0, 3, 154, 156, 164, 7, 45, 115, 122,
148, 110, 24, 121, 126, 23, 175, 21, 113, 58, 43, 26, 143, 56, 142,
39, 147, 30, 25, 101, 145, 136, 19, 4, 48, 158, 118, 133, 49, 20,
102, 14, 151, 5, 2, 72, 103, 75, 60, 84, 34, 157, 169, 31, 161, 81,
70, 85, 159, 132, 41, 152, 179, 98, 144, 36, 16, 87, 40, 91, 1,
130, 108, 139, 94, 97, 8, 104, 13, 150, 137, 47, 73, 62, 12, 50,
61, 105, 100, 86, 146, 165, 22, 17, 57, 167, 59, 96, 120, 155, 77,
162, 55, 68, 140, 134, 82, 76, 125, 32, 176, 138, 173, 177, 163,
107, 170, 71, 129, 63, 93, 42, 52, 116, 149, 54, 128, 124, 114, 67,
and 64.
[2251] FIG. 133 is an illustration of a 25th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2252] According to the GW pattern of FIG. 133, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2253] 18, 150, 165, 42, 81, 48, 63, 45, 93, 152, 25, 16, 174, 29,
47, 83, 8, 60, 30, 66, 11, 113, 44, 148, 4, 155, 59, 33, 134, 99,
32, 176, 109, 72, 36, 111, 106, 73, 170, 126, 64, 88, 20, 17, 172,
154, 120, 121, 139, 77, 98, 43, 105, 133, 19, 41, 78, 15, 7, 145,
94, 136, 131, 163, 65, 31, 96, 79, 119, 143, 10, 95, 9, 146, 14,
118, 162, 37, 97, 49, 22, 51, 127, 6, 71, 132, 87, 21, 39, 38, 54,
115, 159, 161, 84, 108, 13, 102, 135, 103, 156, 67, 173, 76, 75,
164, 52, 142, 69, 130, 56, 153, 74, 166, 158, 124, 141, 58, 116,
85, 175, 169, 168, 147, 35, 62, 5, 123, 100, 90, 122, 101, 149,
112, 140, 86, 68, 89, 125, 27, 177, 160, 0, 80, 55, 151, 53, 2, 70,
167, 114, 129, 179, 138, 1, 92, 26, 50, 28, 110, 61, 82, 91, 117,
107, 178, 34, 157, 137, 128, 40, 24, 57, 3, 171, 46, 104, 12, 144,
and 23.
[2254] FIG. 134 is an illustration of a 26th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2255] According to the GW pattern of FIG. 134, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2256] 18, 8, 166, 117, 4, 111, 142, 148, 176, 91, 120, 144, 99,
124, 20, 25, 31, 78, 36, 72, 2, 98, 93, 74, 174, 52, 152, 62, 88,
75, 23, 97, 147, 15, 71, 1, 127, 138, 81, 83, 68, 94, 112, 119,
121, 89, 163, 85, 86, 28, 17, 64, 14, 44, 158, 159, 150, 32, 128,
70, 90, 29, 30, 63, 100, 65, 129, 140, 177, 46, 84, 92, 10, 33, 58,
7, 96, 151, 171, 40, 76, 6, 3, 37, 104, 57, 135, 103, 141, 107,
116, 160, 41, 153, 175, 55, 130, 118, 131, 42, 27, 133, 95, 179,
34, 21, 87, 106, 105, 108, 79, 134, 113, 26, 164, 114, 73, 102, 77,
22, 110, 161, 43, 122, 123, 82, 5, 48, 139, 60, 49, 154, 115, 146,
67, 69, 137, 109, 143, 24, 101, 45, 16, 12, 19, 178, 80, 51, 47,
149, 50, 172, 170, 169, 61, 9, 39, 136, 59, 38, 54, 156, 126, 125,
145, 0, 13, 155, 132, 162, 11, 157, 66, 165, 173, 56, 168, 167, 53,
and 35.
[2257] FIG. 135 is an illustration of a 27th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2258] According to the GW pattern of FIG. 135, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2259] 77, 50, 109, 128, 153, 12, 48, 17, 147, 55, 173, 172, 135,
121, 99, 162, 52, 40, 129, 168, 103, 87, 134, 105, 179, 10, 131,
151, 3, 26, 100, 15, 123, 88, 18, 91, 54, 160, 49, 1, 76, 80, 74,
31, 47, 58, 161, 9, 16, 34, 41, 21, 177, 11, 63, 6, 39, 165, 169,
125, 114, 57, 37, 67, 93, 96, 73, 106, 83, 166, 24, 51, 142, 65,
43, 64, 53, 72, 156, 81, 4, 155, 33, 163, 56, 150, 70, 167, 107,
112, 144, 149, 36, 32, 35, 59, 101, 29, 127, 138, 176, 90, 141, 92,
170, 102, 119, 25, 75, 14, 0, 68, 20, 97, 110, 28, 89, 118, 154,
126, 2, 22, 124, 85, 175, 78, 46, 152, 23, 86, 27, 79, 130, 66, 45,
113, 111, 62, 61, 7, 30, 133, 108, 171, 143, 60, 178, 5, 122, 44,
38, 148, 157, 84, 42, 139, 145, 8, 104, 115, 71, 137, 132, 146,
164, 98, 13, 117, 174, 158, 95, 116, 140, 94, 136, 120, 82, 69,
159, and 19.
[2260] FIG. 136 is an illustration of a 28th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2261] According to the GW pattern of FIG. 136, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2262] 51, 47, 53, 43, 55, 59, 49, 33, 35, 31, 24, 37, 0, 2, 45,
41, 39, 57, 42, 44, 52, 40, 23, 30, 32, 34, 54, 56, 46, 50, 122,
48, 1, 36, 38, 58, 77, 3, 65, 81, 67, 147, 83, 69, 26, 75, 85, 73,
79, 145, 71, 63, 5, 61, 70, 78, 68, 62, 66, 6, 64, 149, 60, 82, 80,
4, 76, 84, 72, 154, 86, 74, 89, 128, 137, 91, 141, 93, 101, 7, 87,
9, 103, 99, 95, 11, 13, 143, 97, 133, 136, 12, 100, 94, 14, 88,
142, 96, 92, 8, 152, 10, 139, 102, 104, 132, 90, 98, 114, 112, 146,
123, 110, 15, 125, 150, 120, 153, 29, 106, 134, 27, 127, 108, 130,
116, 28, 107, 126, 25, 131, 124, 129, 151, 121, 105, 111, 115, 135,
148, 109, 117, 158, 113, 170, 119, 162, 178, 155, 176, 18, 20, 164,
157, 160, 22, 140, 16, 168, 166, 172, 174, 175, 179, 118, 138, 156,
19, 169, 167, 163, 173, 161, 177, 165, 144, 171, 17, 21, and
159.
[2263] FIG. 137 is an illustration of a 29th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2264] According to the GW pattern of FIG. 137, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2265] 49, 2, 57, 47, 31, 35, 24, 39, 59, 0, 45, 41, 55, 53, 51,
37, 33, 43, 56, 38, 48, 32, 50, 23, 34, 54, 1, 36, 44, 52, 40, 58,
122, 46, 42, 30, 3, 75, 73, 65, 145, 71, 79, 67, 69, 83, 85, 147,
63, 81, 77, 61, 5, 26, 62, 64, 74, 70, 82, 149, 76, 4, 78, 84, 80,
86, 66, 68, 72, 6, 60, 154, 103, 95, 101, 143, 9, 89, 141, 128, 97,
137, 133, 7, 13, 99, 91, 93, 87, 11, 136, 90, 88, 94, 10, 8, 14,
96, 104, 92, 132, 142, 100, 98, 12, 102, 152, 139, 150, 106, 146,
130, 27, 108, 153, 112, 114, 29, 110, 134, 116, 15, 127, 125, 123,
120, 148, 151, 113, 126, 124, 135, 129, 109, 25, 28, 158, 117, 105,
115, 111, 131, 107, 121, 18, 170, 164, 20, 140, 160, 166, 162, 119,
155, 168, 178, 22, 174, 172, 176, 16, 157, 159, 171, 161, 118, 17,
163, 21, 165, 19, 179, 177, 167, 138, 173, 156, 144, 169, and
175.
[2266] FIG. 138 is an illustration of a 30th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2267] According to the GW pattern of FIG. 138, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2268] 71, 38, 98, 159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151,
66, 92, 140, 6, 165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110,
128, 73, 148, 14, 5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122,
150, 103, 178, 119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143,
147, 89, 4, 107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153,
90, 152, 124, 7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175,
94, 115, 15, 112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162,
167, 164, 97, 82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105,
134, 173, 84, 9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111,
133, 56, 170, 104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35,
58, 45, 155, 70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69,
158, 129, 139, 62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and
137.
[2269] FIG. 139 is an illustration of a 31th example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2270] According to the GW pattern of FIG. 139, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2271] 66, 61, 150, 157, 63, 42, 78, 44, 23, 154, 133, 101, 82, 26,
84, 123, 89, 31, 45, 102, 36, 134, 83, 117, 170, 27, 73, 137, 25,
32, 62, 91, 4, 20, 144, 145, 21, 74, 113, 148, 24, 135, 5, 19, 2,
34, 43, 168, 14, 64, 142, 115, 87, 38, 147, 39, 51, 152, 56, 86,
122, 76, 57, 129, 172, 6, 126, 10, 97, 85, 164, 3, 80, 90, 79, 124,
138, 120, 17, 103, 99, 116, 46, 98, 162, 151, 143, 11, 175, 160,
96, 132, 81, 171, 94, 65, 118, 161, 125, 178, 95, 112, 88, 174, 13,
35, 1, 167, 0, 128, 12, 58, 29, 169, 67, 28, 119, 166, 60, 55, 54,
130, 92, 146, 177, 149, 111, 9, 173, 179, 176, 75, 77, 114, 48,
159, 8, 141, 107, 139, 52, 100, 136, 105, 127, 47, 18, 69, 109, 16,
121, 59, 163, 165, 108, 106, 70, 22, 93, 41, 33, 110, 53, 140, 153,
158, 50, 15, 37, 72, 156, 7, 131, 49, 71, 68, 104, 30, 40, 155.
[2272] FIG. 140 is an illustration of a 32nd example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2273] According to the GW pattern of FIG. 140, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2274] 75, 83, 11, 24, 86, 104, 156, 76, 37, 173, 127, 61, 43, 139,
106, 69, 49, 2, 128, 140, 68, 14, 100, 8, 36, 73, 148, 65, 16, 47,
177, 6, 132, 45, 5, 30, 13, 22, 29, 27, 101, 150, 23, 90, 41, 93,
89, 92, 135, 4, 71, 87, 44, 124, 26, 64, 1, 129, 157, 130, 107, 18,
91, 118, 3, 82, 144, 113, 121, 54, 84, 97, 122, 120, 7, 154, 56,
134, 57, 161, 33, 116, 28, 96, 72, 172, 12, 115, 38, 164, 32, 167,
145, 17, 88, 39, 151, 80, 0, 136, 169, 142, 74, 147, 126, 166, 163,
40, 110, 171, 50, 160, 131, 70, 175, 103, 125, 77, 162, 31, 85, 66,
67, 52, 108, 159, 133, 42, 153, 21, 51, 119, 123, 98, 35, 48, 111,
149, 25, 58, 60, 158, 102, 59, 117, 20, 141, 143, 46, 53, 155, 15,
165, 152, 112, 176, 105, 178, 99, 174, 168, 114, 179, 78, 10, 19,
62, 63, 170, 138, 34, 109, 9, 146, 95, 94, 55, 137, 81, and 79.
[2275] FIG. 141 is an illustration of a 33rd example of the GW
pattern for an LDPC code in which the code length N is 64
kbits.
[2276] According to the GW pattern of FIG. 141, a sequence of bit
groups 0 to 179 of the LDPC code of 64 kbits is interleaved into a
sequence of bit groups
[2277] 98, 159, 59, 125, 163, 89, 26, 4, 102, 70, 92, 36, 37, 142,
176, 95, 71, 19, 87, 45, 81, 47, 65, 170, 103, 48, 67, 61, 64, 35,
76, 80, 140, 77, 10, 167, 178, 155, 120, 156, 151, 12, 58, 5, 83,
137, 41, 109, 2, 66, 133, 62, 135, 28, 93, 128, 86, 57, 153, 161,
110, 52, 147, 141, 31, 79, 32, 88, 160, 84, 150, 6, 100, 73, 126,
164, 17, 42, 101, 7, 55, 105, 91, 22, 130, 154, 1, 82, 14, 0, 9,
21, 50, 165, 72, 138, 175, 106, 108, 3, 169, 30, 157, 54, 18, 20,
44, 34, 134, 107, 56, 53, 15, 162, 38, 166, 24, 33, 60, 85, 145,
115, 43, 39, 40, 124, 149, 144, 132, 96, 11, 146, 90, 129, 119,
111, 171, 8, 152, 121, 173, 131, 49, 27, 118, 16, 148, 68, 177, 94,
179, 13, 114, 75, 51, 117, 25, 46, 136, 143, 139, 113, 127, 174,
74, 29, 122, 158, 69, 97, 78, 63, 99, 112, 104, 116, 172, 168, 23,
and 123.
[2278] The 1st to 33rd examples of the GW pattern for the LDPC code
in which the code length N is 64 kbits can be applied to any
combination of the LDPC code in which the code length N is 64 kbits
with an arbitrary encoding rate r and modulation scheme
(constellation).
[2279] However, when the GW pattern to be applied to the group-wise
interleave is set for each combination of the code length N of the
LDPC code, the encoding rate r of the LDPC code, and the modulation
scheme (constellation), the error rate of each combination can be
further improved.
[2280] When the GW pattern of FIG. 109 is applied to, for example,
the combination of the ETRI symbol (64 k, 5/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2281] When the GW pattern of FIG. 110 is applied to, for example,
the combination of the ETRI symbol (64 k, 5/15) and 16QAM of FIG.
90, a particularly excellent error rate can be achieved.
[2282] When the GW pattern of FIG. 111 is applied to, for example,
the combination of the ETRI symbol (64 k, 5/15) and 64QAM of FIG.
91, a particularly excellent error rate can be achieved.
[2283] When the GW pattern of FIG. 112 is applied to, for example,
the combination of the Sony symbol (64 k, 7/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2284] When the GW pattern of FIG. 113 is applied to, for example,
the combination of the Sony symbol (64 k, 7/15) and 16QAM of FIG.
90, a particularly excellent error rate can be achieved.
[2285] When the GW pattern of FIG. 114 is applied to, for example,
the combination of the Sony symbol (64 k, 7/15) and 64QAM of FIG.
91, a particularly excellent error rate can be achieved.
[2286] When the GW pattern of FIG. 115 is applied to, for example,
the combination of the Sony symbol (64 k, 9/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2287] When the GW pattern of FIG. 116 is applied to, for example,
the combination of the Sony symbol (64 k, 9/15) and 16QAM of FIG.
90, a particularly excellent error rate can be achieved.
[2288] When the GW pattern of FIG. 117 is applied to, for example,
the combination of the Sony symbol (64 k, 9/15) and 64QAM of FIG.
91, a particularly excellent error rate can be achieved.
[2289] When the GW pattern of FIG. 118 is applied to, for example,
the combination of the Sony symbol (64 k, 11/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2290] When the GW pattern of FIG. 119 is applied to, for example,
the combination of the Sony symbol (64 k, 11/15) and 16QAM of FIG.
90, a particularly excellent error rate can be achieved.
[2291] When the GW pattern of FIG. 120 is applied to, for example,
the combination of the Sony symbol (64 k, 11/15) and 64QAM of FIG.
91, a particularly excellent error rate can be achieved.
[2292] When the GW pattern of FIG. 121 is applied to, for example,
the combination of the Sony symbol (64 k, 13/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2293] When the GW pattern of FIG. 122 is applied to, for example,
the combination of the Sony symbol (64 k, 13/15) and 16QAM of FIG.
90, a particularly excellent error rate can be achieved.
[2294] When the GW pattern of FIG. 123 is applied to, for example,
the combination of the Sony symbol (64 k, 13/15) and 64QAM of FIG.
91, a particularly excellent error rate can be achieved.
[2295] When the GW pattern of FIG. 124 is applied to, for example,
the combination of the ETRI symbol (64 k, 5/15) and 256QAM of FIGS.
92 and 93, a particularly excellent error rate can be achieved.
[2296] When the GW pattern of FIG. 125 is applied to, for example,
the combination of the ETRI symbol (64 k, 7/15) and 256QAM of FIGS.
92 and 93, a particularly excellent error rate can be achieved.
[2297] When the GW pattern of FIG. 126 is applied to, for example,
the combination of the Sony symbol (64 k, 7/15) and 256QAM of FIGS.
92 and 93, a particularly excellent error rate can be achieved.
[2298] When the GW pattern of FIG. 127 is applied to, for example,
the combination of the Sony symbol (64 k, 9/15) and 256QAM of FIGS.
92 and 93, a particularly excellent error rate can be achieved.
[2299] When the GW pattern of FIG. 128 is applied to, for example,
the combination of the NERC symbol (64 k, 9/15) and 256QAM of FIGS.
92 and 93, a particularly excellent error rate can be achieved.
[2300] When the GW pattern of FIG. 129 is applied to, for example,
the combination of the Sony symbol (64 k, 11/15) and 256QAM of
FIGS. 92 and 93, a particularly excellent error rate can be
achieved.
[2301] When the GW pattern of FIG. 130 is applied to, for example,
the combination of the Sony symbol (64 k, 13/15) and 256QAM of
FIGS. 92 and 93, a particularly excellent error rate can be
achieved.
[2302] When the GW pattern of FIG. 131 is applied to, for example,
the combination of the ETRI symbol (64 k, 5/15) and 1024QAM of
FIGS. 94 and 95, a particularly excellent error rate can be
achieved.
[2303] When the GW pattern of FIG. 132 is applied to, for example,
the combination of the ETRI symbol (64 k, 7/15) and 1024QAM of
FIGS. 94 and 95, a particularly excellent error rate can be
achieved.
[2304] When the GW pattern of FIG. 133 is applied to, for example,
the combination of the Sony symbol (64 k, 7/15) and 1024QAM of
FIGS. 94 and 95, a particularly excellent error rate can be
achieved.
[2305] When the GW pattern of FIG. 134 is applied to, for example,
the combination of the Sony symbol (64 k, 9/15) and 1024QAM of
FIGS. 94 and 95, a particularly excellent error rate can be
achieved.
[2306] When the GW pattern of FIG. 135 is applied to, for example,
the combination of the NERC symbol (64 k, 9/15) and 1024QAM of
FIGS. 94 and 95, a particularly excellent error rate can be
achieved.
[2307] When the GW pattern of FIG. 136 is applied to, for example,
the combination of the Sony symbol (64 k, 11/15) and 1024QAM of
FIGS. 94 and 95, a particularly excellent error rate can be
achieved.
[2308] When the GW pattern of FIG. 137 is applied to, for example,
the combination of the Sony symbol (64 k, 13/15) and 1024QAM of
FIGS. 94 and 95, a particularly excellent error rate can be
achieved.
[2309] When the GW pattern of FIG. 138 is applied to, for example,
the combination of the Samsung symbol (64 k, 6/15) and 4096QAM of
FIGS. 96 and 97, a particularly excellent error rate can be
achieved.
[2310] When the GW pattern of FIG. 139 is applied to, for example,
the combination of the ETRI symbol (64 k, 7/15) and 4096QAM of
FIGS. 96 and 97, a particularly excellent error rate can be
achieved.
[2311] When the GW pattern of FIG. 140 is applied to, for example,
the combination of the Samsung symbol (64 k, 8/15) and 4096QAM of
FIGS. 96 and 97, a particularly excellent error rate can be
achieved.
[2312] When the GW pattern of FIG. 141 is applied to, for example,
the combination of the Sony symbol (64 k, 9/15) and 4096QAM of
FIGS. 96 and 97, a particularly excellent error rate can be
achieved.
[2313] <Example of GW Pattern for LDPC Code of 16 k Bits>
[2314] FIG. 142 is an illustration of a 1st example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[2315] According to the GW pattern of FIG. 142, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2316] 21, 41, 15, 29, 0, 23, 16, 12, 38, 43, 2, 3, 4, 20, 31, 27,
5, 33, 28, 30, 36, 8, 40, 13, 6, 9, 18, 24, 7, 39, 10, 17, 37, 1,
19, 22, 25, 26, 14, 32, 34, 11, 35, 42, and 44.
[2317] FIG. 143 is an illustration of a 2nd example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[2318] According to the GW pattern of FIG. 143, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2319] 1, 3, 2, 8, 5, 23, 13, 12, 18, 19, 17, 20, 24, 26, 28, 30,
32, 34, 36, 38, 40, 42, 0, 4, 6, 7, 21, 16, 10, 15, 9, 11, 22, 14,
25, 27, 29, 31, 33, 35, 37, 39, 41, 43, and 44.
[2320] FIG. 144 is an illustration of a 3rd example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[2321] According to the GW pattern of FIG. 144, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2322] 1, 4, 5, 6, 24, 21, 18, 7, 17, 12, 8, 20, 23, 29, 28, 30,
32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22, 13, 10, 25, 9, 27, 19, 16,
15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and 44.
[2323] FIG. 145 is an illustration of a 4th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[2324] According to the GW pattern of FIG. 145, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2325] 3, 0, 4, 7, 18, 9, 19, 27, 32, 10, 12, 24, 8, 35, 30, 17,
22, 20, 36, 38, 40, 42, 2, 5, 1, 6, 14, 15, 23, 16, 11, 21, 26, 13,
29, 33, 31, 28, 25, 34, 37, 39, 41, 43, and 44.
[2326] FIG. 146 is an illustration of a 5th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[2327] According to the GW pattern of FIG. 146, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2328] 37, 0, 41, 19, 43, 8, 38, 3, 29, 13, 22, 6, 4, 2, 9, 26, 39,
15, 12, 10, 33, 17, 20, 16, 21, 44, 42, 27, 7, 11, 30, 34, 24, 1,
23, 35, 36, 25, 31, 18, 28, 32, 40, 5, and 14.
[2329] FIG. 147 is an illustration of a 6th example of a GW pattern
for an LDPC code in which a code length IN is 16 k bits.
[2330] According to the GW pattern of FIG. 147, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2331] 6, 28, 17, 4, 3, 38, 13, 41, 44, 43, 7, 40, 19, 2, 23, 16,
37, 15, 30, 20, 11, 8, 1, 27, 32, 34, 33, 39, 5, 9, 10, 18, 0, 31,
29, 26, 14, 21, 42, 22, 12, 24, 35, 25, and 36.
[2332] FIG. 148 is an illustration of a 7th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[2333] According to the GW pattern of FIG. 148, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2334] 27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13,
17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2,
40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38.
[2335] FIG. 149 is an illustration of an 8th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2336] According to the GW pattern of FIG. 149, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2337] 3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14,
11, 42, 16, 9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41,
38, 17, 25, 43, 35, 36, 13, 39, 12, 1, and 31.
[2338] FIG. 150 is an illustration of a 9th example of a GW pattern
for an LDPC code in which a code length N is 16 k bits.
[2339] According to the GW pattern of FIG. 150, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2340] 31, 38, 7, 9, 13, 21, 39, 12, 10, 1, 43, 15, 30, 0, 14, 3,
42, 34, 40, 24, 28, 35, 8, 11, 23, 4, 20, 17, 41, 19, 5, 37, 22,
32, 18, 2, 26, 44, 25, 33, 36, 27, 16, 6, and 29.
[2341] FIG. 151 is an illustration of a 10th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2342] According to the GW pattern of FIG. 151, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2343] 36, 6, 2, 20, 43, 17, 33, 22, 23, 25, 13, 0, 10, 7, 21, 1,
19, 26, 8, 14, 31, 35, 16, 5, 29, 40, 11, 9, 4, 34, 15, 42, 32, 28,
18, 37, 30, 39, 24, 41, 3, 38, 27, 12, and 44.
[2344] FIG. 152 is an illustration of a 11th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2345] According to the GW pattern of FIG. 152, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2346] 14, 22, 18, 11, 28, 26, 2, 38, 10, 0, 5, 12, 24, 17, 29, 16,
39, 13, 23, 8, 25, 43, 34, 33, 27, 15, 7, 1, 9, 35, 40, 32, 30, 20,
36, 31, 21, 41, 44, 3, 42, 6, 19, 37, and 4.
[2347] FIG. 153 is an illustration of a 12th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2348] According to the GW pattern of FIG. 153, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2349] 17, 11, 14, 7, 31, 10, 2, 26, 0, 32, 29, 22, 33, 12, 20, 28,
27, 39, 37, 15, 4, 5, 8, 13, 38, 18, 23, 34, 24, 6, 1, 9, 16, 44,
21, 3, 36, 30, 40, 35, 43, 42, 25, 19, and 41.
[2350] FIG. 154 is an illustration of a 13th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2351] According to the GW pattern of FIG. 154, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2352] 1, 27, 17, 30, 11, 15, 9, 7, 5, 6, 32, 33, 2, 14, 3, 39, 18,
12, 29, 13, 41, 31, 4, 43, 35, 34, 40, 10, 19, 44, 8, 26, 21, 16,
28, 0, 23, 38, 25, 36, 22, 37, 42, 24, and 20.
[2353] FIG. 155 is an illustration of a 14th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2354] According to the GW pattern of FIG. 155, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2355] 41, 2, 12, 6, 33, 1, 13, 11, 26, 10, 39, 43, 36, 23, 42, 7,
44, 20, 8, 38, 18, 22, 24, 40, 4, 28, 29, 19, 14, 5, 9, 0, 30, 25,
35, 37, 27, 32, 31, 34, 21, 3, 15, 17, and 16,
[2356] FIG. 156 is an illustration of a 15th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2357] According to the GW pattern of FIG. 156, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2358] 17, 2, 30, 12, 7, 25, 27, 3, 15, 14, 4, 26, 34, 31, 13, 22,
0, 39, 23, 24, 21, 6, 38, 5, 19, 42, 11, 32, 28, 40, 20, 18, 36, 9,
41, 10, 33, 37, 1, 16, 8, 43, 29, 35, and 44.
[2359] FIG. 157 is an illustration of a 16th example of a GW
pattern for an LDPC code in which a code length N is 16 k bits.
[2360] According to the GW pattern of FIG. 157, a sequence of bit
groups 0 to 44 of the LDPC code of 16 kbits is interleaved into a
sequence of bit groups
[2361] 28, 21, 10, 15, 8, 22, 26, 2, 14, 1, 27, 3, 39, 20, 34, 25,
12, 6, 7, 40, 30, 29, 38, 16, 43, 33, 4, 35, 9, 32, 5, 36, 0, 41,
37, 18, 17, 13, 24, 42, 31, 23, 19, 11, and 44.
[2362] The 1st to 16th examples of the GW pattern for the LDPC code
in which the code length N is 16 kbits can be applied to any
combination of the LDPC code in which the code length N is 16 kbits
with an arbitrary encoding rate r and modulation scheme
(constellation).
[2363] However, when the GW pattern to be applied to the group-wise
interleave is set for each combination of the code length N of the
LDPC code, the encoding rate r of the LDPC code, and the modulation
scheme (constellation), the error rate of each combination can be
further improved.
[2364] When the GW pattern of FIG. 142 is applied to, for example,
the combination of the LGE symbol (16 k, 6/15) and QPSK of FIG. 89,
a particularly excellent error rate can be achieved.
[2365] When the GW pattern of FIG. 143 is applied to, for example,
the combination of the Sony symbol (16 k, 8/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2366] When the GW pattern of FIG. 144 is applied to, for example,
the combination of the Sony symbol (16 k, 10/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2367] When the GW pattern of FIG. 145 is applied to, for example,
the combination of the Sony symbol (16 k, 12/15) and QPSK of FIG.
89, a particularly excellent error rate can be achieved.
[2368] When the GW pattern of FIG. 146 is applied to, for example,
the combination of the LGE symbol (16 k, 6/15) and 16QAM of FIG.
101, a particularly excellent error rate can be achieved.
[2369] When the GW pattern of FIG. 147 is applied to, for example,
the combination of the Sony symbol (16 k, 8/15) and 16QAM of FIG.
101, a particularly excellent error rate can be achieved.
[2370] When the GW pattern of FIG. 148 is applied to, for example,
the combination of the Sony symbol (16 k, 10/15) and 16QAM of FIG.
101, a particularly excellent error rate can be achieved.
[2371] When the GW pattern of FIG. 149 is applied to, for example,
the combination of the Sony symbol (16 k, 12/15) and 16QAM of FIG.
101, a particularly excellent error rate can be achieved.
[2372] When the GW pattern of FIG. 150 is applied to, for example,
the combination of the LGE symbol (16 k, 6/15) and 64QAM of FIG.
102, a particularly excellent error rate can be achieved.
[2373] When the GW pattern of FIG. 151 is applied to, for example,
the combination of the Sony symbol (16 k, 8/15) and 64QAM of FIG.
102 a particularly excellent error rate can be achieved.
[2374] When the GW pattern of FIG. 152 is applied to, for example,
the combination of the Sony symbol (16 k, 10/15) and 64QAM of FIG.
102 a particularly excellent error rate can be achieved.
[2375] When the GW pattern of FIG. 153 is applied to, for example,
the combination of the Sony symbol (16 k, 12/15) and 64QAM of FIG.
102 a particularly excellent error rate can be achieved.
[2376] When the GW pattern of FIG. 154 is applied to, for example,
the combination of the LGE symbol (16 k, 6/15) and 256QAM of FIGS.
103 and 104 a particularly excellent error rate can be
achieved.
[2377] When the GW pattern of FIG. 155 is applied to, for example,
the combination of the Sony symbol (16 k, 8/15) and 256QAM of FIGS.
103 and 104 a particularly excellent error rate can be
achieved.
[2378] When the GW pattern of FIG. 156 is applied to, for example,
the combination of the Sony symbol (16 k, 10/15) and 256QAM of
FIGS. 103 and 104 a particularly excellent error rate can be
achieved.
[2379] When the GW pattern of FIG. 157 is applied to, for example,
the combination of the Sony symbol (16 k, 12/15) and 256QAM of
FIGS. 103 and 104 a particularly excellent error rate can be
achieved.
[2380] <Simulation Result>
[2381] FIG. 158 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 109 is applied to a combination of the ETRI
symbol (64 k, 5/15) and QPSK of FIG. 89.
[2382] FIG. 159 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 110 is applied to a combination of the ETRI
symbol (64 k, 5/15) and 16QAM of FIG. 90.
[2383] FIG. 160 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 111 is applied to a combination of the ETRI
symbol (64 k, 5/15) and 64QAM of FIG. 91.
[2384] FIG. 161 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 112 is applied to a combination of the Sony
symbol (64 k, 7/15) and QPSK of FIG. 89.
[2385] FIG. 162 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 113 is applied to a combination of the Sony
symbol (64 k, 7/15) and 16QAM of FIG. 90.
[2386] FIG. 163 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 114 is applied to a combination of the Sony
symbol (64 k, 7/15) and 64QAM of FIG. 91.
[2387] FIG. 164 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 115 is applied to a combination of the Sony
symbol (64 k, 9/15) and QPSK of FIG. 89.
[2388] FIG. 165 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 116 is applied to a combination of the Sony
symbol (64 k, 9/15) and 16QAM of FIG. 90.
[2389] FIG. 166 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 117 is applied to a combination of the Sony
symbol (64 k, 9/15) and 64QAM of FIG. 91.
[2390] FIG. 167 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 118 is applied to a combination of the Sony
symbol (64 k, 11/15) and QPSK of FIG. 89.
[2391] FIG. 168 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 119 is applied to a combination of the Sony
symbol (64 k, 11/15) and 16QAM of FIG. 90.
[2392] FIG. 169 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 120 is applied to a combination of the Sony
symbol (64 k, 11/15) and 64QAM of FIG. 91.
[2393] FIG. 170 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 121 is applied to a combination of the Sony
symbol (64 k, 13/15) and QPSK of FIG. 89.
[2394] FIG. 171 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 122 is applied to a combination of the Sony
symbol (64 k, 13/15) and 16QAM of FIG. 90.
[2395] FIG. 172 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 123 is applied to a combination of the Sony
symbol (64 k, 13/15) and 64QAM of FIG. 91.
[2396] FIG. 173 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 124 is applied to a combination of the ETRI
symbol (64 k, 5/15) and 256QAM of FIGS. 92 and 93.
[2397] FIG. 174 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 125 is applied to a combination of the ETRI
symbol (64 k, 7/15) and 256QAM of FIGS. 92 and 93.
[2398] FIG. 175 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 126 is applied to a combination of the Sony
symbol (64 k, 7/15) and 256QAM of FIGS. 92 and 93.
[2399] FIG. 176 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 127 is applied to a combination of the Sony
symbol (64 k, 9/15) and 256QAM of FIGS. 92 and 93.
[2400] FIG. 177 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 128 is applied to a combination of the NERC
symbol (64 k, 9/15) and 256QAM of FIGS. 92 and 93.
[2401] FIG. 178 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 129 is applied to a combination of the Sony
symbol (64 k, 9/15) and 256QAM of FIGS. 92 and 93.
[2402] FIG. 179 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 130 is applied to a combination of the Sony
symbol (64 k, 13/15) and 256QAM of FIGS. 92 and 93.
[2403] FIG. 180 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 131 is applied to a combination of the ETRI
symbol (64 k, 5/15) and 1024QAM of FIGS. 94 and 95.
[2404] FIG. 181 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 132 is applied to a combination of the ETRI
symbol (64 k, 7/15) and 1024QAM of FIGS. 94 and 95.
[2405] FIG. 182 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 133 is applied to a combination of the Sony
symbol (64 k, 7/15) and 1024QAM of FIGS. 94 and 95.
[2406] FIG. 183 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 134 is applied to a combination of the Sony
symbol (64 k, 9/15) and 1024QAM of FIGS. 94 and 95.
[2407] FIG. 184 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 135 is applied to a combination of the NERC
symbol (64 k, 9/15) and 1024QAM of FIGS. 94 and 95
[2408] FIG. 185 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 136 is applied to a combination of the Sony
symbol (64 k, 11/15) and 1024QAM of FIGS. 94 and 95.
[2409] FIG. 186 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 137 is applied to a combination of the Sony
symbol (64 k, 13/15) and 1024QAM of FIGS. 94 and 95.
[2410] FIG. 187 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 138 is applied to a combination of the
Samsung symbol (64 k, 6/15) and 4096QAM of FIGS. 96 and 97.
[2411] FIG. 188 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 139 is applied to a combination of the ETRI
symbol (64 k, 7/15) and 4096QAM of FIGS. 96 and 97.
[2412] FIG. 189 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 140 is applied to a combination of the
Samsung symbol (64 k, 8/15) and 4096QAM of FIGS. 96 and 97.
[2413] FIG. 190 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 141 is applied to a combination of the Sony
symbol (64 k, 9/15) and 4096QAM of FIGS. 96 and 97.
[2414] FIG. 191 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 142 is applied to a combination of the LGE
symbol (16 k, 6/15) and QPSK of FIG. 89.
[2415] FIG. 192 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 143 is applied to a combination of the Sony
symbol (16 k, 8/15) and QPSK of FIG. 89.
[2416] FIG. 193 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 144 is applied to a combination of the Sony
symbol (16 k, 10/15) and QPSK of FIG. 89.
[2417] FIG. 194 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 145 is applied to a combination of the Sony
symbol (16 k, 12/15) and QPSK of FIG. 89.
[2418] FIG. 195 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 146 is applied to a combination of the LGE
symbol (16 k, 6/15) and 16QAM of FIG. 101.
[2419] FIG. 196 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 147 is applied to a combination of the Sony
symbol (16 k, 8/15) and 16QAM of FIG. 101.
[2420] FIG. 197 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 148 is applied to a combination of the Sony
symbol (16 k, 10/15) and 16QAM of FIG. 101.
[2421] FIG. 198 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 149 is applied to a combination of the Sony
symbol (16 k, 12/15) and 16QAM of FIG. 101.
[2422] FIG. 199 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 150 is applied to a combination of the LGE
symbol (16 k, 6/15) and 64QAM of FIG. 102.
[2423] FIG. 200 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 151 is applied to a combination of the Sony
symbol (16 k, 8/15) and 64QAM of FIG. 102.
[2424] FIG. 201 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 152 is applied to a combination of the Sony
symbol (16 k, 10/15) and 64QAM of FIG. 102.
[2425] FIG. 202 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 153 is applied to a combination of the Sony
symbol (16 k, 12/15) and 64QAM of FIG. 102.
[2426] FIG. 203 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 154 is applied to a combination of the LGE
symbol (16 k, 6/15) and 256QAM of FIGS. 103 and 104.
[2427] FIG. 204 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 155 is applied to a combination of the Sony
symbol (16 k, 8/15) and 256QAM of FIGS. 103 and 104.
[2428] FIG. 205 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 156 is applied to a combination of the Sony
symbol (16 k, 10/15) and 256QAM of FIGS. 103 and 104.
[2429] FIG. 206 is an illustration of a BER/FER curve indicating a
simulation result of a simulation of measuring the error rate when
the GW pattern of FIG. 157 is applied to a combination of the Sony
symbol (16 k, 12/15) and 256QAM of FIGS. 103 and 104.
[2430] FIGS. 158 to 206 illustrate BER/FER curves when an AWGN
channel is employed as the communication path 13 (FIG. 7) (the
upper drawings) and BER/FER curves when a Rayleigh (fading) channel
is employed as the communication path 13 (FIG. 7) (the lower
drawings).
[2431] In FIGS. 158 to 206, "w bil" indicates a BER/FER curve when
the parity interleave, the group-wise interleave, and the
block-wise interleave are performed, and "w/o bil" indicates a
BER/FER curve when the parity interleave, the group-wise
interleave, and the block-wise interleave are not performed.
[2432] As can be seen from FIGS. 158 to 206, when the parity
interleave, the group-wise interleave, and the block-wise
interleave are performed, it is possible to improve the BER/FER and
achieve the excellent the error rate compared to when they are not
performed.
[2433] Further, it is possible to apply the GW patterns of FIGS.
109 to 157 to the constellation in which the signal point
arrangements illustrated in FIGS. 83 to 104 have been moved
symmetrically to the I axis or the Q axis, the constellation in
which the signal point arrangements illustrated in FIGS. 83 to 104
have been moved symmetrically to the origin, the constellation in
which the signal point arrangements illustrated in FIGS. 83 to 104
have been rotated at an arbitrary angle centering on the origin,
and the like in addition to the constellation of QPSK, 16QAM,
64QAM, 256QAM, 1024QAM, and 4096QAM of the signal point
arrangements illustrated in FIGS. 83 to 104, and it is possible to
obtain the same effects as when the GW patterns of FIGS. 109 to 157
are applied to the constellation of QPSK, 16QAM, 64QAM, 256QAM,
1024QAM, and 4096QAM of the signal point arrangements illustrated
in FIGS. 83 to 104.
[2434] Further, it is possible to apply the GW pattern of FIGS. 109
to 157 to the constellation in which the most significant bit (MSB)
and the least significant bit (LSB) of the symbol to be associated
with (allocated to) the signal point are interchanged in the signal
point arrangements illustrated in FIGS. 83 to 104 in addition to
the constellation of QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and
4096QAM of the signal point arrangements illustrated in FIGS. 83 to
104, and it is possible to obtain the same effects as when the GW
patterns of FIGS. 109 to 157 are applied to the constellation of
QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM of the signal
point arrangements illustrated in FIGS. 83 to 104 as well.
[2435] <Configuration Example of Receiving Device 12>
[2436] FIG. 207 is a block diagram illustrating a configuration
example of the receiving device 12 of FIG. 7.
[2437] An OFDM operating unit 151 receives an OFDM signal from the
transmitting device 11 (FIG. 7) and executes signal processing of
the OFDM signal. Data that is obtained by executing the signal
processing by the OFDM operating unit 151 is supplied to a frame
managing unit 152.
[2438] The frame managing unit 152 executes processing (frame
interpretation) of a frame configured by the data supplied from the
OFDM operating unit 151 and supplies a signal of target data
obtained as a result and a signal of signaling to frequency
deinterleavers 161 and 153.
[2439] The frequency deinterleaver 153 performs frequency
deinterleave in a unit of symbol, with respect to the data supplied
from the frame managing unit 152, and supplies the symbol to a
demapper 154.
[2440] The demapper 154 performs demapping (signal point
arrangement decoding) and orthogonal demodulation on the data (the
data on the constellation) supplied from the frequency
deinterleaver 153 based on the arrangement (constellation) of the
signal points decided according to the orthogonal modulation
performed at the transmitting device 11 side, and supplies the data
((the likelihood of) the LDPC code) obtained as a result to the
LDPC decoder 155.
[2441] The LDPC decoder 155 performs LDPC decoding of the LDPC code
supplied from the demapper 154 and supplies LDPC target data (in
this case, a BCH code) obtained as a result to a BCH decoder
156.
[2442] The BCH decoder 156 performs BCH decoding of the LDPC target
data supplied from the LDPC decoder 155 and outputs control data
(signaling) obtained as a result.
[2443] Meanwhile, the frequency deinterleaver 161 performs
frequency deinterleave in a unit of symbol, with respect to the
data supplied from the frame managing unit 152, and supplies the
symbol to a SISO/MISO decoder 162.
[2444] The SISO/MISO decoder 162 performs spatiotemporal decoding
of the data supplied from the frequency deinterleaver 161 and
supplies the data to a time deinterleaver 163.
[2445] The time deinterleaver 163 performs time deinterleave in a
unit of symbol, with respect to the data supplied from the
SISO/MISO decoder 162, and supplies the data to a demapper 164.
[2446] The demapper 164 performs demapping (signal point
arrangement decoding) and orthogonal demodulation on the data (the
data on the constellation) supplied from the time deinterleaver 163
based on the arrangement (constellation) of the signal points
decided according to the orthogonal modulation performed at the
transmitting device 11 side, and supplies the data obtained as a
result to a bit deinterleaver 165.
[2447] The bit deinterleaver 165 perform the bit deinterleave on
the data supplied from the demapper 164, and supplies (the
likelihood of) the LDPC code serving as the data that has undergone
the bit deinterleave to an LDPC decoder 166.
[2448] The LDPC decoder 166 performs LDPC decoding of the LDPC code
supplied from the bit deinterleaver 165 and supplies LDPC target
data (in this case, a BCH code) obtained as a result to a BCH
decoder 167.
[2449] The BCH decoder 167 performs BCH decoding of the LDPC target
data supplied from the LDPC decoder 155 and supplies data obtained
as a result to a BB descrambler 168.
[2450] The BB descrambler 168 executes BB descramble with respect
to the data supplied from the BCH decoder 167 and supplies data
obtained as a result to a null deletion unit 169.
[2451] The null deletion unit 169 deletes null inserted by the
padder 112 of FIG. 8, from the data supplied from the BB
descrambler 168, and supplies the data to a demultiplexer 170.
[2452] The demultiplexer 170 individually separates one or more
streams (target data) multiplexed with the data supplied from the
null deletion unit 169, performs necessary processing to output the
streams as output streams.
[2453] Here, the receiving device 12 can be configured without
including part of the blocks illustrated in FIG. 207. That is, for
example, in a case where the transmitting device 11 (FIG. 8) is
configured without including the time interleaver 118, the
SISO/MISO encoder 119, the frequency interleaver 120 and the
frequency interleaver 124, the receiving device 12 can be
configured without including the time deinterleaver 163, the
SISO/MISO decoder 162, the frequency deinterleaver 161 and the
frequency deinterleaver 153 which are blocks respectively
corresponding to the time interleaver 118, the SISO/MISO encoder
119, the frequency interleaver 120 and the frequency interleaver
124 of the transmitting device 11.
[2454] <Configuration Example of Bit Deinterleaver 165>
[2455] FIG. 208 is a block diagram illustrating a configuration
example of the bit deinterleaver 165 of FIG. 207.
[2456] The bit deinterleaver 165 is configured with a block
deinterleaver 54 and a group-wise deinterleaver 55, and performs
the (bit) deinterleave of the symbol bits of the symbol serving as
the data supplied from the demapper 164 (FIG. 207).
[2457] In other words, the block deinterleaver 54 performs the
block deinterleave (the inverse process of the block interleave)
corresponding to the block interleave performed by the block
interleaver 25 of FIG. 9, that is, the block deinterleave of
restoring the positions of (the likelihood of) of the code bits of
the LDPC code rearranged by the block interleave to the original
positions on the symbol bits of the symbol supplied from the
demapper 164, and supplies the LDPC code obtained as a result to
the group-wise deinterleaver 55.
[2458] The group-wise deinterleaver 55 performs the group-wise
deinterleave (the inverse process of the group-wise interleave)
corresponding to the group-wise interleave performed by the
group-wise interleaver 24 of FIG. 9, that is, the group-wise
deinterleave of restoring the original sequence by rearranging the
code bits of the LDPC code whose sequence has been changed in units
of bit groups by the group-wise interleave described above, for
example, with reference to FIG. 108 in units of bit groups on the
LDPC code supplied from the block deinterleaver 54
[2459] Here, when the LDPC code supplied from the demapper 164 to
the bit deinterleaver 165 has undergone the parity interleave, the
group-wise interleave, and the block interleave, the bit
deinterleaver 165 can perform all of the parity deinterleave (the
inverse process of the parity interleave, that is, the parity
deinterleave of restoring the code bits of the LDPC code whose
sequence has been changed by the parity interleave to the original
sequence) corresponding to the parity interleave, the block
deinterleave corresponding to the block interleave, and the
group-wise deinterleave corresponding to the group-wise
interleave.
[2460] However, the bit deinterleaver 165 of FIG. 208 is provided
with the block deinterleaver 54 that performs the block
deinterleave corresponding to the block interleave and the
group-wise deinterleaver 55 that performs the group-wise
deinterleave corresponding to the group-wise interleave, but no
block that performs the parity deinterleave corresponding to the
parity interleave is provided, and thus the parity deinterleave is
not performed.
[2461] Thus, the LDPC code that has undergone the block
deinterleave and group-wise deinterleave but has not undergone the
parity deinterleave is supplied from (the group-wise deinterleaver
55 of) the bit deinterleaver 165 to the LDPC decoder 166.
[2462] The LDPC decoder 166 performs LDPC decoding of the LDPC code
supplied from the bit deinterleaver 165 using the transformed
parity check matrix obtained by performing at least the column
permutation corresponding to the parity interleave on the parity
check matrix H of the DVB scheme used for the LDPC encoding by the
LDPC encoder 115 of FIG. 8 (or the transformed parity check matrix
(FIG. 29) obtained by performing the row permutation on the parity
check matrix of the ETRI scheme (FIG. 27)), and outputs data
obtained as a result as a decoding result of LDPC target data.
[2463] FIG. 209 is a flowchart illustrating a process performed by
the demapper 164, the bit deinterleaver 165, and the LDPC decoder
166 of FIG. 208.
[2464] In step S111, the demapper 164 performs demapping and
orthogonal demodulation on the data (the data on the constellation
mapped to the signal points) supplied from the time deinterleaver
163, and supplies the resulting data to the bit deinterleaver 165,
and the process proceeds to step S112.
[2465] In step S112, the bit deinterleaver 165 performs the
deinterleave (the bit deinterleave) on the data supplied from the
demapper 164, and the process proceeds to step S113.
[2466] In other words, in step S112, in the bit deinterleaver 165,
the block deinterleaver 54 performs the block deinterleave on the
data (symbol) supplied from the demapper 164, and supplies the code
bits of the LDPC code obtained as a result to the group-wise
deinterleaver 55.
[2467] The group-wise deinterleaver 55 performs the group-wise
deinterleave on the LDPC code supplied from the block deinterleaver
54, and supplies (the likelihood of) the LDPC code obtained as a
result to the LDPC decoder 166.
[2468] In step S113, the LDPC decoder 166 performs LDPC decoding of
the LDPC code supplied from the group-wise deinterleaver 55 using
the parity check matrix H used for the LDPC encoding by the LDPC
encoder 115 of FIG. 8, that is, using the transformed parity check
matrix obtained from the parity check matrix H, for example, and
outputs the data obtained as a result to the BCH decoder 167 as a
decoding result of the LDPC target data.
[2469] In FIG. 208, similarly to the example of FIG. 9, for the
sake of convenience of description, the block deinterleaver 54 that
performs the block deinterleave and the group-wise deinterleaver 55
that performs the group-wise deinterleave are configured
individually, but the block deinterleaver 54 and the group-wise
deinterleaver 55 may be configured integrally.
[2470] <LDPC Decoding>
[2471] The LDPC decoding performed by the LDPC decoder 166 of FIG.
207 will be described.
[2472] As described above, the LDPC decoder 166 of FIG. 207
performs the LDPC decoding of the LDPC code that is supplied from
the bit deinterleaver 165 and has undergone the block deinterleave
and the group-wise deinterleave but has not undergone the parity
deinterleave using the transformed parity check matrix obtained by
performing at least the column permutation corresponding to the
parity interleave on the parity check matrix H of the DVB scheme
used for the LDPC encoding by the LDPC encoder 115 of FIG. 8 (or
the transformed parity check matrix (FIG. 29) obtained by
performing the row permutation on the parity check matrix of the
ETRI scheme (FIG. 27)).
[2473] In this case, LDPC decoding that can suppress an operation
frequency at a sufficiently realizable range while suppressing a
circuit scale, by performing the LDPC decoding using the
transformed parity check matrix, is previously suggested (for
example, refer to JP 4224777B).
[2474] Therefore, first, the previously suggested LDPC decoding
using the transformed parity check matrix will be described with
reference to FIGS. 210 to 213.
[2475] FIG. 210 illustrates an example of a parity check matrix H
of an LDPC code in which a code length N is 90 and an encoding rate
is 2/3.
[2476] In FIG. 210 (and FIGS. 211 and 212 to be described later), 0
is represented by a period (.).
[2477] In the parity check matrix H of FIG. 210, the parity matrix
becomes a staircase structure.
[2478] FIG. 211 illustrates a parity check matrix that is obtained
by executing row replacement of an expression (11) and column
replacement of an expression (12) with respect to the parity check
matrix H of FIG. 210.
Row Replacement: (6s+t+1)-th row.fwdarw.(5t+s+1)-th row (11)
Column Replacement: (6x+y+61)-th column.fwdarw.(5y+x+61)-th column
(12)
[2479] In the expressions (11) and (12), s, t, x, and y are
integers in ranges of 0.ltoreq.s<5, 0.ltoreq.t<6,
0.ltoreq.x<5, and 0.ltoreq.t.ltoreq.6, respectively.
[2480] According to the row replacement of the expression (11),
replacement is performed such that the 1st, 7th, 13rd, 19th, and
25th rows having remainders of 1 when being divided by 6 are
replaced with the 1st, 2nd, 3rd, 4th, and 5th rows, and the 2nd,
8th, 14th, 20th, and 26th rows having remainders of 2 when being
divided by 6 are replaced with the 6th, 7th, 8th, 9th, and 10th
rows, respectively.
[2481] According to the column replacement of the expression (12),
replacement is performed such that the 61st, 67th, 73rd, 79th, and
85th columns having remainders of 1 when being divided by 6 are
replaced with the 61st, 62nd, 63rd, 64th, and 65th columns,
respectively, and the 62nd, 68th, 74th, 80th, and 86th columns
having remainders of 2 when being divided by 6 are replaced with
the 66th, 67th, 68th, 69th, and 70th columns, respectively, with
respect to the 61st and following columns (parity matrix).
[2482] In this way, a matrix that is obtained by performing the
replacements of the rows and the columns with respect to the parity
check matrix H of FIG. 210 is a parity check matrix H' of FIG.
211.
[2483] In this case, even when the row replacement of the parity
check matrix H is performed, the sequence of the code bits of the
LDPC code is not influenced.
[2484] The column replacement of the expression (12) corresponds to
parity interleave to interleave the (K+qx+y+1)-th code bit into the
position of the (K+Py+x+1)-th code bit, when the information length
K is 60, the unit size P is 5, and the divisor q (=M/P) of the
parity length M (in this case, 30) is 6.
[2485] Therefore, the parity check matrix H' in FIG. 211 is a
transformed parity check matrix obtained by performing at least
column replacement that replaces the K+qx+y+1-th column of the
parity check matrix H in FIG. 210 (which may be arbitrarily called
an original parity check matrix below) with the K+Py+x+1-th
column.
[2486] If the parity check matrix H' of FIG. 211 is multiplied with
a result obtained by performing the same replacement as the
expression (12) with respect to the LDPC code of the parity check
matrix H of FIG. 210, a zero vector is output. That is, if a row
vector obtained by performing the column replacement of the
expression (12) with respect to a row vector c as the LDPC code
(one code word) of the original parity check matrix H is
represented as c', HcT becomes the zero vector from the property of
the parity check matrix. Therefore, H'c'T naturally becomes the
zero vector.
[2487] Thereby, the transformed parity check matrix H' of FIG. 211
becomes a parity check matrix of an LDPC code c' that is obtained
by performing the column replacement of the expression (12) with
respect to the LDPC code c of the original parity check matrix
H.
[2488] Therefore, the column replacement of the expression (12) is
performed with respect to the LDPC code of the original parity
check matrix H, the LDPC code c' after the column replacement is
decoded (LDPC decoding) using the transformed parity check matrix
H' of FIG. 211, reverse replacement of the column replacement of
the expression (12) is performed with respect to a decoding result,
and the same decoding result as the case in which the LDPC code of
the original parity check matrix H is decoded using the parity
check matrix H can be obtained.
[2489] FIG. 212 illustrates the transformed parity check matrix H'
of FIG. 211 with being spaced in units of 5.times.5 matrixes.
[2490] In FIG. 212, the transformed parity check matrix H' is
represented by a combination of a 5.times.5 (=p.times.p) unit
matrix that is a unit size P, a matrix (hereinafter, appropriately
referred to as a quasi unit matrix) obtained by setting one or more
1 of the unit matrix to zero, a matrix (hereinafter, appropriately
referred to as a shifted matrix) obtained by cyclically shifting
the unit matrix or the quasi unit matrix, a sum (hereinafter,
appropriately referred to as a sum matrix) of two or more matrixes
of the unit matrix, the quasi unit matrix, and the shifted matrix,
and a 5.times.5 zero matrix.
[2491] The transformed parity check matrix H' of FIG. 212 can be
configured using the 5.times.5 unit matrix, the quasi unit matrix,
the shifted matrix, the sum matrix, and the zero matrix. Therefore,
the 5.times.5 matrixes (the unit matrix, the quasi unit matrix, the
shifted matrix, the sum matrix, and the zero matrix) that
constitute the transformed parity check matrix H' are appropriately
referred to as constitutive matrixes hereinafter.
[2492] When the LDPC code represented by the parity check matrix
represented by the P.times.P constitutive matrixes is decoded, an
architecture in which P check node operations and variable node
operations are simultaneously performed can be used.
[2493] FIG. 213 is a block diagram illustrating a configuration
example of a decoding device that performs the decoding.
[2494] That is, FIG. 213 illustrates the configuration example of
the decoding device that performs decoding of the LDPC code, using
the transformed parity check matrix H' of FIG. 210 obtained by
performing at least the column replacement of the expression (12)
with respect to the original parity check matrix H of FIG. 212.
[2495] The decoding device of FIG. 213 includes a branch data
storing memory 300 that includes 6 FIFOs 300.sub.1 to 300.sub.6, a
selector 301 that selects the FIFOs 300.sub.1 to 300.sub.6, a check
node calculating unit 302, two cyclic shift circuits 303 and 308, a
branch data storing memory 304 that includes 18 FIFOs 304.sub.1 to
304.sub.18, a selector 305 that selects the FIFOs 304.sub.1 to
304.sub.18, a reception data memory 306 that stores reception data,
a variable node calculating unit 307, a decoding word calculating
unit 309, a reception data rearranging unit 310, and a decoded data
rearranging unit 311.
[2496] First, a method of storing data in the branch data storing
memories 300 and 304 will be described.
[2497] The branch data storing memory 300 includes the 6 FIFOs
300.sub.1 to 300.sub.6 that correspond to a number obtained by
dividing a row number 30 of the transformed parity check matrix H'
of FIG. 212 by a row number 5 of the constitutive matrix (the unit
size P). The FIFO 300.sub.y (y=1, 2, . . . , and 6) includes a
plurality of steps of storage regions. In the storage region of
each step, messages corresponding to five branches to be a row
number and a column number of the constitutive matrix (the unit
size P) can be simultaneously read or written. The number of steps
of the storage regions of the FIFO 300.sub.y becomes 9 to be a
maximum number of the number (Hamming weight) of 1 of a row
direction of the transformed parity check matrix of FIG. 212.
[2498] In the FIFO 300.sub.1, data (messages v.sub.i from variable
nodes) corresponding to positions of 1 in the first to fifth rows
of the transformed parity check matrix H' of FIG. 212 is stored in
a form filling each row in a transverse direction (a form in which
0 is ignored). That is, if a j-th row and an i-th column are
represented as (j, i), data corresponding to positions of 1 of a
5.times.5 unit matrix of (1, 1) to (5, 5) of the transformed parity
check matrix H' is stored in the storage region of the first step
of the FIFO 300.sub.1. In the storage region of the second step,
data corresponding to positions of 1 of a shifted matrix (shifted
matrix obtained by cyclically shifting the 5.times.5 unit matrix to
the right side by 3) of (1, 21) to (5, 25) of the transformed
parity check matrix H' is stored. Similar to the above case, in the
storage regions of the third to eighth steps, data is stored in
association with the transformed parity check matrix H'. In the
storage region of the ninth step, data corresponding to positions
of 1 of a shifted matrix (shifted matrix obtained by replacing 1 of
the first row of the 5.times.5 unit matrix with 0 and cyclically
shifting the unit matrix to the left side by 1) of (1, 86) to (5,
90) of the transformed parity check matrix H' is stored.
[2499] In the FIFO 300.sub.2, data corresponding to positions of 1
in the sixth to tenth rows of the transformed parity check matrix
H' of FIG. 212 is stored. That is, in the storage region of the
first step of the FIFO 300.sub.2, data corresponding to positions
of 1 of the first shifted matrix constituting a sum matrix (sum
matrix to be a sum of the first shifted matrix obtained by
cyclically shifting the 5.times.5 unit matrix to the right side by
1 and the second shifted matrix obtained by cyclically shifting the
5.times.5 unit matrix to the right side by 2) of (6, 1) to (10, 5)
of the transformed parity check matrix H' is stored. In addition,
in the storage region of the second step, data corresponding to
positions of 1 of the second shifted matrix constituting the sum
matrix of (6, 1) to (10, 5) of the transformed parity check matrix
H' is stored.
[2500] That is, with respect to a constitutive matrix of which the
weight is two or more, when the constitutive matrix is represented
by a sum of multiple parts of a P.times.P unit matrix of which the
weight is 1, a quasi unit matrix in which one or more elements of 1
in the unit matrix become 0, or a shifted matrix obtained by
cyclically shifting the unit matrix or the quasi unit matrix, data
(messages corresponding to branches belonging to the unit matrix,
the quasi unit matrix, or the shifted matrix) corresponding to the
positions of 1 in the unit matrix of the weight of 1, the quasi
unit matrix, or the shifted matrix is stored at the same address
(the same FIFO among the FIFOs 300.sub.1 to 300.sub.6).
[2501] Subsequently, in the storage regions of the third to ninth
steps, data is stored in association with the transformed parity
check matrix H', similar to the above case.
[2502] In the FIFOs 300.sub.3 to 300.sub.6, data is stored in
association with the transformed parity check matrix H', similar to
the above case.
[2503] The branch data storing memory 304 includes 18 FIFOs
304.sub.1 to 304.sub.18 that correspond to a number obtained by
dividing a column number 90 of the transformed parity check matrix
H' by 5 to be a column number of a constitutive matrix (the unit
size P). The FIFO 304.sub.x (x=1, 2, . . . , and 18) includes a
plurality of steps of storage regions. In the storage region of
each step, messages corresponding to five branches corresponding to
a row number and a column number of the constitutive matrix (the
unit size P) can be simultaneously read or written.
[2504] In the FIFO 304.sub.1, data (messages u.sub.j from check
nodes) corresponding to positions of 1 in the first to fifth
columns of the transformed parity check matrix H' of FIG. 212 is
stored in a form filling each column in a longitudinal direction (a
form in which 0 is ignored). That is, if a j-th row and an i-th
column are represented as (j, i), data corresponding to positions
of 1 of a 5.times.5 unit matrix of (1, 1) to (5, 5) of the
transformed parity check matrix H' is stored in the storage region
of the first step of the FIFO 304.sub.1. In the storage region of
the second step, data corresponding to positions of 1 of the first
shifted matrix constituting a sum matrix (sum matrix to be a sum of
the first shifted matrix obtained by cyclically shifting the
5.times.5 unit matrix to the right side by 1 and the second shifted
matrix obtained by cyclically shifting the 5.times.5 unit matrix to
the right side by 2) of (6, 1) to (10, 5) of the transformed parity
check matrix H' is stored. In addition, in the storage region of
the third step, data corresponding to positions of 1 of the second
shifted matrix constituting the sum matrix of (6, 1) to (10, 5) of
the transformed parity check matrix H' is stored.
[2505] That is, with respect to a constitutive matrix of which the
weight is two or more, when the constitutive matrix is represented
by a sum of multiple parts of a P.times.P unit matrix of which the
weight is 1, a quasi unit matrix in which one or more elements of 1
in the unit matrix become 0, or a shifted matrix obtained by
cyclically shifting the unit matrix or the quasi unit matrix, data
(messages corresponding to branches belonging to the unit matrix,
the quasi unit matrix, or the shifted matrix) corresponding to the
positions of 1 in the unit matrix of the weight of 1, the quasi
unit matrix, or the shifted matrix is stored at the same address
(the same FIFO among the FIFOs 304.sub.1 to 304.sub.18)
[2506] Subsequently, in the storage regions of the fourth and fifth
steps, data is stored in association with the transformed parity
check matrix H', similar to the above case. The number of steps of
the storage regions of the FIFO 304.sub.1 becomes 5 to be a maximum
number of the number (Hamming weight) of 1 of a row direction in
the first to fifth columns of the transformed parity check matrix
H'.
[2507] In the FIFOs 304.sub.2 and 304.sub.3, data is stored in
association with the transformed parity check matrix H', similar to
the above case, and each length (the number of steps) is 5. In the
FIFOs 304.sub.4 to 304.sub.12, data is stored in association with
the transformed parity check matrix H', similar to the above case,
and each length is 3. In the FIFOs 304.sub.13 to 304.sub.18, data
is stored in association with the transformed parity check matrix
H', similar to the above case, and each length is 2.
[2508] Next, an operation of the decoding device of FIG. 213 will
be described.
[2509] The branch data storing memory 300 includes the 6 FIFOs
300.sub.1 to 300.sub.6. According to information (matrix data) D312
on which row of the transformed parity check matrix H' in FIG. 212
five messages D311 supplied from a cyclic shift circuit 308 of a
previous step belongs to, the FIFO storing data is selected from
the FIFOs 300.sub.1 to 300.sub.6 and the five messages D311 are
collectively stored sequentially in the selected FIFO. When the
data is read, the branch data storing memory 300 sequentially reads
the five messages D300.sub.1 from the FIFO 300.sub.1 and supplies
the messages to the selector 301 of a next step. After reading of
the messages from the FIFO 300.sub.1 ends, the branch data storing
memory 300 reads the messages sequentially from the FIFOs 300.sub.2
to 300.sub.6 and supplies the messages to the selector 301.
[2510] The selector 301 selects the five messages from the FIFO
from which data is currently read, among the FIFOs 300.sub.1 to
300.sub.6, according to a select signal D301, and supplies the
selected messages as messages D302 to the check node calculating
unit 302.
[2511] The check node calculating unit 302 includes five check node
calculators 302.sub.1 to 302.sub.5. The check node calculating unit
302 performs a check node operation according to the expression
(7), using the messages D302 (D302.sub.1 to D302.sub.5) (messages
v.sub.i of the expression 7) supplied through the selector 301, and
supplies five messages D303 (D303.sub.1 to D303.sub.5) (messages
u.sub.j of the expression (7)) obtained as a result of the check
node operation to a cyclic shift circuit 303.
[2512] The cyclic shift circuit 303 cyclically shifts the five
messages D303.sub.1 to D303.sub.5 calculated by the check node
calculating unit 302, on the basis of information (matrix data)
D305 on how many the unit matrixes (or the quasi unit matrix)
becoming the origin in the transformed parity check matrix H' are
cyclically shifted to obtain the corresponding branches, and
supplies a result as messages D304 to the branch data storing
memory 304.
[2513] The branch data storing memory 304 includes the eighteen
FIFOs 304.sub.1 to 304.sub.18. According to information D305 on
which row of the transformed parity check matrix H' five messages
D304 supplied from a cyclic shift circuit 303 of a previous step
belongs to, the FIFO storing data is selected from the FIFOs
304.sub.1 to 304.sub.18 and the five messages D304 are collectively
stored sequentially in the selected FIFO. When the data is read,
the branch data storing memory 304 sequentially reads the five
messages D304.sub.1 from the FIFO 304.sub.1 and supplies the
messages to the selector 305 of a next step. After reading of the
messages from the FIFO 304.sub.1 ends, the branch data storing
memory 304 reads the messages sequentially from the FIFOs 304.sub.2
to 304.sub.18 and supplies the messages to the selector 305.
[2514] The selector 305 selects the five messages from the FIFO
from which data is currently read, among the FIFOs 304.sub.1 to
304.sub.18, according to a select signal D307, and supplies the
selected messages as messages D308 to the variable node calculating
unit 307 and the decoding word calculating unit 309.
[2515] Meanwhile, the reception data rearranging unit 310
rearranges the LDPC code D313, that is corresponding to the parity
check matrix H in FIG. 210, received through the communication path
13 by performing the column replacement of the expression (12) and
supplies the LDPC code as reception data D314 to the reception data
memory 306. The reception data memory 306 calculates a reception
LLR (Log Likelihood Ratio) from the reception data D314 supplied
from the reception data rearranging unit 310, stores the reception
LLR, collects five reception LLRs, and supplies the reception LLRs
as reception values D309 to the variable node calculating unit 307
and the decoding word calculating unit 309.
[2516] The variable node calculating unit 307 includes five
variable node calculators 307.sub.1 to 307.sub.5. The variable node
calculating unit 307 performs the variable node operation according
to the expression (1), using the messages D308 (D308.sub.1 to
D308.sub.5) (messages u.sub.j of the expression (1)) supplied
through the selector 305 and the five reception values D309
(reception values u.sub.0i of the expression (1)) supplied from the
reception data memory 306, and supplies messages D310 (D310.sub.1
to D310.sub.5) (message v.sub.i of the expression (1)) obtained as
an operation result to the cyclic shift circuit 308.
[2517] The cyclic shift circuit 308 cyclically shifts the messages
D310.sub.1 to D310.sub.5 calculated by the variable node
calculating unit 307, on the basis of information on how many the
unit matrixes (or the quasi unit matrix) becoming the origin in the
transformed parity check matrix H' are cyclically shifted to obtain
the corresponding branches, and supplies a result as messages D311
to the branch data storing memory 300.
[2518] By circulating the above operation in one cycle, decoding
(variable node operation and check node operation) of the LDPC code
can be performed once. After decoding the LDPC code by the
predetermined number of times, the decoding device of FIG. 213
calculates a final decoding result and outputs the final decoding
result, in the decoding word calculating unit 309 and the decoded
data rearranging unit 311.
[2519] That is, the decoding word calculating unit 309 includes
five decoding word calculators 309.sub.1 to 309.sub.5. The decoding
word calculating unit 309 calculates a decoding result (decoding
word) on the basis of the expression (5), as a final step of
multiple decoding, using the five messages D308 (D308.sub.1 to
D308.sub.5) (messages u.sub.j of the expression) output by the
selector 305 and the five reception values D309 (reception values
u.sub.0i of the expression (5)) supplied from the reception data
memory 306, and supplies decoded data D315 obtained as a result to
the decoded data rearranging unit 311.
[2520] The decoded data rearranging unit 311 performs the reverse
replacement of the column replacement of the expression (12) with
respect to the decoded data D315 supplied from the decoding word
calculating unit 309, rearranges the order thereof, and outputs the
decoded data as a final decoding result D316.
[2521] As mentioned above, by performing one or both of row
replacement and column replacement on the parity check matrix
(original parity check matrix) and converting it into a parity
check matrix (transformed parity check matrix) that can be shown by
the combination of a p.times.p unit matrix, a quasi unit matrix in
which one or more elements of 1 thereof become 0, a shifted matrix
that cyclically shifts the unit matrix or the quasi unit matrix, a
sum matrix that is the sum of two or more of the unit matrix, the
quasi unit matrix and the shifted matrix, and a p.times.p 0 matrix,
that is, the combination of constitutive matrixes, as for LDPC code
decoding, it becomes possible to adopt architecture that
simultaneously performs check node calculation and variable node
calculation by P which is the number less than the row number and
column number of the parity check matrix. In the case of adopting
the architecture that simultaneously performs node calculation
(check node calculation and variable node calculation) by P which
is the number less than the row number and column number of the
parity check matrix, as compared with a case where the node
calculation is simultaneously performed by the number equal to the
row number and column number of the parity check matrix, it is
possible to suppress the operation frequency within a feasible
range and perform many items of iterative decoding.
[2522] The LDPC decoder 166 that constitutes the receiving device
12 of FIG. 207 performs the LDPC decoding by simultaneously
performing P check node operations and variable node operations,
similar to the decoding device of FIG. 213.
[2523] That is, for the simplification of explanation, if the
parity check matrix of the LDPC code output by the LDPC encoder 115
constituting the transmitting device 11 of FIG. 8 is regarded as
the parity check matrix H illustrated in FIG. 210 in which the
parity matrix becomes a staircase structure, in the parity
interleaver 23 of the transmitting device 11, the parity interleave
to interleave the (K+qx+y+1)-th code bit into the position of the
(K+Py+x+1)-th code bit is performed in a state in which the
information K is set to 60, the unit size P is set to 5, and the
divisor q (=M/P) of the parity length M is set to 6.
[2524] Because the parity interleave corresponds to the column
replacement of the expression (12) as described above, it is not
necessary to perform the column replacement of the expression (12)
in the LDPC decoder 166.
[2525] For this reason, in the receiving device 12 of FIG. 207, as
described above, the LDPC code in which the parity deinterleave is
not performed, that is, the LDPC code in a state in which the
column replacement of the expression (12) is performed is supplied
from the group-wise deinterleaver 55 to the LDPC decoder 166. In
the LDPC decoder 166, the same processing as the decoding device of
FIG. 213, except that the column replacement of the expression (12)
is not performed, is executed.
[2526] That is, FIG. 214 illustrates a configuration example of the
LDPC decoder 166 of FIG. 207.
[2527] In FIG. 214, the LDPC decoder 166 has the same configuration
as the decoding device of FIG. 213, except that the reception data
rearranging unit 310 of FIG. 213 is not provided, and executes the
same processing as the decoding device of FIG. 213, except that the
column replacement of the expression (12) is not performed.
Therefore, explanation of the LDPC decoder is omitted.
[2528] As described above, because the LDPC decoder 166 can be
configured without providing the reception data rearranging unit
310, a scale can be decreased as compared with the decoding device
of FIG. 213.
[2529] In FIGS. 210 to 214, for the simplification of explanation,
the code length N of the LDPC code is set to 90, the information
length K is set to 60, the unit size (the row number and the column
number of the constitutive matrix) P is set to 5, and the divisor q
(=M/P) of the parity length M is set to 6. However, the code length
N, the information length K, the unit size P, and the divisor q
(=M/P) are not limited to the above values.
[2530] That is, in the transmitting device 11 of FIG. 8, the LDPC
encoder 115 outputs the LDPC code in which the code length N is set
to 64800 or 16200, the information length K is set to N-Pq (=N-M),
the unit size P is set to 360, and the divisor q is set to M/P.
However, the LDPC decoder 166 of FIG. 214 can be applied to the
case in which P check node operation and variable node operations
are simultaneously performed with respect to the LDPC code and the
LDPC decoding is performed.
[2531] Further, when the parity portion of the decoding result is
unnecessary, and only the information bits of the decoding result
are output after the decoding of the LDPC code by the LDPC decoder
166, the LDPC decoder 166 may be configured without the decoded
data rearranging unit 311
[2532] <Configuration Example of Block Deinterleaver 54>
[2533] FIG. 215 is a block diagram illustrating a configuration
example of the block deinterleaver 54 of FIG. 208.
[2534] The block deinterleaver 54 has a similar configuration to
the block interleaver 25 described above with reference to FIG.
105.
[2535] Thus, the block deinterleaver 54 includes the storage region
called the part 1 and the storage region called the part 2, and
each of the parts 1 and 2 is configured such that a number C of
columns equal in number to the number m of bits of the symbol and
serving as storage regions that store one bit in the row
(horizontal) direction and store a predetermined number of bits in
the column (vertical) direction are arranged.
[2536] The block deinterleaver 54 performs the block deinterleave
by writing the LDPC code in the parts 1 and 2 and reading the LDPC
code from the parts 1 and 2.
[2537] However, in the block deinterleave, the writing of the LDPC
code (serving as the symbol) is performed in the order in which the
LDPC code is read by the block interleaver 25 of FIG. 105.
[2538] Further, in the block deinterleave, the reading of the LDPC
code is performed in the order in which the LDPC code is written by
the block interleaver 25 of FIG. 105.
[2539] In other words, in the block interleave performed by the
block interleaver 25 of FIG. 105, the LDPC code is written in the
parts 1 and 2 in the column direction and read from the parts 1 and
2 in the row direction, but in the block deinterleave performed by
the block deinterleaver 54 of FIG. 215, the LDPC code is written in
the parts 1 and 2 in the row direction and read from the parts 1
and 2 in the column direction.
[2540] <Other Configuration Example of Bit Deinterleaver
165>
[2541] FIG. 216 is a block diagram illustrating another
configuration example of the bit deinterleaver 165 of FIG. 217.
[2542] In the drawings, portions that correspond to the case of
FIG. 208 are denoted with the same reference numerals and
explanation thereof is appropriately omitted hereinafter.
[2543] That is, the bit deinterleaver 165 of FIG. 216 has the same
configuration as the case of FIG. 208, except that a parity
deinterleaver 1011 is newly provided.
[2544] Referring to FIG. 216, the bit deinterleaver 165 is
configured with a block deinterleaver 54, a group-wise
deinterleaver 55, and a parity deinterleaver 1011, and performs the
bit deinterleave on the code bits of the LDPC code supplied from
the demapper 164.
[2545] In other words, the block deinterleaver 54 performs the
block deinterleave (the inverse process of the block interleave)
corresponding to the block interleave performed by the block
interleaver 25 of the transmitting device 11, that is, the block
deinterleave of restoring the positions of the code bits rearranged
by the block interleave to the original positions on the LDPC code
supplied from the demapper 164, and supplies the LDPC code obtained
as a result to the group-wise deinterleaver 55.
[2546] The group-wise deinterleaver 55 performs the group-wise
deinterleave corresponding to the group-wise interleave serving as
the rearrangement process performed by the group-wise interleaver
24 of the transmitting device 11 on the LDPC code supplied from the
block deinterleaver 54.
[2547] The LDPC code that is obtained as a result of the group-wise
deinterleave is supplied from the group-wise deinterleaver 55 to
the parity deinterleaver 1011.
[2548] The parity deinterleaver 1011 performs the parity
deinterleave (reverse processing of the parity interleave)
corresponding to the parity interleave performed by the parity
interleaver 23 of the transmitting device 11, that is, the parity
deinterleave to restore the sequence of the code bits of the LDPC
code of which a sequence is changed by the parity interleave to the
original sequence, with respect to the code bits after the
group-wise deinterleave in the group-wise deinterleaver 55.
[2549] The LDPC code that is obtained as a result of the parity
deinterleave is supplied from the parity deinterleaver 1011 to the
LDPC decoder 166.
[2550] Therefore, in the bit deinterleaver 165 of FIG. 216, the
LDPC code in which the block deinterleave, the group-wise
deinterleave, and the parity deinterleave are performed, that is,
the LDPC code that is obtained by the LDPC encoding according to
the parity check matrix H is supplied to the LDPC decoder 166.
[2551] The LDPC decoder 166 performs the LDPC decoding of the LDPC
code supplied from the bit deinterleaver 165 using the parity check
matrix H used for the LDPC encoding by the LDPC encoder 115 of the
transmitting device 11. In other words, the LDPC decoder 166
performs the LDPC decoding of the LDPC code supplied from the bit
deinterleaver 165 using the parity check matrix H (of the DVB
scheme) used for the LDPC encoding by the LDPC encoder 115 of the
transmitting device 11 or the transformed parity check matrix
obtained by performing at least the column permutation
corresponding to the parity interleave on the parity check matrix H
(for the ETRI scheme, the parity check matrix (FIG. 28) obtained by
performing the column permutation on the parity check matrix (FIG.
27) used for the LDPC encoding or the transformed parity check
matrix (FIG. 29) obtained by performing the row permutation on the
parity check matrix (FIG. 27) used for the LDPC encoding).
[2552] In FIG. 216, the LDPC code that is obtained by the LDPC
encoding according to the parity check matrix H is supplied from
(the parity deinterleaver 1011 of) the bit deinterleaver 165 to the
LDPC decoder 166. For this reason, when the LDPC decoding of the
LDPC code is performed using the parity check matrix H (of the DVB
method) itself used by the LDPC encoder 115 of the transmitting
device 11 to perform the LDPC encoding (for the ETRI scheme, the
parity check matrix (FIG. 28) obtained by performing the column
permutation on the parity check matrix (FIG. 27) used for the LDPC
encoding), the LDPC decoder 166 can be configured by a decoding
device performing the LDPC decoding according to a full serial
decoding method to sequentially perform operations of messages (a
check node message and a variable node message) for each node or a
decoding device performing the LDPC decoding according to a full
parallel decoding method to simultaneously (in parallel) perform
operations of messages for all nodes.
[2553] In the LDPC decoder 166, when the LDPC decoding of the LDPC
code is performed using the transformed parity check matrix
obtained by performing at least the column replacement
corresponding to the parity interleave with respect to the parity
check matrix H (of the DVB method) used by the LDPC encoder 115 of
the transmitting device 11 to perform the LDPC encoding (for the
ETRI scheme, the transformed parity check matrix (FIG. 29) obtained
by performing the row permutation on the parity check matrix (FIG.
27) used for the LDPC encoding), the LDPC decoder 166 can be
configured by a decoding device (FIG. 213) that is a decoding
device of an architecture simultaneously performing P (or divisor
of P other than 1) check node operations and variable node
operations and has the reception data rearranging unit 310 to
perform the same column replacement as the column replacement
(parity interleave) to obtain the transformed parity check matrix
with respect to the LDPC code and rearrange the code bits of the
LDPC code.
[2554] In FIG. 216, for the sake of convenience of description, the
block deinterleaver 54 that performs the block deinterleave, the
group-wise deinterleaver 55 that performs the group-wise
deinterleave, and the parity deinterleaver 1011 that performs the
parity deinterleave are configured individually, but two or more of
the block deinterleaver 54, the group-wise deinterleaver 55, and
the parity deinterleaver 1011 may be configured integrally,
similarly to the parity interleaver 23, the group-wise interleaver
24, and the block interleaver 25 of the transmitting device 11.
[2555] <Configuration Example of Reception System>
[2556] FIG. 217 is a block diagram illustrating a first
configuration example of a reception system that can be applied to
the receiving device 12.
[2557] In FIG. 217, the reception system includes an acquiring unit
1101, a transmission path decoding processing unit 1102, and an
information source decoding processing unit 1103.
[2558] The acquiring unit 1101 acquires a signal including an LDPC
code obtained by performing at least LDPC encoding with respect to
LDPC target data such as image data or sound data of a program,
through a transmission path (communication path) not illustrated in
the drawings, such as terrestrial digital broadcasting, satellite
digital broadcasting, a CATV network, the Internet, or other
networks, and supplies the signal to the transmission path decoding
processing unit 1102.
[2559] In this case, when the signal acquired by the acquiring unit
1101 is broadcast from a broadcasting station through a ground
wave, a satellite wave, or a CATV (Cable Television) network, the
acquiring unit 1101 is configured using a tuner and an STB (Set Top
Box). When the signal acquired by the acquiring unit 1101 is
transmitted from a web server by multicasting like an IPTV
(Internet Protocol Television), the acquiring unit 1101 is
configured using a network I/F (Interface) such as an NIC (Network
Interface Card).
[2560] The transmission path decoding processing unit 1102
corresponds to the receiving device 12. The transmission path
decoding processing unit 1102 executes transmission path decoding
processing including at least processing for correcting error
generated in a transmission path, with respect to the signal
acquired by the acquiring unit 1101 through the transmission path,
and supplies a signal obtained as a result to the information
source decoding processing unit 1103.
[2561] That is, the signal that is acquired by the acquiring unit
1101 through the transmission path is a signal that is obtained by
performing at least error correction encoding to correct the error
generated in the transmission path. The transmission path decoding
processing unit 1102 executes transmission path decoding processing
such as error correction processing, with respect to the
signal.
[2562] As the error correction encoding, for example, LDPC encoding
or BCH encoding exists. In this case, as the error correction
encoding, at least the LDPC encoding is performed.
[2563] The transmission path decoding processing includes
demodulation of a modulation signal.
[2564] The information source decoding processing unit 1103
executes information source decoding processing including at least
processing for extending compressed information to original
information, with respect to the signal on which the transmission
path decoding processing is executed.
[2565] That is, compression encoding that compresses information
may be performed with respect to the signal acquired by the
acquiring unit 1101 through the transmission path to decrease a
data amount of an image or a sound corresponding to information. In
this case, the information source decoding processing unit 1103
executes the information source decoding processing such as the
processing (extension processing) for extending the compressed
information to the original information, with respect to the signal
on which the transmission path decoding processing is executed.
[2566] When the compression encoding is not performed with respect
to the signal acquired by the acquiring unit 1101 through the
transmission path, the processing for extending the compressed
information to the original information is not executed in the
information source decoding processing unit 1103.
[2567] In this case, as the extension processing, for example, MPEG
decoding exists. In the transmission path decoding processing, in
addition to the extension processing, descramble may be
included.
[2568] In the reception system that is configured as described
above, in the acquiring unit 1101, a signal in which the
compression encoding such as the MPEG encoding and the error
correction encoding such as the LDPC encoding are performed with
respect to data such as an image or a sound is acquired through the
transmission path and is supplied to the transmission path decoding
processing unit 1102.
[2569] In the transmission path decoding processing unit 1102, the
same processing as the receiving device 12 executes as the
transmission path decoding processing with respect to the signal
supplied from the acquiring unit 1101 and a signal obtained as a
result is supplied to the information source decoding processing
unit 1103.
[2570] In the information source decoding processing unit 1103, the
information source decoding processing such as the MPEG decoding is
executed with respect to the signal supplied from the transmission
path decoding processing unit 1102 and an image or a sound obtained
as a result is output.
[2571] The reception system of FIG. 217 described above can be
applied to a television tuner to receive television broadcasting
corresponding to digital broadcasting.
[2572] Each of the acquiring unit 1101, the transmission path
decoding processing unit 1102, and the information source decoding
processing unit 1103 can be configured as one independent device
(hardware (IC (Integrated Circuit) and the like) or software
module).
[2573] With respect to the acquiring unit 1101, the transmission
path decoding processing unit 1102, and the information source
decoding processing unit 1103, each of a set of the acquiring unit
1101 and the transmission path decoding processing unit 1102, a set
of the transmission path decoding processing unit 1102 and the
information source decoding processing unit 1103, and a set of the
acquiring unit 1101, the transmission path decoding processing unit
1102, and the information source decoding processing unit 1103 can
be configured as one independent device.
[2574] FIG. 218 is a block diagram illustrating a second
configuration example of the reception system that can be applied
to the receiving device 12.
[2575] In the drawings, portions that correspond to the case of
FIG. 217 are denoted with the same reference numerals and
explanation thereof is appropriately omitted herein after.
[2576] The reception system of FIG. 218 is common to the case of
FIG. 217 in that the acquiring unit 1101, the transmission path
decoding processing unit 1102, and the information source decoding
processing unit 1103 are provided and is different from the case of
FIG. 217 in that an output unit 1111 is newly provided.
[2577] The output unit 1111 is a display device to display an image
or a speaker to output a sound and outputs an image or a sound
corresponding to a signal output from the information source
decoding processing unit 1103. That is, the output unit 1111
displays the image or outputs the sound.
[2578] The reception system of FIG. 218 described above can be
applied to a TV (television receiver) receiving television
broadcasting corresponding to digital broadcasting or a radio
receiver receiving radio broadcasting.
[2579] When the compression encoding is not performed with respect
to the signal acquired in the acquiring unit 1101, the signal that
is output by the transmission path decoding processing unit 1102 is
supplied to the output unit 1111.
[2580] FIG. 219 is a block diagram illustrating a third
configuration example of the reception system that can be applied
to the receiving device 12.
[2581] In the drawings, portions that correspond to the case of
FIG. 217 are denoted with the same reference numerals and
explanation thereof is appropriately omitted hereinafter.
[2582] The reception system of FIG. 219 is common to the case of
FIG. 217 in that the acquiring unit 1101 and the transmission path
decoding processing unit 1102 are provided.
[2583] However, the reception system of FIG. 219 is different from
the case of FIG. 217 in that the information source decoding
processing unit 1103 is not provided and a recording unit 1121 is
newly provided.
[2584] The recording unit 1121 records (stores) a signal (for
example, TS packets of TS of MPEG) output by the transmission path
decoding processing unit 1102 on recording (storage) media such as
an optical disk, a hard disk (magnetic disk), and a flash
memory.
[2585] The reception system of FIG. 219 described above can be
applied to a recorder that records television broadcasting.
[2586] In FIG. 219, the reception system is configured by providing
the information source decoding processing unit 1103 and can record
the signal obtained by executing the information source decoding
processing by the information source decoding processing unit 1103,
that is, the image or the sound obtained by decoding, by the
recording unit 1121.
[2587] <Embodiment of Computer>
[2588] Next, the series of processing described above can be
executed by hardware or can be executed by software. In the case in
which the series of processing is executed by the software, a
program configuring the software is installed in a general-purpose
computer.
[2589] Therefore, FIG. 220 illustrates a configuration example of
an embodiment of the computer in which a program executing the
series of processing is installed.
[2590] The program can be previously recorded on a hard disk 705
and a ROM 703 corresponding to recording media embedded in the
computer.
[2591] Alternatively, the program can be temporarily or permanently
stored (recorded) on removable recording media 711 such as a
flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO
(Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic
disk, and a semiconductor memory. The removable recording media 711
can be provided as so-called package software.
[2592] The program is installed from the removable recording media
711 to the computer. In addition, the program can be transmitted
from a download site to the computer by wireless through an
artificial satellite for digital satellite broadcasting or can be
transmitted to the computer by wire through a network such as a LAN
(Local Area Network) or the Internet. The computer can receive the
program transmitted as described above by a communication unit 708
and install the program in the embedded hard disk 705.
[2593] The computer includes a CPU (Central Processing Unit) 702
embedded therein. An input/output interface 710 is connected to the
CPU 702 through a bus 701. If a user operates an input unit 707
configured using a keyboard, a mouse, and a microphone and a
command is input through the input/output interface 710, the CPU
702 executes the program stored in the ROM (Read Only Memory) 703,
according to the command. Alternatively, the CPU 702 loads the
program stored in the hard disk 705, the program transmitted from a
satellite or a network, received by the communication unit 708, and
installed in the hard disk 705, or the program read from the
removable recording media 711 mounted to a drive 709 and installed
in the hard disk 705 to the RAM (Random Access Memory) 704 and
executes the program. Thereby, the CPU 702 executes the processing
according to the flowcharts described above or the processing
executed by the configurations of the block diagrams described
above. In addition, the CPU 702 outputs the processing result from
the output unit 706 configured using an LCD (Liquid Crystal
Display) or a speaker, transmits the processing result from the
communication unit 708, and records the processing result on the
hard disk 705, through the input/output interface 710, according to
necessity.
[2594] In the present specification, it is not necessary to process
the processing steps describing the program for causing the
computer to execute the various processing in time series according
to the order described as the flowcharts and processing executed in
parallel or individually (for example, parallel processing or
processing using an object) is also included.
[2595] The program may be processed by one computer or may be
processed by a plurality of computers in a distributed manner. The
program may be transmitted to a remote computer and may be
executed.
[2596] An embodiment of the disclosure is not limited to the
embodiments described above, and various changes and modifications
may be made without departing from the scope of the disclosure.
[2597] That is, for example, (the parity check matrix initial value
table of) the above-described new LDPC code can be used even if the
communication path 13 (FIG. 7) is any of a satellite circuit, a
ground wave, a cable (wire circuit) and others. In addition, the
new LDPC code can also be used for data transmission other than
digital broadcasting.
[2598] The GW patterns can be applied to a code other than the new
LDPC code. Further, the modulation scheme to which the GW patterns
are applied is not limited to QPSK, 16QAM, 64QAM, 256QAM, 1024QAM,
and 4096QAM.
[2599] The effects described in this specification are merely
examples and not limited, and any other effect may be obtained.
REFERENCE SIGNS LIST
[2600] 11 transmitting device [2601] 12 receiving device [2602] 23
parity interleaver [2603] 24 group-wise interleaver [2604] 25 block
interleaver [2605] 54 block deinterleaver [2606] 55 group-wise
deinterleaver [2607] 111 mode adaptation/multiplexer [2608] 112
padder [2609] 113 BB scrambler [2610] 114 BCH encoder [2611] 115
LDPC encoder [2612] 116 bit interleaver [2613] 117 mapper [2614]
118 time interleaver [2615] 119 SISO/MISO encoder [2616] 120
frequency interleaver [2617] 121 BCH encoder [2618] 122 LDPC
encoder [2619] 123 mapper [2620] 124 frequency interleaver [2621]
131 frame builder/resource allocation unit [2622] 132 OFDM
generating unit [2623] 151 OFDM operating unit [2624] 152 frame
managing unit [2625] 153 frequency deinterleaver [2626] 154
demapper [2627] 155 LDPC decoder [2628] 156 BCH decoder [2629] 161
frequency deinterleaver [2630] 162 SISO/MISO decoder [2631] 163
time deinterleaver [2632] 164 demapper [2633] 165 bit deinterleaver
[2634] 166 LDPC decoder [2635] 167 BCH decoder [2636] 168 BB
descrambler [2637] 169 null deletion unit [2638] 170 demultiplexer
[2639] 300 branch data storing memory [2640] 301 selector [2641]
302 check node calculating unit [2642] 303 cyclic shift circuit
[2643] 304 branch data storing memory [2644] 305 selector [2645]
306 reception data memory [2646] 307 variable node calculating unit
[2647] 308 cyclic shift circuit [2648] 309 decoding word
calculating unit [2649] 310 reception data rearranging unit [2650]
311 decoded data rearranging unit [2651] 601 encoding processing
unit [2652] 602 storage unit [2653] 611 encoding rate setting unit
[2654] 612 initial value table reading unit [2655] 613 parity check
matrix generating unit [2656] 614 information bit reading unit
[2657] 615 encoding parity operation unit [2658] 616 control unit
[2659] 701 bus [2660] 702 CPU [2661] 703 ROM [2662] 704 RAM [2663]
705 hard disk [2664] 706 output unit [2665] 707 input unit [2666]
708 communication unit [2667] 709 drive [2668] 710 input/output
interface [2669] 711 removable recording media [2670] 1001 reverse
interchanging unit [2671] 1002 memory [2672] 1011 parity
deinterleaver [2673] 1101 acquiring unit [2674] 1101 transmission
path decoding processing unit [2675] 1103 information source
decoding processing unit [2676] 1111 output unit [2677] 1121
recording unit
* * * * *