U.S. patent application number 15/017116 was filed with the patent office on 2016-06-02 for memory string and semiconductor device including the same.
This patent application is currently assigned to SK hynix Inc.. The applicant listed for this patent is SK hynix Inc.. Invention is credited to Sung Wook JUNG, Dong Kee LEE, Yu Jin PARK, Hyun Seung YOO.
Application Number | 20160155509 15/017116 |
Document ID | / |
Family ID | 53006921 |
Filed Date | 2016-06-02 |
United States Patent
Application |
20160155509 |
Kind Code |
A1 |
JUNG; Sung Wook ; et
al. |
June 2, 2016 |
MEMORY STRING AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
Abstract
A memory string includes a pass transistor, first memory cells
connected in series to a drain terminal of the pass transistor, and
first to k.sup.th memory cell groups connected in parallel to a
source terminal of the pass transistor and each including a
plurality of second memory cells connected in series. Here, `k`
denotes an integer that is equal to or greater than `2`.
Inventors: |
JUNG; Sung Wook;
(Gyeonggi-do, KR) ; LEE; Dong Kee; (Seoul, KR)
; YOO; Hyun Seung; (Gyeonggi-do, KR) ; PARK; Yu
Jin; (Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Gyeonggi-do |
|
KR |
|
|
Assignee: |
SK hynix Inc.
|
Family ID: |
53006921 |
Appl. No.: |
15/017116 |
Filed: |
February 5, 2016 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
14220976 |
Mar 20, 2014 |
9286983 |
|
|
15017116 |
|
|
|
|
Current U.S.
Class: |
365/185.05 ;
257/314 |
Current CPC
Class: |
H01L 23/535 20130101;
H01L 2924/0002 20130101; H01L 2924/0002 20130101; G11C 16/0483
20130101; H01L 27/11556 20130101; H01L 27/11524 20130101; H01L
27/11582 20130101; H01L 27/1157 20130101; H01L 2924/00
20130101 |
International
Class: |
G11C 16/04 20060101
G11C016/04; H01L 23/535 20060101 H01L023/535; H01L 27/115 20060101
H01L027/115 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 1, 2013 |
KR |
10-2013-0132088 |
Claims
1-7. (canceled)
8. A semiconductor device comprising: first and second memory
strings each comprising: a pass transistor; drain-side memory cells
connected in series to a drain terminal of the pass transistor; and
first and second source-side memory groups connected in parallel to
a source terminal of the pass transistor and each including a
plurality of source-side memory cells connected in series.
9. The semiconductor device of claim 8, further comprising: first
source lines connected to and suitable for driving the first
source-side memory groups, respectively; and second source lines
connected to and suitable for driving the second source-side memory
groups, respectively.
10. The semiconductor device of claim 8, further comprising: a
first source line suitable for driving the second source-side
memory group of the first memory string and the first source-side
memory group of the second memory string; and second source lines
suitable for driving the first source-side memory group of the
first memory string and the second source-side memory group of the
second memory string, respectively.
11. The semiconductor device of claim 8, further comprising: a
first bit line suitable for driving the drain-side memory cells of
the first memory string; and a second bit line suitable for driving
the drain-side memory cells of the second memory string.
12. The semiconductor device of claim 8, further comprising a third
memory string configured as the same as the first and second memory
strings, wherein the source line comprises: a first source line
suitable for driving the second source-side memory group of the
first memory string and the first source-side memory group of the
second memory string; a second source line suitable for driving the
second source-side memory group of the second memory string and a
first source-side memory group of the third memory string; and
third source lines suitable for driving the first source-side
memory group of the first memory string and a second source-side
memory group of the third memory string, respectively.
13. The semiconductor device of claim 12, further comprising: a
first bit line suitable for driving drain-side memory cells of the
first and third memory strings; and a second bit line suitable for
driving the drain-side memory cells of the second memory
string.
14. A semiconductor device comprising: a first channel layer
comprising: a first pipe channel layer; and a first source-side
channel layer, a first drain-side channel layer, and a second
source-side channel layer connected to the first pipe channel
layer, and arranged in a first direction; first source-side gates
stacked and surrounding the first source-side channel layer; second
source-side gates stacked and surrounding the second source-side
channel layer; and first drain-side gates stacked and surrounding
the first drain-side channel layer, wherein the first source-side
gates, the second source-side gates, and the first drain-side gates
are separated from one another.
15. The semiconductor device of claim 14, further comprising: a
second channel layer arranged adjacent to the first channel layer
in the first direction, and including a second pipe channel layer,
and a third source-side channel layer, a second drain-side channel
layer, and a fourth source-side channel layer connected to the
second pipe channel layer and arranged in the first direction.
16. The semiconductor device of claim 15, further comprising: first
to fourth source lines connected to the first to fourth source-side
channel layers, respectively; and first and second bit lines
connected to the first and second drain-side channel layer,
respectively.
17. The semiconductor device of claim 15, wherein the second
source-side channel layer and the third source-side channel layer
are connected to a same source line, and the first drain-side
channel layer and the second drain-side channel layer are connected
to different bit lines.
18. The semiconductor device of claim 14, further comprising: a
second channel layer arranged adjacent to the first channel layer
in a second direction crossing the first direction, and including a
second pipe channel layer, and a third source-side channel layer, a
second drain-side channel layer, and a fourth source-side channel
layer connected to the second pipe channel layer and arranged in
the first direction.
19. The semiconductor device of claim 18, further comprising: a
first source line connected to the first and third source-side
channel layers; a second source lines connected to the second and
fourth source-side channel layers; and first and second bit lines
connected to the first and second drain-side channel layers,
respectively, wherein the first channel layer and the second
channel layer are arranged in the second direction to have a center
axis oblique to the second direction.
20. The semiconductor device of claim 14, wherein the first channel
layer further comprises: a third source-side channel layer
connected to the first pipe channel layer and disposed between the
first source-side channel layer and the first drain-side channel
layer; and a fourth source-side channel layer connected to the
first pipe channel layer and disposed between the second
source-side channel layer and the first drain-side channel layer,
wherein the semiconductor device includes memory blocks each having
the first channel layer in the first direction.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims priority to Korean patent
application number 10-2013-0132088 filed on Nov. 1, 2013, in the
Korean Intellectual Property Office, the entire disclosure of which
is incorporated by reference herein.
BACKGROUND
[0002] 1. Technical Field
[0003] Various embodiments of the present invention relate to
electronic devices. More specifically, the exemplary embodiments of
the present invention relate to memory strings and a semiconductor
device including the same.
[0004] 2. Related Art
[0005] A non-volatile memory device is a memory device capable of
retaining data stored therein even when power cut-off occurs, and
it may include memory strings as a cell array for storing data.
Here, each of the memory strings includes a drain selection
transistor, a plurality of memory cells, and a source selection
transistor that are connected in series. Each of the memory strings
is connected to a source line via the source selection transistor,
and connected to a bit line via the drain selection transistor.
[0006] The memory strings are arranged on a substrate in a
horizontal or vertical direction. In the related art, memory
strings are arranged on a substrate in the horizontal direction by
forming memory cells in a single layer. However, a method of
arranging memory strings on a substrate in the vertical direction
by stacking memory cells has been suggested.
[0007] However, memory strings having the structure described above
are limited in increasing cell current. Furthermore, when memory
strings are arranged in the vertical direction, the properties of a
memory device may be degraded due to interferences between memory
cells adjacent in x/y/z-axis direction, respectively.
BRIEF SUMMARY
[0008] One or more exemplary embodiments of the present invention
are directed to memory strings having improved properties and a
semiconductor device including the same.
[0009] One aspect of the present invention provides a memory string
including a pass transistor, first memory cells connected in series
to a drain terminal of the pass transistor, and first to k.sup.th
memory cell groups connected in parallel to a source terminal of
the pass transistor and each including a plurality of second memory
cells connected in series, wherein k denotes an integer that is
equal to or greater than `2`.
[0010] Another aspect of the present invention provides a
semiconductor device including first and second memory strings each
including a pass transistor, drain-side memory cells connected in
series to a drain terminal of the pass transistor, and first and
second source-side memory groups connected in parallel to a source
terminal of the pass transistor and each including a plurality of
source-side memory cells connected in series.
[0011] Further aspect of the present invention provides a
semiconductor device including a first channel layer including a
first pipe channel layer, and a first source-side channel layer, a
first drain-side channel layer, and a second source-side channel
layer connected to the first pipe channel layer and arranged in a
first direction, first source-side gates stacked and surrounding
the first source-side channel layer, second source-side gates
stacked and surrounding the second source-side channel layer, and
first drain-side gates stacked and surrounding the first drain-side
channel layer, wherein the first source-side gates, the second
source-side gates, and the first drain-side gates are separated
from one another.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The above and other features and advantages of the present
invention will become more apparent to those of ordinary skill in
the art by describing in detail exemplary embodiments thereof with
reference to the attached drawings in which:
[0013] FIG. 1A is a circuit diagram of a memory string according to
an exemplary embodiment of the present invention;
[0014] FIGS. 1B and 1C are circuit diagrams illustrating memory
strings according to exemplary embodiments of the present
invention;
[0015] FIGS. 2A and 2B are circuit diagrams illustrating program
operations performed on the memory string according to the
exemplary embodiment of the present invention;
[0016] FIGS. 3A and 3B are circuit diagrams illustrating read
operations performed on the memory string according to the
exemplary embodiment of the present invention;
[0017] FIGS. 4A to 4C are cross-sectional views of semiconductor
devices including memory strings according to exemplary embodiments
of the present invention;
[0018] FIG. 5 is a block diagram of a memory system according to an
exemplary embodiment of the present invention;
[0019] FIG. 6 is a block diagram of a memory system according to
another exemplary embodiment of the present invention;
[0020] FIG. 7 is a block diagram of a computing system according to
an exemplary embodiment of the present invention; and
[0021] FIG. 8 is a block diagram of a computing system according to
another exemplary embodiment of the present invention.
DETAILED DESCRIPTION
[0022] The present invention will be described more fully
hereinafter with reference to the accompanying drawings, in which
exemplary embodiments of the invention are shown. In the drawings,
the thicknesses of and distances between elements may be
exaggerated for clarity. In the present disclosure, well-known
functions or constructions that are not related to the gist of the
present invention may not be described. When reference numerals are
assigned to the elements shown in the drawings, the same reference
numeral is assigned to the same elements even if these elements are
illustrated in different drawings.
[0023] FIG. 1A is a circuit diagram of a memory string according to
an exemplary embodiment of the present invention.
[0024] Referring to FIG. 1A, the memory string according to an
exemplary embodiment of the present invention includes at least one
pass transistor PTr, a plurality of first memory cells connected in
series to a drain terminal of the pass transistor PTr, and first to
k.sup.th memory cell groups connected in parallel to a source
terminal of the pass transistor PTr. Here, each of the memory cell
groups includes a plurality of second memory cells connected in
series. In addition, the first memory cells may be drain-side
memory transistors D_MT, and the second memory cells may be
source-side memory transistors S_MT1 to S_MTk. Here, `k` denotes an
integer that is equal to or greater than `2`.
[0025] The drain-side memory transistors D_MT are connected in
series to a drain terminal of the at least one pass transistor PTr.
The first to k.sup.th source-side memory transistors S_MT1 to S_MTk
are connected in parallel to a source terminal of the at least one
pass transistor PTr.
[0026] The memory string according to an exemplary embodiment of
the present invention further includes a drain selection transistor
DST, and first to k.sup.th source selection transistors SST1 to
SSTk. For example, at least one drain selection transistor DST is
connected in series to the drain-side memory transistors D_MT, at
least a first source selection transistor SST1 is connected in
series to the first source-side memory transistors S_MT1, and at
least a k.sup.th source selection transistor SSTk is connected in
series to the k.sup.th source-side memory transistors S_MTk.
[0027] Here, the drain selection transistor DST is connected to a
bit line BL, the first source selection transistor SST1 is
connected to a first source line SL1, and the second source
selection transistor SST2 is connected to a second source line
SL2.
[0028] In the structure described above, one memory string is
connected to one bit line BL and a plurality of source lines SL1 to
SLk. Thus, the first to k.sup.th source-side memory transistors
S_MT1 to S_MTk are driven by different source lines SL1 to SLk,
respectively. For example, the first source-side memory transistors
S_MT1 are driven by the first source line SL1, and the k.sup.th
source-side memory transistors S_MTk are driven by the k.sup.th
source line SLk. As described above, the amount of cell current may
be increased by connecting the plurality of source lines SL1 to SLk
to one memory string.
[0029] FIGS. 1B and 1C are circuit diagrams illustrating memory
strings according to exemplary embodiments of the present
invention.
[0030] Referring to FIG. 1B, a first memory string and a second
memory string according to an exemplary embodiment of the present
invention may be driven by different bit lines BL1 and BL2 and
different source lines S11, S12, S21, and S22.
[0031] In the first memory string, first source-side memory
transistors S_MT11 are driven by the first source line SL11 and
second source-side memory transistors S_MT12 are driven by the
second source line SL12. The first memory string is driven by the
first bit line BL1.
[0032] In the second memory string, third source-side memory
transistors S_MT21 are driven by the third source line SL21, and
fourth source-side memory transistors S_MT22 are driven by the
fourth source line SL22. The second memory string is driven by the
second bit line BL2.
[0033] Here, the first memory string and the second memory string
may belong to one memory block or different memory blocks. When the
first and second memory strings belong to one memory block, a first
pipe transistor PTr1 and a second pipe transistor PTr2 are driven
by the same pipe gate. When the first and second memory strings
belong to different memory blocks, the first pipe transistor PTr1
and the second pipe transistor PTr2 are driven by different pipe
gates.
[0034] Referring to FIG. 1C, first to third memory strings
according to another exemplary embodiment of the present invention
may share bit lines BL1 and BL2 or source lines SL1 to SL4.
[0035] Second source-side memory transistors S_MT12 of the first
memory string and third source-side memory transistors S_MT21 of
the second memory string share the second source line SL2. Fourth
source-side memory transistors S_MT22 of the second memory string
and fifth source-side memory transistors S_MT31 of the third memory
string share the third source line SL3.
[0036] Here, the first to third memory strings may be driven by
different bit lines or some of the first to third memory strings
may share a bit line. For example, the first and third memory
strings may be driven by the first bit line BL1, and the second
memory string may be driven by the second bit line BL2. In this
case, first source-side memory transistor S_MT11 of the first
memory string are driven by the first source line SL1 and sixth
source-side memory transistors S_MT32 of the third memory string
may be driven by the fourth source line SL4. As another example,
the first to third memory strings are driven by first to third bit
lines, respectively. In this case, the first source-side memory
transistors S_MT11 of the first memory string and the sixth
source-side memory transistors S_MT32 of the third memory string
may share the first source line SL1.
[0037] Also, the first to third memory strings may belong to one
memory block or different memory blocks. When the first to third
memory strings belong to one memory block, first to third pipe
transistors PTr1 to PTr3 are driven by the same pipe gate. When the
first to third memory strings belong to different memory blocks,
the first to third pipe transistors PTr1 to PTr3 are driven by
different pipe gates.
[0038] FIGS. 2A and 2B are circuit diagrams illustrating program
operations performed on the memory string according to the
exemplary embodiment of the present invention.
[0039] Referring to FIG. 2A, it will be described below that
certain conditions of voltages are applied to respective gates of
various transistors when a program operation is performed by
selecting a source-side memory transistor included in the memory
string according to the exemplary embodiment of the present
invention.
[0040] For example, when one of first source-side memory
transistors S_MT1 is selected, a program voltage Vpgm is applied to
a word line connected to the selected first source-side memory
transistor S_MT1 and a pass voltage Vpass is applied to the other
word lines. A pass selection transistor PTr is turned on by
applying the pass voltage Vpass to a gate thereof.
[0041] Also, a first source selection transistor SST1 is turned off
by applying a ground voltage (0 V) to a gate thereof, and an
operating voltage Vcc is applied to a first source line SL1. A
drain selection transistor DST is turned on by applying the
operation voltage Vcc to a gate thereof, and a bit line BL is
grounded. The non-selected second to k.sup.th source selection
transistors SST2 to SSTk are turned off or on, and second to
k.sup.th source lines SL2 to SLk are grounded.
[0042] Referring to FIG. 2B, it will be described below that
certain conditions of voltages are applied to respective gates of
various transistors when a program operation is performed by
selecting a drain-side memory transistor included in the memory
string according to the exemplary embodiment of the present
invention.
[0043] For example, when one of drain-side memory transistors D_MT
is selected, a program voltage Vpgm is applied to a word line
connected to the selected drain-side memory transistor D_MT and a
pass voltage Vpass is applied to the other word lines. A pass
selection transistor PTr is turned on by applying the pass voltage
Vpass to a gate thereof.
[0044] Also, one of first to k.sup.th source selection transistors
SST1 to SSTk, for example, a first source selection transistor
SST1, is selected and turned off by applying a ground voltage (0 V)
to a gate thereof, and an operating voltage Vcc is applied to a
first source line SL1 of the first source selection transistor
SST1. A drain selection transistor DST is turned on by applying the
operating voltage Vcc to a gate thereof, and a bit line BL is
grounded. The non-selected second to k.sup.th source selection
transistors SST2 to SSTk are turned off or on, and second to
k.sup.th source lines SL2 to SLk are grounded.
[0045] FIGS. 3A and 3B are circuit diagrams illustrating read
operations performed on the memory string according to the
exemplary embodiment of the present invention.
[0046] Referring to FIG. 3A, it will be described below that
certain conditions of voltages are applied to respective gates of
various transistors when the read operation is performed by
selecting a source-side memory transistor included in the memory
string according to the exemplary embodiment of the present
invention.
[0047] For example, when one of first source-side memory
transistors S_MT1 is selected, a read voltage Vread is applied to a
gate of the selected first source-side memory transistor S_MT1 and
a pass voltage Vpass is applied to gates of the other first
source-side memory transistors S_MT1. Also, the pass voltage Vpass
is applied to gates of drain-side memory transistors D_MT. Here,
the read voltage Vread is applied to read data stored in a selected
memory transistor, and has such a level that it causes a programmed
memory transistor to be turned off and an erased memory transistor
to be turned on. Also, the pass voltage Vpass has such a level that
it causes a memory transistor to be turned on regardless of a state
of the memory transistor.
[0048] Also, a drain selection transistor DST and a selected first
source selection transistor SST1 are turned on by applying an
operating voltage Vcc to gates thereof, a bit line BL is precharged
to a high level (e.g., the operating voltage Vcc), and a selected
first source line SL1 is maintained at a low level (e.g., a ground
voltage). In this case, a current does not flow to the first source
line SL1 when the selected first source-side memory transistor
S_MT1 is in a programmed state, and it flows to the first source
line SL1 when the selected first source-side memory transistor
S_MT1 is in an erased state. Thus, data stored in the selected
first source-side memory transistor S_MT1 is read by sensing a
level of a bit line BL.
[0049] The ground voltage (0 V) or the pass voltage Vpass is
applied to gates of the second to k.sup.th source-side memory
transistors S_MT2 to S_MTk that are not selected, and the ground
voltage (0 V) or the operating voltage Vcc is applied to gates of
the second to k.sup.th source selection transistors SST2 to SSTk
that are not selected. Also, the second to k.sup.th source lines
SL2 to SLk that are not selected are maintained at a high
level.
[0050] Referring to FIG. 3B, it will be described below that
certain conditions of voltages are applied to respective gates of
various transistors when a read operation is performed by selecting
a drain-side memory transistor included in the memory string
according to the exemplary embodiment of the present invention.
[0051] For example, when one of drain-side memory transistors D_MT
is selected, a read voltage Vread is applied to a gate of the
selected drain-side memory transistor D_MT and a pass voltage Vpass
is applied to the other drain-side memory transistors D_MT.
[0052] One of first to k.sup.th source lines SL1 to SLk, for
example, a first source line SL1, is selected, an operating voltage
Vcc is applied to a gate of a first source selection transistor
SST1 connected to the first source line SL1, and the pass voltage
Vpass is applied to gates of the first source-side memory
transistors S_MT1.
[0053] Also, a drain selection transistor DST is turned on by
applying the operating voltage Vcc to a gate thereof, a bit line BL
is precharged to a high level (e.g., the operating voltage Vcc),
and the first source line SL1 is maintained at a low level (e.g.,
the ground voltage). In this case, a current does not flow to the
first source line SL1 when the selected drain-side memory
transistor D_MT is in a programmed state, and it flows to the first
source line SL1 when the selected drain-side memory transistor D_MT
is in an erased state. Thus, data stored in the selected drain-side
memory transistor D_MT is read by sensing a level of the bit line
BL.
[0054] The ground voltage (0 V) or the pass voltage Vpass is
applied to gates of the non-selected second to k.sup.th source-side
memory transistors S_MT2 to S_MTk, and the ground voltage (0 V) or
the operating voltage Vcc is applied to gates of the non-selected
second to k.sup.th source selection transistors SST2 to SSTk. Also,
the non-selected second to k.sup.th source lines SL2 to SLk are
maintained at a high level.
[0055] FIG. 4A is a cross-sectional view of a semiconductor device
including memory strings according to a first exemplary embodiment
of the present invention. In the present embodiment, it will be
described below that a first memory string and a second memory
string are driven by different bit lines and different source
lines.
[0056] Referring to FIG. 4A, the semiconductor device according to
the first exemplary embodiment of the present invention includes a
plurality of channel layers CH. Each of the channel layers CH
includes a pipe channel layer P_CH, a drain-side channel layer
D_CH, and first to k.sup.th source channel layers S_CH1 to S_CHk.
Here, `k` denotes an integer that is equal to or greater than
`2`.
[0057] The pipe channel layer P_CH connects the drain-side channel
layer D_CH and the first to k.sup.th source channel layers S_CH1 to
S_CHk. For example, the pipe channel layer P_CH connects the first
source-side channel layer S_CH1, the drain-side channel layer D_CH,
and the second source-side channel layer S_CH2 that are arranged in
a first direction I in the order listed. Here, the order in which
the first source-side channel layer S_CH1, the drain-side channel
layer D_CH, and the second source-side channel layer S_CH2 are
arranged may be changed.
[0058] Also, the channel layers CH are arranged in the first
direction I and a second direction II crossing the first direction
I. For example, the channel layers CH may be arranged in the form
of matrix or arranged in a zigzag pattern to improve the degree of
integration.
[0059] The semiconductor device according to the first exemplary
embodiment of the present invention includes conductive layers 44
and insulating layers 45 that are alternately stacked on a
substrate (SUB) 41. The conductive layers 44 and the insulating
layers 45 are patterned by slits S, and the conductive layers 44
may be used as a gate. For example, among the conductive layers 44,
the lowermost conductive layer 44 may be a pipe gate PG, at least
one uppermost conductive layer 44 may be selection lines SSL and
DSL, and the other conductive layers 44 may be word lines S_WL and
D_WL. Here, the conductive layers 44 are stacked while surrounding
the channel layers CH. For example, the pipe gate PG wraps the pipe
channel layers P_CH. The source-side word lines S_WL and the source
selection lines SSL are stacked while surrounding the source-side
channel layers S_CH, and the drain-side word lines D_WL and the
drain selection lines DSL are stacked while surrounding the
drain-side channel layers D_CH.
[0060] The semiconductor device according to the first exemplary
embodiment of the present invention further includes a memory layer
46 disposed between the channel layers CH and the word lines S_WL
and D_WL. The memory layer 46 may include a tunnel insulating
layer, a data storage layer, and a charge blocking layer. For
example, the data storage layer includes a trapping layer such as a
nitride layer, a polysilicon layer, nano dots, a phase-change
material layer, etc.
[0061] The semiconductor device according to the first exemplary
embodiment of the present invention further includes source lines
SL11, SL12, S21, and S22 connected to the source-side channel
layers S_CH, and bit lines BL1 and BL2 connected to the drain-side
channel layers D_CH. The source lines SL11, SL12, S21, and S22 and
the bit lines BL1, BL2 may extend in a direction in which they
intersect each other.
[0062] In the structure described above, drain selection
transistors DST are formed in regions in which the channel layers
CH and the drain selection lines DSL intersect one another, and
source selection transistors SST are formed in regions in which the
channel layers CH and the source selection lines SSL intersect one
another. Source-side memory transistors S_MT are formed in regions
in which the channel layers CH and the source-side word lines S_WL
intersect one another, and drain-side memory transistors D_MT are
formed in regions in which the channel layers CH and the drain-side
word lines D_WL intersect one another.
[0063] Thus, a pipe transistor, a plurality of drain-side memory
transistors, and at least one drain selection transistor that are
connected in series to a drain terminal of the pipe transistor, and
a plurality of source-side memory transistors and at least one
source selection transistor that are connected in parallel to a
source terminal of the pipe transistor, form one memory string
together, and memory strings may be arranged in the form of W.
[0064] As described above, the degree of memory integration may be
improved by increasing the number of memory transistors to be
included in one memory string and decreasing the number of slits S,
compared to the related art.
[0065] FIG. 4B is a cross-sectional view of a semiconductor device
to which memory strings according to a second exemplary embodiment
of the present invention. In the present embodiment, it will be
described below that first to third memory strings share bit lines
or source lines. Features of the semiconductor device of FIG. 4B
that are the same as the previous embodiments will not be
redundantly described here.
[0066] Referring to FIG. 4B, the semiconductor device according to
the second exemplary embodiment of the present invention includes a
plurality of channel layers CH1 to CH3. For example, the first
channel layer CH1 includes a first pipe channel layer P_CH1, a
first source-side channel layer S_CH11, a second source-side
channel layer S_CH12, and a first drain-side channel layer D_CH1.
The second and third channel layers CH2 and CH3 may have the same
structure as the first channel layer CH1. The first to third
channel layers CH1 to CH3 are sequentially arranged in a first
direction I.
[0067] The semiconductor device according to the second exemplary
embodiment of the present invention further includes conductive
layers 44 and insulating layers 45 that are alternately stacked on
a substrate 41. The conductive layers 44 include a pipe gate PG,
source and drain-side word lines S_WL and D_WL, and source and
drain selection lines SSL and DSL.
[0068] The semiconductor device according to the second exemplary
embodiment of the present invention further includes a memory layer
46 disposed between the channel layers CH1 to CH3 and the word
lines S_WL and D_WL.
[0069] The semiconductor device according to the second exemplary
embodiment of the present invention further includes source lines
SL1 to SL4 connected to the source-side channel layers S_CH, and
bit lines BL1 and BL2 connected to the drain-side channel layers
D_CH.
[0070] For example, the first and third channel layers CH1 and CH3
are connected to the first bit line BL1, and the second channel
layer CH2 is connected to the second bit line BL2. In this case,
the first source-side channel layer S_CH11 is connected to the
first source line SL1, the second source-side channel layer S_CH12
and a third source-side channel layer S_CH21 are connected to the
second source line SL2, a fourth source-side channel layer S_CH22
and a fifth source-side channel layer S_CH31 are connected to the
third source line SL3, and a sixth source-side channel layer S_CH32
is connected to the fourth source line SL4.
[0071] As another example, the first to third channel layers CH1 to
CH3 are connected to the first to third bit lines BL1 to BL3,
respectively (not shown). In this case, the first source-side
channel layer S_CH11 and the sixth source-side channel layer S_CH32
share the first source line SL1, the second source-side channel
layer S_CH12 and the third source-side channel layer S_CH21 share
the second source line SL2, and the fourth source-side channel
layer S_CH22 and the fifth source-side channel layer S_CH31 share
the third source line SL3.
[0072] In the structure described above, second source-side memory
transistors S_MT12 and third source-side memory transistors S_MT21
share the source-side word lines S_WL, respectively. Also, fourth
source-side memory transistors S_MT22 and fifth source-side memory
transistors S_MT31 share the source-side word lines S_WL,
respectively. Thus, the number of slits is reduced to decrease a
cell area, compared to the embodiment described above with
reference to FIG. 4A. Also, since the conductive layers 44 stacked
increase in width, stacks may be prevented from being tilted during
a fabrication process.
[0073] FIG. 4C is a cross-sectional view of a semiconductor device
including memory strings according to a third exemplary embodiment
of the present invention. In the present embodiment, it will be
described below that one string includes first to fourth
source-side memory transistors. Features of the semiconductor
device of FIG. 4C that are the same as the previous embodiments
will not be redundantly described here.
[0074] Referring to FIG. 4C, the semiconductor device according to
the third exemplary embodiment of the present invention includes a
plurality of channel layers CH1 and CH2. For example, each of the
channel layers CH1 and CH2 includes a pipe channel layer P_CH,
first to fourth source-side channel layers S_CH, and a drain-side
channel layer D_CH. For example, a pipe channel layer P_CH1
connects a first source-side channel layer S_CH11, a second
source-side channel layer S_CH12, a drain-side channel layer D_CH1,
a third source-side channel layer S_CH13, and a fourth source-side
channel layer S_CH14 that are arranged in a first direction I in
the order listed.
[0075] Here, the first channel layer CH1 and the second channel
layer CH2 are arranged in a second direction II crossing the first
direction I. For example, the first channel layer CH1 and the
second channel layer CH2 are arranged in a zigzag pattern such that
the center axis thereof are oblique to the second direction II with
an offset.
[0076] The semiconductor device according to the third exemplary
embodiment of the present invention further includes conductive
layers 44 and insulating layers 45 that are alternately stacked on
the substrate 41. The conductive layers 44 includes a pipe gate PG,
source and drain-side word lines S_WL and D_WL, and source and
drain selection lines SSL and DSL.
[0077] The semiconductor device according to the third exemplary
embodiment of the present invention further includes a memory layer
46 disposed between the channel layers CH1 and CH2 and the word
lines S_WL and D_WL.
[0078] The semiconductor device according to the third exemplary
embodiment of the present invention further includes source lines
SL1 to SL4 connected to the source-side channel layers S_CH, and
bit lines BL1 and BL2 connected to the drain-side channel layers
D_CH. In the first channel layer CH1 and the second channel layer
CH2, first source-side channel layers S_CH11 and S_CH21 share the
first source line SL1, second source-side channel layers S_CH12 and
S-CH22 share the second source line SL2, third source-side channel
layers S_CH13 and S_CH23 share the third source line SL3, and
fourth source-side channel layers S_CH14 and S_CH24 share the
fourth source line SL4.
[0079] In the structure described above, the first and second
channel layers CH1 and CH2 arranged in the zigzag pattern share the
first to fourth source lines SL1 to SL4, thereby reducing the
number of wires. Also, only one memory string is formed in one
memory block in the first direction I, thereby reducing
disturbances during a program operation.
[0080] FIG. 5 is a block diagram of the structure of a memory
system 1000 according to an exemplary embodiment of the present
invention.
[0081] As illustrated in FIG. 5, the memory system 1000 according
to the present embodiment includes a memory device 1200 and a
controller 1100.
[0082] The memory device 1200 is used to store various types of
data such as texts, graphics, software codes, etc. The memory
device 1200 may be a non-volatile memory device and include memory
strings as described above with reference to FIGS. 1A to 4C. Also,
the memory device 1200 may include a pass transistor, drain-side
memory transistors connected in series to a drain terminal of the
pass transistor, and first to k.sup.th source-side memory
transistors connected in parallel to a source terminal of the pass
transistor. Here, `k` denotes an integer that is equal to or
greater than `2`. The structure and method of fabricating the
memory device 1200 are the same as described above and are not
redundantly described here.
[0083] The controller 1100 is connected to a host and the memory
device 1200, and may access the memory device 1200 in response to a
request from the host. For example, the controller 1100 may control
read, write, erase, background operations, etc. of the memory
device 1200.
[0084] The controller 1100 includes a random access memory (RAM)
1110, a central processing unit (CPU) 1120, a host interface 1130,
an error correction code (ECC) circuit 1140, a memory interface
1150, etc.
[0085] Here, the RAM 1110 may be used as an operating memory of the
CPU 1120, a cache memory between the memory device 1200 and the
host, a buffer memory between the memory device 1200 and the host,
etc. The RAM 1110 may be replaced with a static random access
memory (SRAM), a read-only memory (ROM), etc.
[0086] The CPU 1120 may control overall operations of the
controller 1100. For example, the CPU 1120 may operate a firmware
such as a flash transition layer (FTL) stored in the RAM 1110.
[0087] The host interface 1130 may interface with the host. For
example, the controller 1100 communicates with the host via at
least one among various interface protocols, such as a Universal
Serial Bus (USB) protocol, a MultiMedia Card (MMC) protocol, a
Peripheral Component Interconnection (PCI) protocol, a PCI-Express
(PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol,
a serial-ATA protocol, a parallel-ATA protocol, a Small Computer
Small Interface (SCSI) protocol, an Enhanced Small Disk Interface
(ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a
private protocol, etc.
[0088] The ECC circuit 1140 may detect and correct an error in data
read from the memory device 1200 using the ECC.
[0089] The memory interface 1150 may interface with the memory
device 1200. For example, the memory interface 1150 includes a NAND
or a NOR interface.
[0090] Alternatively, the controller 1100 may further include a
buffer memory (not shown) for temporarily storing data. The buffer
memory may be used to temporarily store data transmitted to the
outside via the host interface 1130 or data transmitted from the
memory device 1200 via the memory interface 1150. The controller
1100 may further include a ROM for storing code data used to
interface with the host.
[0091] As described above, the memory system 1000 according to an
exemplary embodiment of the present invention includes the memory
device 1200 improved in cell current and interference
characteristics, and may thus have improved characteristics.
[0092] FIG. 6 is a block diagram of a memory system 1000' according
to another exemplary embodiment of the present invention. The
features of the memory system 1000' of FIG. 6 that are the same as
the previous embodiments will not be redundantly described
here.
[0093] As illustrated in FIG. 6, the memory system 1000' according
to another exemplary embodiment of the present invention includes a
memory device 1200' and a controller 1100. The controller 1100
includes a RAM 1110, a CPU 1120, a host interface 1130, an ECC
circuit 1140, a memory interface 1150, etc.
[0094] The memory device 1200' may be a non-volatile memory and
include memory strings as described above with reference to FIG. 1A
to 4C. Also, the memory device 1200' includes a pass transistor,
drain-side memory transistors connected in series to a drain
terminal of the pass transistor, and first to k.sup.th source-side
memory transistors connected in parallel to a source terminal of
the pass transistor. Here, `k` denotes an integer that is equal to
or greater than `2`. A structure of and a method of fabricating the
memory device 1200' are the same as described above and will not be
described here in detail.
[0095] The memory device 1200' may be a multi-chip package
including a plurality of memory chips. The plurality of memory
chips are divided into a plurality of groups. The plurality of
groups may communicate with the controller 1100 via first to
k.sup.th channels CH1 to CHk. Also, memory chips belonging to one
of the plurality of groups may communicate with the controller 1100
via a common channel. Alternatively, the memory system 1000' may be
modified such that one memory chip is connected to one channel.
[0096] As described above, the memory system 1000' according to
another exemplary embodiment of the present invention includes the
memory device 1000' improved in cell current and interference
characteristics and may thus have improved characteristics. In
particular, when the memory device 1200' is configured as a
multi-chip package, the data storage capacity and operating speed
of the memory system 1000' may be improved.
[0097] FIG. 7 is a block diagram illustrating a configuration of a
computing system 2000 according to an exemplary embodiment of the
present invention. The features of the computing system 2000 of
FIG. 7 that are the same as the previous embodiments will not be
redundantly described here.
[0098] As illustrated in FIG. 7, the computing system 2000
according to an exemplary embodiment of the preset invention
includes a memory device 2100, a CPU 2200, a RAM 2300, a user
interface 2400, a power supply 2500, a system bus 2600, etc.
[0099] The memory device 2100 stores data provided from the user
interface 2400, data processed by the CPU 2200, etc. Also, the
memory device 2100 is electrically connected to the CPU 2200, the
RAM 2300, the user interface 2400, the power source 2500, etc. via
the system bus 2600. For example, the memory device 2100 may be
connected to the system bus 2600 directly or via a controller (not
shown). When the memory device 2100 is connected directly to the
system bus 2600, the functions of the controller may be performed
using the CPU 2200, the RAM 2300, etc.
[0100] The memory device 2100 may be a non-volatile memory and
include memory strings as described above with reference to FIGS.
1A to 4C. The memory device 2100 further includes a pass
transistor, drain-side memory transistors connected in series to a
drain terminal of the pass transistor, and first to k.sup.th
source-side memory transistors connected in parallel to a source
terminal of the pass transistor. Here, `k` denotes an integer that
is equal to or greater than `2`. A structure of and a method of
fabricating the memory device 2100 are the same as described above
and will not be described here in detail.
[0101] Also, the memory device 2100 may be a multi-chip package
including a plurality of memory chips as described above with
reference to FIG. 6.
[0102] The computing system 2000 having the structure described
above may be a computer, a Ultra Mobile Personal Computer (UMPC), a
workstation, a net-book, a Personal Digital Assistants (PDA), a
portable computer, a web tablet, a wireless phone, a mobile phone,
a smart phone, an e-book, a Portable Multimedia Player (PMP), a
portable game console, a navigation device, a black box, a digital
camera, a 3-dimensional (3D) television, a digital audio recorder,
a digital audio player, a digital picture recorder, a digital
picture player, a digital video recorder, a digital video player,
an apparatus capable of transmitting/receiving information in a
wireless environment, one of various electronic devices that form a
home, computer, a telematics network, a radio-frequency
identification (RFID) device, etc.
[0103] As described above, the computing system 2000 according to
an exemplary embodiment of the present invention includes the
memory device 2100 improved in cell current and interference
characteristics and may thus have improved characteristics.
[0104] FIG. 8 is a block diagram of a computing system 3000
according to another exemplary embodiment of the present
invention.
[0105] As illustrated in FIG. 8, the computing system 3000
according to another exemplary embodiment of the present invention
includes a software layer including an operating system 3200, an
application 3100, a file system 3300, a translation layer 3400,
etc. The computing system 3000 further includes a hardware layer
such as a memory device 3500.
[0106] The operating system 3200 may manage software and hardware
resources, etc. of the computing system 3000, and is capable of
controlling execution of a program of a CPU (not shown). The
application 3100, as various programs that may be performed by the
computing system 3000, may be a utility performed by the operating
system 3200.
[0107] The file system 3300 means a logical structure used to
manage data, files, etc. that are present in the computing system
3000, and systemize files or data to be stored in the memory device
3500 according to a rule. The file system 3300 may be determined by
the operating system 3200 used in the computing system 3000. For
example, when the operating system 3200 is Windows by Microsoft,
the file system 3300 may be a file allocation table (FAT), an NT
file system (NTFS), etc. When the operating system 3200 is
Unix/Linux, the file system 3300 may be an extended file system
(EXT), a Unix file system (UFS), a journaling file system (JFS),
etc.
[0108] Although the operating system 3200, the application 3100,
and the file system 3300 are illustrated as separate blocks in FIG.
8, the application 3100 and the file system 3300 may be included in
the operating system 3200.
[0109] The translation layer 3400 translates an address into a form
suitable for the memory device 3500 in response to a request from
the file system 3300. For example, the translation layer 3400
translates a logic address generated by the file system 3300 into a
physical address of the memory device 3500. Here, mapping
information between the logic address and the physical address may
be stored in the form of an address translation table. For example,
the translation layer 3400 may be a flash translation layer (FTL),
a universal flash storage link layer (ULL), etc.
[0110] The memory device 3500 may be a non-volatile memory and
include memory strings as described above with reference to FIGS.
1A to 4C. Also, the memory device 3500 may further include a pass
transistor, drain-side memory transistors connected in series to a
drain terminal of the pass transistor, and first to k.sup.th
source-side memory transistors connected in parallel to a source
terminal of the pass transistor. Here, `k` denotes an integer that
is equal to or greater than `2`. The structure and method of
fabricating the memory device 3500 are the same as described above
and are not described here in detail.
[0111] The computing system 3000 having the structure described
above may be divided into an operating system layer implemented in
an upper-level region and a controller layer implemented in a
lower-level region. Here, the application 3100, the operating
system 3200, and the file system 3300 may be included in the
operating system layer, and driven by an operating memory of the
computing system 3000. The translation layer 3400 may be included
in the operating system layer or the controller layer.
[0112] As described above, the computing system 3000 according to
another exemplary embodiment of the present invention includes the
memory device 3500 improved in cell current and interference
characteristics and may thus have improved characteristics.
[0113] As described above, each of memory strings includes first to
k.sup.th source-side memory transistors connected in parallel to a
source terminal of a pipe transistor. Also, each of the memory
strings is connected to a plurality of source lines. Thus, the
integration degree and cell current characteristics of a
semiconductor device may be improved. Also, the characteristics of
the semiconductor device may be improved by reducing interferences
between memory cells.
[0114] In the drawings and specification, there have been disclosed
typical exemplary embodiments of the invention and, although
specific terms are employed, they are used in a generic and
descriptive sense only and not for purposes of limitation. As for
the scope of the invention, it is to be set forth in the following
claims. Therefore, it will be understood by those of ordinary skill
in the art that various changes in form and details may be made
therein without departing from the spirit and scope of the present
invention as defined by the following claims.
* * * * *