U.S. patent application number 15/012979 was filed with the patent office on 2016-05-26 for vertical cell-type semiconductor device having protective pattern.
The applicant listed for this patent is Dong-Seog EUN, Joon-Hee LEE, Seung-Woo PAEK, Jin-Yeon WON. Invention is credited to Dong-Seog EUN, Joon-Hee LEE, Seung-Woo PAEK, Jin-Yeon WON.
Application Number | 20160149010 15/012979 |
Document ID | / |
Family ID | 51568528 |
Filed Date | 2016-05-26 |
United States Patent
Application |
20160149010 |
Kind Code |
A1 |
WON; Jin-Yeon ; et
al. |
May 26, 2016 |
VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE
PATTERN
Abstract
According to example embodiments of inventive concepts, a
semiconductor device includes: a substrate, and a stacked structure
including interlayer insulating layers and gate electrodes
alternately stacked on the substrate. The stacked structure defines
a through-hole over the substrate. The gate electrodes each include
a first portion between the through-hole and a second portion of
the gate electrodes. A channel pattern may be in the through-hole.
A tunneling layer may surround the channel pattern. A charge trap
layer may surround the tunneling layer, and protective patterns may
surround the first portions of the gate electrodes. The protective
patterns may be between the first portions of the gate electrodes
and the charge trap layer.
Inventors: |
WON; Jin-Yeon; (Seoul,
KR) ; LEE; Joon-Hee; (Seongnam-si, KR) ; PAEK;
Seung-Woo; (Yongln-si, KR) ; EUN; Dong-Seog;
(Seongnam-sl, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
WON; Jin-Yeon
LEE; Joon-Hee
PAEK; Seung-Woo
EUN; Dong-Seog |
Seoul
Seongnam-si
Yongln-si
Seongnam-sl |
|
KR
KR
KR
KR |
|
|
Family ID: |
51568528 |
Appl. No.: |
15/012979 |
Filed: |
February 2, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
14151288 |
Jan 9, 2014 |
9281414 |
|
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15012979 |
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Current U.S.
Class: |
257/326 |
Current CPC
Class: |
H01L 29/42344 20130101;
H01L 29/66833 20130101; H01L 29/7926 20130101; H01L 27/11582
20130101; H01L 27/1157 20130101 |
International
Class: |
H01L 29/423 20060101
H01L029/423; H01L 29/792 20060101 H01L029/792; H01L 27/115 20060101
H01L027/115 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 19, 2013 |
KR |
10-2013-0029103 |
Claims
1.-20. (canceled)
21. A semiconductor device, comprising: a substrate; a stacked
structure including interlayer insulating layers and gate
electrodes alternately stacked on the substrate, the stacked
structure defining a through-hole, each of the gate electrodes
including a portion in which a vertical width thereof is reduced
with the approach to one end thereof; blocking layers between the
interlayer insulating layers and the gate electrodes; and a
vertical structure in the through-hole, the vertical structure
including a gap-fill pattern in a middle of the through-hole, a
channel pattern surrounding an outer surface of the gap-fill
pattern, and a gate dielectric layer surrounding an outer surface
of the channel pattern, wherein the gate dielectric layer includes
a tunneling layer in contact with the channel pattern, a charge
trap layer in contact with the tunneling layer, a barrier layer in
contact with the charge trap layer, and protective patterns being
between the barrier layer and one of the gate electrodes, each one
of the protective patterns extending between two of the interlayer
insulating layers, and wherein the protective patterns include an
oxide of silicon.
22. The semiconductor device of claim 21, wherein the blocking
layers includes a dielectric material having a metal.
23. The semiconductor device of claim 22, wherein the blocking
layers include aluminum oxide or hafnium oxide.
24. The semiconductor device of claim 21, wherein the protective
patterns is a higher density than the barrier layer.
25. The semiconductor device of claim 21, wherein each of the
portions of the gate electrodes includes an upper inclined surface
and a lower inclined surface opposite to the upper inclined
surface, and wherein each one of the protective patterns extends
between one of the interlayer insulating layers and the upper
inclined surface of the portion of one of the gate electrodes, and
between one of the interlayer insulating layers and the lower
inclined surface of the portion of one of the gate electrodes.
26. The semiconductor device of claim 25, wherein each of the gate
electrode further includes an upper surface opposite to a lower
surface, and wherein the blocking layers extends between one of the
interlayer insulating layer and the upper surface of one of the
gate electrodes, and between one of the interlayer insulating layer
and the lower surface of one of the gate electrode.
27. The semiconductor device of claim 21, wherein each one of the
protective patterns includes a protrusion protruding into the
through-hole.
28. The semiconductor device of claim 27, wherein the barrier layer
contacts exposed lateral surfaces of the interlayer insulating
layers, and the protrusions of the protective patterns.
29. The semiconductor device of claim 21, wherein a horizontal
distance between the portion of one of the gate electrodes and the
channel layer is greater than a horizontal distance between the
channel layer to one of the interlayer insulating layers.
30. The semiconductor device of claim 21, further comprising: a
contact electrode on the gap-fill pattern and contacting the
channel pattern.
31. The semiconductor device of claim 30, further comprising:
capping layers on the stacked structure, wherein the capping layers
define a hole exposing an upper surface of the contact
electrode.
32. The semiconductor device of claim 31, further comprising: a
conductive interconnection on the capping layers, wherein the
conductive interconnection is electrically connected to the exposed
upper surface of the contact electrode.
33. A semiconductor device, comprising: a substrate; a stacked
structure including interlayer insulating layers and gate
electrodes alternately stacked on the substrate, the stacked
structure defining a through-hole, each of the gate electrodes
including a portion in which a vertical width thereof is reduced
with the approach to one end thereof; blocking layers between the
interlayer insulating layers and the gate electrodes; a gap-fill
pattern in a middle of the through-hole; a channel pattern
surrounding an outer surface of the gap-fill pattern; and a gate
dielectric layer between the stacked structure and the channel
pattern, the gate dielectric layer includes a tunneling layer in
contact with the channel pattern, a charge trap layer in contact
with the tunneling layer, a protective layer in contact with the
charge trap layer, protective patterns that are integral with the
protective layer, the protective patterns extending to the gate
electrodes.
34. The semiconductor device of claim 33, wherein each of the
blocking layers extends between the gate electrodes and the gate
dielectric layer.
35. The semiconductor device of claim 33, wherein the protective
patterns include an oxide of silicon, the charge trap layer
includes one of silicon nitride, aluminum oxide, zirconium oxide,
hafnium oxide, lanthanum oxide, and the tunneling layer includes
one of silicon oxide and nitrogen-doped silicon oxide.
36. A semiconductor device, comprising: a substrate; interlayer
insulating layers on the substrate; gate electrodes between the
interlayer insulating layers, each of the gate electrode including
a first portion having a first lateral surface, and a second
portion having a second lateral surface opposite to the first
lateral surface, a length of the first lateral surface being
shorter than a length of the second lateral surface; blocking
layers between the interlayer insulating layers and the second
portions of the gate electrodes; a channel pattern on the first
portions of the gate electrodes, the channel pattern extending on
lateral surfaces of the interlayer insulating layers; and a gate
dielectric layer extending vertically over the substrate between
interlayer insulating layers and the channel pattern, the gate
dielectric layer including protective patterns between the channel
pattern and the blocking layers, the protective patterns extending
between the interlayer insulating layers and the first portions of
the gate electrodes.
37. The semiconductor device of claim 36, wherein the first
portions of the gate electrodes each have a thickness that
gradually reduces from the second portions of the gate electrodes
towards the gate dielectric layer.
38. The semiconductor device of claim 36, wherein the protective
patterns include an oxide of silicon, the interlayer insulating
layers include an oxide, and the oxide of silicon in the protective
patterns is more compact than the oxide of the interlayer
insulating layers.
39. The semiconductor device of claim 36, further comprising: a
protective layer that extends vertically over the substrate, the
protective layer extending between the gate dielectric layer and
the protective patterns, and between the interlayer insulating
layer and the gate dielectric layer.
40. The semiconductor device of claim 39, wherein a material of the
protective layer is the same as a material of the protective
patterns.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of U.S. application Ser.
No. 14/151,288, filed on Jan. 9, 2014, which claims priority under
35 U.S.C. .sctn.119 to Korean Patent Application No.
10-2013-0029103, filed on Mar. 19, 2013, the entire contents of
each of the above-referenced applications are hereby incorporated
by reference.
BACKGROUND
[0002] 1. Field
[0003] The present disclosure relates to a vertical cell-type
semiconductor device having a protective pattern, and/or a method
of fabricating the same.
[0004] 2. Description of Related Art
[0005] As integrated circuits are downscaled faster and faster, a
vertical cell-type semiconductor device in which components formed
in a vertical direction, has been proposed.
[0006] In a process of fabricating the vertical cell-type
semiconductor device, it may be desirable to limit (and/or prevent)
the components of the semiconductor device from being damaged by an
etchant used to remove sacrificial layers, and to reduce (and/or
minimize) voids or seams from being present in gate electrodes when
the gate electrodes are formed.
SUMMARY
[0007] Example embodiments of inventive concepts relate to a
vertical cell-type semiconductor device and/or a method of
fabricating the same.
[0008] Example embodiments of inventive concepts also relate to a
vertical cell-type semiconductor device having a protective pattern
resistant to a wet etching process, and a method of fabricating the
same.
[0009] Example embodiments of inventive concepts relate to a
vertical cell-type semiconductor device having protective patterns
of a new type, which are configured to remove or reduce (and/or
minimize) voids or seams in gate electrodes when the gate
electrodes are formed, and/or a method of fabricating the same.
[0010] According to example embodiments of inventive concepts, a
semiconductor device includes: a substrate; a stacked structure
including interlayer insulating layers and gate electrodes
alternately stacked on the substrate, the stacked structure
defining a through-hole, each of the gate electrodes including a
portion in which a vertical width thereof is reduced with the
approach to one end thereof; and a vertical structure filling the
through-hole. The vertical structure includes a gap-fill pattern in
a middle of the through-hole, a channel pattern surrounding an
outer surface of the gap-fill pattern, and a gate dielectric layer
surrounding an outer surface of the channel pattern. The gate
dielectric layer includes a tunneling layer in contact with the
channel pattern, a charge trap layer in contact with the tunneling
layer, a barrier layer in contact with the charge trap layer, and
protective patterns. Each one of the protective patterns is between
the barrier layer and one of the gate electrodes, and each one of
the protective patterns extends between two of the interlayer
insulating layers and the protective patterns surround the portions
the gate electrodes in which the vertical width thereof is
reduced.
[0011] In example embodiments, the protective patterns may include
an oxide of silicon, such as oxidized silicon.
[0012] In example embodiments, each one of the gate electrodes may
include an upper surface opposite a lower surface, a first lateral
surface opposite a second lateral surface, and an upper inclined
surface opposite a lower inclined surface. The first lateral
surface may connect one end of the upper surface to one end of the
lower surface. The upper inclined surface connected to one end of
the second lateral surface and an other end of the upper surface,
and the lower inclined surface may connect an other end of the
second lateral surface and an other end of the lower surface. A
length of the second lateral surface may be shorter than a length
of the first lateral surface.
[0013] In example embodiments, each one of the protective patterns
may include an upper part between a lower surface of one of the
interlayer insulating layers above and the upper inclined surface
of an adjacent one of the gate electrodes, a lower part between the
lower surface of one of the interlayer insulating layers below and
the lower inclined surface of the adjacent one of the gate
electrodes, and a body part connecting the upper part and the lower
part.
[0014] In example embodiments, the upper part of each one of the
protective patterns may include an inclined inner surface in
contact with the upper inclined surface of one of the gate
electrodes, and the lower part of each one of the protective
patterns may include an inclined inner surface in contact with the
lower inclined surface of one of the gate electrodes.
[0015] In example embodiments, the semiconductor device may further
include blocking layers. Each one of the blocking layers may have
one surface in contact with the upper surface, lower surface, upper
inclined surface, lower inclined surface, and second lateral
surface of one of the gate electrodes. Each one of the blocking
layers may have an other surface in contact with parts of two
interlayer insulating layers, the inclined upper and lower inner
surfaces and one surface of the body part of one of the protective
patterns.
[0016] In example embodiments, the body part of each one of the
protective patterns may include a protrusion that protrudes into
the through-hole.
[0017] In example embodiments, the barrier layer may contact
exposed surfaces of the interlayer insulating layers and the
protrusions of the body parts of the protective patterns.
[0018] In example embodiment, a contact electrode may be on the
gap-fill pattern and contact the channel pattern.
[0019] In example embodiments, the semiconductor device may further
include: capping layers on the stacked structure, wherein the
capping layers may define a hole exposing an upper surface of the
contact electrode.
[0020] In example embodiments, a conductive interconnection may be
on the capping layers. The conductive interconnection may be
electrically connected to the exposed contact electrode.
[0021] According to example embodiments of inventive concepts, a
semiconductor device includes: a substrate, a stacked structure
including interlayer insulating layers and gate electrodes
alternately stacked on the substrate, the stacked structure
defining a through-hole, each of the gate electrodes including a
portion in which a vertical width thereof is reduced with the
approach to one end thereof; and a vertical structure in the
through-hole. The vertical structure includes a gap-fill pattern in
a middle of the through-hole, a channel pattern surrounding an
outer surface of the gap-fill pattern, and a gate dielectric layer
surrounding an outer surface of the channel pattern. The gate
dielectric layer includes a tunneling layer in contact with the
channel pattern, a charge trap layer in contact with the tunneling
layer, a protective layer in contact with the charge trap layer,
and protective patterns that are integral with the protective
layer. The protective patterns extend to the gate electrodes, and
surround the portions of the gate electrodes in which the vertical
width is reduced.
[0022] According to example embodiments of inventive concepts, a
semiconductor device includes: a substrate; a stacked structure
including interlayer insulating layers and gate electrodes
alternately stacked on the substrate, the stacked structure
defining a through-hole over the substrate, the gate electrodes
each including a first portion between the through-hole and a
second portion of the gate electrodes; a channel pattern extending
vertically in the through-hole over the substrate; a tunneling
layer surrounding the channel pattern; a charge trap layer
surrounding the tunneling layer; and protective patterns
surrounding the first portions of the gate electrodes. The
protective patterns are between the first portions of the gate
electrodes and the charge trap layer.
[0023] In example embodiments, the first portions of the gate
electrodes may each have a thickness that gradually reduces from
the second portions of the gate electrodes towards the
through-hole, and the protective patterns may be arranged so they
do not surround the second portions of the gate electrodes.
[0024] In example embodiments, a barrier layer may be between the
protective patterns and the charge trap layer.
[0025] In example embodiments, a protective layer may extend
vertically in the through-hole between the charge trap layer and
the protective patterns. Each one of the protective patterns may
extend from a side of the protective layer to surround the first
portion of one of the gate electrodes.
[0026] In example embodiments, the protective patterns may include
an oxide of silicon, the interlayer insulating layer may include an
oxide, and the oxide of silicon in the protective patterns may be
more compact than the oxide of the interlayer insulating
layers.
[0027] Details of example embodiments of inventive concepts are
included in the detailed description and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The foregoing and other features and advantages of example
embodiments of inventive concepts will be apparent from the more
particular description of non-limiting embodiments of inventive
concepts, as illustrated in the accompanying drawings in which like
reference characters refer to the same parts throughout the
different views. The drawings are not necessarily to scale,
emphasis instead being placed upon illustrating the principles of
inventive concepts. In the drawings:
[0029] FIG. 1A is a cross-sectional view showing a vertical
cell-type semiconductor device according to example embodiments of
inventive concepts;
[0030] FIG. 1B illustrates an enlarged view of part A of FIG.
1A;
[0031] FIG. 1C illustrates an enlarged view of part B of FIG.
1B;
[0032] FIG. 2A illustrates a cross-sectional view showing a
vertical cell-type semiconductor device according to example
embodiments of inventive concepts;
[0033] FIG. 2B illustrates an enlarged view of part C of FIG.
2A;
[0034] FIG. 3A illustrates a cross-sectional view showing a
vertical cell-type semiconductor device according to example
embodiments of inventive concepts;
[0035] FIG. 3B illustrates an enlarged view of part D of FIG.
3A;
[0036] FIGS. 4A to 4Q illustrate process cross-sectional views
showing a method of fabricating a vertical cell-type semiconductor
device according to example embodiments of inventive concepts in a
process sequence;
[0037] FIGS. 5A to 5F illustrate process cross-sectional views
showing a method of fabricating a vertical cell-type semiconductor
device according to example embodiments of inventive concepts in a
process sequence;
[0038] FIGS. 6A to 6D illustrate process cross-sectional views
showing a method of fabricating a vertical cell-type semiconductor
device according to example embodiments of inventive concepts in a
process sequence;
[0039] FIG. 7 illustrates a conceptual view showing a semiconductor
module, which includes one of the semiconductor devices according
to example embodiments of inventive concepts;
[0040] FIG. 8 illustrates a conceptual block diagram showing an
electromagnetic system, which includes one of the semiconductor
devices according to example embodiments of inventive concepts;
[0041] FIG. 9 illustrates a schematic block diagram showing an
electromagnetic system, which includes a semiconductor device
according to example embodiments of inventive concepts; and
[0042] FIG. 10 schematically illustrates a mobile electromagnetic
appliance, which includes a semiconductor devices according to
example embodiments of inventive concepts.
DETAILED DESCRIPTION
[0043] Example embodiments of inventive concepts will now be
described more fully with reference to the accompanying drawings in
which some embodiments are shown. These example embodiments of
inventive concepts may, however, be embodied in different forms and
should not be construed as limited to the embodiments set forth
herein. Rather, these example embodiments of inventive concepts are
provided so that this disclosure is thorough and complete and fully
convey the scope of inventive concepts to those skilled in the art.
In the drawings, the sizes and relative sizes of layers and regions
may be exaggerated for clarity. Like reference numerals in the
drawings denote like elements, and thus their description may be
omitted.
[0044] It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it can be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected" or "directly coupled" to another
element, there are no intervening elements. Other words used to
describe relationships between elements should be interpreted in a
like fashion (e.g., "between" versus "directly between," "adjacent"
versus "directly adjacent," "on" versus "directly on", etc.). As
used herein the term "and/or" includes any and all combinations of
one or more of the associated listed items.
[0045] It will be understood that, although the terms first,
second, A, B, etc. may be used herein to describe various elements,
components, regions, layers and/or sections. These elements,
components, regions, layers and/or sections should not be limited
by these terms. These terms are only used to distinguish one
element, component, region, layer or section from another element,
component, region, layer or section. Thus, a first element,
component, region, layer or section discussed below could be termed
a second element, component, region, layer or section without
departing from the teachings of example embodiments.
[0046] Spatially relative terms, such as "beneath," "below,"
"lower," "above," "upper" and the like, may be used herein for ease
of description to describe one element's or feature's relationship
to another element(s) or feature(s) as illustrated in the figures.
It will be understood that the spatially relative terms are
intended to encompass different orientations of the device in use
or operation in addition to the orientation depicted in the
figures. For example, if the device in the figures is turned over,
elements described as "below" or "beneath" other elements or
features would then be oriented "above" the other elements or
features. Thus, the term "below" can encompass both an orientation
of above and below. The device may be otherwise oriented (rotated
90 degrees or at other orientations) and the spatially relative
descriptors used herein interpreted accordingly.
[0047] The terminology used herein to describe particular
embodiment and is not intended to limit the scope of example
embodiments of inventive concepts. The articles "a," "an," and
"the" are singular in that they have a single referent, however the
use of the singular form in the present document should not
preclude the presence of more than one referent. In other words,
elements referred to in the singular may number one or more, unless
the context clearly indicates otherwise. It will be further
understood that the terms "comprises," "comprising," "includes,"
and/or "including," when used herein, specify the presence of
stated features, items, steps, operations, elements, and/or
components, but do not preclude the presence or addition of one or
more other features, items, steps, operations, elements,
components, and/or groups thereof.
[0048] Example embodiments are described herein with reference to
cross-sectional illustrations that are schematic illustrations of
idealized embodiments (and intermediate structures). As such,
variations from the shapes of the illustrations as a result, for
example, of manufacturing techniques and/or tolerances, are to be
expected. Thus, example embodiments of inventive concepts should
not be construed as limited to the particular shapes of regions
illustrated herein but are to include deviations in shapes that
result, for example, from manufacturing. For example, an implanted
region illustrated as a rectangle will, typically, have rounded or
curved features and/or a gradient of implant concentration at its
edges rather than a binary change from implanted to non-implanted
region. Likewise, a buried region formed by implantation may result
in some implantation in the region between the buried region and
the surface through which the implantation takes place. Thus, the
regions illustrated in the figures are schematic in nature and
their shapes are not intended to illustrate the actual shape of a
region of a device and are not intended to limit the scope of the
present inventive concept.
[0049] Unless otherwise defined, all terms (including technical and
scientific terms) used herein are to be interpreted as is customary
in the art to which example embodiments of inventive concepts
belong. It will be further understood that terms in common usage
should also be interpreted as is customary in the relevant art and
not in an idealized or overly formal sense unless expressly so
defined herein.
[0050] FIG. 1A illustrates a cross-sectional view showing a
vertical cell-type semiconductor device according to example
embodiments of inventive concepts. FIG. 1B illustrates an enlarged
view of part A of FIG. 1A. FIG. 1C illustrates an enlarged view of
part B of FIG. 1B.
[0051] Referring to FIGS. 1A and 1B, a vertical cell-type
semiconductor device 100A according to example embodiments of
inventive concepts may include a stacked structure 100S formed on a
substrate 102, first to third capping layers 110, 126, and 128
covering the stacked structure 100S, a trench T passing through the
first to third capping layers 110, 126, and 128 in vertical and
horizontal directions, a through-hole H that is spaced apart from
the trench T and passes through the stacked structure 100S and the
first capping layer 110, first and second vertical structures VS1a
and VS2 filling the through-hole H and the trench T respectively, a
contact pad 124 disposed on a gap-fill pattern 122, a contact
electrode 140 passing through the second and third capping layers
126 and 128 to be in contact with the contact pad 124, and a
conductive interconnection 142 disposed on an upper surface of the
third capping layer 128 in contact with the contact electrodes
140.
[0052] The stacked structure 100S may include interlayer insulating
layers 104 and gate electrodes 134GS, 134C, and 134SS. The gate
electrodes 134C may be alternately stacked with interlayer
insulating layers 104 between the gate electrodes 134GS and 134SS.
The gate electrode 134GS may be on a lowermost one of the
interlayer insulating layers 104. An uppermost one of the
interlayer insulating layers 104 may be on the gate electrode
134SS. The interlayer insulating layers 104 may include silicon
oxide (SiO.sub.2), and the gate electrodes 134GS, 134C, and 134SS
may include a conductive material, such as tungsten (W), copper
(Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN),
tantalum (Ta), or doped silicon (n- or p-type Si).
[0053] The first vertical structure VS1a may include a gate
dielectric layer GDa formed along an inner wall of the through-hole
H, a cylindrical channel pattern 120 formed along an inner wall of
the gate dielectric layer GDa, and a gap-fill pattern 122 formed in
the center of the through-hole H so as to fill the interior of the
channel pattern 120. The channel pattern 120 may enclose an outer
surface of the gap-fill pattern 122, and the gate dielectric layer
GDa may enclose an outer surface of the channel pattern 120. An
upper surface of the gap-fill pattern 122 may be located lower than
an upper end of the through-hole H. Since the through-hole H may be
circular when viewed in a plan view, the first vertical structure
VS1a may look to be symmetrically formed on the inner wall of the
through-hole H when viewed in a longitudinal sectional view.
[0054] A lower portion of the channel pattern 120 may be in contact
with a surface of the substrate 102 and the surface of the
substrate 102 may be a bottom surface of the through-hole H. An
upper portion of the channel pattern 120 may be in contact with an
entire outer surface of the contact pad 124. The channel pattern
120 may include a semiconductor material, such as single
crystalline silicon or poly-crystalline silicon.
[0055] The substrate 102 may include a semiconductor substrate,
such as a silicon (Si) substrate, a silicon germanium (SiGe)
substrate, or a semiconductor-on-insulator (SOI) substrate. For
example, the semiconductor-on-insulator (SOI) substrate may be a
silicon-on-insulator substrate.
[0056] The contact pad 124 may include a conductive or
semiconductor material, such as single crystalline silicon or
poly-crystalline silicon. The first to third capping layers 110,
126, and 128 may include an insulating material, such as silicon
oxide. The contact electrode 140 and the conductive interconnection
142 may include a conductive material, such as copper (Cu),
tungsten (W), or aluminum (Al).
[0057] Among the plurality of gate electrodes 134GS, 134C, and
134SS, the lowermost gate electrode 134GS may be used as a ground
selection gate electrode 134GS, and the uppermost gate electrode
134SS may be used as a string selection gate electrode 134SS. Gate
electrodes 134C formed between the ground selection gate electrode
134GS and the string selection gate electrode 134SS may be used as
cell gate electrodes 134C. Thus, the ground selection gate
electrode 134GS, the gate dielectric layer GDa that is in contact
with the ground selection gate electrode 134GS, and the channel
pattern 120 may constitute a ground selection transistor. The cell
gate electrodes 134C, the gate dielectric layer GDa that is in
contact with the cell gate electrodes 134C, and the channel pattern
120 may constitute cell transistors. The string selection gate
electrode 134SS, the gate dielectric layer GDa that is in contact
with the string selection gate electrode 134SS, and the channel
pattern 120 may constitute a string selection transistor. In this
way, the ground selection transistor, the numerous cell
transistors, and the string selection transistor may form a unit
vertical cell string. The conductive interconnection 142 may be
used as a bit line.
[0058] The second vertical structure VS2 may have the shape of a
fence filling the trench T. The second vertical structure VS2 may
include silicon oxide.
[0059] Further referring FIGS. 1B and 1C, the gate electrodes
134GS, 134C, and 134SS of the vertical cell-type semiconductor
device 100A according to example embodiments of inventive concepts
may each include an upper surface GB1, a lower surface GB2, a first
lateral surface GB3, a second lateral surface GB4, an upper
inclined surface GB5 between the upper surface GB1 and the first
lateral surface GB4, and a lower inclined surface GB6 between the
lower surface GB2 and the second lateral surface GB4. A vertical
length of the second lateral surface GB4 may be shorter than that
of the first lateral surface GB3. The gate electrodes 134GS, 134C,
and 134SS may have a shape in which a vertical width W1 is reduced
with the approach to the second lateral surface GB4.
[0060] The gate dielectric layer GDa may include protective
patterns 112a, each of which partly encloses each of the gate
electrodes 134GS, 134C, and 134SS, a barrier layer 114 that is in
contact with exposed lateral surfaces of the protective patterns
112a and the interlayer insulating layers 104, a charge trap layer
116 that is in contact with the barrier layer 114, and a tunneling
layer 118 that have one surface of which is in contact with the
charge trap layer 116, and the other surface of which is in contact
with the channel pattern 120. Further, the gate dielectric layer
GDa may further include blocking layers 132 disposed among the gate
electrodes 134GS, 134C, and 134SS, the protective patterns 112a,
and the interlayer insulating layers 104.
[0061] The blocking layers 132 may each enclose the upper surface
GB1, the lower surface GB2, the first lateral surface GB3, the
second lateral surface GB4, the upper inclined surface GB5, and the
lower inclined surface GB6 of each of the gate electrodes 134GS,
134C, and 134SS. Thus, the blocking layers 132 may each include an
upper inclined part BK1 and a lower inclined part BK2 enclosing the
upper inclined surface GB5 and the lower inclined surface GB6 of
each of the gate electrodes 134GS, 134C, and 134SS.
[0062] The protective patterns 112a may include upper parts BB1
partly enclosing the upper inclined surfaces GB5 of the gate
electrodes 134GS, 134C, and 134SS and/or the upper inclined parts
BK1 of the blocking layers 132, lower parts BB2 enclosing the lower
inclined surface GB6 of the gate electrodes 134GS, 134C, and 134SS
and/or the lower inclined parts BK2 of the blocking layers 132, and
body parts BB3 enclosing the second lateral surfaces GB4 of the
gate electrodes 134GS, 134C, and 134SS and/or the lateral surfaces
of the blocking layers 132. The upper part BB1 of each protective
pattern 112a may have an inclined inner surface BB1a that is in
contact with the upper inclined part BK1 of each blocking layer
132. The lower part BB2 of each protective pattern 112a may have an
inclined inner surface BB2a that is in contact with the lower
inclined part BK2 of each blocking layer 132.
[0063] Each protective pattern 112a may include oxidized silicon
more compact (e.g., higher density) than oxide included in the
interlayer insulating layer 104 and barrier layer 114. A process of
forming the protective patterns 112a may include a radical
oxidation process.
[0064] A lateral profile of the barrier layer 114 may protrude or
be recessed along profiles of the protective patterns 112a. That
is, the barrier layer 114 may be in contact with portions P, each
of which protrudes into the through-hole H in the body part BB3 of
each protective pattern 112a, and one lateral surface of each
interlayer insulating layer 104. The barrier layer 114 may include
(deposited) silicon oxide.
[0065] In some cases, the barrier layer 114 may be omitted.
[0066] The charge trap layer 116 may be in contact with the barrier
layer 114. The charge trap layer 116 is an information storage
layer that functions to trap and hold electric charges implanted
from the channel pattern 120 through the tunneling layer 118, or to
eliminate the electric charges trapped in the tunneling layer 118.
A material of which the charge trap layer 116 is formed may include
silicon nitride (SiN.sub.x), aluminum oxide (Al.sub.2O.sub.3),
zirconium oxide (ZrO), hafnium oxide (HfO), or lanthanum oxide
(LaO), (e.g., a material having a higher dielectric constant
compared to silicon oxide.
[0067] The tunneling layer 118 is a passage through which the
electrons introduced from the channel pattern 120 move to the
charge trap layer 116. The tunneling layer 118 may include silicon
oxide or nitrogen-doped silicon oxide.
[0068] Each blocking layer 132 limits (and/or prevents) the
electric charges stored in the charge trap layer 116 from being
tunneled to each cell gate electrode 134C, and thereby can improve
information storage capability. Each blocking layer 132 may be in
contact with an upper and/or lower surface of each interlayer
insulating layer 104. Each blocking layer 132 may include an
insulating material having a high work function (and/or dielectric
constant), such as aluminum oxide (Al.sub.2O.sub.3) or hafnium
oxide (HfO.sub.2).
[0069] The vertical cell-type semiconductor device 100A according
to example embodiments of inventive concepts includes the barrier
layer 114 between the gate electrodes 134GS, 134C, and 134SS and
the charge trap layer 116, and the protective patterns 112a more
compact than the barrier layer 114, and thereby can limit (and/or
prevent) the charge trap layer 116 and the channel pattern 120 from
being damaged by an etchant.
[0070] Further, since each of the gate electrodes 134GS, 134C, and
134SS has a shape in which the vertical width W1 thereof is reduced
with the approach to one end thereof at an arbitrary position by
each protective pattern 112a, no or a (reduced and/or minimum
amount of) voids or seams can be present in the gate electrodes
134GS, 134C, and 134SS.
[0071] FIG. 2A illustrates a cross-sectional view showing a
vertical cell-type semiconductor device according to example
embodiments of inventive concepts. FIG. 2B illustrates an enlarged
view of part C of FIG. 2A.
[0072] Referring to FIGS. 2A, 2B, and 1C a vertical cell-type
semiconductor device 100b according to example embodiments of
inventive concepts may include a stacked structure 100S in which
interlayer insulating layers 104 and gate electrodes 134GS, 134C,
and 134SS are alternately and repeatedly stacked on a substrate
102, first to third capping layers 110, 126, and 128 covering the
stacked structure 100S, a through-hole H passing through the
stacked structure 100S and the first capping layer 110, a trench T
passing through the stacked structure 100S and the first to third
capping layers 110, 126, and 128, first and second vertical
structures VS1b and VS2 filling the through-hole H and the trench T
respectively, a contact pad 124 being in contact with the first
vertical structure VS1b, a contact electrode 140 passing through
the second and third capping layers 126 and 128 to be in contact
with the contact pad 124, and a conductive interconnection 142
formed on an upper surface of the third capping layer 128 in
contact with the contact electrode 140.
[0073] The first vertical structure VS1b may include a cylindrical
gate dielectric layer GDb formed along an inner wall of the
through-hole H, a channel pattern 120 formed along an inner wall of
the gate dielectric layer GDb, and a gap-fill pattern 122 filling
the interior of the channel pattern 120. The channel pattern 120
may be in contact with a surface of the substrate 102, which is a
bottom surface of the through-hole H, and an entire outer surface
of the contact pad 124.
[0074] The gate dielectric layer GDb may include a tunneling layer
118 enclosing the channel pattern 120, a charge trap layer 116
enclosing the tunneling layer 118, a barrier layer 114 enclosing
the charge trap layer 116, a protective layer 112b surrounding the
barrier layer 114, protective patterns 112c that are integrally
formed with the protective layer 112b, extend toward the gate
electrodes 134SS, 134C, and 134GS, and enclose one sides of the
gate electrodes 134SS, 134C, and 134GS, and blocking layers 132
that are in contact with the protective patterns 112c and enclose
the gate electrodes 134GS, 134C, and 134SS.
[0075] One surface of each blocking layer 132 may be in contact
with an upper surface GB1, a lower surface GB2, a first lateral
surface GB4, a second lateral surface GB5, and an upper inclined
surface GB6 of each of the gate electrodes 134SS, 134C, and 134GS,
and the other surface of each blocking layer 132 may be in contact
with parts of upper and lower surfaces of each interlayer
insulating layer 104 and an upper part BB1, a lower part BB2, and a
body part BB3 of each protective pattern 112c.
[0076] The protective layer 112b and the protective patterns 112c
may include oxidized silicon. The barrier layer 114 may include
deposited silicon oxide. The oxidized silicon included in the
protective layer 112b and the protective patterns 112c may be more
compact than the deposited silicon oxide included in the barrier
layer 114.
[0077] Since the protective layer 112b is present, the upper part
BB1, the lower part BB2, an inclined upper inner surface BB1a, and
an inclined lower inner surface BB2a of each protective pattern
112c that is in contact with the lower and upper surfaces of the
interlayer insulating layer 104, may be formed at a short length.
This configuration may mean that an area of the protective patterns
112c enclosing the gate electrodes 134SS, 134C, and 134GS within a
desired (and/or alternatively predetermined) space can be reduced,
compared to that of the semiconductor device 100A according to
example embodiments.
[0078] Thus, as an area which the protective patterns 112c occupy
within the desired (and/or alternatively predetermined) space is
reduced, an area of the gate electrode 134SS, 134C, and 134GS can
be increased as such. Nevertheless, since one side of each of the
gate electrodes 134SS, 134C, and 134GS can be formed in a shape in
which a vertical width thereof is reduced, voids and seams in the
gate electrodes 134SS, 134C, and 134GS can be reduced (and/or
minimized).
[0079] FIG. 3A illustrates a cross-sectional view showing a
vertical cell-type semiconductor device according to example
embodiments of inventive concepts. FIG. 3B illustrates an enlarged
view of part D of FIG. 3A.
[0080] Referring to FIGS. 3A, 3B, and 1C, a vertical cell-type
semiconductor device 100C according to example embodiments of
inventive concepts may include a stacked structure 100S in which
interlayer insulating layers 104 and gate electrodes 134GS, 134C,
and 134SS are alternately and repeatedly stacked on a substrate
102, first to third capping layers 110, 126, and 128 covering the
stacked structure 100S, a through-hole H passing through the
stacked structure 100S and the first capping layer 110, a trench T
passing through the stacked structure 100S and the first to third
capping layers 110, 126, and 128, first and second vertical
structures VS1c and VS2 filling the through-hole H and the trench T
respectively, a contact pad 124 being in contact with the first
vertical structure VS1c, a contact electrode 140 passing through
the second and third capping layers 126 and 128 to be in contact
with the contact pad 124, and a conductive interconnection 142
formed on an upper surface of the third capping layer 128 in
contact with the contact electrode 140.
[0081] The first vertical structure VS1c may include a gate
dielectric layer GDc formed along an inner wall of the through-hole
H, a cylindrical channel pattern 120 formed along an inner wall of
the gate dielectric layer GDc, and a gap-fill pattern 122 filling
the interior of the channel pattern.
[0082] The gate dielectric layer GDc may include a tunneling layer
118 enclosing the channel pattern 120, a charge trap layer 116
enclosing the tunneling layer 118, a protective layer 112d
enclosing the charge trap layer 116, protective patterns 112e that
are integrally formed with the protective layer 112d, extend toward
the gate electrodes 134SS, 134C, and 134GS, and enclose one sides
of the gate electrodes 134SS, 134C, and 134GS, and blocking layers
132 that are located between the protective patterns 112e and the
gate electrodes 134GS, 134C, and 134SS and enclose the gate
electrodes 134SS, 134C, and 134GS. Each blocking layer 132 may
enclose an upper surface, a lower surface, and one side of each of
the gate electrodes 134SS, 134C, and 134GS.
[0083] The protective layer 112d and the protective patterns 112e
may include oxidized silicon more compact than oxide included in
the barrier layer 114.
[0084] Since the protective layer 112d is present, the time
required for an oxidation process of forming the protective
patterns 112e can be reduced compared to the semiconductor device
100A according to example embodiments. As such, an upper part BB1,
a lower part BB2, an upper inner surface BB1a and a lower inner
surface BB2a of each protective pattern 112e that is in contact
with lower and upper surfaces of the interlayer insulating layer
104, may be formed at a short length. Thus, as described above, an
area which the protective patterns 112e occupy is reduced, an area
of the gate electrode 134SS, 134C, and 134GS can be increased as
such. Nevertheless, since one side of each of the gate electrodes
134SS, 134C, and 134GS may be formed in a shape in which a vertical
width thereof is reduced, voids and seams in the gate electrodes
134SS, 134C, and 134GS can be reduced (and/or minimized).
[0085] Further, since the protective patterns 112e and the
protective layer 112d are formed between the gate electrodes 134GS,
134C, and 134SS and the charge trap layer 116, they can replace a
function of the barrier layer 114 described above, and thus the
barrier layer 114 can be omitted. In this case, a horizontal width
W2 of the protective patterns 112e and the protective layer 112d
may be formed so as to be somewhat wider.
[0086] FIGS. 4A to 4Q illustrate process cross-sectional views
showing a method of fabricating the vertical cell-type
semiconductor device according to example embodiments of inventive
concepts in a process sequence.
[0087] Referring to FIG. 4A, a method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include alternately stacking
a plurality of interlayer insulating layers 104 and a plurality of
sacrificial layers 106 on a substrate 102 to form a preliminary
stacked structure 108, and stacking a first capping layer 110 on
the preliminary stacked structure 108. The substrate 102 may be
formed of a semiconductor material, and include, for instance, a
silicon (Si) substrate, a silicon germanium (SiGe) substrate, or a
silicon-on-insulator (SOI) substrate. The interlayer insulating
layers 104 may include silicon oxide (SiO.sub.2), and the
sacrificial layers 106 may include silicon nitride (SiNx). Further,
the first capping layer 110 may include silicon oxide
(SiO.sub.2).
[0088] Referring to FIG. 4B, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a
through-hole H vertically passing through the preliminary stacked
structure 108 and the first capping layer 110. An inner wall of the
through-hole H may be exposed lateral surfaces of the interlayer
insulating layers 104 and the sacrificial layers 106. A surface of
the substrate 102 may be a bottom surface of the through-hole
H.
[0089] Referring to FIG. 4C, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include oxidizing the exposed
sacrificial layers 106 to form protective patterns 112a. The
oxidation reaction of the sacrificial layers 106 may proceed from
the lateral surfaces exposed to the through-hole H. During the
oxidation reaction, oxygen radicals may penetrate into surfaces of
the sacrificial layers 106, and interfaces of the sacrificial
layers 106 and the interlayer insulating layers 104. The oxygen
radicals may penetrate along the interfaces of the sacrificial
layers 106 and the interlayer insulating layers 104 deeper than the
surfaces of the sacrificial layers 106. Thus, the protective
patterns 112a may be shaped of an open square bracket ([) or a
close square bracket (]). A thickness of each protective pattern
112a gets thinner and thinner in proportion to a distance from the
through-hole H. In contrast, each sacrificial layer 106 may have a
shape in which a vertical width W3 thereof is reduced in inverse
proportion to the distance from the through-hole H. Each protective
pattern 112a may be formed so as to enclose parts of upper and
lower surfaces of each sacrificial layer 106, and a lateral surface
of each sacrificial layer 106. Further, each protective pattern
112a may be in contact with parts of upper and lower surfaces of
each interlayer insulating layer 104. One vertical surface BB4 of
each protective pattern 112a may protrude toward the center of the
through-hole H. Here, during the oxidation reaction, the exposed
surface of the substrate 102, which is the bottom surface of the
through-hole H, may also be subjected to the oxidation
reaction.
[0090] The process of oxidizing the sacrificial layers 106 supplies
the oxygen radicals to the exposed surfaces of the sacrificial
layers 106. The oxidation process may include a radical oxidation
process. The radical oxidation process may include an in-situ steam
generation (ISSG) oxidation process and a plasma oxidation process.
The ISSG oxidation process is a radical oxidation process using
heat, and may use hydrogen (H.sub.2) gas, oxygen (O.sub.2) gas, or
water vapor (H.sub.2O) under low pressure at a high temperature of
800 to 1000.degree. C. For example, oxygen radicals are penetrated
into the sacrificial layers 106 and then coupled with silicon
dangling bonds in the sacrificial layers 106, or an oxygen radical
is penetrated with a strong force, cuts a nitrogen atom coupled to
a silicon atom and then is coupled to the silicon atom, and thereby
oxidized silicon may be formed. The plasma oxidation process is a
radical oxidation process using plasma, and may use a mixture gas
of argon (Ar), hydrogen, and oxygen gases, a mixture gas of argon
and oxygen gases, a mixture gas of helium (He), hydrogen, and
oxygen gases, a mixture gas of helium and oxygen gases, or a
mixture gas of hydrogen and oxygen gases. The plasma oxidation
process may proceed at a lower temperature compared to the ISSG
oxidation process. In the plasma oxidation process, temperature and
pressure conditions may be adjusted in order to enhance the
penetration of the oxygen radicals. The oxide formed in the
oxidation process has a more compact composition and a stronger
bond than that formed in a deposition process, and thus is
excellent in chemical and physical durability. For example, the
oxide formed in the oxidation process may have more excellent
etching resistance than that formed in the deposition process.
[0091] Referring to FIG. 4D, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include conformally forming a
first dielectric layer 114a on the exposed lateral surfaces of the
protective patterns 112a, interlayer insulating layers 104, and the
first capping layer 110 in the through-hole H and on an upper
surface of the first capping layer 110, conformally forming a
second dielectric layer 116a on an upper surface of the first
dielectric layer 114a, and conformally forming a third dielectric
layer 118a on an upper surface of the second dielectric layer 116a.
The first dielectric layer 114a may include silicon oxide, and the
second dielectric layer 116a may include silicon nitride (SiNx).
Further, the third dielectric layer 118a may include silicon oxide
or nitrogen-doped silicon oxide.
[0092] Referring to FIG. 4E, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a barrier
layer 114, a charge trap layer 116, and a tunneling layer 118 in
the through-hole H. The process of forming the barrier layer 114,
the charge trap layer 116, and the tunneling layer 118 may include
performing an etch-back process on the first to third dielectric
layers 114a, 116a, and 118a to remove the third, second, and first
dielectric layers 118a, 116a, and 114a on the first capping layer
110. The first to third dielectric layers 114a, 116a, and 118a
formed on the first capping layer 110 may be removed by an overall
anisotropic etching process(the etch back process), and thereby the
barrier layer 114 that are in contact with the vertical lateral
surfaces of the interlayer insulating layers 104, the charge trap
layer 116 and the tunneling layer 118, may be formed. Further,
during the etching process, the upper surface of the substrate 102
may be exposed at the bottom of the through-hole H.
[0093] Referring to FIG. 4F, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a channel
layer 120a along the upper surface of the substrate 102 which is
exposed at the bottom of the through-hole H, a surface of the
tunneling layer 118, and lateral and upper surfaces of the first
capping layer 110, and forming a gap-fill layer 122a on a surface
of the channel layer 120a so as to fill the interior of the
through-hole H. The process of forming the channel layer 120a may
include a chemical vapor deposition (CVD) process, such as an
atomic layer deposition (ALD) process. The channel layer 120a may
be formed in a polycrystalline state by continuous heat treatment.
Thus, the channel layer 120a may include polysilicon. The gap-fill
layer 122a may include an insulating material, such as silicon
oxide.
[0094] Referring to FIG. 4G, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a gap-fill
pattern 122 filling part of the through-hole H, and forming a
contact layer 124a on upper surfaces of the gap-fill pattern 122
and the channel layer 120a. The process of forming the gap-fill
pattern 122 may include removing a part of the gap-fill layer 122a
using an etch-back process so as to remain only in the through-hole
H. A surface of the gap-fill pattern 122 may be located lower than
that of the first capping layer 110. The contact layer 124a may
include polysilicon.
[0095] Referring to FIG. 4H, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a contact pad
124 and a channel pattern 120 in the through-hole H. The process of
forming the contact pad 124 and the channel pattern 120 may include
a planarization process of partly removing the contact layer 124a
and the channel layer 120a to expose the upper surface of the first
capping layer 110, for instance a chemical mechanical polishing
(CMP) process.
[0096] Referring to FIG. 4I, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a second
capping layer 126 and a third capping layer 128 on the through-hole
H and the first capping layer 110. The second and third capping
layers 126 and 128 may have an etch selectivity with respect to the
sacrificial layers 106. For example, if the sacrificial layers 106
are formed of silicon nitride, the second and third capping layers
126 and 128 may include silicon oxide.
[0097] Referring to FIG. 4J, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a trench T,
which passes through the first to third capping layers 110, 126,
and 128, and the preliminary stacked structure 108, at a position
spaced apart from the through-hole H.
[0098] Referring to FIG. 4K, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include removing the
sacrificial layers 106 located between the interlayer insulating
layers 104 in the trench T to form interlayer spaces 130. As an
etchant for removing the sacrificial layers 106, phosphoric acid
(H.sub.3PO.sub.4) may be used. After the sacrificial layers 106 are
removed using the phosphoric acid, a cleaning process using
standard clean 1 (SC-1) may further proceed. Here, in the process
of removing the sacrificial layers 106 using the phosphoric acid
(H.sub.3PO.sub.4), the protective patterns 112a may be exposed. The
protective patterns 112a can limit (and/or prevent) the phosphoric
acid (H.sub.3PO.sub.4) from penetrating the interior of the
through-hole H to cause damage to the barrier layer 114 and the
charge trap layer 116.
[0099] Referring to FIG. 4L, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include conformally forming a
fourth dielectric layer 132a on the exposed surfaces of the
interlayer insulating layers 104 and the first to third capping
layers 110, 126, and 128 which are exposed to the trench T. The
fourth dielectric layer 132a may include aluminum oxide
(Al.sub.2O.sub.3) or hafnium oxide (HfO).
[0100] Referring to FIG. 4M, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a conductive
layer 134a on the fourth dielectric layer 132a. The conductive
layer 134a may be formed so as to fill the interlayer spaces 130
(see FIG. 4L). A material of which the conductive layer 134a is
formed may include a doped semiconductor such as doped silicon, a
metal such as tungsten (W), copper (Cu), or aluminum (Al),
conductive metal nitride such as titanium nitride (TiN) or tantalum
nitride (TaN), a conductive metal-semiconductor compound such as
metal silicide, or transition metal such as titanium (Ti) or
tantalum (Ta). For example, the conductive layer 134a may include
tungsten (W) or titanium nitride (TiN).
[0101] Referring to FIG. 4N, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include partly removing the
conductive layer 134a to form a plurality of gate electrodes 134SS,
134C, and 134GS. The gate electrodes 134SS, 134C, and 134GS may
include a ground selection gate electrode 134GS located at a
lowermost side so as to be adjacent to the substrate 102, a string
selection gate electrode 134SS located at an uppermost side, and
cell gate electrodes 134C located between the ground selection gate
electrode 134GS and the string selection gate electrode 134SS.
Here, the number of cell gate electrodes 134C may be 2.sup.n (n is
the natural number). The gate electrodes 134SS, 134C, and 134GS may
each be formed in a shape in which a vertical width thereof is
reduced with the approach to the through-hole H.
[0102] Referring to FIGS. 4O and 1C, the method of fabricating the
vertical cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include partly removing the
fourth dielectric layer 132a to form blocking layers 132 enclosing
the gate electrodes 134GS, 134C, and 134SS. One surface of each
blocking layer 132 may be in contact with an upper surface GB1, a
lower surface GB2, an upper inclined surface GB5, a lower inclined
surface GB6, and a second lateral surface GB4 of each of the gate
electrodes 134GS, 134C, and 134SS, and the other surface of each
blocking layer 132 may be in contact with parts of the upper and
lower surfaces of the interlayer insulating layer 104 and the
protective patterns 112a.
[0103] Referring to FIG. 4P, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a second
vertical structure VS2 in the trench T, and forming a via 138
exposing the contact pad 124. The second vertical structure VS2 may
include silicon oxide (SiO.sub.2).
[0104] Referring to FIG. 4Q, the method of fabricating the vertical
cell-type semiconductor device 100A according to example
embodiments of inventive concepts may include forming a contact
electrode 140 that fills the via 138 and is in contact with the
contact pad 124, and forming a conductive interconnection 142
extending along an upper surface of the third capping layer 128 in
contact with the contact electrode 140. The contact electrode 140
and the conductive interconnection 142 may include a conductive
material, such as copper (Cu), tungsten (W), or aluminum (Al).
[0105] FIGS. 5A to 5F illustrate process cross-sectional views
showing a method of fabricating the vertical cell-type
semiconductor device according to example embodiments of inventive
concepts in a process sequence.
[0106] Referring to FIG. 5A, a method of fabricating the vertical
cell-type semiconductor device 100B according to example
embodiments of inventive concepts may include alternately stacking
a plurality of interlayer insulating layers 104 and a plurality of
sacrificial layers 106 on a substrate 102 to form a preliminary
stacked structure 108, and forming a first capping layer 110 on the
preliminary stacked structure 108 The interlayer insulating layers
104 may include silicon oxide, and the sacrificial layers 106 may
include silicon nitride.
[0107] Referring to FIG. 5B, the method of fabricating the vertical
cell-type semiconductor device 100B according to example
embodiments of inventive concepts may include forming a
through-hole H vertically passing through the first capping layer
110 and the preliminary stacked structure 108. An inner wall of the
through-hole H may correspond to exposed lateral surfaces of the
interlayer insulating layers 104 and the sacrificial layers 106.
The surface of the substrate 102 may be a bottom surface of the
through-hole H.
[0108] Referring to FIG. 5C, the method of fabricating the vertical
cell-type semiconductor device 100B according to example
embodiments of inventive concepts may include forming a first
dielectric layer 112baa on the inner wall of the through-hole H.
The first dielectric layer 112baa may include silicon nitride
(SiN.sub.X).
[0109] Referring to FIG. 5D, the method of fabricating the vertical
cell-type semiconductor device 100B according to example
embodiments of inventive concepts may include oxidizing the first
dielectric layer 112baa and a part of each sacrificial layer 106 to
form an oxide layer 112ba, and forming protective patterns 112c,
each of which extends from the oxide layer and encloses a part of
each sacrificial layer 106. Here, the process of oxidizing the
first dielectric layer 112baa and the sacrificial layers 106 may
include causing oxygen radicals to penetrate the first dielectric
layer 112baa and the sacrificial layers 106 to react with silicon
atoms. The oxidation reaction begins from a surface of the first
dielectric layer 112baa to proceed to a part of each sacrificial
layer 106.
[0110] In comparison with the semiconductor device 100A as
described above, each protective pattern 112c formed by oxidizing a
part of each sacrificial layer 106, may be formed at a short length
E at which it is in contact with lower and upper surfaces of each
interlayer insulating layer 106. This is because the oxide layer
112ba blocks or screens the oxygen radicals penetrating into an
interface between the interlayer insulating layer 104 and each
sacrificial layer 106. Thus, depending on the thickness of the
first dielectric layer 112baa, a thickness of the oxide layer 112ba
and a profile of each protective pattern 112c may be adjusted.
[0111] Referring to FIG. 5E, the method of fabricating the vertical
cell-type semiconductor device 100B according to example
embodiments of inventive concepts may include conformally forming a
second dielectric layer 114a on the exposed surface of the oxide
layer 112ba, conformally forming a third dielectric layer 116a on
the second dielectric layer 114a, and conformally forming a fourth
dielectric layer 118a on the third dielectric layer 116a. The
second dielectric layer 114a may include silicon oxide, and the
third dielectric layer 116a may include silicon nitride. Further,
the fourth dielectric layer 118a may include silicon oxide or
nitrogen-doped silicon nitride.
[0112] Referring to FIG. 5F, the method of fabricating the vertical
cell-type semiconductor device 100B according to example
embodiments of inventive concepts may include forming a protective
layer 112b, a barrier layer 114, a charge trap layer 116, and a
tunneling layer 118 in the through-hole H. The process of forming
the protective layer 112b, the barrier layer 114, the charge trap
layer 116, and the tunneling layer 118 may include an overall
anisotropic etching process of partly removing the oxide layer
112ba and the second to fourth dielectric layers 114a, 116a, and
118a so that the oxide layer 112ba and the second to fourth
dielectric layers 114a, 116a, and 118a are left only on the inner
wall of the through-hole H. Due to the overall anisotropic etching
process, the oxide layer 112ba may be etched to form the protective
layer 112b that is in contact with the inner wall of the
through-hole H, and the second dielectric layer 114a may be etched
to form the barrier layer 114 that is in contact with the
protective layer 112b. Further, the third dielectric layer 116a may
be etched to form the charge trap layer 116 that is in contact with
the barrier layer 114, and the fourth dielectric layer 118a may be
etched to form the tunneling layer 118 that is in contact with the
charge trap layer 116. The following processes are equal to those
described with reference to FIGS. 4F to 4Q, and description thereof
will be omitted.
[0113] FIGS. 6A to 6D illustrate process cross-sectional views
showing a method of fabricating a vertical cell-type semiconductor
device according to example embodiments of inventive concepts in a
process sequence.
[0114] Referring to FIG. 6A, a method of fabricating a vertical
cell-type semiconductor device 100C according to example
embodiments of inventive concepts may include alternately stacking
a plurality of interlayer insulating layers 104 and a plurality of
sacrificial layers 106 on a substrate 102 to form a preliminary
stacked structure 108, forming a first capping layer 110 on the
preliminary stacked structure 108, and forming a through-hole H
passing through the first capping layer 110 and the preliminary
stacked structure 108. Further, the method may include forming a
first dielectric layer 112daa on an inner wall of the through-hole
H. The first dielectric layer 112daa may include silicon
nitride.
[0115] Referring to FIG. 6B, the method of fabricating the vertical
cell-type semiconductor device 100C according to example
embodiments of inventive concepts may include oxidizing the first
dielectric layer 112daa and a part of each sacrificial layer 106 to
form an oxide layer 112da, and forming protective patterns 112e
extending from the oxide layer 112da. Here, the process of
oxidizing the first dielectric layer 112daa and the interlayer
insulating layer 104 may include causing oxygen radicals to
penetrate the first dielectric layer and the interlayer insulating
layer 104 to react with silicon atoms. The oxidation reaction of
the silicon atoms may begin from a surface of the first dielectric
layer 112daa to proceed to a part of each sacrificial layer 106.
The protective patterns 112e may be formed by the oxidation
reaction.
[0116] Referring to FIG. 6C, a method of fabricating the vertical
cell-type semiconductor device 100C according to example
embodiments of inventive concepts may include conformally forming a
second dielectric layer 116a on the exposed surface of the oxide
layer 112da, and conformally forming a third dielectric layer 118a
on the second dielectric layer 116a. The second dielectric layer
116a may include silicon nitride, and the third dielectric layer
118a may include silicon oxide.
[0117] Referring to FIG. 6D, the method may include etching an
oxide layer 112da, a trap dielectric layer 114a, and a tunneling
dielectric layer 116a to form a protective layer 112d, a charge
trap layer 116, and a tunneling layer 118. The protective layer
112d and the protective patterns 112e has etching resistance to an
etchant for removing the sacrificial layers 106, and simultaneously
performs a barrier function. For example, the barrier layer 114 may
be omitted. The following processes are equal to those described
with reference to FIGS. 4F to 4Q, and description thereof will be
omitted.
[0118] FIG. 7 illustrates a conceptual view showing a semiconductor
module, which includes a semiconductor devices according to example
embodiments of inventive concepts.
[0119] Referring to FIG. 7, a semiconductor module 500 according to
example embodiments of inventive concepts may include a
semiconductor device according to example embodiments of inventive
concepts (e.g., one of the semiconductor devices 100A, 100B, and
100C according to example embodiments of inventive concept) that is
mounted on a semiconductor module board 510. The semiconductor
module 500 may further include a microprocessor 520 mounted on the
module board 510. Input/output terminals 540 may be disposed on at
least one side of the module board 510. The semiconductor module
500 may include a memory card or a solid state drive (SSD).
[0120] FIG. 8 illustrates a conceptual block diagram showing an
electromagnetic system, which includes a semiconductor devices
according to example embodiments of inventive concepts.
[0121] Referring to FIG. 8, one of the semiconductor devices 100A,
100B, and 100C according to example embodiments of inventive
concepts may be applied to an electromagnetic system 600. The
electromagnetic system 600 may include a body 610, a microprocessor
unit 620, a power distributor 630, a function unit 640, and/or a
display controller unit 650. The body 610 may be a system board or
a motherboard having a printed circuit board (PCB). The
microprocessor unit 620, the power distributor 630, the function
unit 640, and the display controller unit 650 may be mounted on the
body 610. A display unit 660 may be disposed on the top of the body
610 or outside the body 610. For example, the display unit 660 may
be disposed on a surface of the body 610, and display an image
processed by the display controller unit 650. The power supply 630
may be supplied with a desired (and/or alternatively predetermined)
voltage from an external power supply, divide the voltage into
various levels, and supply those voltages to the microprocessor
unit 620, the function unit 640, and the display controller unit
650. The function unit 640 may perform various functions of the
electromagnetic system 600. For example, if the electromagnetic
system 600 is a mobile electromagnetic appliance such a mobile
phone, the function unit 640 may include various components that
can perform wireless communication functions such as image output,
or voice output to a speaker, by dialing or communication with an
external apparatus 670. If the electromagnetic system 600 includes
a camera, the function unit 640 may serve as an image processor. In
example embodiments, if the electromagnetic system 600 is connected
to a memory card for capacity expansion, the function unit 640 may
be a memory card controller. The function unit 640 may send/receive
a signal to/from the external apparatus 670 via a wired or wireless
communication unit 680. Further, if the electromagnetic system 600
requires a universal serial bus (USB) for function expansion, the
function unit 640 may serve as an interface controller. One of the
semiconductor devices 100A, 100B, and 100C according to example
embodiments of inventive concepts may be included in the function
unit 640.
[0122] FIG. 9 illustrates a schematic block diagram showing an
electromagnetic system, including a semiconductor device according
to example embodiments of inventive concepts.
[0123] Referring to FIG. 9, an electromagnetic system 700 may
include one of the semiconductor devices 100A, 100B, and 100C
described previously.
[0124] The electromagnetic system 700 may be applied to a mobile
electromagnetic appliance or a computer. For example, the
electromagnetic system 700 may include a memory 712, a
microprocessor 714, and a user interface 718 performing data
communication using a random access memory (RAM) 716 and a bus 720.
The microprocessor 714 may program and control the electromagnetic
system 700. The RAM 716 may be used as an operation memory of the
microprocessor 714. For example, the microprocessor 714 or the RAM
716 may include one of the semiconductor devices 100A, 100B, and
100C according to example embodiments of inventive concepts.
[0125] The microprocessor 714, the RAM 716, and/or other components
may be assembled in a single package. The user interface 718 may be
used to input/output data to/from the electromagnetic system 700.
The memory 712 may store codes for operating the microprocessor
714, data processed by the microprocessor 714, or external input
data. The memory 712 may include a controller and a memory.
[0126] FIG. 10 schematically shows a mobile electromagnetic
appliance, which includes one of the semiconductor devices
according to example embodiments of inventive concepts. The mobile
electromagnetic appliance 800 may be understood to be a tablet
personal computer (PC). In addition, at least one of the
semiconductor devices 100A, 100B, and 100C according to example
embodiments of inventive concepts may be used for a portable
computer, such as a laptop computer, a MPEG-1 or MPEG-2 Audio Layer
III (MP3) player, an MP4 player, a navigation device, a solid state
disk (SSD), a desktop computer, a vehicle, and a household electric
appliance, in addition to the tablet PC.
[0127] According to example embodiments of inventive concepts, the
protective patterns can reduce (and/or prevent) a wet etching
solution from causing damage to the gate dielectric layers (charge
trap layer, tunneling layer, etc.) and the channel pattern.
[0128] Further, since each protective pattern is formed within a
desired (and/or alternatively predetermined) space so as to enclose
one side of each gate electrode, each gate electrode can be formed
in a shape in which the vertical width thereof is reduced with the
approach to one side thereof. In this case, no or minimum voids or
seams can be present in each gate electrode.
[0129] The foregoing disclosure is illustrative of example
embodiments of inventive concepts and is not to be construed as
limiting thereof. Although a few embodiments have been described,
those skilled in the art will readily appreciate that many
modifications are possible without materially departing from the
scope of the claims. Accordingly, all such modifications are
intended to be included within the scope of example embodiments of
inventive concepts as defined in the claims. In the claims,
means-plus-function clauses are intended to cover the structures
described herein as performing the recited function, and not only
structural equivalents but also equivalent structures.
* * * * *