U.S. patent application number 14/923824 was filed with the patent office on 2016-05-19 for three dimensional non-volatile memory with separate source lines.
This patent application is currently assigned to SANDISK TECHNOLOGIES INC.. The applicant listed for this patent is SANDISK TECHNOLOGIES INC.. Invention is credited to Alexander Chu, Nima Mokhlesi.
Application Number | 20160141301 14/923824 |
Document ID | / |
Family ID | 55962392 |
Filed Date | 2016-05-19 |
United States Patent
Application |
20160141301 |
Kind Code |
A1 |
Mokhlesi; Nima ; et
al. |
May 19, 2016 |
THREE DIMENSIONAL NON-VOLATILE MEMORY WITH SEPARATE SOURCE
LINES
Abstract
A three dimensional stacked non-volatile memory device comprises
alternating dielectric layers and conductive layers in a stack, a
plurality of bit lines below the stack, and a plurality of source
lines above the stack. There is a separate source line for each bit
line. Each source lines is connected to a different subset of NAND
strings. Each bit line is connected to a different subset of NAND
strings. Multiple data states are verified concurrently. Reading is
performed sequentially for the data states. The data states are
programmed concurrently with memory cells being programmed to lower
data states having their programming slowed by applying appropriate
source line voltages and bit line voltages.
Inventors: |
Mokhlesi; Nima; (Los Altos,
CA) ; Chu; Alexander; (San Francisco, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SANDISK TECHNOLOGIES INC. |
Plano |
TX |
US |
|
|
Assignee: |
SANDISK TECHNOLOGIES INC.
Plano
TX
|
Family ID: |
55962392 |
Appl. No.: |
14/923824 |
Filed: |
October 27, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62081463 |
Nov 18, 2014 |
|
|
|
Current U.S.
Class: |
365/185.22 ;
257/324; 365/185.18; 365/185.23 |
Current CPC
Class: |
H01L 27/11517 20130101;
G11C 11/5628 20130101; G11C 11/5642 20130101; G11C 16/26 20130101;
G11C 16/0483 20130101; H01L 27/11526 20130101; H01L 27/11582
20130101; G11C 16/24 20130101; G11C 16/3459 20130101; H01L 27/11578
20130101; H01L 27/11573 20130101; G11C 16/10 20130101; G11C 16/08
20130101 |
International
Class: |
H01L 27/115 20060101
H01L027/115; G11C 16/34 20060101 G11C016/34; G11C 16/26 20060101
G11C016/26; G11C 16/04 20060101 G11C016/04; G11C 16/10 20060101
G11C016/10; G11C 16/24 20060101 G11C016/24 |
Claims
1. An apparatus, comprising: a stack of alternating dielectric
layers and conductive layers; columns of memory cells formed in the
stack; a plurality of bit lines connected to the columns and
positioned at a first side of the stack; and a plurality of source
lines connected to the columns and positioned at a second side of
the stack.
2. The apparatus of claim 1, wherein: the first side is opposite
the second side; and the plurality of bit lines are positioned
below the stack and the plurality of source lines are positioned
above the stack.
3. The apparatus of claim 1, wherein: each source line of the
plurality of source lines is connected to a different subset of
columns of memory cells; and each bit line of the plurality of bit
lines is connected to a different group of columns of memory
cells.
4. The apparatus of claim 3, wherein: a separate source line of the
plurality of source lines is associated with each bit line of the
plurality of bit lines; and each source line is connected to a same
plurality of columns as its associated bit line.
5. The apparatus of claim 1, further comprising: bit line drivers
connected to the bit lines and positioned beneath the stack; and
source line drivers connected to the source lines and positioned to
the side of the stack.
6. The apparatus of claim 1, further comprising: a control circuit
connected to the bit lines and the source lines, the control
circuit configured to perform a memory operation on memory cells in
different active columns of memory cells, each of the active
columns has a unique dedicated bit line of the plurality of bit
lines and a unique dedicated source line of the plurality of source
lines.
7. The apparatus of claim 1, further comprising: a control circuit
connected to the bit lines and the source lines, the control
circuit configured to apply data dependent voltages to the source
lines and the bit lines and the control circuit configured to apply
a fixed number of program pulses to selected memory cells to
concurrently program the selected memory cells to a set of data
states in separate threshold voltage distributions for the data
states.
8. The apparatus of claim 1, further comprising: word lines
connected to the memory cells; and a control circuit connected to
the source lines, bit lines and word lines, the control circuit
configured to apply data dependent voltages to the source lines and
the bit lines to concurrently verify the memory cells for multiple
data states in response to a common word line voltage.
9. The apparatus of claim 8, wherein: the control circuit
configured to read data from the memory cells one data state at a
time.
10. The apparatus of claim 8, further comprising: multiple pads to
bring in multiple voltages that serve as the data dependent
voltages.
11. The apparatus of claim 1, further comprising: a control circuit
connected to the source lines, the control circuit configured to
apply data dependent voltages to the source lines to program the
memory cells for multiple data states and subsequently apply data
dependent voltages to the source lines to verify the memory cells
for multiple data states without lowering source line voltages.
12. The apparatus of claim 1, wherein: each column of memory cells
forms a NAND string; and the stack is a three dimensional memory
array.
13. A method, comprising: applying a particular voltage to a word
line connected to multiple memory cells in different active columns
of memory cells formed in a three dimensional memory structure,
each of the active columns having a unique dedicated bit line of a
set of bit lines and a unique dedicated source line of a set of
source lines; applying voltages to the source lines; and performing
a memory operation on the memory cells in response to the
particular voltage and the voltages applied to the source
lines.
14. The method of claim 13, further comprising: applying data
dependent voltages to the bit lines, the voltages applied to the
source lines are data dependent voltages, the memory operation is
performed in response to the particular voltage, the data dependent
voltages applied to the source lines and the data dependent
voltages applied to the bit lines.
15. The method of claim 14, wherein: the applying data dependent
voltages to the bit lines and the applying voltages to the source
lines comprises ramping up the bit lines and the source lines
before a program pulse in two stages, during a first stage the bit
lines and source lines are raised to a lower of their respective
target or VCC and in a second stage the bit lines and source lines
are raised to their respective target if they were not already at
their target.
16. The method of claim 13, wherein: the particular voltage
includes a voltage pulse; the applying data dependent voltages to
the source lines comprises applying different source line voltages
based on target data states; and the performing the memory
operation comprises concurrently verifying for all target data
states in response to the voltage pulse and the different source
line voltages based on target data states.
17. The method of claim 13, wherein: the particular voltage
includes a number of voltage pulses; the applying data dependent
voltages to the source lines comprises applying different source
line voltages based on target data states; and the performing the
memory operation comprises concurrently programming memory cells to
the target data states in response to the number of voltage pulses
and the different source line voltages based on target data
states.
18. The method of claim 13, wherein: the performing the memory
operation includes applying programming while applying the data
dependent voltages to the source lines and subsequently verifying
programming without lowering the source lines while transitioning
from programming to verifying.
19. An apparatus, comprising: a plurality of memory cells arranged
as NAND strings in a three dimensional memory structure; a
plurality of bit lines below the three dimensional memory
structure, each bit line is connected to a different subset of
multiple NAND strings; and a plurality of source lines above the
three dimensional memory structure, each NAND string is a vertical
column of memory cells having a charge trapping layer with one end
of the column connected to one of the source lines and an opposite
end of the column connected to one of the bit lines, a separate
source line is associated with each bit line, each source line is
connected to a different subset of multiple NAND strings, each
source line and its associated bit line connect to the same
multiple NAND strings.
20. The apparatus of claim 19, further comprising: a word line
connected to the NAND strings, all of the memory cells being
programmed are concurrently verified for all target data states
using a single voltage pulse on the word line and data dependent
voltages on the bit lines and source lines.
Description
CLAIM OF PRIORITY
[0001] This application claims the benefit of U.S. Provisional
Application 62/081,463, filed Nov. 18, 2014, incorporated herein by
reference in its entirety.
BACKGROUND
[0002] 1. Field
[0003] The present technology relates to three dimensional
non-volatile memory.
[0004] 2. Description of Related Art
[0005] Recently, ultra high density storage devices have been
proposed using a three dimensional (3D) stacked memory structure
sometimes referred to as a Bit Cost Scalable (BiCS) architecture.
For example, a 3D NAND stacked memory device can be formed from an
array of alternating conductive and dielectric layers. A memory
hole is drilled in the layers to define many memory layers
simultaneously. A NAND string is then formed by filling the memory
hole with appropriate materials. A straight NAND string (I-BiCS)
extends in one memory hole, while a pipe- or U-shaped NAND string
(P-BiCS) includes a pair of vertical columns of memory cells which
extend in two memory holes and which are joined by a bottom back
gate. Control gates of the memory cells are provided by the
conductive layers. However, various challenges are presented in
operating such memory devices.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Like-numbered elements refer to common components in the
different figures.
[0007] FIG. 1A is a perspective view of a portion of a 3D stacked
non-volatile memory.
[0008] FIG. 1B is a functional block diagram of a memory system
that includes the 3D stacked non-volatile memory of FIG. 1A.
[0009] FIG. 1C and FIG. 1D show the positioning of the memory
array, source line drivers and bit line drivers.
[0010] FIG. 2 is a perspective view of a portion of a 3D stacked
non-volatile memory.
[0011] FIG. 3 is a side view of a portion of a 3D stacked
non-volatile memory.
[0012] FIG. 4 is a cross sectional and perspective view of a column
of the 3D stacked non-volatile memory.
[0013] FIG. 5 is a block diagram of a 3D memory array.
[0014] FIG. 6 is a top view of one layer of the 3D stacked
non-volatile memory.
[0015] FIG. 7 is a side view of a portion of a 3D stacked
non-volatile memory.
[0016] FIG. 8 depicts a set of threshold voltage distributions
representing data states.
[0017] FIGS. 9A-9E depict a programming process.
[0018] FIG. 10 is a flow chart describing one embodiment of a
process for programming.
[0019] FIG. 11 is a table identifying various voltages applied to
the individual source lines and bit lines.
[0020] FIG. 12 is a table identifying various voltages applied to
word lines and select gate lines.
[0021] FIG. 13 depicts the voltage applied to the selected word
line during a programming process.
[0022] FIG. 14 is a flow chart describing one embodiment of a
process for verifying.
[0023] FIG. 15 is a flow chart describing one embodiment of a
process for reading
[0024] FIG. 16 is a table of voltages used during one embodiment of
programming and verification of programming.
DETAILED DESCRIPTION
[0025] A three dimensional stacked non-volatile memory device is
proposed that comprises alternating dielectric layers and
conductive layers in a stack, a plurality of bit lines below the
stack, and a plurality of source lines above the stack. There is a
separate source line associated with each bit line, rather than one
source line for an entire block, plane or array. Each source line
is connected to a different subset of NAND strings. Each bit line
is connected to a different subset of NAND strings. Because the bit
lines are below the stack, there is no need for signal lines to
carry signals from the substrate surface to the top of the stack
for the bit lines and no crowding of lines occurs as bit lines try
to pass through source lines when they are both at minimum pitch.
Since bit line driver circuits are bigger than source line driver
circuits, one embodiment locates bit lines on the bottom so that
the bit line driver residing on the silicon surface under the array
have direct access to the bit lines. In one embodiment, the source
line drivers, being smaller in size, are placed on the side of the
memory array in. Since the source line drivers are smaller than the
bit line drivers and also smaller than the traditional sense amp
circuits, this arrangement shrinks the memory die size by saving
the area which is traditionally reserved for sense amplifiers (the
traditional bit line drivers).
[0026] The three dimensional stacked memory device comprises a
plurality of memory cells arranged in blocks. Each block includes
memory holes (or pillars) which extend vertically in the stack, and
comprise a column of memory cells such as, for example, in a NAND
string. The three dimensional stacked non-volatile memory device
includes N layers. In one embodiment, a block includes one word
line on each layer. The memory holes are divided into four groups
at each level of a block and each group has a separate set of
source side and drain side select signals so that a subset of
memory holes can be active at any given time. Because of the
concurrency in the programming and verifying, the number of
programming and verify pulses is reduced and the overall
programming process is faster than other architectures. This is
enabled because each memory channel/hole in a selected group has
its own dedicated source line in addition to having its own
dedicated bit line. With this architecture each memory channel can
be driven to its own designated voltage at both its source line and
its bit line. This provides full control of the channel potential.
Each channel can have one of 8 (or another number) different
potentials applied to it based on what data state is to be
programmed on the memory cell that is along that channel and
belongs to the selected word line. A data state is a condition of
the memory cell which correlates to storing a predefined pattern of
data. The meaning of a data state can change based on the type of
memory technology used in various embodiments. For example, in a
multi-level memory cell different threshold voltage levels for the
cell may correlate to a particular data pattern that represents
data settings on two or more logical levels of data stored in the
multi-level memory cell. In another example, the data state may
comprise the level of resistance for a filament formed in the cell.
In another example, the data state may comprise the magnetic
orientation of a magnetic layer in a Spin-transfer torque random
access memory cell (STT-RAM).
[0027] The proposed structure allows for multiple data states to be
verified concurrently, as is explained below. Memory cells are
concurrently programmed to different data states, with memory cells
being programmed to lower data states having their programming
slowed by applying appropriate source line voltages and bit line
voltages. In one embodiment, reading is performed sequentially for
the data states.
[0028] FIG. 1A is a perspective view of a portion of a 3D stacked
non-volatile memory device. The memory device 100 includes a
substrate 101. On the substrate are example blocks BLK0 and BLK1 of
memory cells and a peripheral area 104 with circuitry for use by
the blocks. The substrate 101 can also carry circuitry under the
blocks, along with one or more metal layers lower than the bit line
layer which are patterned in conductive paths to carry signals of
the circuitry. The blocks are formed in an intermediate region 102
of the memory device. In an upper region 103 of the memory device,
one or more upper metal layers are patterned in conductive paths to
carry signals of the circuitry. Each block comprises a stacked area
of memory cells, where alternating levels of the stack represent
word lines. While two blocks are depicted in FIG. 1A as an example,
additional blocks can be used, extending in the x- and/or
y-directions.
[0029] In one possible approach, the length of the plane, in the
x-direction, represents a direction in which word lines extend, and
the width of the plane, in the y-direction, represents a direction
in which bit lines extend. The z-direction represents a height of
the memory device.
[0030] FIG. 1B is a functional block diagram of the 3D stacked
non-volatile memory device 100 of FIG. 1A. The memory device 100
may include one or more memory die 108. The memory die 108 includes
a memory array 126 of memory cells, control circuitry 110, and
read/write circuits 128. The memory array 126 is addressable by
word lines via a row decoder 124 and by bit lines via a column
decoder 132. The read/write circuits 128 include multiple sense
blocks 130 (sensing circuitry) and allow a page of memory cells to
be read or programmed in parallel. In some embodiments, a
controller 122 is included in the same memory device 100 (e.g., a
removable storage card) as the one or more memory die 108. Commands
and data are transferred between the host and controller 122 via
lines 120 and between the controller and the one or more memory die
108 via lines 118.
[0031] The control circuitry 110 cooperates with the read/write
circuits 128 to perform memory operations on the memory array 126,
and includes a state machine 112, an on-chip address decoder 114,
and a power control module 116. The state machine 112 provides
chip-level control of memory operations. The on-chip address
decoder 114 provides an address interface between that used by the
host or a memory controller to the hardware address used by the
decoders 124 and 132. The power control module 116 controls the
power and voltages supplied to the word lines and bit lines during
memory operations. It can include drivers for word lines, source
side select lines (SGS) and drain side select lines (SGD) and
source lines. The sense blocks 130 can include bit line drivers and
circuits for sensing. Control circuitry 110 is also in
communication with source control circuits 127, which includes
source line driver circuit 1, source line driver circuit 2, . . . ,
source line driver circuit p. The source line driver circuits are
used to drive different (or the same) voltages on the individual
source lines. The present architecture provides individual control
of one source line per active memory cell. Hundreds of thousands
(for example about 300,000) of source line driver circuits are
required in addition to the same number of bit line driver
circuits. The control of memory cell along the Y direction requires
two individual drivers per cell being simultaneously programmed or
simultaneously verified.
[0032] In some implementations, some of the components can be
combined. In various designs, one or more of the components (alone
or in combination), other than memory array 126, can be thought of
as at least one control circuit. For example, a control circuit may
include any one of, or a combination of, control circuitry 110,
state machine 112, decoders 114/132, power control module 116,
sense blocks 130, read/write circuits 128, and controller 122, and
so forth.
[0033] FIG. 1C and FIG. 1D show the positioning of the memory
array, source line drivers and bit line drivers. FIG. 1C shows the
embodiment where bit line drivers (BL Driver) are below the memory
array (memory) and source line drivers (SL Driver) are to the side
(where the bit line drivers are in some of the prior art). FIG. 1C
also shows an example source line SL above the memory and an
example bit line BL below the memory. The SL Driver includes a
unity gain buffer for matching BL voltage during programming and a
low Vth single transistor amp (source follower) for subtracting
.about.0.5V from VBL to apply to SL. FIG. 1D shows the embodiment
where bit line drivers (BL Driver) and source line drivers (SL
Driver) are below the memory. One of the metal layers bellow the
memory layer will be consumed. Then there would be 3 available
metal layers, for example, for connecting the bit line drivers, but
only two layers available for connecting the source line drivers.
It also means that the layer below the bit line layer becomes a
critical layer at minimum pitch. FIGS. 1C/D show how bit lines and
source lines can coexist without any difficulty encountered when
one set try to pass through the other set. No such difficulty
exists because one set does not need to try to pass through the
other set. FIGS. 1C/D illustrate that both sets can be comfortably
connected to their drivers without having to cross each other's
metal layers. Any 3D memory architecture that has vertical channels
as well as channels fabricated above metal layers (e.g. poly
silicon channels as opposed to crystalline silicon channel) can
benefit from the attributes of this new architecture. Note that
crystalline channels require crystalline seed layer of silicon from
which the crystalline silicon channel can be grown by epitaxy.
[0034] FIG. 2 is a perspective view of a portion of one embodiment
of memory array 126 that is a three dimensional stacked
non-volatile memory comprising alternating dielectric layers and
conductive layers in a stack, a plurality of bit lines below the
stack, and a plurality of source lines above the stack. For
example, FIG. 2 shows conductive layers 202, 204, 206, 208, 210,
212, 214, 216, and 218, each of which operates as a word line and,
therefore, can be referred to as a word line layer. To allow the
drawing to fit on one page and be readable, not all of the
conductive layers are depicted. For example, FIG. 2 does not show
any of the conductive layers operating as source side select layers
(SGSs) and drain side select layers (SGDs). One embodiment may
include 60 conductive layers, with 48 conductive layers operating
as word line layers, 2 layers above the 48 word line layers as
dummy layers on the source side, 4 layers above dummy source layers
operating as source side select layers (SGS) and 2 layers below the
48 word line layers as dummy layers on the drain side, 4 layers
below dummy drain layers operating as drain side select layers
(SGDs). Other embodiments can implement different numbers of word
line layers, dummy layers, source side select layers and drain side
select layers.
[0035] Between the conductive layers are dielectric layers. Many
different dielectric materials can be used. One example of a
suitable dielectric material is SiO.sub.2. Note that FIG. 2 does
not show the dielectric material between the conductive layers.
[0036] Below the stack of alternating dielectric layers and
conductive layers are bit lines 220, 222, 224, 226, 228, 230, 232,
and 234. Although FIG. 2 only shows eight bit lines, the memory
system is likely to have many more than eight bit lines (e.g.
300,000).
[0037] Above the stack of alternating dielectric layers and
conductive layers are source lines 240, 242, 244, 246, 248, 250,
252 and 254. Although FIG. 2 only shows eight source lines, the
memory system is likely to have many more than eight source lines
(e.g. 300,000). In one embodiment, the bit line drivers (which
include the sense amps) are located below the stack while the
source line drivers are located to the side of the stack. In
another embodiment, both bit line drivers and source line drivers
are located under the array. This provides further die size savings
at the expense of consuming one of a number of available metal
layers over the source line drivers and under the bit lines for
connecting the source line drivers to the source lines. The number
of available metal layers above the silicon surface and below the
bit line layer in certain embodiments is either 2 or 3.
[0038] The stack of alternating dielectric layers and conductive
layers includes memory holes or pillars which extend vertically in
the stack, and comprise a column of memory cells such as in a NAND
string. FIG. 2 shows columns/holes/pillars 260, 262, 264, 266, 268,
270, and 272. Although FIG. 2 only shows seven columns, the memory
system is likely to have many more than seven columns. As depicted,
each conductive layer will surround a set of columns, with the
interface between the conductive layer (serving as a word line) and
the column comprising the memory cell.
[0039] Each bit line is connected to a subset of columns. For
example, FIG. 2 shows bit 230 connected to column 272, bit line 224
connected to column 270, bit line 220 connected to column 268 (note
that column 268 is only partially depicted), and bit line 222
connected to column 262. Note that the terms "connected," "coupled"
and "in communication with" include direct connections and
connections via other components. The bit lines connect to the
columns through a combination of vias and plugs. For example, bit
230 is connected to column 272 by via 284 and plug 274, bit line
224 is connected to column 270 by via 286 and plug 276, bit line
220 is connected to column 268 by via 288 and plug 278, and bit
line 222 is connected to column 262 by via 290 and plug 280.
[0040] Each source line is connected to a subset of columns. In one
embodiment, the source lines connect to the columns through vias
and plugs. FIG. 2 shows plugs 291, 292, 293 and 294, as well as
vias 295 and 296. Many of the via for the source lines are hidden
due to the perspective view. However, FIG. 2 does show column 270
connected to source line 244 by via 295 and plug 292.
[0041] In prior memory systems, all of the source lines are
connected together such that all of the NAND strings receive a
common source voltage. In the embodiment of FIG. 2, the source
lines are not connected together and can carry different signals.
In one embodiment, each source line is associated with a bit line.
That is, the system includes source line and bit line pairs. Each
bit line is associated with a different and separate source line. A
source line is connected to the same column as its associated bit
line. For example, bit line 230 is associated with source line 252
and both are connected to column 272, bit line 224 is associated
with source line 244 and both are connected to column 270, bit line
220 is associated with source line 240 and both are connected to
column 268, and bit line 222 is associated with source line 242 and
both are connected to column 262. In one embodiment, the bit lines
are made of Tungsten, the source lines are made of Tungsten, the
vias are made of Tungsten and the plugs are made of polysilicon. In
one embodiment, the conductive word line layers are made of
Tungsten. Tungsten may be preferable as it can withstand the
process thermal budget associated with processing the layers above
it, and the required dopant activation or polysilicon channel grain
size expansion anneal steps that follow the deposition of the
Tungsten.
[0042] FIG. 3 is a side view of the structure depicted in FIG. 2.
Like FIG. 2, although FIG. 3 shows conductive layers 202, 204, 206,
208, 210, 212, 214, 216, and 218, FIG. 3 does not explicitly depict
the dielectric layers between the conductive layers. Furthermore,
FIG. 3 (like FIG. 2) only shows a subset of the conductive
layers.
[0043] FIG. 4 is a perspective view of a cross section of a column
from the stack described above. Each column includes a number of
layers which are deposited along the sidewalls of the column. These
layers formed on the sidewall of the memory holes can include, from
the outer perimeter of the hole moving radially in toward the
center, a charge trapping layer such as a specially formulated
silicon nitride that increases trap density, followed by
oxide-nitride-oxide (O--N--O) stack layer that acts as a band gap
engineered tunnel dielectric, followed by polysilicon layer(s),
followed by the inner most dielectric such as silicon oxide core
fill. These layers are deposited using methods such as atomic layer
deposition, chemical vapor deposition, or physical vapor
deposition. There are many other intermediary steps such as
anneals, densifications and sacrificial layers that are temporarily
deposited and later removed. The inner most oxide of the ONO tunnel
dielectric that is in contact with the polysilicon channel can be
created by converting some thickness of the deposited nitride layer
to oxide by methods such as ISSG (In-Situ Steam Generation). Other
layers of the cell structure can be formed by depositions into the
sacrificial nitride layers as opposed to by deposition in the
memory hole. Such layers can include the silicon oxide blocking
layer and the aluminum oxide high K transition layer between the
blocking payer and the word line. The word line deposition can
start with titanium nitride layer deposited on aluminum oxide
followed by a tungsten seed layer deposition and then the remainder
of the cavities for word line fingers can be filled tungsten.
Inside the cavities between word line layers, for example, a
blocking oxide (SiO.sub.2) can be deposited. The Blocking Oxide
surrounds the charge trapping layer. Surrounding the Blocking
Oxide, and between the Blocking Oxide and the Word Line
(TiN+Tungsten) is an Aluminum Oxide layer. The polysilicon channel
is connected to a bit line at the bottom of the column and
connected to the associated source line at the top of the column
through intermediary deposited patterned layers including a metal
via and a doped polysilicon plug, as discussed above. The
polysilicon plugs can be n-type, preferably doped with some
combination of Arsenic or phosphorus, or they can be p-type
preferably doped with some combination of Boron or indium. In some
embodiments Arsenic and indium are preferable because they diffuse
more slowly during high temperature anneals which are required for
poly crystalline grain size changes and other purposes.
[0044] When a memory cell is programmed, electrons are stored in a
portion of the charge trapping layer which is associated with the
memory cell. These electrons are drawn into the charge trapping
layer from the polysilicon channel, and through the ONO tunnel
dielectric. The threshold voltage (Vth) of a memory cell is
increased in proportion to the amount of stored charge.
[0045] Each of the memory holes is thus filled with a plurality of
annular layers comprising a charge trapping layer, a tunneling
layer and a channel layer. A core region of each of the memory
holes is filled with a body material, and the plurality of annular
layers are between the core region and the WLLs in each of the
memory holes.
[0046] Looking back at FIG. 2, memory system 100 includes a memory
array 126 having the structure depicted in FIGS. 2, 3, and 4. FIG.
5 is a block diagram explaining the organization of memory array
126, which is divided into two planes 502 and 504. Each plane is
then divided into N blocks. In one example, each plane has about
2000 blocks. However, different numbers of blocks and planes can
also be used.
[0047] FIG. 6 is a block diagram depicting a portion of a top view
of one layer of one block. The portion of the block depicted in
FIG. 6 corresponds to box 450 in block 2 of FIG. 5. As can be seen
from FIG. 5, the block depicted in FIG. 6 extends in the direction
of arrow 632 and in the direction of arrow 630. In one embodiment,
the memory array will have 48 memory layers; therefore, block will
have 48 layers. However, FIG. 6 only shows one layer. Each layer of
a block has only one word line. For example, the layer of block 2
depicted in FIG. 6 includes word line 210 (see FIG. 2) surrounding
a plurality of circles. Each circle represents a column (see FIG.
4). FIG. 6 has reference numbers for columns 270 (see FIG. 2), 272
(see FIG. 2), 650, 652, 654, 656, 658, 670, 672, 674, 676 and 678.
Not all columns are provided with reference numbers in order to
keep FIG. 6 readable. Some of the circles are shaded to indicate
that those columns will not be used to store data, and are
sacrificed to provide spacing.
[0048] FIG. 6 also shows dashed vertical lines. These are the bit
lines. FIG. 6 shows sixteen bit lines: 220, 222, 224, 226, 228,
230, 232, 234, 604, 606, 608, 610, 612, 614 and 616. The lines are
dashed to indicate that the bit lines are not part of this layer,
rather they are below the stack. Each of the non-shaded circles has
an "x" to indicate its connection to a bit line.
[0049] FIG. 6 does not show the source lines in order to keep the
drawing readable. However, the source lines would be in the same
position as the bit lines, but located above the stack rather than
below. The source lines would connect to the columns in the same
manner as the bit lines. Therefore, a source line and its
associated bit line connect to the same columns. In this manner,
the structure of the source lines is symmetrical to the structure
of the bit lines. Thus for every active column, there is a
dedicated bit line and source line. If multiple columns are active
at the same time, then each of the active columns has a unique
dedicated bit line and a unique dedicated source line.
[0050] As can be seen from FIG. 6, each block has sixteen rows of
active columns and each bit line connects to four columns in each
block. For example, bit line 228 is connected to columns 652, 654,
670 and 674. Since all of these columns 652, 654, 670 and 674 are
connected to the same word line 210, the system uses the source
side select lines and the drain side select lines to choose one (or
another subset) of the four to be subjected to a memory operation
(program, verify, read, and/or erase).
[0051] FIG. 7 is a side cutaway view of a portion of the memory
array, along bit line 228 and source line 254. Note that bit line
228 is the associated bit line for source line 254. FIG. 7 shows
that while the word line layers extend across the entire block, the
source side select lines and the drain side select lines are broken
up into four sections. In one embodiment, the source side select
lines are implemented as four vertical layers connected together
(in some embodiments not connected together). Within each block,
all four layers are broken into four sets of source side select
lines: SGS0, SGS1, SGS2 and SGS3. Similarly, the drain side select
lines are implemented as four vertical layers connected together
(in some embodiments not connected together). Within each block,
all four layers of drain side select lines are broken into four
sets of drain side select lines: SGD0, SGD1, SGD2 and SGD3. In one
embodiment, SGS0 and SGD0 are used to control columns 764 and 676,
SGS1 and SGD1 are used to control columns 672 and 670, SGS2 and
SGD2 are used to control columns 654 and 656, and SGS3 and SGD3 are
used to control columns 272 and 652.
[0052] FIG. 8 illustrates example threshold voltage distributions
for the memory cell array when each memory cell stores three bits
of data. Other embodiments, however, may use more or less than
three bits of data per memory cell (e.g., such as two bits of data
per memory cell, or four bits of data per memory cell). In the
example of FIG. 8, there are eight valid threshold voltage
distributions, also called data states (or target states): S0, S1,
S2, S3, S4, S5, S6 and S7. In one embodiment, data state S0 is
below 0 volts and data states S1-S7 are above 0 volts. In other
embodiments, all eight data states are above 0 volts, or other
arrangements can be implemented. In one embodiment, the threshold
voltage distribution for S0 is wider than for S1-S7. In one
embodiment, S0 is for erased memory cells. Data is programmed from
S0 to S1-S7.
[0053] Each data state corresponds to a unique value for the three
data bits stored in the memory cell. In one embodiment, S0=111,
S1=110, S2=101, S3=100, S4=011, S5=010, S6=001 and S7=000. Other
mapping of data to states S0-S7 can also be used. The specific
relationship between the data programmed into the memory cell and
the threshold voltage levels of the cell depends upon the data
encoding scheme adopted for the cells. For example, U.S. Pat. No.
6,222,762 and U.S. Patent Application Publication No. 2004/0255090,
"Tracking Cells For A Memory System," filed on Jun. 13, 2003,
describe various data encoding schemes for multi-state flash memory
cells. In one embodiment, data values are assigned to the threshold
voltage ranges using a Gray code assignment so that if the
threshold voltage of a floating gate erroneously shifts to its
neighboring threshold voltage distribution, only one bit will be
affected. However, in other embodiments, Gray code is not used.
[0054] In one embodiment, all of the bits of data stored in a
memory cell are stored in the same logical page. In other
embodiments, each bit of data stored in a memory cell corresponds
to different logical pages. Thus, a memory cell storing three bits
of data would include data in a first page, data in a second page
and data in a third page. In some embodiments, all of the memory
cells connected to the same word line would store data in the same
three pages of data. In some embodiments, the memory cells
connected to a word line can be grouped into different sets of
pages (e.g., by odd and even bit lines, or by other
arrangements).
[0055] In some devices, the memory cells will be erased to state
S0. From state S0, the memory cells can be programmed to any of
states S1-S7. In one embodiment, known as full sequence
programming, memory cells can be programmed from the erased state
S0 directly to any of the programmed states S1-S7. For example, a
population of memory cells to be programmed may first be erased so
that all memory cells in the population are in erased state S0.
While some memory cells are being programmed from state S0 to state
S1, other memory cells are being programmed from state S0 to state
S2, state S0 to state S3, state S0 to state S4, state S0 to state
S5, state S0 to state S6, and state S0 to state S7. Full sequence
programming is graphically depicted by the seven curved arrows of
FIG. 8. In other embodiments, memory cells can be programmed using
a coarse/fine methodology or other scheme.
[0056] FIG. 8 shows a set of verify target levels Vv1, Vv2, Vv3,
Vv4, Vv5, Vv6, and Vv7. These verify levels are used as comparison
levels (also known as target levels and/or compare levels) during
the programming process. For example, when programming memory cells
to state S1, the system will check to see if the threshold voltages
of the memory cells have reached Vv1. If the threshold voltage of a
memory cell has not reached Vv1, then programming will continue for
that memory cell until its threshold voltage is greater than or
equal to Vv1. If the threshold voltage of a memory cell has reached
Vv1, then programming will stop for that memory cell. Verify target
level Vv2 is used for memory cells being programmed to state S2.
Verify target level Vv3 is used for memory cells being programmed
to state S3. Verify target level Vv4 is used for memory cells being
programmed to state S4. Verify target level Vv5 is used for memory
cells being programmed to state S5. Verify target level Vv6 is used
for memory cells being programmed to state S6. Verify target level
Vv7 is used for memory cells being programmed to state S7.
[0057] FIG. 8 also shows a set of read compare levels Vr1, Vr2,
Vr3, Vr4, Vr5, Vr6, and Vr7. These read compare levels are used as
comparison levels during the read process. By testing whether the
memory cells turn on or remain off in response to the read compare
levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 being separately
applied to the control gates of the memory cells, the system can
determine for which states that memory cells are storing data. In
one embodiment, Vr1=0.2 v, Vr2=1.0 v, Vr3=1.8 v, Vr4=2.6 v, Vr5=3.4
v, Vr6=4.2 v and Vr7=5.0 v. However, other values can also be
used.
[0058] In general, during verify operations and read operations,
the selected word line is connected to a voltage (one example of a
reference signal), a level of which is specified for each read
operation (e.g., see read compare levels Vr1, Vr2, Vr3, Vr4, Vr5,
Vr6, and Vr7, of FIG. 8) or verify operation (e.g. one voltage is
used to verify all states, as discussed below) in order to
determine whether a threshold voltage of the concerned memory cell
has reached such level. After applying the word line voltage, the
conduction current of the memory cell is measured to determine
whether the memory cell turned on (conducted current) in response
to the voltage applied to the word line. If the conduction current
is measured to be greater than a certain value, then it is assumed
that the memory cell turned on and the voltage applied to the word
line is greater than the threshold voltage of the memory cell. If
the conduction current is not measured to be greater than the
certain value, then it is assumed that the memory cell did not turn
on and the voltage applied to the word line is not greater than the
threshold voltage of the memory cell. During a read or verify
process, the unselected memory cells on selected columns (i.e. NAND
chains) corresponding to a selected word line (i.e. finger) are
provided with one or more read pass voltages at their control gates
so that these memory cells will operate as pass gates (e.g.,
conducting current regardless of whether they are programmed or
erased).
[0059] There are many ways to measure the conduction current of a
memory cell during a read or verify operation. In one example, the
conduction current of a memory cell is measured by the rate it
discharges or charges a dedicated capacitor in the sense amplifier
while maintaining a specified bit line voltage. In another example,
the conduction current of the selected memory cell allows (or fails
to allow) the NAND string that includes the memory cell to
discharge a corresponding bit line. The voltage on the bit line is
measured after a period of time to see whether it has been
discharged or not. Note that the technology described herein can be
used with different methods known in the art for verifying/reading.
Other read and verify techniques known in the art can also be
used.
[0060] In some embodiments, the program voltage applied to the
control gate includes a series of pulses that are increased in
magnitude with each successive pulse by a predetermined step size
(e.g. 0.2 v, 0.3 v, 0.4 v, 0.6 v, or others). Between pulses, some
memory systems will verify whether the individual memory cells have
reached their respective target threshold voltage ranges.
[0061] FIGS. 9A-9E depict one example programming process that uses
six Vpgm program pulses on the selected word line to achieve
threshold voltage distributions as per FIG. 8. Initially, in one
embodiment, all memory cells being programmed are erased to data
state S0. After erasing, a first Vpgm program pulse is applied. In
one embodiment, the first Vpgm program pulse is at 19 v. All memory
cells being programmed will receive that same Vpgm program pulse.
However, data dependent voltages are individually applied to the
different bit lines and the different source lines so that memory
cells being programmed to higher data states (e.g., S7) will
increase in threshold voltage more quickly and memory cells being
programmed to lower data states (e.g., S1) will increase in
threshold voltage slower. The voltages applied to the bit lines and
source lines are based on the target data state. therefore, all
memory cells being programmed to S1 will be subjected to a first
bit line voltage and a first source line voltage, all memory cells
being programmed to S2 will be subjected to a second bit line
voltage and a second source line voltage, all memory cells being
programmed to S3 will be subjected to a third bit line voltage and
a third source line voltage, all memory cells being programmed to
S4 will be subjected to a fourth bit line voltage and a fourth
source line voltage, all memory cells being programmed to S5 will
be subjected to a fifth bit line voltage and a fifth source line
voltage, all memory cells being programmed to S6 will be subjected
to a six bit line voltage and a six source line voltage, and all
memory cells being programmed to S7 will be subjected to a seventh
bit line voltage and a seventh source line voltage.
[0062] FIG. 9A depicts the results of applying the first Vpgm
program pulse. FIG. 9A shows the target data states in solid lines
and shows the actual threshold voltage distributions in dashed
lines 802, 804, 806, 808, 810, 812 and 814. Actual threshold
voltage distribution 802 represent the threshold voltage
distribution for memory cells being programmed to data state S1.
Actual threshold voltage distribution 804 represent the threshold
voltage distribution for memory cells being programmed to data
state S2. Actual threshold voltage distribution 806 represent the
threshold voltage distribution for memory cells being programmed to
data state S3. Actual threshold voltage distribution 808 represent
the threshold voltage distribution for memory cells being
programmed to data state S4. Actual threshold voltage distribution
810 represent the threshold voltage distribution for memory cells
being programmed to data state S5. Actual threshold voltage
distribution 812 represent the threshold voltage distribution for
memory cells being programmed to data state S6. Actual threshold
voltage distribution 814 represent the threshold voltage
distribution for memory cells being programmed to data state S7.
Note that the height/magnitude of the actual threshold voltage
distributions 802, 804, 806, 808, 810, 812 and 814 is somewhat
exaggerated in Figures A-E in order to make the drawings easier to
read.
[0063] FIG. 9B depicts the results of applying the second Vpgm
program pulse. As depicted, actual threshold voltage distributions
802, 804, 806, 808, 810, 812 and 814 have moved toward higher
voltages.
[0064] FIG. 9C depicts the results of applying the third Vpgm
program pulse. As depicted, actual threshold voltage distributions
802, 804, 806, 808, 810, 812 and 814 have moved toward higher
voltages.
[0065] FIG. 9D depicts the results of applying the fourth Vpgm
program pulse. As depicted, actual threshold voltage distributions
802, 804, 806, 808, 810, 812 and 814 have moved toward higher
voltages.
[0066] FIG. 9E depicts the results of applying the fifth Vpgm
program pulse. As depicted, actual threshold voltage distributions
802, 804, 806, 808, 810, 812 and 814 have moved toward higher
voltages. After the sixth Vpgm program pulse, the actual threshold
voltage distributions should be the same (or close) to the
threshold voltage distributions depicted in FIG. 8.
[0067] FIG. 10 is a flow chart describing one embodiment of a
process for performing programming on memory cells connected to a
common word line to one or more targets (e.g., data states or
threshold voltage ranges). The process of FIG. 10 is one example of
how to implement the behavior depicted in FIG. 9. The process of
FIG. 10 can also be used to implement programming strategies
different than that of FIG. 9.
[0068] Typically, the program voltage applied to the control gate
during a program operation is applied as a series of program
pulses. Between programming pulses the system will perform
verification. In many implementations, the magnitude of the program
pulses is increased with each successive pulse by a predetermined
step size. In step 868 of FIG. 10, the programming voltage (Vpgm)
is initialized to the starting magnitude (e.g., .about.19V or
another suitable level) and a program counter PC maintained by
state machine 112 is initialized at 1. In step 870, data dependent
voltages are individually applied to the different bit lines and
the different source lines. Data dependent voltages are voltages
that vary based on the data pattern being programmed. More details
of step 870 are discussed below with respect to FIG. 11. In step
872, a program pulse of the program signal Vpgm is applied to the
selected word line (the word line selected for programming) In one
embodiment, the group of memory cells being programmed concurrently
are all connected to the same word line (the selected word line).
In step 572, the program pulse is concurrently applied to all
memory cells connected to the selected word line.
[0069] In step 874, it is determined whether the program counter PC
is less than K. In one embodiment, K=6, which means that the
programming process will apply six programming pulses. The number 6
is based on the assumption that the natural VT distribution is
about 3V wide and that the average VT shift up per program pulse is
0.5V. then 3.0/0.5=6 pulses. If the step size is changed or the
assumption about the width of the natural distribution is wrong,
then more or less pulses are needed. The natural distribution is
the response (i.e. new VT distribution) of a group of cells to a
single program pulse when the same program pulse (or the same
sequence of program pulses) is (are) applied to all of cells. The
group of cells can be composed of, for example, all cells to be
programmed on a word line, all cells to be programmed to a
particular state on a word line, all cells on a block, all cells on
a chip, all cells across many chips depending on the context in
which the term natural VT distribution is used. Generally the
larger the group of cells under consideration, the wider the
natural distribution from end to end. FIG. 9A shows seven different
natural distributions (one per program state) where each one is the
outcome for cells to be programmed to a particular state, and these
outcomes are different due to the fact that lower states'
programming is retarded by virtue of applied higher voltages to the
cell's source line and bit line. The lower the state, the higher
the retarding potential transferred to its channel by application
of these higher voltages to bit lines and source lines.
[0070] If the program counter PC is less than K, then the process
continues at step 876, during which all of the memory cells being
programmed are concurrently verified for all target data states
using a single read voltage pulse on the selected word line and
data dependent voltages on individual bit lines and individual
source lines. Memory cells that verify successfully will be locked
out from further programming for the remainder of the programming
process. In step 878, the Program Counter PC is incremented by 1
and the program voltage Vpgm is stepped up to the next magnitude.
After step 878, the process loops back to step 870 and another
program pulse is applied to the selected word line. In one
embodiment, the six program pulses are at 19 v, 19.6 v, 20.2 v,
20.8 v, 21.4 v and 22 v.
[0071] If, in step 874, it is determined that the program counter
is not less than K (i.e. PC=K) then the programming process of FIG.
10 is complete. In this embodiment, there is no verification
performed for the last program pulse. In other embodiments,
verification can be performed for the last program pulse and the
system can (optionally) determine whether enough memory cells have
been successfully programmed.
[0072] FIG. 11 is a table that identifies one embodiment of data
dependent source line voltages and bit line voltages for
programming, verifying and reading. Step 870 of FIG. 10 includes
applying data dependent voltages to individual source lines and bit
lines for programming. The second column of FIG. 11 (second row has
header of "Program") identifies the data dependent voltages applied
to individual source lines and the seventh column of FIG. 11
(second row has header of "Program") identifies the data dependent
voltages applied to individual bit lines. For example, if a memory
cell is being programmed to state S1, then in step 870 the source
line receives 4.8 volts and the bit line receives 4.8 volts. If a
memory cell is being programmed to state S2, then in step 870 the
source line receives 4.0 volts and the bit line receives 4.0 volts.
If a memory cell is being programmed to state S3, then in step 870
the source line receives 3.2 volts and the bit line receives 3.2
volts. If a memory cell is being programmed to state S4, then in
step 870 the source line receives 2.4 volts and the bit line
receives 2.4 volts. If a memory cell is being programmed to state
S5, then in step 870 the source line receives 1.6 volts and the bit
line receives 1.6 volts. If a memory cell is being programmed to
state S6, then in step 870 the source line receives 0.8 volts and
the bit line receives 0.8 volts. If a memory cell is being
programmed to state S7, then in step 870 the source line receives
0.0 volts and the bit line receives 0.0 volts. If the memory cell
is to remain in the erased state S0, then in step 870 the source
line receives 6.0 volts and the bit line receives 6.0 volts. Once a
decision has been made based on one of the verify operations to
lock out any particular cell from further programming (due to
cell's VT exceeding its verify level), then from that point on the
cell/column will be treated the same way as an erased cell (i.e. it
will be locked out of further programming by boosting or other
methods that inhibit programming).
[0073] Step 870 of FIG. 10 includes applying data dependent
voltages to individual source lines and bit lines for verifying.
The fourth column of FIG. 11 (second row has header of "Verify")
identifies the data dependent voltages applied to individual source
lines and the ninth column of FIG. 11 (second row has header of
"Verify") identifies the data dependent voltages applied to
individual bit lines. For example, if a memory cell is being
programmed to state S1, then in step 870 the source line receives
4.8 volts and the bit line receives 5.3 volts. If a memory cell is
being programmed to state S2, then in step 870 the source line
receives 4.0 volts and the bit line receives 4.5 volts. If a memory
cell is being programmed to state S3, then in step 870 the source
line receives 3.2 volts and the bit line receives 3.7 volts. If a
memory cell is being programmed to state S4, then in step 870 the
source line receives 2.4 volts and the bit line receives 2.9 volts.
If a memory cell is being programmed to state S5, then in step 870
the source line receives 1.6 volts and the bit line receives 2.1
volts. If a memory cell is being programmed to state S6, then in
step 870 the source line receives 0.8 volts and the bit line
receives 1.3 volts. If a memory cell is being programmed to state
S7, then in step 874 the source line receives 0.0 volts and the bit
line receives 0.5 volts. If the memory cell is to remain in the
erased state S0, then in step 874 the source line receives 6.0
volts and the bit line receives 6.0 volts.
[0074] Step 870 of FIG. 10 also include locking out memory cells
that have been successfully verified to have reached their target
data state. The third column of FIG. 11 (second row has header of
"Lock out") identifies the data dependent voltages applied to
individual source lines and the tenth column of FIG. 11 (second row
has header of "Lock out") identifies the data dependent voltages
applied to individual bit lines. In all cases, when a memory cell
is locked out the source line and bit line are set at 6 volts. Any
memory cell that should be inhibited from programming has its
source line and bit line set to 6.0 volts, as per the third and
eighth columns of FIG. 11 (second row has header of "Inhibit").
Note that the numerical values listed in FIG. 11 are examples, and
other values can also be used.
[0075] Because memory cells being programmed to lower states
receive higher source line voltages and bit line voltages, the
programming pulses will cause the memory cells being programmed to
lower states to increase threshold voltage at a lower rate, as per
the graphs of FIG. 9. Similarly, because memory cells being
verified for lower states receive higher source line voltages and
bit line voltages, the verification test can use the same single
verification voltage pulse on the selected word line. FIG. 13 shows
a sample voltage signal applied to a selected word line. There are
six Vpgm program pulses 557, 558, 559, 560, 561 and 562 that
increase in magnitude, as described above. One of the program
pulses is applied during each iteration of step 872 of FIG. 10.
Between the Vpgm program pulses are verify pulses 570. That is,
between any two Vpgm program pulses is one verify pulse that is
used to verify all data states by using different source line and
bit line voltages as per the table of FIG. 11. One verify pulse 570
is applied during each iteration of step 874.
[0076] FIG. 12 is a table that provides example voltages for the
drain side select signal (VSGD), source side select signal (VSGS),
selected word line (WL N), unselected word lines on the source side
of the selected word line (WL#.ltoreq.N-1), and unselected word
lines on the drain side of the selected word line (WL#.gtoreq.N+1).
For example, during verify operations the selected word line
receives one voltage pulse at 5.2 volts, while the unselected word
lines, source side select signal, and drain side select signal
receive 6 volts, and while the unselected word lines on the source
side receive 12 volts. Other voltages than 6V can be applied, and
engineering optimization will determine the best voltages to apply
to unselected word lines, various source side select gates, and
various drain side select gates during both verify and program
operations. During programming, the selected word line receives
Vpgm (see FIG. 13), while the unselected word lines on the drain
side, the source side select signal, and the drain side select
signal receive 6 volts, and while the unselected word lines on the
source side receive 12 volts. During reading, the selected word
line receive Vcgr (ie Vr1, Vr2, Vr3, Vr4, Vr5, Vr6 or Vr 7), the
source side select signal receive 4 volts, the drain side select
signal receives 4 volts, and all unselected word lines receive 7
volts. Note that the numerical values listed in FIG. 12 are
examples, and other values can also be used.
[0077] FIG. 14 is a flow chart describing one embodiment of a
process for verifying that is performed as part of step 874 of FIG.
10. In step 902, the individual bit lines receive a data dependent
signal, as discussed above, and the individual source lines receive
a data dependent signal, as discussed above. In some embodiments
the system continues to apply the voltage (i.e. hold the voltage),
since the system does not want to bring down the voltages applied
to bit lines and source lines at the end of a program pulse by
discharging them, only to recharge them back up to pretty much the
same voltage for following verify operation. This saves energy.
[0078] In step 904, the drain side selection signal is applied. In
step 906, the source side selection signal is applied. Steps 904
and 906 can be performed concurrently or sequentially. If performed
sequentially, either 904 or 906 can be performed first. In step
910, the set of sense amplifiers concurrently perform sensing
operation for all (or a subset) of the memory cells for all data
states. That is, the system will sense for S0, S1, S2, S3, S4, S5,
S6 and S7 at the same time. Note that in some embodiments, for
verifying after the first program pulse, WLs, SGSs, SGDs, BLs,
& SLs can all start to rise together in order to save time.
They will reach final voltage values at different times.
[0079] In another embodiment, the system can start ramping up
(raising the voltage of) the word lines, the select gates, the bit
lines, and the source lines all together for the selected finger
(i.e. word line). The bit lines and the source lines can be slower
to rise due to either their RC time constants being longer or the
energy requirements being more (which would necessitate an
intentional controlled ramp up of these .about.600,000 lines in
order not to exceed maximum allowed instantaneous currents), in
some embodiments it may be safe to assume that word lines and
select gates will reach high voltages before bit lines and source
lines reach high voltages. Note that one embodiment charges the bit
lines and the source lines in two stages: stage 1 takes lines to
VCC or less, and stage 2 takes those lines that have to go to
higher than VCC values from VCC to these higher values. Each stage
is allotted a minimum of 20 micro seconds based on worst case bit
line or source line RC time constants. The maximum time for each
stage is based on how many cells will require their bit lines and
source lines to be raised in voltage during the BL/SL charging
phase which occurs before each program pulse. Some program pulses
will have very few numbers of BLs and SLs charging up to high
voltages (e.g. charge ups for program pulses #2 & #6, for which
the circuit is RC dominated and 20 us per stage will be adequate.
But there are other charging phases when the system needs to allow
more than 20 us per one or both stages of charge up before the
associated program pulse. Thus, there is a pulse by pulse control
of ramp up time and pulse dependent charge up times. There is a lot
of BL & SL charge up activity prior to program pulse #1.
[0080] FIG. 15 is a flow chart describing one embodiment of a
process for reading. Unlike verification, reading is performed
sequentially. That is, the system will perform a read operation for
one data state at a time. In one embodiments, the system will first
read to determine which memory cells are in S0, then S1, then S2, .
. . S7. In other embodiments, other orders can be implemented. Each
data state is associated with its own word line voltage, referred
to as Vcgr (ie Vr1, Vr2, Vr3, Vr4, Vr5, Vr6 or Vr 7). In step 950,
the Vcgr voltage for the compare level (ie Vr1, Vr2, Vr3, Vr4, Vr5,
Vr6 or Vr 7) is applied to the selected word line. Additionally,
the unselected word line receive the voltages indicated in FIG. 14.
In step 952, the drain side selection signal is applied. In step
954, the source side selection signal is applied. In step 956, the
common bit line voltage is applied to all bit lines. In step 958,
the common source line voltage is applied to all source lines. In
step 960, the sense amplifiers will sense data for the Vcgr applied
in step 950. If there are more compare levels to apply (step 962),
then the process loops back to step 950. In one set of embodiments,
there are seven compare levels, so there will be seven iteration of
steps 950-960. When there are no more compare levels to evaluate
(step 962), then the process continues at step 964 the system
determines which data state each memory cell read is in and what
the corresponding data stores is. That data is reported to the
host.
[0081] Note that the processes of FIG. 10 (programming), 14
(verifying) and 15 (reading) can be performed together in any
combination, separate, concurrently, serially or in another
manner.
[0082] In one embodiment, erasing is performed in the same manner
as in the prior art. In another embodiment, erasing is performed by
taking advantage of Gate Induced Drain Leakage.
[0083] In one embodiment, immediately after programming, a read
operation is performed to make sure that the bit error rate is
sufficiently low to all future reads to be performed. Note that ECC
can be used to fix a number of bit errors.
[0084] FIG. 16 is a table of voltages used during programming and
verification of programming for selected word lines (WLn) in
selected block for program/verify and shows the transition of
waveforms for the first two program pulses and the associated
verify operations. The remaining operations are the same as the
second program pulse (i.e. repeats of stages 2.1 to 2.7). The last
program pulse (6th pulse in this example) does not require a verify
in some embodiments and its stages 6.1 to 6.5 are similar to other
program pulses' corresponding stages. An addition step 6.6 during
which all lines are brought back to ground will bring the program
verify sequence to an end. The voltages and timings serve as
examples and can be different in various scenarios. Even the
sequence of events can be changed to some extent. Other than the
first column of labels, each column shows voltages during a
different stage of operation. The first program pulse has seven
stages: 1.1, 1.2, 1.3, 1.4, 1.5, 1.6 and 1.6. The second program
pulse also has seven stages: 2.1, 2.2, 2.3, 2.4, 2.5, 2.6 and 2.7.
Stages 1.1, 1.2 as well as 2.1 and 2.2 are an example
implementation of step 870 of FIG. 10. Stages 1.4 and 1.5 as well
as 2.4 and 2.5 are example implementation of step 872 of FIG. 10.
Stages 1.7 and 2.7 are example implementations of step 876 of FIG.
10, as well as the process of FIG. 14. The table shows voltages for
the four source side select lines (SGSA, SGAB, SGSC, SGSD), the
four drain side select lines (SGDA, SGDB, SGDC, SGDD), the two
drain side dummy word lines (WLDD1, WLDD2), the two drain side
dummy word lines (WLDS1, WLDS2), the selected word line WLN,
unselected word lines (WLO, WL<N-1, WLN-1, WLN+1, WL>N+1,
WL47), source lines and bit line. With respect to the stage number,
the digit to the left of the decimal point indicates the program
pulse associated with the iteration of the programming process and
the digit to the left of the decimal point refers to the sub stage
(0.1-0.7).
[0085] The first two sub stages for the first program pulse include
setting the various bit line and source voltages to their data
dependent values. This is done in two stages, with the first stage
(1.1) bring the bit lines and source line to the lower of their
target or VCC (.about.3.1 v). The other signals are depicted to
transition from 0 to the values noted. For example, SGSA shows
"0.fwdarw.8" which represents a transition from 0 volts to 8 volts.
In the second stage (1.2), the bit lines and source lines are
raised from VCC to their targets (if they were not already at their
targets). In third stage (1.3), the drain side select lines and
source side select lines are lowered. The third stages (i.e. 1.3,
2.3, . . . , 6.3) can be eliminated in some embodiments for all
program verify pulses. If they are to be eliminated, then select
gate source and drain voltages are raised only to 6 v as opposed to
8 v in the first stages (i.e. 1.1, 2.1, . . . , 6.1). In the fourth
stage, the word lines are raised to Vpass (e.g., 7-10 volts) to
boost unselected NAND strings and prevent program disturb. In the
fifth stage (1.5), the program pulse is applied. In the sixth stage
(1.6), the system transitions to verify without bringing all of the
signals down to 0 volts. In one embodiment, the system transitions
to verify without bringing any of the listed signals down to 0
volts (or another resting or transition voltage). In the seventh
stage, concurrent verification is performed. The stages for the
second and subsequent program pulses are similar to the first
program pulse, except in the first stage (e.g., 2.1, 3.1, 4.1, 5.1,
and 6.1), the transition of voltages is from the previous verify
voltage levels rather than 0. For some of the sub stages, the bit
line voltage shows "x or 6" which represents applying the data
dependent value x or 6 volts because the memory cell is locked
out.
[0086] In one embodiment, the memory system does not necessarily
have to have its bit lines below memory layers and its source line
above. There can be embodiments with bit lines above the memory and
source lines below the memory.
[0087] There is a description above of two stage charging for the
bit lines and source lines. In other embodiments, three stage
charging can be used for the bit lines and source lines. Three
stage charging could become useful, if VCC <6/2=(BL/SL voltage
for inhibit)/2. Then stage 1 takes the lines to VCC or below, stage
2 to takes the lines to slightly lower than 2*VCC, and stage 3
takes the lines to voltages above slightly lower than 2*VCC.
[0088] The above-described architecture reduces the number of
program pulses and verify pulses, which results in an increase in
performance of the memory system. As described, the time needed for
verification is dramatically reduced as all states are verified
simultaneously. Additionally, because the bit lines are below the
stack, there is no need for bit line interconnects that run from
below to above the stack, which saves space. Since there is only
one word line per block per level, as opposed to multiple word
lines on a level, the word line RC is reduced and less space is
needed. Additionally, locating the bit line drivers (sense
amplifiers) below the stack also save room on the integrated
circuit.
[0089] If, in some embodiments, programming all states concurrently
or verifying all states concurrently proves too costly (e.g. too
much leakage or disturb), the system can instead deploy a scheme
that would break each program pulse into two sets: one set geared
for states A, B, C, & D, and the other set geared for states E,
F, and G for example. For A to D states the Vpgm pulse will start
at 16.2V, and when E to G are to be programmed the first pulse for
these states starts at 19V. Verify can also be broken up into two
sets. This provides semi-concurrency. It will reduce the
performance gain and will increase energy per bit programmed, but
it may be the last resort to some leakage, or disturb problem due
to very high bit line and source line voltages of full concurrent
program and verify. Also, since it will reduce bit line and source
line voltage requirements, it will be able to eliminate or
significantly reduce the need to pump up the bit line and source
line voltages that have to charge up and maintain voltages
significantly higher than VCC.
[0090] Another embodiment includes adding more pads to memory chips
to bring in other voltage supplies than just VCC. For example, the
system can bring as many as 6 other voltages from the outside onto
the chip (not just 0 v & VCC). An example would be to supply 0,
0.8, 1.6, 2.4, 3.2, 4.0, 4.8, & 6.0V from outside the chip.
Another example is to bring 0, 0.9, 1.7, 2.5, 3.3, 4.1, 4.9, and
6.1V from outside and regulate them down to supply 0, 0.8, 1.6,
2.4, 3.2, 4.0, 4.8, & 6.0V. This will allow the memory chips to
run a lot cooler by not having to use inefficient pumps to pump up
about 600,000 bit lines and source lines to voltages that go as
high as 6V. On solid states drives SSDs and ESSDs it may be easier
to generate these voltages off chip. If these pads are on the chip
and the circuits that accompany them as well, the system will have
the option to use them or not depending on the type of product
being offered.
[0091] One embodiment includes a stack of alternating dielectric
layers and conductive layers; columns of memory cells formed in the
stack; a plurality of bit lines connected to the columns and
positioned at a first side of the stack; and a plurality of source
lines connected to the columns and positioned at a second side of
the stack.
[0092] One embodiment includes applying a particular voltage to a
word line connected to multiple memory cells in different active
columns of memory cells formed in a three dimensional memory
structure, each of the active columns having a unique dedicated bit
line of a set of bit lines and a unique dedicated source line of a
set of source lines; applying voltages to the source lines; and
performing a memory operation on the memory cells in response to
the particular voltage and the voltages applied to the source
lines.
[0093] One embodiment includes a plurality of memory cells arranged
as NAND strings in a three dimensional memory structure; a
plurality of bit lines below the three dimensional memory
structure, each bit line is connected to a different subset of
multiple NAND strings; and a plurality of source lines above the
three dimensional memory structure, each NAND string is a vertical
column of memory cells having a charge trapping layer with one end
of the column connected to one of the source lines and an opposite
end of the column connected to one of the bit lines, a separate
source line is associated with each bit line, each source line is
connected to a different subset of multiple NAND strings, each
source line and its associated bit line connect to the same
multiple NAND strings.
[0094] The foregoing detailed description of the invention has been
presented for purposes of illustration and description. It is not
intended to be exhaustive or to limit the invention to the precise
form disclosed. Many modifications and variations are possible in
light of the above teaching. The described embodiments were chosen
in order to best explain the principles of the invention and its
practical application, to thereby enable others skilled in the art
to best utilize the invention in various embodiments and with
various modifications as are suited to the particular use
contemplated. It is intended that the scope of the invention be
defined by the claims appended hereto.
* * * * *